Datasheet ADV7320 Datasheet (Analog Devices)

Multiformat 216 MHz

A

FEATURES

High definition input formats

16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb

Fully compliant with:

SMPTE 274M (1080i, 1080p @ 74.25 MHz) SMPTE 296M (720p) SMPTE 240M (1035i) RGB in 3- × 10-bit 4:4:4 input format

HDTV RGB supported:

RGB, RGBHV Other high definition formats using async

timing mode

Enhanced definition input formats

8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb SMPTE 293M (525p) BTA T-1004 EDTV2 (525p) ITU-R BT.1358 (625p/525p) ITU-R BT.1362 (625p/525p) RGB in 3- × 10-bit 4:4:4 input format

Standard definition input formats

CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input

High definition output formats

YPrPb HDTV (EIA 770.3) RGB, RGBHV CGMS-A (720p/1080i)

Enhanced definition output formats

Macrovision Rev 1.2 (525p/625p) (ADV7320 only) CGMS-A (525p/625p) YPrPb progressive scan (EIA-770.1, EIA-770.2) RGB, RGBHV

Standard definition output formats

Composite NTSC M/N Composite PAL M/N/B/D/G/H/I, PAL-60 SMPTE 170M NTSC-compatible composite video ITU-R BT.470 PAL-compatible composite video S-video (Y/C) EuroScart RGB Component YPrPb (Betacam, MII, SMPTE/EBU N10) Macrovision Rev 7.1.L1 (ADV7320 only)

CGMS/WSS Closed captioning

GENERAL FEATURES

Simultaneous SD/HD, PS/SD inputs and outputs Oversampling up to 216 MHz

Video Encoder with Six NSV® 12-Bit DACs

ADV7320/ADV7321

Programmable DAC gain control Sync outputs in all modes On-board voltage reference Six 12-bit NSV (noise shaped video) precision video DACs 2-wire serial I Dual I/O supply 2.5 V/3.3 V operation Analog and digital supply 2.5 V On-board PLL 64-lead LQFP package Lead (Pb) free product

APPLICATIONS

EVD players (enhanced versatile disk) High end /SD/PS DVD recorders/players SD/progressive scan/HDTV display devices SD/HDTV set top boxes Professional video systems

Y9–Y0 C9–C0 S9–S0

HSYNC VSYNC BLANK

CLKIN_ CLKIN_B

GENERAL DESCRIPTION

The ADV®7320/ADV7321 are high speed, digital-to-analog encoders on single monolithic chips. They include six high speed NSV video D/A converters with TTL compatible inputs. They have separate 8-/10-, 16-/20-, and 24-/30-bit input ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical, and blanking signals or EAV/SAV timing codes control the insertion of appropriate synchronization signals into the digital data stream and, therefore, the output signal.

2

C® interface, open-drain configuration

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE

D E M U X

TIMING

GENERATOR

PLL

FILTERS

SD TEST PATTERN

PROGRAMMABLE

RGB MATRIX

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

O V E R S A M P L

N G

Figure 1. Simplified Functional Block Diagram

ADV7320/ ADV7321

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

I

12-BIT

DAC

12-BIT

DAC

I2C

INTERFACE

05067-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADV7320/ADV7321

TABLE OF CONTENTS

Specifications..................................................................................... 6

Programmable DAC Gain Control.......................................... 53

Dynamic Specifications ................................................................... 7

Timing Specifications....................................................................... 8

Timing Diagrams.............................................................................. 9

Absolute Maximum Ratings.......................................................... 16

Thermal Characteristics ............................................................16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ...........................................19

MPU Port Description................................................................... 23

Register Access................................................................................ 25

Register Programming............................................................... 25

Subaddress Register (SR7 to SR0)............................................ 25

Input Configuration....................................................................... 38

Standard Definition Only.......................................................... 38

Progressive Scan Only or HDTV Only ................................... 38

Simultaneous Standard Definition and

Progressive Scan or HDTV....................................................... 38

Gamma Correction .................................................................... 53

HD Sharpness Filter and Adaptive Filter Controls................ 55

HD Sharpness Filter and Adaptive Filter

Application Examples ................................................................ 56

SD Digital Noise Reduction...................................................... 57

Coring Gain Border ................................................................... 58

Coring Gain Data....................................................................... 58

DNR Threshold .......................................................................... 58

Border Area................................................................................. 58

Block Size Control...................................................................... 58

DNR Input Select Control......................................................... 58

DNR Mode Control ................................................................... 59

Block Offset Control.................................................................. 59

SD Active Video Edge................................................................ 59

SAV/EAV Step Edge Control.................................................... 59

HSYNC

Board Design and Layout.............................................................. 62

/

Output Control ............................................ 61

VSYNC

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz ........... 39

Features............................................................................................ 41

Output Configuration................................................................ 41

HD Async Timing Mode........................................................... 42

HD Timing Reset........................................................................ 43

SD Real-Time Control, Subcarrier Reset, and

Timing Reset ............................................................................... 43

Reset Sequence............................................................................ 45

SD VCR FF/RW Sync................................................................. 45

Vertical Blanking Interval ......................................................... 46

Subcarrier Frequency Registers................................................ 46

Square Pixel Timing Mode........................................................ 47

Filters............................................................................................ 48

Color Controls and RGB Matrix .............................................. 49

Rev. 0 | Page 2 of 88

DAC Termination and Layout Considerations ...................... 62

Video Output Buffer and Optional Output Filter.................. 62

PCB Board Layout...................................................................... 63

Appendix 1—Copy Generation Management System .............. 65

PS CGMS..................................................................................... 65

HD CGMS................................................................................... 65

SD CGMS .................................................................................... 65

Function of CGMS Bits ............................................................. 65

CGMS Functionality.................................................................. 65

Appendix 2—SD Wide Screen Signaling .................................... 68

Appendix 3—SD Closed Captioning ........................................... 69

Appendix 4—Test Patterns............................................................ 70

Appendix 5—SD Timing Modes .................................................. 73

ADV7320/ADV7321

Mode 0 (CCIR-656)—Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0) ............................73

Mode 0 (CCIR-656)—Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1) ............................74

Mode 1—Slave Option

(Timing Register 0 TR0 = X X X X X 0 1 0) ............................76

Mode 1—Master Option

(Timing Register 0 TR0 = X X X X X 0 1 1) ............................77

Mode 2— Slave Option

(Timing Register 0 TR0 = X X X X X 1 0 0) ............................78

Appendix 6—HD Timing..............................................................81

Appendix 7—Video Output Levels...............................................82

HD YPrPb Output Levels ..........................................................82

RGB Output Levels.....................................................................83

YPrPb Levels—SMPTE/EBU N10............................................84

Appendix 8—Video Standards......................................................86

Outline Dimensions........................................................................88

Ordering Guide...........................................................................88

Mode 2—Master Option

(Timing Register 0 TR0 = X X X X X 1 0 1) ............................79

Mode 3—Master/Slave Option (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

.......................................................................................................80

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 3 of 88

ADV7320/ADV7321

DETAILED FEATURES

High definition programmable features (720p/1080i/1035i)

2× oversampling (148.5 MHz) Internal test pattern generator

Color hatch, black bar, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS-A (720p/1080i)

Enhanced definition programmable features (525p/625p)

8× oversampling (216 MHz output) Internal test pattern generator

Color hatch, black bar, flat frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) (ADV7320 only) CGMS-A (525p/625p)

Standard definition programmable features

16× oversampling (216 MHz) Internal test pattern generator

Color bars, black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAF™ filter with programmable gain/attenuation PrPb SSAF™ Separate pedestal control on component and

composite/S-video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 (ADV7320 only)

CGMS/WSS

Closed captioning

Table 1. Standards Directly Supported1

Frame

Interlace/

Resolution

720 × 480 I 29.97 27

720 × 576 I 25 27

720 × 480 I 29.97 24.54

720 × 576 I 25 29.5

720 × 483 P 59.94 27

720 × 483 P 59.94 27 BTA T-1004 720 × 483 P 59.94 27

720 × 576 P 50 27

720 × 483 P 59.94 27

720 × 576 P 50 27

1280 × 720 P

Prog.

Rate (Hz)

30 74.25 1920 × 1035 I

29.97 74.1758 60, 50,

30, 25, 24,

23.97,

59.94,

29.97 30, 25 74.25 1920 × 1080 I

29.97 74.1758 30, 25, 24 74.25 1920 × 1080 P

23.98,

29.97,

Clk Input (MHz) Standard

ITU-R BT.656

NTSC Square Pixel

PAL Square Pixel

SMPTE 293M

ITU-R BT.1358

ITU-R BT.1362

SMPTE 240M

74.25,

74.1758

SMPTE 296M

SMPTE 274M

1

Other standards are supported in async timing mode.

Rev. 0 | Page 4 of 88

ADV7320/ADV7321

HD PIXEL

INPUT

CLKIN_B

P_HSYNC P_VSYNC P_BLANK

S_HSYNC S_VSYNC S_BLANK

CLKIN_A

SD PIXEL

INPUT

DEINTERLEAVE

CR CB

CB CR

Y

TEST

PATTERN

TEST

PATTERN

TERMINOLOGY

SD: standard definition video, conforming to ITU-R BT.601/ITU-R BT.656.

HD: high definition video, i.e., 720p/1080i/1035i.

EDTV: enhanced definition television (525p/625p)

PS: progressive scan video, conforming to SMPTE 293M, ITU-R BT.1358, BTAT-1004EDTV2, or ITU-R BT.13621362.

SHARPNESS

ADAPTIVE CONTROL

TIMING

GENERATOR

TIMING

GENERATOR

GAMMA

AND

FILTER

DNR

Y COLOR CR COLOR CB COLOR

COLOR

CONTROL

CLOCK

CONTROL

AND PLL

SYNC

INSERTION

4:2:2

TO

4:4:4

U

UV SSAF

V

LUMA

AND

CHROMA

FILTERS

Figure 2. Detailed Functional Block Diagram

HDTV: high definition television video, conforming to SMPTE 274M, or SMPTE 296M and SMPTE240M.

YCrCb SD, PS, or HD component: digital video.

YPrPb SD, PS, or HD component: analog video.

MATRIX

2×OVER-

SAMPLING

RGB

F

SC

MODU-

LATION

CGMS

WSS

PS 8×

HDTV 2×

SD 16×

DAC

05067-002

Rev. 0 | Page 5 of 88

ADV7320/ADV7321

SPECIFICATIONS

VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, V specifications T

MIN

to T

(0°C to 70°C), unless otherwise noted.

MAX

Table 2.

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE1

Resolution 12 Bits Integral Nonlinearity 1.5 LSB Differential Nonlinearity,2 +ve 0.25 LSB Differential Nonlinearity,2 −ve 1.5 LSB

DIGITAL OUTPUTS

Output Low Voltage, VOL 0.4 [0.4]3 V I Output High Voltage, VOH 2.4 [2.0]3 V I Three-State Leakage Current ±1.0 µA VIN = 0.4 V, 2.4 V Three-State Output Capacitance 2 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Leakage Current 10 µA VIN = 2.4 V Input Capacitance, CIN 2 pF

ANALOG OUTPUTS

Full-Scale Output Current 4.1 4.33 4.6 mA Output Current Range 4.1 4.33 4.6 mA DAC to DAC Matching 1.0 % Output Compliance Range, VOC 0 1.0 1.4 V Output Capacitance, C

7 pF

OUT

VOLTAGE REFERENCE

Internal Reference Range, V External Reference Range, V V

Current4 ±10 µA

REF

1.15 1.235 1.3 V

REF

1.15 1.235 1.3 V

REF

POWER REQUIREMENTS

Normal Power Mode

5

I

137 mA SD only (16×)

DD

78 mA PS only (8×) 73 mA HDTV only (2×) 140 1906 mA SD (16×, 10 bit) + PS (8×, 20 bit)

I

1.0 mA

DD_IO

7, 8

I

37 45 mA

AA

Sleep Mode

IDD 80 µA IAA 7 µA I

250 µA

DD_IO

POWER SUPPLY REJECTION RATIO 0.01 %/%

= 2.375 V to 3.6 V, V

DD_IO

= 1.235 V, R

REF

= 3040 Ω, R

SET

= 3.2 mA

SINK

SOURCE

LOAD

= 400 µA

= 300 Ω. All

1

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

2

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for −ve DNL, the

actual step value lies below the ideal step value.

3

Value in brackets for V

4

External current required to overdrive internal V

5

IDD, the circuit current, is the continuous current required to drive the digital core.

6

Guaranteed maximum by characterization.

7

All DACs on.

8

IAA is the total current required to supply all DACs including the V

= 2.375 V to 2.75 V.

DD_IO

.

REF

circuitry and the PLL circuitry.

REF

Rev. 0 | Page 6 of 88

ADV7320/ADV7321

DYNAMIC SPECIFICATIONS

VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, V specifications T

MIN

to T

(0°C to 70°C), unless otherwise noted.

MAX

Table 3.

Parameter Min Typ Max Unit Test Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth 12.5 MHz Chroma Bandwidth 5.8 MHz

SNR 65.6 dB Luma ramp unweighted 72 dB Flat field full bandwidth HDTV MODE

Luma Bandwidth 30 MHz

Chroma Bandwidth 13.75 MHz STANDARD DEFINITION MODE

Hue Accuracy 0.2 Degrees

Color Saturation Accuracy 0.20 %

Chroma Nonlinear Gain 0.84 ±% Referenced to 40 IRE

Chroma Nonlinear Phase −0.2 ± Degrees

Chroma/Luma Intermodulation 0 ±%

Chroma/Luma Gain Inequality 96.7 ±%

Chroma/Luma Delay Inequality −1.0 ns

Luminance Nonlinearity 0.2 ±%

Chroma AM Noise 84 dB

Chroma PM Noise 75.3 dB

Differential Gain 0.25 % NTSC

Differential Phase 0.2 Degrees NTSC

SNR 63.5 dB Luma ramp

77.7 dB Flat field full bandwidth

= 2.375 V to 3.6 V, V

DD_IO

= 1.235 V, R

REF

= 3040 Ω, R

SET

= 300 Ω. All

LOAD

Rev. 0 | Page 7 of 88

ADV7320/ADV7321

TIMING SPECIFICATIONS

VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, V specifications T

MIN

to T

(0°C to 70°C), unless otherwise noted.

MAX

Table 4.

Parameter Min Typ Max Unit Test Conditions

MPU PORT1

SCLOCK Frequency 0 400 kHz SCLOCK High Pulse Width, t1 0.6 µs SCLOCK Low Pulse Width, t2 1.3 µs Hold Time (Start Condition), t3 0.6 µs

Setup Time (Start Condition), t4 0.6 µs Data Setup Time, t5 100 ns SDATA, SCLOCK Rise Time, t6 300 ns SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 µs

Low Time 100 ns

RESET

ANALOG OUTPUTS

Analog Output Delay2 7 ns Output Skew 1 ns

CLOCK CONTROL AND PIXEL PORT3

f

29.5 MHz SD PAL square pixel mode

CLK

f

81 MHz PS/HD async mode

CLK

Clock High Time, t9 40 % of one clk cycle Clock Low Time, t10 40 % of one clk cycle Data Setup Time, t Data Hold Time, t

1

2.0 ns

11

1

2.0 ns

12

SD Output Access Time, t13 15 ns SD Output Hold Time, t14 5.0 ns HD Output Access Time, t13 14 ns

HD Output Hold Time, t14 5.0 ns PIPELINE DELAY4 63 clk cycles SD (2×, 16×)

76 clk cycles SD component mode (16×) 35 clk cycles PS (1×) 41 clk cycles PS (8×) 36 clk cycles HD (2×, 1×)

1

Guaranteed by characterization.

2

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3

Data: C[9:0]; Y[9:0], S[9:0]

P_HSYNC

Control:

4

SD, PS = 27 MHz, HD = 74.25 MHz.

P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK

,

= 2.375 V to 3.6 V, V

DD_IO

= 1.235 V, R

REF

= 3040 Ω, R

SET

First clock generated after this period relevant for repeated start condition

= 300 Ω. All

LOAD

Rev. 0 | Page 8 of 88

ADV7320/ADV7321

C

TIMING DIAGRAMS

CLKIN_A

CONTROL

INPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

ONTROL

INPUTS

Cb2

t

12

Cr2

Cb4

t

14

Cr4

t

13

P_HSYNC, P_VSYNC, P_BLANK

Y9–Y0

C9–C0

CONTROL

OUTPUTS

t

10

9

Y0 Y1 Y2 Y3 Y4 Y5

Cb0

Cr0

t

11

Figure 3. HD Only 4:2:2 Input Mode (Input Mode 010); PS Only 4:2:2 Input Mode (Input Mode 001)

CLKIN_A

t

12

P_HSYNC, P_VSYNC, P_BLANK

t

9

10

05067-003

CONTROL

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Figure 4. HD Only 4:4:4 Input Mode (Input Mode 010); PS Only 4:4:4 Input Mode (Input Mode 001)

Y9–Y0

C9–C0

S9–S0

OUTPUTS

Y0 Y1 Y2 Y3 Y4 Y5

Cb0

Cr0

Cb2Cb1

t

11

Cr2Cr1

Cb4Cb3

Cr4Cr3

t

14

t

13

Cb5

Cr5

05067-004

Rev. 0 | Page 9 of 88

ADV7320/ADV7321

t

CLKIN_A

CONTROL

INPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

P_HSYNC, P_VSYNC, P_BLANK

CONTROL

INPUTS

Y9–Y0

C9–C0

S9–S0

OUTPUTS

CLKIN_B*

P_HSYNC, P_VSYNC, P_BLANK

Y9–Y0

t

9

10

G0 G1 G2 G3 G4 G5

B0 B1 B2 B3 B4 B5

t

11

R0 R1 R2 R3 R4 R5

t

12

t

14

t

13

Figure 5. HD RGB 4:4:4 Input Mode (Input Mode 010)

t

9

t

10

Cb0

Cr0

Y0

Y1

Crxxx

Yxxx

05067-005

= CLOCK HIGH TIME

9

= CLOCK LOW TIME

10

= DATA SETUP TIME

11

= DATA HOLD TIME

12

CONTROL

INPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

P_VSYNC, P_HSYNC, P_BLANK

CONTROL

t

12

t

11

CONTROL

OUTPUTS

*CLKIN_B MUST BE USED IN THIS PS MODE.

Figure 6. PS 4:2:2 10-Bit Interleaved at 27 MHz

CLKIN_A

t

10

9

Y9–Y0

OUTPUTS

Cb0

t

12

t

11

Y0

Figure 7. PS 4:2:2 10-Bit Interleaved at 54 MHz

Cr0

t

11

HSYNC

t

12

t

13

t

14

VSYNC

/

Input Mode (Input Mode 100)

Y1

t

13

t

14

VSYNC

/

Input Mode (Input Mode 111)

Crxxx

Yxxx

05067-006

05067-007

Rev. 0 | Page 10 of 88

ADV7320/ADV7321

t

CLKIN_B*

t

9

10

= CLOCK HIGH TIME

9

= CLOCK LOW TIME

10

= DATA SETUP TIME

11

= DATA HOLD TIME

12

CONTROL

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Y9–Y0

CONTROL

OUTPUTS

3FF

t

12

t

11

*CLKIN_B USED IN THIS PS ONLY MODE.

t

11

t

12

Y0Cb0XY0000

Cr0

t

13

t

14

Figure 8. PS Only 4:2:2 10-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100)

CLKIN_A

t

10

9

Y9–Y0

OUTPUTS

3FF

t

12

t

11

00

NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT-1

00

XY

t

Cb0

t

13

14

Y0

Figure 9. PS Only 4:2:2 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 111)

Y1

05067-008

Cr0

Y1

05067-009

CLKIN_B

t

12

Y2

Cb2

t

11

Cr0

Y3 Y4 Y5

Cb4Cr2

t

12

Y1

t

11

Cb1

Cr4

Y2

HD INPUT

SD INPUT

05067-010

CONTROL

INPUTS

CONTROL

INPUTS

P_HSYNC, P_VSYNC, P_BLANK

Y9–Y0

C9–C0

CLKIN_A

S_HSYNC, S_VSYNC, S_BLANK

S9–S0

t

10

9

Y0 Y1

Cb0

t

9

10

Cb0

Cr0

Y0

Figure 10. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode (Input Mode 101: SD Oversampled) (Input Mode 110: HD Oversampled)

Rev. 0 | Page 11 of 88

ADV7320/ADV7321

CLKIN_B

CONTROL

INPUTS

P_HSYNC, P_VSYNC, P_BLANK

Y9–Y0

Cb0

t

9

10

PS INPUT

Crxxx

Cr0

Y0

Y1

Yxxx

CONTROL

INPUTS

CONTROL

INPUTS

CONTROL

INPUTS

CLKIN_A

S_HSYNC,

S_VSYNC,

S_BLANK

S9–S0

CLKIN_B

P_HSYNC, P_VSYNC, P_BLANK

Y9–Y0

CLKIN_A

S_HSYNC,

S_VSYNC,

S_BLANK

S9–S0

t

12

t

11

t

9

10

Cb0

Y0

t

12

t

11

t

12

Cr0

Y1

t

11

Cb1

Y2

Figure 11. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode (Input Mode 011)

t

9

10

Crxxx

Cb1

Yxxx

Y2

Cr0

Y0

Cb0

t

12

t

11

t

9

10

Cb0

Y0

Y1

t

12

t

11

t

12

Cr0

Y1

t

11

Figure 12. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode (Input Mode 100)

PS INPUT

SD INPUT

05067-012

Rev. 0 | Page 12 of 88

ADV7320/ADV7321

CLKIN_A

CONTROL

INPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

CONTROL

INPUTS

S_HSYNC, S_VSYNC, S_BLANK

S9–S0/Y9–Y0*

CONTROL

OUTPUTS

CLKIN_A

S_HSYNC, S_VSYNC, S_BLANK

S9–S0/Y9–Y0* Y0 Y2 Y3Y1

Cb0

t

10

9

Cr0

t

11

t

12

IN SLAVE MODE

Cr2Cb2

Cb4

t

14

Cr4

t

13

IN MASTER/SLAVE MODE

05067-013

Figure 13. 10-/8-Bit SD Only Pixel Input Mode (Input Mode 000)

t

9

10

t

12

IN SLAVE MODE

C9–C0

CONTROL

OUTPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

Cb0 Cr0 Cb2 Cr2

t

11

t

13

t

14

Figure 14. 20-/16-Bit SD Only Pixel Input Mode (Input Mode 000)

IN MASTER/SLAVE MODE

05067-014

Rev. 0 | Page 13 of 88

ADV7320/ADV7321

Y OUTPUT

P_HSYNC

P_VSYNC

P_BLANK

c

a

Y9–Y0

C9–C0

b

a AND b AS PER RELEVANT STANDARD c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE TIMING SPECIFICATION

SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC IN TO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

Y0 Y1

Y2 Y3

Figure 15. HD 4:2:2 Input Timing Diagram

P_HSYNC

P_VSYNC

a

P_BLANK

Cb1Cr1Cr0Cb0

05067-015

Y9–Y0 Cb Y

b

a = 32 CLKCYCLES FOR 525p a = 24 CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p

Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram

Rev. 0 | Page 14 of 88

Cr Y

05067-016

ADV7320/ADV7321

S_HSYNC

S_VSYNC

PAL = 24 CLK CYCLES

NTSC = 32 CLK CYCLES

S_BLANK

S9–S0/Y9–Y0*

*SELECTED BY ADDRESS 0x01 BIT 7

Cb Y

PAL = 264 CLOCK CYCLES

NTSC = 244 CLOCK CYCLES

Cr Y

05067-017

Figure 17. SD Timing Input for Timing Mode 1

t

3

t

4

t

8

05067-018

SDA

SCLK

t

3

t

6

t

2

t

5

t

1

t

7

Figure 18. MPU Port Timing Diagram

Rev. 0 | Page 15 of 88

ADV7320/ADV7321

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter1 Value

VAA to AGND −0.3 V to +3.0 V VDD to DGND −0.3 V to +3.0 V V

to GND_IO −0.3 V to +4.6 V

DD_IO

Digital Input Voltage to DGND −0.3 V to V VAA to VDD −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V DGND to GND_IO −0.3 V to +0.3 V AGND to GND_IO −0.3 V to +0.3 V Ambient Operating Temperature (TA) 0°C to 70°C Storage Temperature (TS) –65°C to +150°C Infrared Reflow Soldering (20 s) 260°C

1

Analog output short circuit to any power supply or common can be of

an indefinite duration.

DD_IO

+0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

θJC = 11°C/W

= 47°C/W

θ

JA

The ADV7320/ADV7321 is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and is able to withstand surface-mount soldering up to 255°C (±5°C).

In addition, it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 16 of 88

ADV7320/ADV7321

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

TOP VIEW

(Not to Scale)

23

24

25

P_VSYNC

P_HSYNC

P_BLANK

55S454S353S252S151S050

26C527C628C729C830C931

S_HSYNC49S_VSYNC

32

RTC_SCR_TR

CLKIN_A

48

S_BLANK

47

R

46

V

45

COMP1

44

DAC A

43

DAC B

42

DAC C

41

V

40

AGND

39

DAC D

38

DAC E

37

DAC F

36

COMP2

35

R

34

EXT_LF

33

RESET

SET1

REF

AA

SET2

05067-019

V

DD_IO

V

DGND

GND_IO63CLKIN_B62S961S860S759S658S557DGND56V

64

1

PIN 1

2

Y0

3

Y1

4

Y2

5

Y3

6

Y4

7

Y5

8

Y6

9

Y7

10

DD

11 12

Y8

13

Y9

14

C0

15

C1

16

C2

17C318C419

ADV7320/ADV7321

20

21

22

C

2

I

SDA

ALSB

SCLK

Figure 19. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Input/Output Description

11, 57 DGND G Digital Ground. 40 AGND G Analog Ground. 32 CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz). 63 CLKIN_B I

Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.

45, 36

COMP1,

O Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V

.

AA

COMP2 44 DAC A O CVBS/Green/Y/Y Analog Output. 43 DAC B O Chroma/Blue/U/Pb Analog Output. 42 DAC C O Luma/Red/V/Pr Analog Output. 39 DAC D O

In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Y/Green [HD] Analog Output.

38 DAC E O

In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red Analog Output.

37 DAC F O

In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pb/Blue [HD] Analog Output.

23 24 25 48 49 50 13,12,

9–2 30–26,

18–14

P_HSYNC

P_VSYNC

P_BLANK

S_BLANK

S_VSYNC

S_HSYNC

Y9 to Y0 I

C9 to C0 I

I Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. I Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. I Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. I/O Video Blanking Control Signal for SD Only. I/O Video Vertical Sync Control Signal for SD Only. I/O Video Horizontal Sync Control Signal for SD Only.

SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2.

Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB is set up on C2.

Rev. 0 | Page 17 of 88

ADV7320/ADV7321

Pin No. Mnemonic Input/Output Description

62–58, 55–51

33

47, 35 R

22 SCLK I I2C Port Serial Interface Clock Input. 21 SDA I/O I2C Port Serial Data Input/Output. 20 ALSB I

1 V 10, 56 VDD P Digital Power Supply. 41 VAA P Analog Power Supply. 46 V 34 EXT_LF I External Loop Filter for the Internal PLL. 31 RTC_SCR_TR I Multifunctional Input. Real-time control (RTC) input, timing reset input, subcarrier reset input. 19 I2C I This input pin must be tied high (V 64 GND_IO Digital Input/Output Ground.

S9 to S0 I

SD or Progressive Scan/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2.

I

This input resets the on-chip timing generator and sets the ADV7320/ADV7321 into default register setting. RESET

is an active low signal.

A 3040 Ω resistor must be connected from this pin to AGND and is used to control the

RESET

SET1

, R

SET2

amplitudes of the DAC outputs.

2

TTL Address Input. This signal sets up the LSB of the I

2

I

C filter is activated, which reduces noise on the I2C interface.

P Power Supply for Digital Inputs and Outputs.

DD_IO

I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

REF

) for the ADV7320/ADV7321 to interface over the I2C port.

DD_IO

C address. When this pin is tied low, the

Rev. 0 | Page 18 of 88

ADV7320/ADV7321

V

A

/

TYPICAL PERFORMANCE CHARACTERISTICS

SS BAND IN PS OVERSAMPLINGMODE

PROGSCAN Pr/Pb RESPONSE. LINEARINTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

Figure 20. PS—UV 8× Oversampling Filter (Linear)

PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

Figure 21. PS—UV 8× Oversampling Filter (SSAF)

1.0

0.5

0

–0.5

–1.0

GAIN (dB)

–1.5

–2.0

–2.5

05067-045

20020 40 60 80 100 120 140 160 1800

–3.0

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

05067-046

20020 40 60 80 100 120 140 160 1800

–80

YP

FREQUENCY (MHz)

122468100

Figure 23. PS—Y 8× Oversampling Filter (Pass Band)

Pb RESPONSE IN HDTVOVERSAMPLINGMODE

Pr

FREQUENCY (MHz)

Figure 24. HDTV—UV 2× Oversampling Filter

05067-048

05067-049

14020 40 60 80 100 1200

Y RESPONSE IN PS O

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

Figure 22. PS—Y 8× Oversampling Filter

ERSAMPLINGMODE

FREQUENCY (MHz)

Y RESPONSE IN HDTV OVERSAMPLINGMODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

05067-047

20020 40 60 80 100 120 140 160 1800

–80

FREQUENCY (MHz)

05067-050

14020 40 60 80 100 1200

Figure 25. HDTV—Y 2× Oversampling Filter

Rev. 0 | Page 19 of 88

ADV7320/ADV7321

MAGNITUDE (dB)

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

0

FREQUENCY (MHz)

Figure 26. Luma NT SC Low-Pass Filter

0

FREQUENCY (MHz)

Figure 27. Luma PAL Low-Pass Filter

121086420

05067-051

05067-052

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

Figure 29. Luma PAL Notch Filter

Y RESPONSE IN SD OVERSAMPLINGMODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

0 20 40 60 80 100 120 140 160 180 200

FREQUENCY (MHz)

Figure 30. Y—16× Oversampling Filter

05067-054

121086420

05067-055

MAGNITUDE (dB)

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE (dB)

–10

–20

–30

–40

–50

–60

–70

0

FREQUENCY (MHz)

Figure 31. Luma SSAF Filter up to 12 MHz

05067-056

121086420

0

05067-053

FREQUENCY (MHz)

121086420

Figure 28. Luma NTSC Notch Filter

Rev. 0 | Page 20 of 88

ADV7320/ADV7321

4

2

0

–2

–4

–6

MAGNITUDE (dB)

–8

–10

–12

0

234

1

FREQUENCY (MHz)

5

Figure 32. Luma SSAF Filter—Programmable Responses

5

4

3

2

MAGNITUDE (dB)

1

0

–1

0

234

1

FREQUENCY (MHz)

5

Figure 33. Luma SSAF Filter—Programmable Gain

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

6

05067-057

7

–70

620

FREQUENCY (MHz)

84

10

05067-060

12

Figure 35. Luma CI F Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

05067-058

6

7

–70

4

620

FREQUENCY (MHz)

8

10

05067-061

12

Figure 36. Luma QCIF Low-Pass Filter

1

0

–1

–2

MAGNITUDE (dB)

–3

–4

–5

0

1

23

FREQUENCY (MHz)

4

5

Figure 34. Luma SSAF Filter—Programmable Attenuation

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

05067-059

6

7

–70

4

620

FREQUENCY (MHz)

8

10

05067-062

12

Figure 37. Chroma 3.0 MHz Low-Pass Filter

Rev. 0 | Page 21 of 88

ADV7320/ADV7321

MAGNITUDE (dB)

0

–10

–20

–30

–40

–50

–60

–70

4

FREQUENCY (MHz)

Figure 38. Chroma 2.0 MHz Low-Pass Filter

0

–10

–20

–30

–40

–50

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

10

620

8

05067-063

12

–70

4

620

FREQUENCY (MHz)

10

8

05067-066

12

Figure 41. Chroma 0.65 MHz Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

MAGNITUDE (dB)

–60

–70

4

FREQUENCY (MHz)

Figure 39. Chroma 1.3 MHz Low-Pass Filter

0

–10

–20

–30

–40

–50

–60

–70

4

FREQUENCY (MHz)

Figure 40. Chroma 1.0 MHz Low-Pass Filter

10

620

8

05067-064

12

05067-065

10

620

8

12

MAGNITUDE (dB)

–60

–70

–10

–20

–30

–40

–50

–60

–70

4

FREQUENCY (MHz)

Figure 42. Chroma CIF Low-Pass Filter

0

4

FREQUENCY (MHz)

Figure 43. Chroma QCIF Low-Pass Filter

05067-067

620

8

10

12

620

8

10

05067-068

12

Rev. 0 | Page 22 of 88

ADV7320/ADV7321

MPU PORT DESCRIPTION

The ADV7320/ADV7321 support a 2-wire serial (I2Ccompatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV7320/ ADV7321. Each slave device is recognized by a unique address. The ADV7320/ADV7321 have four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 44. The LSB sets either a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. A1 is enabled by setting the ALSB pin of the ADV7320/ADV7321 to Logic 0 or Logic 1. When ALSB is set to 1, there is greater input

2

bandwidth on the I

C lines, which allows high speed data

transfers on this bus. When ALSB is set to 0, there is reduced

2

input bandwidth on the I less than 50 ns will not pass into the I

C lines, which means that pulses of

2

C internal controller. This

mode is recommended for noisy systems.

1 1 0 1 0 1 A1 X

ADDRESS CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL 0 WRITE

1 READ

Figure 44. ADV7320 Slave Address = 0xD4

0 1 0 1 0 1 A1 X

ADDRESS CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL 0 WRITE

1 READ

Figure 45. ADV7321 Slave Address = 0x54

05067-020

05067-021

To control the various devices on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-tolow transition on SDA while SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address

bit). The bits are transferred from MSB down to LSB.

+ R/

W

The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the

correct transmitted address. The R/ direction of the data.

Logic 0 on the LSB of the first byte means that the master will write information to the peripheral. Logic 1 on the LSB of the first byte means that the master will read information from the peripheral.

The ADV7320/ADV7321 act as standard slave devices on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/

bit. It interprets the first byte as

W the device address and the second byte as the starting subaddress. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one

basis without updating all the registers.

Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then they cause an immediate jump to the idle condition. During a given SCL high period, the user should only issue a start condition, a stop condition, or a stop condition followed by a start condition. If an invalid subaddress is issued by the user, the ADV7320/ADV7321 will not issue an acknowledge and will return to the idle condition. If the user utilizes the autoincrement method of addressing the encoder and exceeds the highest subaddress, the following actions are taken:

• In read mode, the highest subaddress register contents are

output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition is when the SDA line is not pulled low on the ninth pulse.

• In write mode, the data for the invalid byte is not loaded into

any subaddress register, a no acknowledge is issued by the ADV7320/ADV7321, and the part returns to the idle condition.

Before writing to the subcarrier frequency registers, it is required to reset ADV7320/ADV7321 at least once after power-up.

The four subcarrier frequency registers must be updated, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3. The subcarrier frequency will only update after the last subcarrier frequency register byte has been received by the ADV7320/ADV7321.

Figure 46 illustrates an example of data transfer for a write sequence and the start and stop conditions. Figure 47 shows bus write and read sequences.

bit determines the

W

Rev. 0 | Page 23 of 88

ADV7320/ADV7321

SDATA

SCLOCK

1–7 8

START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP

9S1–7

9

8

1–7

8

P

9

05067-022

Figure 46. Bus Data Transfer

WRITE

SEQUENCE

READ

SEQUENCE

S SLAVE ADDR A(S) SUBADDR A(S) DATA DATA A(S) P

LSB = 0

S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER

A(S)

LSB = 1

A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER

05067-023

Figure 47. Read and Write Sequence

Rev. 0 | Page 24 of 88

ADV7320/ADV7321

REGISTER ACCESS

The MPU can write to or read from all registers of the ADV7320/ADV7321 except the subaddress registers, which are write only registers. The subaddress register determines which register the next read or write operation will access. All communication with the part through the bus starts with an access to the subaddress register. A read/write operation is then performed from/to the target address, which increments to the next address until a stop command is performed on the bus.

Table 7. Registers 0x00 to 0x01

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x00 Power

Mode Register

0x01 Mode

Select Register

control enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled. I registers can be read from and written to in sleep mode.

Control. This control allows the internal PLL cct to be powered down and the oversampling to be switched off.

DAC A: Power On/Off.

Reserved. 0 Reserved.

Clock Edge.

Reserved. 0

Input Mode.

Y/C/S Bus Swap.

2

C

0 Sleep mode off. 0xFC Sleep Mode. With this 1 Sleep mode on.

0 PLL on. PLL and Oversampling 1 PLL off.

0 DAC F off. DAC F: Power On/Off. 1 DAC F on. 0 DAC E off. DAC E: Power On/Off. 1 DAC E on. 0 DAC D off. DAC D: Power On/Off. 1 DAC D on. 0 DAC C off. DAC C: Power On/Off. 1 DAC C on. 0 DAC B off. DAC B: Power On/Off. 1 DAC B on. 0 DAC A off. 1 DAC A on.

0 Cb clocked upon rising

1 Y clocked upon rising

0 Clock Align. 1 Must be set if the phase

0 0 0 SD input only. 0x38 0 0 1 PS input only. 0 1 0 HDTV input only. 0 1 1 SD and PS (20-bit). 1 0 0 SD and PS (10-bit). 1 0 1 SD and HDTV (SD

1 1 0 SD and HDTV (HDTV

1 1 1 PS only (at 54 MHz). 0

1

REGISTER PROGRAMMING

The following tables describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated.

SUBADDRESS REGISTER (SR7 TO SR0)

The communication register is an 8-bit write only register. After the encoder’s bus is accessed and a read/write operation is selected, the subaddress is set up. The subaddress register determines to or from which register the operation takes place.

Reg. Reset Values (Shaded)

edge.

delay between the two input clocks is <9.25 ns or >27.75 ns.

oversampled).

Allows data to be applied to data ports in various configurations (SD feature only).

Only for PS interleaved input at 27 MHz.

Only if two input clocks are used.

See Table 21.

Rev. 0 | Page 25 of 88

ADV7320/ADV7321

Table 8. Registers 0x02 to 0x0F

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values

0x02 Mode Register 0

0x03 RGB Matrix 0 x x LSB for GY. 0x03 0x04 RGB Matrix 1

0x05 RGB Matrix 2 x x x x x x x x Bits 9 to 2 for GY. 0x4E 0x06 RGB Matrix 3 x x x x x x x x Bits 9 to 2 for GU. 0x0E 0x07 RGB Matrix 4 x x x x x x x x Bits 9 to 2 for GV. 0x24 0x08 RGB Matrix 5 x x x x x x x x Bits 9 to 2 for BU. 0x92 0x09 RGB Matrix 6 x x x x x x x x Bits 9 to 2 for RV. 0x7C 0x0A DAC A, B, C Output

0 0 0 0 0 0 0 1 +0.018% 0 0 0 0 0 0 1 0 +0.036% … … 0 0 1 1 1 1 1 1 +7.382% 0 1 0 0 0 0 0 0 +7.5% Negative Gain to

1 1 0 0 0 0 0 1 −7.382% 1 0 0 0 0 0 1 0 −7.364% … … 1 1 1 1 1 1 1 1 −0.018% 0x0B DAC D, E, F Output

0 0 0 0 0 0 0 1 +0.018% 0 0 0 0 0 0 1 0 +0.036% … … 0 0 1 1 1 1 1 1 +7.382% 0 1 0 0 0 0 0 0 +7.5% Negative Gain to

1 1 0 0 0 0 0 1 −7.382% 1 0 0 0 0 0 1 0 −7.364% … … 1 1 1 1 1 1 1 1 −0.018% 0x0C Reserved 0x00 0x0D Reserved 0x00 0x0E Reserved 0x00 0x0F Reserved 0x00

Level

2

1

For more detail, refer to Appendix 7.

2

For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

Reserved 0 0 Zero must be written to

Bar Manual RGB

Matrix Adjust

Output

HD Sync

Positive Gain to DAC Output Voltage

DAC Output Voltage

Positive Gain to DAC Output Voltage

DAC Output Voltage

0 Disabled. Test Pattern Black 1 Enabled. 0 Disable manual RGB matrix

1 Enable manual RGB matrix

0 No sync. Sync on RGB1 1 Sync on all RGB outputs. 0 RGB component outputs. RGB/YPrPb 1 YPrPb component outputs. 0 No sync output. SD Sync 1 Output SD syncs on

0 No sync output. 1 Output HD, ED, syncs on

x x LSB for RV. 0xF0 x x LSB for BU. x x LSB for GV. x x LSB for GU.

0 0 0 0 0 0 0 0 0%

1 1 0 0 0 0 0 0 −7.5%

0 0 0 0 0 0 0 0 0%

1 1 0 0 0 0 0 0 −7.5%

these bits.

adjust.

S_HSYNC S_BLANK

S_HSYNC

,

S_VSYNC

pins.

,

S_VSYNC

,

.

0x20

0x11, Bit 2 must also be enabled.

0x00

Rev. 0 | Page 26 of 88

ADV7320/ADV7321

Table 9. Registers 0x10 to 0x11

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Note

0x10

0x11

HD Mode Register 1

HD Mode Register 2

HD Output Standard

Input Sync Format

HD/ED Input Mode

HD Pixel Data Valid

HD Test Pattern Enable

HD Test Pattern Hatch/Field

HD Undershoot Limiter

HD Sharpness Filter

0 0 EIA770.2 output 0x00 0 1 EIA770.1 output 1 0

1 1 Reserved 0

1 EAV/SAV codes

0 0 0 0 0

0 0 0 0 1 Async mode 0 0 0 1 0

0 0 0 1 1 ITU-BT 1358

0 0 1 0 0 ITU-BT 1362

0 0 1 0 1 SMPTE 296M-1, 2

0 0 1 1 0 SMPTE 296M-3

0 0 1 1 1 SMPTE 296M-4, 5

0 1 0 0 0 SMPTE 296M-6

0 1 0 0 1 SMPTE 296M-7, 8

0 1 0 1 0 SMPTE 240M

0 1 0 1 1 Reserved 0 1 1 0 0 Reserved 0 1 1 0 1 SMPTE 274M-4, 5

0 1 1 1 0 SMPTE 274M-6

0 1 1 1 1 SMPTE 274M-7, 8

1 0 0 0 0 SMPTE 274M-9

1 0 0 0 1

10010–11111 Reserved 0 Pixel data valid off 1 Pixel data valid on 0 Reserved 0 HD test pattern off 1 HD test pattern on 0 Hatch 1 Field/frame 0 Disabled HD VBI Open 1 Enabled 0 0 Disabled 0 1 −11 IRE 1 0 −6 IRE 1 1 −1.5 IRE 0 Disabled 1 Enabled

Output levels for full input range

HSYNC, VSYNC BLANK

SMPTE 293M, ITUBT 1358

BTA-1004, ITUBT 1362

SMPTE 274M10, 11

,

525p @

59.94 Hz

525p @

59.94 Hz 625p @

50 Hz 625p @

50 Hz 720p @

60/59.94 Hz 720p @

50 Hz 720p @

30/29.97 Hz 720p @

25 Hz 720p @

24/23.98 Hz 1035i @

60/59.94 Hz

1080i @ 30/29.97 Hz

1080i @ 25 Hz

1080p @ 30/29.97 Hz

1080p @ 25 Hz

1080p @ 24/23.98 Hz

Only available in EDTV (525p/625p)

Reset Values

0x00

Rev. 0 | Page 27 of 88

ADV7320/ADV7321

Table 10. Register 0x12

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x12

HD Mode Register 3

HD Y Delay with Respect to Falling Edge of

HD Color Delay with Respect to Falling Edge of HSYNC

HD CGMS CRC

HSYNC

Table 11. Registers 0x13 to 0x14

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x13

HD Mode Register 4

Reserved 0 0 must be written to this bit.

HD Double Buffering

0x14

HD Mode Register 5

HD Timing Reset x

HD Macrovision for 525p and 625p

Reserved 0 0 must be written to these bits.

/Field Input

VSYNC

Horizontal/Vertical

2

Counters

1

Used in conjunction with HD_SYNC in Register 0x02, Bit 7 set to 1.

2

When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

0 0 0 0 clk cycles 0x00 0 0 1 1 clk cycles 0 1 0 2 clk cycles 0 1 1 3 clk cycles 1 0 0 4 clk cycles 0 0 0 0 clk cycles 0 0 1 1 clk cycle 0 1 0 2 clk cycles 0 1 1 3 clk cycles 1 0 0 4 clk cycles 0 Disabled HD CGMS 1 Enabled 0 Disabled 1 Enabled

0 Cb after falling edge of

1 Cr after falling edge of

0 8-bit input. HD Input Format 1 10-bit input. 0 Disabled. Sinc Filter on DAC D, E, F 1 Enabled.

0 Disabled. HD Chroma SSAF 1 Enabled. 0 4:4:4 HD Chroma Input 1 4:2:2 0 Disabled. 1 Enabled.

A low-high-low transition resets the internal HD timing

counters. 0 HD Hsync Generation1 1 0 HD Vsync Generation1 1 0

1

0 Macrovision disabled. 1 Macrovision enabled.

0 0 = field input. HD 1 1 =

0 Update field/line counter. 1 Field/line counter free running.

Refer to the / Output Control

section.

active high. HD Blank Polarity

BLANK

active low.

BLANK

input.

VSYNC

HSYNC

. 0x4C HD Cr/Cb Sequence

.

Reset Values

0x00

Rev. 0 | Page 28 of 88

ADV7320/ADV7321

Table 12. Register 0x15

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x15

HD Mode Register 6

Reserved 0 0 must be written to this bit. 0x00

0 Disabled. HD RGB Input 1 Enabled. 0 Disabled. HD Sync on PrPb 1 Enabled. 0 DAC E = Pb; DAC F = Pr. HD Color DAC Swap 1 DAC E = Pr; DAC F = Pb. 0 Gamma Curve A. HD Gamma Curve A/B 1 Gamma Curve B. 0 Disabled. HD Gamma Curve Enable 1 Enabled. 0 Mode A. HD Adaptive Filter Mode 1 Mode B.

HD Adaptive Filter Enable

0 Disabled. 1 Enabled.

Reset Values

Rev. 0 | Page 29 of 88

ADV7320/ADV7321

Table 13. Registers 0x16 to 0x37

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x16 HD Y Level1 x x x x x x x x Y level value 0xA0 0x17

HD Cr Level

0x18

HD Cb Level

0x19 Reserved 0x00 0x1A Reserved 0x00 0x1B Reserved 0x00 0x1C Reserved 0x00 0x1D Reserved 0x00 0x1E Reserved 0x00 0x1F Reserved 0x00 0x20

HD Sharpness Filter Gain

0x21 HD CGMS Data 0 HD CGMS Data Bits 0 0 0 0 C19 C18 C17 C16 CGMS 19 to 16 0x00 0x22 HD CGMS Data 1 HD CGMS Data Bits C15 C14 C13 C12 C11 C10 C9 C8 CGMS 15 to 8 0x00 0x23 HD CGMS Data 2 HD CGMS Data Bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS 7 to 0 0x00 0x24 HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A0 0x00 0x25 HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A1 0x00 0x26 HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A2 0x00 0x27 HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A3 0x00 0x28 HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A4 0x00 0x29 HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A5 0x00 0x2A HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A6 0x00 0x2B HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A7 0x00 0x2C HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A8 0x00 0x2D HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A9 0x00 0x2E HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B0 0x00 0x2F HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B1 0x00 0x30 HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B2 0x00 0x31 HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B3 0x00 0x32 HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B4 0x00 0x33 HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B5 0x00 0x34 HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B6 0x00 0x35 HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B7 0x00 0x36 HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B8 0x00 0x37 HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B9 0x00

1

x x x x x x x x Cr level value

x x x x x x x x Cb level value

HD Sharpness Filter Gain Value A

HD Sharpness Filter Gain Value B

0 0 0 0 Gain A = 0 0x00 0 0 0 1 Gain A = +1 … … … … … 0 1 1 1 Gain A = +7 1 0 0 0 Gain A = −8 … … … … … 1 1 1 1 Gain A = −1 0 0 0 0 Gain B = 0 0 0 0 1 Gain B = +1 … … … … … 0 1 1 1 Gain B = +7 1 0 0 0 Gain B = −8 … … … … … 1 1 1 1 Gain B = −1

1

For use with internal test pattern only.

Register Setting

Reset Values

0x80

Rev. 0 | Page 30 of 88

ADV7320/ADV7321

Table 14. Registers 0x38 to 0x3D

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x38

0x39

0x3A

0x3B

0x3C

0x3D

HD Adaptive Filter Gain 1

HD Adaptive Filter Gain 2

HD Adaptive Filter Gain 3

HD Adaptive Filter Threshold A

HD Adaptive Filter Threshold B

HD Adaptive Filter Threshold C

HD Adaptive Filter Gain 1 Value A

HD Adaptive Filter Gain 1 Value B

HD Adaptive Filter Gain 2 Value A

HD Adaptive Filter Gain 2 Value B

HD Adaptive Filter Gain 3 Value A

HD Adaptive Filter Gain 3 Value B

HD Adaptive Filter Threshold A

HD Adaptive Filter Threshold B

HD Adaptive Filter Threshold C

0 0 0 0 Gain A = 0 0x00 0 0 0 1 Gain A = +1 … … … … … 0 1 1 1 Gain A = +7 1 0 0 0 Gain A = −8 … … … … … 1 1 1 1 Gain A = −1 0 0 0 0 Gain B = 0 0 0 0 1 Gain B = +1 … … … … … 0 1 1 1 Gain B = +7 1 0 0 0 Gain B = −8 … … … … … 1 1 1 1 Gain B = −1 0 0 0 0 Gain A = 0 0x00 0 0 0 1 Gain A = +1 … … … … … 0 1 1 1 Gain A = +7 1 0 0 0 Gain A = −8 … … … … … 1 1 1 1 Gain A = −1 0 0 0 0 Gain B = 0 0 0 0 1 Gain B = +1 … … … … … 0 1 1 1 Gain B = +7 1 0 0 0 Gain B = −8 … … … … … 1 1 1 1 Gain B = −1 0 0 0 0 Gain A = 0 0x00 0 0 0 1 Gain A = +1 … … … … … 0 1 1 1 Gain A = +7 1 0 0 0 Gain A = −8 … … … … … 1 1 1 1 Gain A = −1 0 0 0 0 Gain B = 0 0 0 0 1 Gain B = +1 … … … … … 0 1 1 1 Gain B = +7 1 0 0 0 Gain B = −8 … … … … … 1 1 1 1 Gain B = −1 x x x x x x x x Threshold A

x x x x x x x x Threshold B

x x x x x x x x Threshold C

Register Setting

Reset Values

0x00

Rev. 0 | Page 31 of 88

ADV7320/ADV7321

Table 15. Registers 0x3E to 0x43

SR7– SR0

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x3E Reserved 0x00 0x3F Reserved 0x00 0x40 SD Mode Register 0

0x41 Reserved 0x00 0x42 SD Mode Register 1

0x43 SD Mode Register 2

SD Standard

SD Luma Filter

SD Chroma Filter

SD DAC Output 1

SD DAC Output 2

SD SAV/EAV Step Edge Control

Output

SD Output Levels PrPb

SD CC Field Control

Reserved 0 Reserved

0 0 NTSC 0x00 0 1 PAL B, D, G, H, I 1 0 PAL M 1 1 PAL N 0 0 0 LPF NTSC 0 0 1 LPF PAL 0 1 0 Notch NTSC 0 1 1 Notch PAL 1 0 0 SSAF luma 1 0 1 Luma CIF 1 1 0 Luma QCIF 1 1 1 Reserved 0 0 0 1.3 MHz 0 0 1 0.65 MHz 0 1 0 1.0 MHz 0 1 1 2.0 MHz 1 0 0 Reserved 1 0 1 Chroma CIF 1 1 0 Chroma QCIF 1 1 1 3.0 MHz

0 Disabled SD PrPb SSAF 1 Enabled 0 Refer to output

configuration section 1 0 Refer to output

configuration section 1 0 Disabled SD Pedestal 1 Enabled 0 Disabled SD Square Pixel 1 Enabled 0 Disabled SD VCR FF/RW Sync 1 Enabled 0 Disabled SD Pixel Data Valid 1 Enabled 0 Disabled 1 Enabled 0 No pedestal on YUV SD Pedestal YPrPb 1 7.5 IRE pedestal on YUV 0 Y = 700 mV/300 mV SD Output Levels Y 1 Y = 714 mV/286 mV 0 0 700 mV p-p (PAL); 1000

mV p-p (NTSC) 0 1 700 mV p-p 1 0 1000 mV p-p 1 1 648 mV p-p 0 Disabled SD VBI Open 1 Enabled 0 0 CC disabled 0 1 CC on odd field only 1 0 CC on even field only 1 1 CC on both fields

Reset Values

0x08

0x00

Rev. 0 | Page 32 of 88

ADV7320/ADV7321

Table 16. Registers 0x44 to 0x49

SR7– SR0

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x44 SD Mode

Register 3

SD RTC/TR/SCR

SD DAC Swap

0x45 Reserved 0x00 0x46 SD Mode

Register 4

0x47 SD Mode

Register 5

0x48 SD Mode

Register 6

0x49 SD Mode

Register 7

NTSC Color Subcarrier Adjust (Falling Edge of HS to Start of Color Burst)

Reserved 0 0 must be written to this bit Reserved 0 0 must be written to this bit Reserved 0 0 must be written to this bit Reserved 0 0x00 Reserved 0 0 must be written to this bit

SD Input Format

Reduction

SD Gamma Curve

SD Undershoot Limiter

Reserved 0 0 must be written to this bit

DAC Luma SD Chroma Delay

Reserved 0 0 must be written to this bit Reserved 0 0 must be written to this bit

VSYNC

1

-3H

0 Disabled SD 1

0 0 Genlock disabled 0 1 Subcarrier Reset 1 0 Timing Reset 1 1 RTC enabled 0 720 pixels SD Active Video Length 1 710 (NTSC)/702 (PAL) 0 Chroma enabled SD Chroma 1 Chroma disabled 0 Enabled SD Burst 1 Disabled 0 Disabled SD Color Bars 1 Enabled 0 DAC A = luma, DAC B = chroma 1 DAC A = chroma, DAC B = luma

0 0 5.17 μs 0 1 5.31 μs (default) 1 0 5.59 μs (must be set for

1 1 Reserved 0 Disabled SD PrPb Scale 1 Enabled 0 Disabled SD Y Scale 1 Enabled 0 Disabled SD Hue Adjust 1 Enabled 0 Disabled SD Brightness 1 Enabled 0 Disabled SD Luma SSAF Gain 1 Enabled

0 Disabled SD Double Buffering 1 Enabled 0 0 8-bit input 0 1 16-bit input 1 0 10-bit input 1 1 20-bit input 0 Disabled SD Digital Noise 1 Enabled 0 Disabled SD Gamma Control 1 Enabled 0 Gamma Curve A 1 Gamma Curve B 0 0 Disabled 0x00 0 1 −11 IRE 1 0 −6 IRE 1 1 −1.5 IRE

0 Disabled SD Black Burst Output on 1 Enabled 0 0 Disabled 0 1 4 clk cycles 1 0 8 clk cycles 1 1 Reserved

= 2.5 lines (PAL),

VSYNC

= 3 lines (NTSC)

VSYNC

Macrovision compliance)

1

NTSC color bar adjust should be set to 10 b for macrovision compliance (ADV7320 only).

Reset Values

0x00

0x01

0x00

Rev. 0 | Page 33 of 88

ADV7320/ADV7321

Table 17. Registers 0x4A to 0x58

SR7– SR0

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x4A SD Timing

Register 0

Mode SD Timing Mode

0 Slave mode. SD Slave/Master 1 Master mode. 0 0 Mode 0. 0 1 Mode 1. 1 0 Mode 2. 1 1 Mode 3. 0 Enabled. SD BLANK Input 1 Disabled.

SD Luma Delay

0 0 No delay. 0 1 2 clk cycles. 1 0 4 clk cycles. 1 1 6 clk cycles. 0 −40 IRE. SD Min. Luma

Value

1 −7.5 IRE.

SD Timing Reset x 0 0 0 0 0 0 0 A low-high-low transition will

reset the internal SD timing counters.

0x4B SD Timing

Register 1

SD

HSYNC

Width

0 0 Ta = 1 clk cycle. 0 1 Ta = 4 clk cycles. 1 0 Ta = 16 clk cycles.

SD VSYNC

HSYNC

Delay

HSYNC

to

VSYNC

Rising Edge Delay

1 1 T 0 0 Tb = 0 clk cycle. 0 1 Tb = 4 clk cycles. 1 0 Tb = 8 clk cycles. 1 1 T x 0 T x 1 T

= 128 clk cycles.

a

= 18 clk cycles.

b

= Tb. SD

c

= Tb + 32 µs.

c

(Mode 1 Only)

Width

VSYNC (Mode 2 Only)

0 0 1 clk cycle. 0 1 4 clk cycles. 1 0 16 clk cycles. 1 1 128 clk cycles.

to Pixel

HSYNC Data Adjust

0 0 0 clk cycles. 0 1 1 clk cycle. 1 0 2 clk cycles. 1 1 3 clk cycles.

0x4C SD FSC Register 01 x x x x x x x x Subcarrier Frequency Bits 7 to 0. 0x4D SD FSC Register 1 x x x x x x x x Subcarrier Frequency Bits 15 to 8. 0x7C

0x4E SD FSC Register 2 x x x x x x x x Subcarrier Frequency Bits 23 to 16. 0xF0 0x4F SD FSC Register 3 x x x x x x x x Subcarrier Frequency Bits 31 to 24. 0x21 0x50 SD FSC Phase x x x x x x x x Subcarrier Phase Bits 9 to 2. 0x00 0x51 SD Closed

Captioning

0x52 SD Closed

Captioning

0x53 SD Closed

Extended Data on

x x x x x x x x Extended Data Bits 7 to 0. 0x00 Even Fields Extended Data on

x x x x x x x x Extended Data Bits 15 to 8. 0x00 Even Fields Data on Odd Fields x x x x x x x x Data Bits 7 to 0. 0x00

Captioning

0x54 SD Closed

Data on Odd Fields x x x x x x x x Data Bits 15 to 8. 0x00

Captioning

0x55 SD Pedestal

Register 0

Pedestal on Odd Fields

17 16 15 14 13 12 11 10 Setting any of these bits to 1 will

disable pedestal on the line number indicated by the bit settings.

0x56 SD Pedestal

Register 1

0x57 SD Pedestal

Register 2

0x58 SD Pedestal

Register 3

Pedestal on Odd Fields Pedestal on Even Fields Pedestal on Even Fields

25 24 23 22 21 20 19 18 0x00

17 16 15 14 13 12 11 10 0x00

25 24 23 22 21 20 19 18 0x00

1

For precise NTSC Fsc, this register should be programmed to 0x1F.

LINE 313 LINE 314LINE 1

HSYNC

VSYNC

t

A

t

B

C

05067-024

Figure 48. Timing Register 1 in PAL Mode

Reset Value

0x08

0x00

0x1E1

0x00

Rev. 0 | Page 34 of 88

ADV7320/ADV7321

Table 18. Registers 0x59 to 0x64

SR7– SR0

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x59 SD CGMS/WSS 0

0x5B SD CGMS/WSS 2 SD CGMS/WSS Data 7 6 5 4 3 2 1 0 CGMS/WSS Data Bits C7 to

0x5C SD LSB Register

0x5D SD Y Scale

Register

0x5E SD Cb Scale

Register

0x5F SD Cr Scale

Register 0x60 SD Hue Register SD Hue Adjust Value x x x x x x x x SD Hue Adjust Bits 7 to 0 0x00 0x61 SD Brightness/

WSS

0x62 SD Luma SSAF SD Luma SSAF

0x63 SD DNR 0

0x64 SD DNR 1

SD CGMS Data 19 18 17 16 CGMS Data Bits C19 to C16 0x00

Fields

Fields SD WSS

SD LSB for Y Scale Value SD LSB for Cb Scale Value SD LSB for Cr Scale Value SD LSB for F SD Y Scale Value x x x x x x x x SD Y Scale Bits 7 to 2 0x00

SD Cb Scale Value x x x x x x x x SD Cb Scale Bits 7 to 2 0x00

SD Cr Scale Value x x x x x x x x SD Cr Scale Bits 7 to 2 0x00

SD Brightness Value x x x x x x x SD Brightness Bits 6 to 0 0x00 SD Blank WSS Data

Gain/Attenuation

Coring Gain Border

Coring Gain Data

DNR Threshold

Block Size Control

Phase x x Subcarrier Phase Bits 1 to 0

SC

0 Disabled SD CGMS CRC 1 Enabled 0 Disabled SD CGMS on Odd 1 Enabled 0 Disabled SD CGMS on Even 1 Enabled 0 Disabled 1 Enabled 13 12 11 10 9 8 CGMS Data Bits C13 to C8,

or WSS Data Bits C13 to C8

15 14 CGMS Data Bits C15 to C14

C0

x x SD Y Scale Bits 1 to 0

x x SD Cb Scale Bits 1 to 0

x x SD Cr Scale Bits 1 to 0

0 Disabled 1 Enabled 0 0 0 0 0 0 0 0 −4 dB 0 0 0 0 0 1 1 0 0 dB 0 0 0 0 1 1 0 0 +4 dB 0 0 0 0 No gain 0x00 0 0 0 1 +1/16 [–1/8] 0 0 1 0 +2/16 [–2/8] 0 0 1 1 +3/16 [–3/8] 0 1 0 0 +4/16 [–4/8] 0 1 0 1 +5/16 [–5/8] 0 1 1 0 +6/16 [–6/8] 0 1 1 1 +7/16 [–7/8] 1 0 0 0 +8/16 [–1] 0 0 0 0 No gain 0 0 0 1 +1/16 [–1/8] 0 0 1 0 +2/16 [–2/8] 0 0 1 1 +3/16 [–3/8] 0 1 0 0 +4/16 [–4/8] 0 1 0 1 +5/16 [–5/8] 0 1 1 0 +6/16 [–6/8] 0 1 1 1 +7/16 [–7/8] 1 0 0 0 +8/16 [–1] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 … … … … … … … 1 1 1 1 1 0 62 1 1 1 1 1 1 63 0 2 pixels Border Area 1 4 pixels 0 8 pixels 1 16 pixels

Reset Values

0x00 0x5A SD CGMS/WSS 1 SD CGMS/WSS Data

0x00 0x00

Line 23

0x00

In DNR mode, the values in brackets apply.

0x00

Rev. 0 | Page 35 of 88

ADV7320/ADV7321

Table 19. Registers 0x65 to 0x7C

SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x65 SD DNR 2

0x66 SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A0 0x00 0x67 SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A1 0x00 0x68 SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A2 0x00 0x69 SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A3 0x00 0x6A SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A4 0x00 0x6B SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A5 0x00 0x6C SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A6 0x00 0x6D SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A7 0x00 0x6E SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A8 0x00 0x6F SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A9 0x00 0x70 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B0 0x00 0x71 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B1 0x00 0x72 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B2 0x00 0x73 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B3 0x00 0x74 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B4 0x00 0x75 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B5 0x00 0x76 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B6 0x00 0x77 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B7 0x00 0x78 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B8 0x00 0x79 SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B9 0x00 0x7A

SD Brightness Detect

0x7B

Field Count Register

0x7C Reserved Reserved 0x00

DNR Input Select

DNR Block Offset

SD Brightness Value x x x x x x x x Read only

Field Count x x x Read only Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Revision Code 1 0 Read only

0 0 1 Filter A 0 1 0 Filter B 0 1 1 Filter C 1 0 0 Filter D 0 DNR mode DNR Mode 1 DNR sharpness mode 0 0 0 0 0 pixel offset 0 0 0 1 1 pixel offset … … … … … 1 1 1 0 14 pixel offset 1 1 1 1 15 pixel offset

Reset Values

0x00

0x8x

Rev. 0 | Page 36 of 88

ADV7320/ADV7321

Table 20. Registers 0x7D to 0x91

SR7SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

0x7D Reserved 0x7E Reserved 0x7F Reserved 0x80 Macrovision1 MV Control Bits x x x x x x x x 0x00 0x81 Macrovision MV Control Bits x x x x x x x x 0x00 0x82 Macrovision MV Control Bits x x x x x x x x 0x00 0x83 Macrovision MV Control Bits x x x x x x x x 0x00 0x84 Macrovision MV Control Bits x x x x x x x x 0x00 0x85 Macrovision MV Control Bits x x x x x x x x 0x00 0x86 Macrovision MV Control Bits x x x x x x x x 0x00 0x87 Macrovision MV Control Bits x x x x x x x x 0x00 0x88 Macrovision MV Control Bits x x x x x x x x 0x00 0x89 Macrovision MV Control Bits x x x x x x x x 0x00 0x8A Macrovision MV Control Bits x x x x x x x x 0x00 0x8B Macrovision MV Control Bits x x x x x x x x 0x00 0x8C Macrovision MV Control Bits x x x x x x x x 0x00 0x8D Macrovision MV Control Bits x x x x x x x x 0x00 0x8E Macrovision MV Control Bits x x x x x x x x 0x00 0x8F Macrovision MV Control Bits x x x x x x x x 0x00 0x90 Macrovision MV Control Bits x x x x x x x x 0x00 0x91 Macrovision MV Control Bit 0 0 0 0 0 0 0 x 0 must be written to these bits 0x00

1

Macrovision registers only on the ADV7320.

Reset Values

Rev. 0 | Page 37 of 88

ADV7320/ADV7321

INPUT CONFIGURATION

When 10-bit input data is applied, the following bits must be set to 1:

Address 0x13, Bit 2 (HD 10-bit enable) Address 0x48, Bit 4 (SD 10-bit enable)

Note that the ADV7320 defaults to simultaneous standard definition and progressive scan upon power-up (Address[0x01]: Input Mode = 011).

STANDARD DEFINITION ONLY

Address[0x01]: Input Mode = 000

The 8-/10-bit, multiplexed input data is input on Pins S9 to S0 (or Pins Y9 to Y0, depending on Register Address 0x01, Bit 7), with S0 being the LSB in 10-bit input mode (see Table 21). Input standards supported are ITU-R BT.601/656. In 16-/20-bit input mode, the Y pixel data is input on Pins S9 to S2 and CrCb data is input on Pins Y9 to Y2 (see Table 21).

16-/20-Bit Mode Operation

When Register 0x01 Bit 7 = 0, CrCb data is input on the Y bus and Y data is input on the S bus. When Register 0x01 Bit 7 = 1, CrCb data is input on the C bus and Y data is input on Y bus.

The 27 MHz clock input must be input on Pin CLKIN_A. Input sync signals are input on the

S_BLANK

pins.

S_VSYNC

,

S_HSYNC

Table 21. SD 8-/10-Bit and 16-/20-Bit Configuration

Configuration Parameter 8-/10-Bit Mode 16-/20-Bit Mode

Register 0x01, Bit 7 = 0

Y Bus CrCb S Bus 656/601, YCrCb Y C Bus

Register 0x01, Bit 7 = 1

Y Bus 656/601, YCrCb Y S Bus C Bus CrCb

ADV7320/ ADV7321

S_VSYNC,

3

MPEG2

DECODER

27MHz

YCrCb

*SELECTED BY ADDRESS 0x01 BIT 7

Figure 49. SD Only Input Mode

S_HSYNC, S_BLANK

CLKIN_A

10

S[9:0] OR Y[9:0]*

, and

05067-025

PROGRESSIVE SCAN ONLY OR HDTV ONLY

Address[0x01]: Input Mode = 001 or 010, Respectively

YCrCb progressive scan, HDTV, or any other HD YCrCb data can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data is input on Pins Y9 to Y0 and the CrCb data is input on Pins C9 to C0. In 4:4:4 input mode, Y data is input on Pins Y9 to Y0, Cb data is input on Pins C9 to C0, and Cr data is input on Pins S9 to S0. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004/1362, the async timing mode must be used. RGB data can only be input in 4:4:4 format in PS or HDTV input modes when HD RGB input is enabled. G data is input on Pins Y9 to Y0, R data is input on Pins S9 to S0, and B data is input on Pins C9 to C0. The clock signal must be input on Pin CLKIN_A.

MPEG2

DECODER

YCrCb

INTERLACED TO

PROGRESSIVE

Figure 50. Progressive Scan Input Mode

27MHz

Cb Cr Y

ADV7320/ ADV7321

CLKIN_A

10

C[9:0]

10

S[9:0]

10

Y[9:0]

P_VSYNC,

3

P_HSYNC, P_BLANK

05067-026

SIMULTANEOUS STANDARD DEFINITION AND PROGRESSIVE SCAN OR HDTV

Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit) or 101 (SD and HD, SD Oversampled), 110 (SD and HD, HD Oversampled), Respectively

YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2 input mode, the HD Y data is input on Pins Y9 to Y0 and the HD CrCb data is input on Pins C9 to C0. If PS 4:2:2 data is interleaved onto a single 10-bit bus, Pins Y9 to Y0 are used for the input port. The input data is to be input at 27 MHz, with the data being clocked upon the rising and falling edges of the input clock. The input mode register at Address 0x01 is set accordingly. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004, the async timing mode must be used.

The 8- or 10-bit standard definition data must be compliant with ITU-R BT.601/656 in 4:2:2 format. Standard definition data is input on Pins S9 to S0, with S0 being the LSB. Using 8-bit input format, the data is input on Pins S9 to S2. The clock input for SD must be input on CLKIN_A, and the clock input for HD must be input on CLKIN_B. Synchronization signals are

Rev. 0 | Page 38 of 88

ADV7320/ADV7321

A

optional. SD syncs are input on Pins

S_BLANK

and

. HD syncs are input on Pins

P_BLANK

.

MPEG2

DECODER

YCrCb

3

27MHz

10

S_VSYNC, S_HSYNC

P_VSYNC, P_HSYNC

ADV7320/ ADV7321

S_VSYNC, S_HSYNC, S_BLANK

CLKIN_A S[9:0]

, and

,

OR 54 MHZ

Address[0x01]: Input Mode 100 or 111, Respectively

YCrCb progressive scan data can be input at 27 MHz or 54 MHz. The input data is interleaved onto a single 8-/10-bit bus and is input on Pins Y9 to Y0. When a 27 MHz clock is supplied, the data is clocked in upon the rising and falling edges of the input clock, and the clock edge bit [Address 0x01, Bit 1] must be set accordingly.

PROGRESSIVE SCAN AT 27 MHZ (DUAL EDGE)

CrCb

10

INTERLACED TO

PROGRESSIVE

Y

27MHz

C[9:0]

10

Y[9:0] P_VSYNC,

3

P_HSYNC, P_BLANK

CLKIN_B

05067-027

Figure 51. Simultaneous PS and SD Input

ADV7320/ ADV7321

S_VSYNC,

3

S_HSYNC,

10YCrCb

10CrCb 10Y

3

S_BLANK

CLKIN_A S[9:0]

C[9:0] Y[9:0]

P_VSYNC, P_HSYNC, P_BLANK

CLKIN_B

05067-028

SDTV

DECODER

HDTV

DECODER

1080i

720p

1035i

27MHz

OR OR

74.25MHz

Figure 52. Simultaneous HD and SD Input

In simultaneous SD/HD input mode, if the two clock phases differ by less than 9.25 ns or more than 27.75 ns, the clock align bit [Address 0x01, Bit 3] must be set accordingly. If the application uses the same clock source for both SD and PS, the clock align bit must be set because the phase difference between both inputs is less than 9.25 ns.

Table 22 provides an overview of all possible input configurations. Figure 54, Figure 55, and Figure 56 show the possible conditions: Cb data on the rising edge, and Y data on the rising edge.

CLKIN_B

Y9–Y0

CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.

3FF 00 00 XY Y0 Y1Cr0

Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

CLKIN_B

Y9–Y0

CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.

3FF 00 00 XY Cb0 Cr0Y1

Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

CLKIN_B

PIXEL INPUT

DATA

WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.

3FF 00 00 XY Cb0 Y0 Y1Cr0

Figure 56. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

Cb0

05067-030

Y0

05067-031

05067-032

CLKIN_

CLKIN_B

t

< 9.25ns OR

DELAY

t

> 27.75ns

DELAY

Figure 53. Clock Phase with Two Input Clocks

05067-029

MPEG2

DECODER

YCrCb

INTERLACED

TO

PROGRESSIVE

27MHz OR 54MHz

YCrCb

10

3

ADV7320/ ADV7321

CLKIN_A

Y[9:0]

P_VSYNC, P_HSYNC, P_BLANK

05067-033

Figure 57. 10-Bit PS at 27 MHz or 54 MHz

Rev. 0 | Page 39 of 88

ADV7320/ADV7321

Table 22. Input Configurations

Input Format Total Bits Input Video Input Pins Subaddress Register Setting

ITU-R BT.656 (See Table 21)

PS Only

HDTV Only

HD RGB

ITU-R BT.656 and PS

ITU-R BT.656 and PS or HDTV

Y S9 to S2 (MSB = S9) 0x01 0x00 16 4:2:2 CrCb Y9 to Y2 (MSB = Y9) 0x48 0x08 Y S9 to S0 (MSB = S9) 0x01 0x00 20 4:2:2 CrCb Y9 to Y0 (MSB = Y9) 0x48 0x18

10 4:2:2 YCrCb Y9 to Y0 (MSB = Y9)

Y Y9 to Y2 (MSB = Y9) 0x01 0x10 16 4:2:2 CrCb C9 to C2 (MSB = C9) 0x13 0x40 Y Y9 to Y0 (MSB = Y9) 0x01 0x10 20 4:2:2 CrCb C9 to C0 (MSB = C9) 0x13 0x44

24 4:4:4

Y Y9 to Y2 (MSB = Y9) 0x01 0x10 Cb C9 to C2 (MSB = C9) Cr S9 to S2 (MSB = S9)

30 4:4:4

Y Y9 to Y0 (MSB = Y9) 0x01 0x10 Cb C9 to C0 (MSB = C9) Cr S9 to S0 (MSB = S9) Y Y9 to Y2 (MSB = Y9) 0x01 0x20 16 4:2:2 CrCb C9 to Y2 (MSB = C9) 0x13 0x40 Y Y9 to Y0 (MSB = Y9) 0x01 0x20 20 4:2:2 CrCb C9 to C0 (MSB = C9) 0x13 0x44

24 4:4:4

Y Y9 to Y2 (MSB = Y9) 0x01 0x20 Cb C9 to C2 (MSB = C9) Cr S9 to S2 (MSB = S9)

30 4:4:4

Y Y9 to Y0 (MSB = Y9) 0x01 0x20 Cb C9 to C0 (MSB = C9) Cr S9 to S0 (MSB = S9)

24 4:4:4

G Y9 to Y2 (MSB = Y9) 0x01 0x10 or 0x20 B C9 to C2 (MSB = C9) 0x13 0x00 R S9 to S2 (MSB = S9) 0x15 0x02

30 4:4:4

G Y9 to Y0 (MSB = Y9) 0x01 0x10 or 0x20 B C9 to C0 (MSB = C9) 0x13 0x04

R S9 to S0 (MSB = S9) 0x15 0x02 8 (SD) 4:2:2 YCrCb S9 to S2 (MSB = S9) 0x01 0x40 8 (PS) 4:2:2 YCrCb Y9 to Y2 (MSB = Y9)

10 (SD) 4:2:2 YCrCb S9 to S0 (MSB = S9) 0x01 0x40 10 (PS) 4:2:2 YCrCb Y9 to Y0 (MSB = Y9)

8 4:2:2 YCrCb S9 to S2 (MSB = S9) 0x01 0x30, 0x50, or 0x60 16 4:2:2

Y Y9 to Y2 (MSB = Y9) 0x13 0x40

CrCb C9 to C2 (MSB = C9) 0x48 0x00 10 4:2:2 YCrCb S9 to S0 (MSB = S9) 0x01 0x30, 0x50, or 0x60 20 4:2:2

Y Y9 to Y0 (MSB = Y9) 0x13 0x44

CrCb C9 to C0 (MSB = C9) 0x48 0x10

0x01 0x00 8 4:2:2 YCrCb S9 to S2 (MSB = S9) 0x48 0x00 0x01 0x00 10 4:2:2 YCrCb S9 to S0 (MSB = S9) 0x48 0x10

0x01 0x80 8 4:2:2 YCrCb Y9 to Y2 (MSB = Y9) 0x48 0x00 0x01 0x80 0x48 0x10 0x01 0x10 8 (27 MHz clock) 4:2:2 YCrCb Y9 to Y2 (MSB = Y9) 0x13 0x40 0x01 0x10 10 (27 MHz clock) 4:2:2 YCrCb Y9 to Y0 (MSB = Y9) 0x13 0x44 0x01 0x70 8 (54 MHz clock) 4:2:2 YCrCb Y9 to Y2 (MSB = Y9) 0x13 0x40 0x01 0x70 10 (54 MHz clock) 4:2:2 YCrCb Y9 to Y0 (MSB = Y9) 0x13 0x44

0x13 0x00

0x13 0x04

0x13 0x00

0x13 0x04

0x13 0x40 0x48 0x00

0x13 0x44 0x48 0x10

Rev. 0 | Page 40 of 88

ADV7320/ADV7321

FEATURES

OUTPUT CONFIGURATION

Table 23, Table 24, and Table 25 demonstrate what output signals are assigned to the DACs when the control bits are set accordingly.

Table 23. Output Configuration in SD Only Mode

RGB/YUV Output 0x02, Bit 5

0 0 0 CVBS Luma Chroma G B R 0 0 1 G B R CVBS Luma Chroma 0 1 0 G Luma Chroma CVBS B R 0 1 1 CVBS B R G Luma Chroma 1 0 0 CVBS Luma Chroma Y U V 1 0 1 Y U V CVBS Luma Chroma 1 1 0 Y Luma Chroma CVBS U V 1 1 1 CVBS U V Y Luma Chroma

Luma/Chroma Swap 0x44, Bit 7

0 Table as above 1 Table as above, but with all luma/chroma instances swapped

Table 24. Output Configuration in HD/PS Only Mode

HD/PS Input Format

YCrCb 4:2:2 0 0 0 N/A N/A N/A G B R YCrCb 4:2:2 0 0 1 N/A N/A N/A G R B YCrCb 4:2:2 0 1 0 N/A N/A N/A Y Pb Pr YCrCb 4:2:2 0 1 1 N/A N/A N/A Y Pr Pb YCrCb 4:4:4 0 0 0 N/A N/A N/A G B R YCrCb 4:4:4 0 0 1 N/A N/A N/A G R B YCrCb 4:4:4 0 1 0 N/A N/A N/A Y Pb Pr YCrCb 4:4:4 0 1 1 N/A N/A N/A Y Pr Pb RGB 4:4:4 1 0 0 N/A N/A N/A G B R RGB 4:4:4 1 0 1 N/A N/A N/A G R B RGB 4:4:4 1 1 0 N/A N/A N/A G B R RGB 4:4:4 1 1 1 N/A N/A N/A G R B

HD/PS RGB Input 0x15, Bit 1

Table 25. Output Configuration in Simultaneous SD and HD/PS Only Mode

Input Formats

ITU-R.BT656 and HD YCrCb in 4:2:2

SD DAC Output 1 0x42, Bit 2

RGB/YPrPb Output 0x02, Bit 5

0 0 CVBS Luma Chroma G B R

0 1 CVBS Luma Chroma G R B

1 0 CVBS Luma Chroma Y Pb Pr

1 1 CVBS Luma Chroma Y Pr Pb

SD DAC Output 2 0x42, Bit 1

HD/PS Color Swap 0x15, Bit 3 DAC A DAC B DAC C DAC D DAC E DAC F

DAC A DAC B DAC C DAC D DAC E DAC F

Rev. 0 | Page 41 of 88

ADV7320/ADV7321

S

HD ASYNC TIMING MODE

[Subaddress 0x10, Bits 3 and 2]

For any input data that does not conform to the standards selectable in input mode, Subaddress 0x10, asynchronous timing mode can be used to interface to the ADV7320/ADV7321. Timing control signals for

HSYNC

,

VSYNC

be programmed by the user. Macrovision and programmable oversampling rates are not available in async timing mode.

Table 26. Async Timing Mode Truth Table

P_HSYNC

1 → 0 0

0 → 1

P_VSYNC

0 0 or 1 50% point of falling edge of trilevel horizontal sync signal a 0 → 1

0 or 1 0 50% point of falling edge of trilevel horizontal sync signal c 1 0 or 1 1 0 or 1

P_BLANK

0 or 1 25% point of rising edge of trilevel horizontal sync signal b

0 → 1 1 → 0

1

When async timing mode is enabled,

CLK

P_HSYNC

P_VSYNC

P_BLANK

Reference

, and

BLANK

must

50% start of active video d 50% end of active video e

, Pin 25, becomes an active high input.

In async mode, the PLL must be turned off [Subaddress 0x00, Bit 1 = 1]. Register 0x10 should be programmed to 0x01.

Figure 58 and Figure 59 show examples of how to program the ADV7320/ADV7321 to accept a high definition standard other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R BT.1358.

Table 26 must be followed when programming the control signals in async timing mode. For standards that do not require a trisync level,

P_BLANK

must be tied low at all times.

Reference in Figure 58 and Figure 59

P_BLANK

is set to active low at Address 0x10, Bit 6.

PROGRAMMABLE INPUT TIMING

P_BLANK

SET ADDRESS 0x14,

BIT 3 = 1

CLK

P_HSYNC

P_VSYNC

P_BLANK

ET ADDRESS 0x14

BIT 3 = 1

ANALOG OUTPUT

HORIZONTAL SYNC

81 66 66 243 1920

ACTIVE VIDEO

Figure 58. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility

HORIZONTAL SYNC

ACTIVE VIDEO

ANALOG OUTPUT

edcba

05067-034

0

1

edcba

Figure 59. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal

Rev. 0 | Page 42 of 88

05067-035

ADV7320/ADV7321

HD TIMING RESET

A timing reset is achieved by toggling the HD timing reset control bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal and vertical counters remain reset. When this bit is set back to 0, the internal counters resume counting.

The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the HD timing counters only.

SD REAL-TIME CONTROL, SUBCARRIER RESET, AND TIMING RESET

[Subaddress 0x44, Bits 2 and 1]

Together with the RTC_SCR_TR pin and SD Mode Register 3 [Address 0x44, Bits 1 and 2], the ADV7320/ADV7321 can be used in (a) timing reset mode, (b) subcarrier phase reset mode, or (c) RTC mode.

a. A timing reset is achieved in a low-to-high transition

on the RTC_SCR_TR pin (Pin 31). In this state, the horizontal and vertical counters remain reset. Upon releasing this pin (set to low), the internal counters resume counting, starting with Field 1, and the subcarrier phase is reset.

The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the SD timing counters only.

b. In subcarrier phase reset, a low-to-high transition on

the RTC_SCR_TR pin (Pin 31) resets the subcarrier phase to zero on the field following the subcarrier phase reset when the SD RTC/TR/SCR control bits at Address 0x44 are set to 01.

This reset signal must be held high for a minimum of one clock cycle.

Because the field counter is not reset, it is recommended that the reset signal is applied in Field 7 (PAL) or Field 3 (NTSC). The reset of the phase will then occur on the next field, i.e., Field 1, lined up correctly with the internal counters. The field count register at Address 0x7B can be used to identify the number of the active field.

c. In RTC mode, the ADV7320/ADV7321 can be used to

lock to an external video source. The real-time control mode allows the ADV7320/ADV7321 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device, such as an ADV7183A video decoder (see Figure 62), that outputs a digital data stream in the RTC format, the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. Write 0x00 into all four subcarrier frequency registers when this mode is used.

DISPLAY

307 310

NO TIMING RESET APPLIED

DISPLAY

START OF FIELD 1

307 1234567 21

TIMING RESET APPLIED

START OF FIELD 4 OR 8 F

313 320

PHASE = FIELD 1

F

SC

Figure 60. Timing Reset Timing Diagram

PHASE = FIELD 4 OR 8

SC

TIMING RESET PULSE

05067-036

Rev. 0 | Page 43 of 88

ADV7320/ADV7321

DISPLAY

307 310 313 320

NO FSC RESET APPLIED

DISPLAY

307 310 313 320

RESET APPLIED

F

SC

START OF FIELD 4 OR 8

F

PHASE = FIELD 4 OR 8

SC

F

PHASE = FIELD 1

SC

F

RESET PULSE

SC

05067-037

Figure 61. Subcarrier Reset Timing Diagram

ADV7320/ ADV7321

CLKIN_A

LCC1

COMPOSITE

VIDEO

H/L TRANSITION

COUNT START

RTC

TIME SLOT 01

NOTES

1

i.e., VCR OR CABLE

2

FSC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7320/ADV7321 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7320/ADV7321.

3

SEQUENCE BIT PAL: 0 = LI NE NORMAL, 1 = LI NE I N VE R T E D NTSC: 0 = NO CHANGE

4

RESET ADV7320/ADV7321 DDS

5

SELECTED BY REGISTER ADDRESS 0x01 BIT 7



128

1

ADV7183A

VIDEO

DECODER

14 BITS

SUBCARRIER

PHASE

LOW

13 0

GLL

P19–P10

RESERVED

142119



4 BITS

RTC_SCR_TR

Y9–Y0/S9–S0

F

SC

VALID

SAMPLE

DAC A DAC B DAC C DAC D

5

DAC E DAC F

PLL INCREMENT

INVALID SAMPLE

SEQUENCE

BIT

2

8/LINE

LOCKED

CLOCK

0

3

6768

5 BITS

RESERVED

RESET

4

BIT

RESERVED

05067-038

Figure 62. RTC Timing and Connections

Rev. 0 | Page 44 of 88

ADV7320/ADV7321

RESET SEQUENCE

A reset is activated with a high-to-low transition on the pin (Pin 33) according to the timing specifications, and the

ADV7320/ADV7321 reverts to the default output configuration. Figure 63 illustrates the

timing sequence.

RESET

SD VCR FF/RW SYNC

[Subaddress 0x42, Bit 5]

In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, i.e., in fast forward or rewind modes.

In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields are reached; in rewind mode, this sync

RESET

DACs

A, B, C

XXXXXX

signal usually occurs after the total number of lines/fields are reached. Conventionally this means that the output video will have corrupted field signals, because one signal is generated by the incoming video and another is generated when the internal lines/field counters reach the end of a field.

When the VCR FF/RW sync control is enabled [Subaddress 0x42, Bit 5], the lines/fields counters are updated according to the incoming

incoming

VSYNC VSYNC

signal, and the analog output matches the signal.

This control is available in all slave timing modes except Slave Mode 0.

OFF

VALID VIDEO

DIGITAL TIMING

PIXEL DATA

VALID

XXXXXX

DIGITAL TIMING SIGNALS SUPPRESSED

Figure 63.

RESET

Timing Sequence

TIMING ACTIVE

05067-039

Rev. 0 | Page 45 of 88

ADV7320/ADV7321

VERTICAL BLANKING INTERVAL

The ADV7320/ADV7321 accepts input data that contains VBI data (such as CGMS, WSS, VITS) in SD and HD modes.

For the SMPTE 293M (525p) standard, VBI data can be inserted on Lines 13 to 42 of each frame, or on Lines 6 to 43 for the ITU-R BT.1358 (625p) standard.

This data can be present on Lines 10 to 20 for SD NTSC and on Lines 7 to 22 for PAL.

If VBI is disabled [Address 0x11, Bit 4 for HD; Address 0x43, Bit 4 for SD], VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave modes.

In Slave Mode 0, if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten. It is possible to use VBI in this timing mode as well.

In Slave Mode 1 or 2, the

BLANK

[Address 0x4A, Bit 3] to allow VBI data to pass through the ADV7320/ADV7321. Otherwise, the ADV7320/ADV7321 automatically blanks the VBI to standard.

If CGMS is enabled and VBI is disabled, the CGMS data will nevertheless be available at the output.

See Appendix 1—Copy Generation Management System.

control bit must be enabled

SUBCARRIER FREQUENCY REGISTERS

[Subaddresses 0x4C to 0x4F]

Four 8-bit registers are used to set up the subcarrier frequency. The value of these registers is calculated using the equation

RegisterFrequencySubcarrier

where the sum is rounded to the nearest integer.

For example, in NTSC mode

where:

Subcarrier Register Value = 0x21F07C1F

SD F

Register 0: 0x1F

SC

SD F

Register 1: 0x7C

SC

SD F

Register 2: 0xF0

SC

Register 3: 0x21

SD F

SC

See the MPU Port Description section for more details on accessing the subcarrier frequency registers.

Programming the FSC

The subcarrier register value is divided into 4 FSC registers as shown above. To load the value into the encoder, users must write to the F

registers in sequence, starting with FSC0. The

SC

value is not loaded until the F

=

linevideooneinperiodssubcarrierofNumber

32

227×

linevideooneincyclesclkMHzofNumber

5.227

⎛

⎞

=ValueRegisterSubcarrier

⎜

1716

⎝

4 write is complete.

SC

32

569408543

=×

2

⎟ ⎠

Note that the ADV7320/ADV7321 power-up value for F 0x1E. For precise NTSC F

, write 0x1F to this register.

SC

0 is

Rev. 0 | Page 46 of 88

ADV7320/ADV7321

SQUARE PIXEL TIMING MODE

[Address 0x42, Bit 4]

In square pixel mode, the following timing diagrams apply.

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

HSYNC

FIELD

BLANK

PIXEL DATA

EAV CODE

FF0000X

C

Y

r

4 CLOCK

END OF ACTIVE

VIDEO LINE

PAL = 44 CLOCK CYCLES

NTSC = 44 CLOCK CYCLES

8

10801

0

Y

0

FF00FFABABA

ANCILLARY DATA

272 CLOCK

344 CLOCK

B

(HANC)

Figure 64. EAV/SAV Embedded Timing

Figure 65. Active Pixel Timing

801

SAV CODE

8 0

0

10FF0

XYC

0

4 CLOCK

START OF ACTIVE

VIDEO LINE

PAL = 308 CLOCK CYCLES

NTSC = 236 CLOCK CYCLES

Y

b

1280 CLOCK

1536 CLOCK

Cb Y

Y

r

b

Y

r

Cr Y

Y

b

05067-040

05067-041

C

Rev. 0 | Page 47 of 88

ADV7320/ADV7321

FILTERS

Table 27 shows an overview of the programmable filters available on the ADV7320/ADV7321.

Table 27. Selectable Filters

Filter Subaddress

SD Luma LPF NTSC 0x40 SD Luma LPF PAL 0x40 SD Luma Notch NTSC 0x40 SD Luma Notch PAL 0x40 SD Luma SSAF 0x40 SD Luma CIF 0x40 SD Luma QCIF 0x40 SD Chroma 0.65 MHz 0x40 SD Chroma 1.0 MHz 0x40 SD Chroma 1.3 MHz 0x40 SD Chroma 2.0 MHz 0x40 SD Chroma 3.0 MHz 0x40 SD Chroma CIF 0x40 SD Chroma QCIF 0x40 SD UV SSAF 0x42 HD Chroma Input 0x13 HD Sinc Filter 0x13 HD Chroma SSAF 0x13

SD Internal Filter Response

[Subaddress 0x40 [7:2]; Subaddress 0x42, Bit 0]

The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. The UV filter supports several different frequency responses, including six low-pass responses, a CIF response, and a QCIF response, as shown in Figure 35 and Figure 36.

If SD SSAF gain is enabled, there are 12 response options in the range −4 dB to +4 dB [Subaddress 0x47, Bit 4]. Choose the desired response by programming the correct value via the I [Subaddress 0x62]. The variation of frequency responses are shown in Figure 32 and Figure 33.

In addition to the chroma filters listed in Table 27, the ADV7320/ADV7321 contains an SSAF filter specifically designed for the color difference component outputs, U and V. This filter has a cutoff frequency of about 2.7 MHz and a gain of

2

C

–40 dB at 3.8 MHz, as shown in Figure 66. This filter can be controlled with Address 0x42, Bit 0.

EXTENDED UV FILTER MODE

0

–10

–20

–30

GAIN (dB)

–40

–50

–60

FREQUENCY (MHz)

Figure 66. UV SSAF Filter

05067-044

6543210

If this filter is disabled, one of the chroma filters shown in Table 28 can be selected and used for the CVBS or luma/ chroma signal.

Table 28. Internal Filter Specifications

Filter

Pass-Band Ripple1 (dB)

3 dB Bandwidth (MHz)

Luma LPF NTSC 0.16 4.24 Luma LPF PAL 0.1 4.81 Luma Notch NTSC 0.09 2.3/4.9/6.6 Luma Notch PAL 0.1 3.1/5.6/6.4 Luma SSAF 0.04 6.45 Luma CIF 0.127 3.02 Luma QCIF Monotonic 1.5 Chroma 0.65 MHz Monotonic 0.65 Chroma 1.0 MHz Monotonic 1 Chroma 1.3 MHz 0.09 1.395 Chroma 2.0 MHz 0.048 2.2 Chroma 3.0 MHz Monotonic 3.2 Chroma CIF Monotonic 0.65 Chroma QCIF Monotonic 0.5

1

Pass-band ripple is the maximum fluctuation from the 0 dB response in the

pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the −3 dB points.

2

3 dB bandwidth refers to the −3 dB cutoff frequency.

2

Rev. 0 | Page 48 of 88

ADV7320/ADV7321

PS/HD Sinc Filter

[Subaddress 0x13, Bit 3]

0.5

0.4

0.3

0.2

0.1

0

GAIN (dB)

–0.1

–0.2

–0.3

–0.4

05067-042

3050

05067-043

3050

GAIN (dB)

–0.5

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

10 15 20 25

FREQUENCY (MHz)

Figure 67. HD Sinc Filter Enabled

0

10 15 20 25

FREQUENCY (MHz)

Figure 68. HD Sinc Filter Disabled

COLOR CONTROLS AND RGB MATRIX

HD Y Level, HD Cr Level, HD Cb Level

[Subaddresses 0x16 to 0x18]

Three 8-bit registers at Addresses 0x16, 0x17, and 0x18 are used to program the output color of the internal HD test pattern generator, be it the lines of the cross hatch pattern or the uniform field test pattern. They are not functional as color controls for external pixel data input. For this purpose the RGB matrix is used.

The values for Y and the color difference signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard.

Table 29 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA 770.2.

Table 29. Sample Color Values for EIA 770.2 Output Standard Selection

Sample Color Y Value Cr Value Cb Value

White 235 (EB) 128 (80) 128 (80) Black 16 (10) 128 (80) 128 (80) Red 81 (51) 240 (F0) 90 (5A) Green 145 (91) 34 (22) 54 (36) Blue 41 (29) 110 (6E) 240 (F0) Yellow 210 (D2) 146 (92) 16 (10) Cyan 170 (AA) 16 (10) 166 (A6) Magenta 106 (6A) 222 (DE) 202 (CA)

RGB Matrix

[Subaddresses 0x03 to 0x09]

The internal RGB matrix automatically performs all YCrCb to RGB scaling according to the input standard programmed in the device as selected by input mode Register 0x01 [6:4]. Table 30 shows the options available in this Matrix.

Note that it is not possible to do a color space conversion from RGB-in to YPrPb-out. Also, it is not possible to input SD RGB.

Table 30. Matrix Conversion Options

HDTV/SD/PS

Reg 0x15, Bit 1

Input Output

Reg 0x02,Bit 5 (YUV/RGB OUT)

(RGB IN/YCrCb IN, PS/HD Only)

YCrCb YPrPb 1 0 YCrCb RGB 0 0 RGB RGB 0 1

Manual RGB Matrix Adjust Feature

Normally, there is no need to enable this feature in Register 0x02, Bit 3, because the RGB matrix automatically performs color space conversion depending on the input mode chosen (SD/PS, HD) and the polarity of RGB/YPrPb output in Register 0x02, Bit 5 (see Table 30). For this reason, the manual RGB matrix adjust feature is disabled by default. However, For HDTV YCrCb-to-RGB conversion, the RGB matrix must be enabled to invoke the correct coefficients for this color space. The coefficients do not need to be adjusted.

The manual RGB matrix adjust feature provides custom coefficient manipulation and is used in progressive scan and high definition modes only.

When the manual RGB matrix adjust feature is enabled, the default values in Registers 0x05 to 0x09 are correct for HDTV color space only. The color components are converted according to the 1080i and 720p standards (SMPTE 274M, SMPTE 296M):

Rev. 0 | Page 49 of 88

ADV7320/ADV7321

R = Y + 1.575Pr

If YPrPb output is selected, the following equations are used:

= Y − 0.468Pr − 0.187Pb

G

= Y + 1.855Pb

B

This is reflected in the preprogrammed values for GY = 0x13B, GU = 0x3B, GV = 0x93, BU = 0x248, and RV = 0x1F0.

If RGB matrix is enabled and another input standard (such as SD or PS) is used, the scale values for GY, GU, GV, BU, and RV must be adjusted according to this input standard color space. The user should consider that the color component conversion might use different scale values. For example, SMPTE 293M uses the following conversion:

R = Y + 1.402Pr

= Y – 0.714Pr – 0.344Pb

G

= Y + 1.773Pb

B

The manual RGB matrix adjust feature can be used to control the HD output levels in cases where the video output does not conform to the standard due to altering the DAC output stages such as termination resistors. The programmable RGB matrix is used for external HD/PS data and is not functional when internal test patterns are enabled. To adjust Registers 0x05 to 0x09, the manual RGB matrix adjust must be enabled [Register 0x02, Bit 3 =1].

Programming the RGB Matrix

If custom manipulation of coefficients is required, enable the RGB matrix in Address 0x02, Bit 3, set the output to RGB [Address 0x02, Bit 5], and disable sync on PrPb (default) [Address 0x15, Bit 2]. Enabling sync on RGB is optional [Address 0x02, Bit 4].

Y = GY × Y

U

= BU × Pb

= RV × Pr

V

Upon power-up, the RGB matrix is programmed with the default values in Table 31.

Table 31. RGB Matrix Default Values

Address Default

0x03 0x03 0x04 0xF0 0x05 0x4E 0x06 0x0E 0x07 0x24 0x08 0x92 0x09 0x7C

When the manual RGB matrix adjust feature is not enabled, the ADV7320/ADV7321 automatically scales YCrCb inputs to all standards supported by this part as selected by the input mode Register 0x01 [6:4].

SD Luma and Color Control

[Subaddresses 0x5C, 0x5D, 0x5E, 0x5F]

SD Y Scale, SD Cr Scale, and SD Cb Scale are three 10-bit-wide control registers that scale the Y, Cb, and Cr output levels.

Each of these registers represents the value required to scale the Cb or Cr level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 of its initial level. The value of these 10 bits is calculated using the following equation:

Y, Cr, or Cb Scalar Value = Scale Factor × 512

GY at Addresses 0x03 and 0x05 controls the green signal output levels. BU at Addresses 0x04 and 0x08 control the blue signal output levels, and RV at Addresses 0x04 and 0x09 control the red signal output levels. To control YPrPb output levels, enable the YUV output [Address 0x02, Bit 5]. In this case GY [Address 0x05; Address 0x03, Bits 0 and 1] is used for the Y output, RV [Address 0x09; Address 0x04, Bits 0 and 1] is used for the Pr output, and BU [Address 0x08; Address 0x04, Bits 2 and 3] is used for the Pb output.

If RGB output is selected, the RGB matrix scaler uses the following equations:

G = GY × Y + GU × Pb + GV × Pr

= GY × Y + BU × Pb

B

= GY × Y + RV × Pr

R

Rev. 0 | Page 50 of 88

For example,

Scale Factor = 1.18

Y, Cb, or Cr Scale Value = 1.18 × 512 = 665.6

Y, Cb, or Cr Scale Value = 665 (rounded to the nearest

)

integer

Y, Cb, or Cr Scale Value

Address 0x5C, SD LSB Register = 0x15 Address 0x5D, SD Y Scale Register = 0xA6 Address 0x5E, SD Cb Scale Register = 0xA6 Address 0x5F, SD Cr Scale Register = 0xA6

Note that this feature affects all interlaced output signals, i.e., CVBS, Y-C, YPrPb, and RGB.

= 1010 0110 01b

ADV7320/ADV7321

SD Hue Adjust Value

[Subaddress 0x60]

The hue adjust value is used to adjust the hue on the composite and chroma outputs.

These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7320/ADV7321 provides a range of ±22.5° increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits (respectively) of adjustment attainable.

Hue Adjust (°) = 0.17578125° (

HCR

− 128) for positive hue

d

adjust value.

For example, to adjust the hue by +4°, write 0x97 to the hue adjust value register:

4

⎛ ⎜

17578125.0

⎝

⎞ ⎟ ⎠

97x0105128

==+

d .

where the sum is rounded to the nearest integer.

To adjust the hue by −4°, write 0x69 to the hue adjust value register:

−

4

⎛ ⎜

17578125.0

⎝

⎞ ⎟ ⎠

69x0105128

==+

d

For example,

1. To add +20 IRE brightness level to an NTSC signal with pedestal, write 0x28 to Address 0x61, SD brightness.

SD Brightness Value] =

0x[

IRE Value × 2.015631] =

0x[20 × 2.015631] = 0x[40.31262] = 0x28

2. To add –7 IRE brightness level to a PAL signal, write 0x72 to Address 0x61, SD brightness.

[

IRE Value| × 2.075631

[7 × 2.015631] = [14.109417] = 0001110

b

[0001110] into twos complement = [1110010]b = 0x72

Table 32. Brightness Control Values

Setup Level In NTSC with Pedestal

22.5 IRE 15 IRE 15 IRE 0x1E

15 IRE 7.5 IRE 7.5 IRE 0x0F

7.5 IRE 0 IRE 0 IRE 0x00

0 IRE –7.5 IRE –7.5 IRE 0x71

Setup Level In NTSC No Pedestal

1

Setup Level In PAL

SD Brightness

1

Values in the range of 0x3F to 0x44 might result in an invalid output

signal.

where the sum is rounded to the nearest integer.

SD Brightness Control

[Subaddress 0x61]

The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the scaled Y data. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and for PAL, the setup can vary from −7.5 IRE to +15 IRE.

The brightness control register is an 8-bit register. Seven bits of this 8-bit register are used to control the brightness level, which can be a positive or negative value.

Rev. 0 | Page 51 of 88

ADV7320/ADV7321

SD Brightness Detect

[Subaddress 0x7A]

The ADV7320/ADV7321 allow monitoring the brightness level of the incoming video data. Brightness detect is a read-only register.

Double Buffering

[Subaddress 0x13, Bit 7; Subaddress 0x48, Bit 2]

Double buffered registers are updated once per field upon the falling edge of the Vsync signal. Double buffering improves the overall performance because modifications to register settings will not be made during active video, but take effect upon the start of the active video.

NTSC WITHOUT PEDESTAL

100 IRE

Double buffering can be activated on the following HD registers: HD gamma A and gamma B curves and HD CGMS registers.

Double buffering can be activated on the following SD registers: SD gamma A and gamma B curves, SD Y scale, SD U scale, SD V scale, SD brightness, SD closed captioning, and SD Macrovision Bits 5 to 0.

+7.5 IRE

0 IRE

NO SETUP

VALUE ADDED

Figure 69. Examples of Brightness Control Values

POSITIVE SETUP

VALUE ADDED

NEGATIVE SETUP

VALUE ADDED

–7.5 IRE

05067-069

Rev. 0 | Page 52 of 88

ADV7320/ADV7321

L

(

PROGRAMMABLE DAC GAIN CONTROL

DACs A, B, and C are controlled by REG 0A.

DACs D, E, and F are controlled by REG 0B.

2

The I

C control registers will adjust the output signal gain up or

down from its absolute level.

CASE A

GAIN PROGRAMMED IN DAC OUTPUT LEVE REGISTERS, SUBADDRESS 0x0A, 0x0B

700mV

300mV

CASE B

700mV

NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0A, 0x0B

Table 33. DAC Gain Control

DAC Reg 0x0A or 0x0B

Current

(mA) % Gain Note

0100 0000 (0x40) 4.658 7.5000% 0011 1111 (0x3F) 4.653 7.3820% 0011 1110 (0x3E) 4.648 7.3640%

... ... ...

0000 0010 (0x02) 4.43 0.0360% 0000 0001 (0x01) 4.38 0.0180% 0000 0000 (0x00) 4.33 0.0000%

1111 1111 (0xFF) 4.25 −0.0180% 1111 1110 (0xFE) 4.23 −0.0360%

... ... ...

1100 0010 (0xC2) 4.018 −7.3640% 1100 0001 (0xC1) 4.013 −7.3820% 1100 0000 (0xC0) 4.008 −7.5000%

GAMMA CORRECTION

[Subaddresses 0x24 to 0x37 for HD, Subaddresses 0x66 to 0x79 for SD]

2

C Reset Value,

(I Nominal)

300mV

Figure 70. Programmable DAC Gain—Positive and Negative Gain

In case A, the video output signal is gained. The absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. The overall gain of the signal is increased from the reference signal.

In case B, the video output signal is reduced. The absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. The overall gain of the signal is reduced from the reference signal.

The range of this feature is specified for ±7.5% of the nominal output from the DACs. For example, if the output current of the DAC is 4.33 mA, the DAC tune feature can change this output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).

The reset value of the vid_out_ctrl registers is 0x00; therefore, nominal DAC current is output. The following table is an example of how the output current of the DACs varies for a nominal 4.33 mA output current.

05067-070

Gamma correction is available for SD and HD video. For each standard, there are twenty 8-bit-wide registers. They are used to program the Gamma Correction Curves A and B. HD Gamma Curve A is programmed at Addresses 0x24 to 0x2D, and HD Gamma Curve B is programmed at 0x2E to 0x7. SD Gamma Curve A is programmed at Addresses 0x66 to 0x6F, and SD Gamma Curve B is programmed at Addresses 0x70 to 0x79.

Generally gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used.

Gamma correction uses the function

γ

)

=

SignalSignal

OUT

where γ = gamma power factor.

IN

Gamma correction is performed on the luma data only. The user may choose either of two curves, Curve A or Curve B. At any one time, only one of these curves can be used.

The response of the curve is programmed at 10 predefined locations. In changing the values at these locations, the gamma curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed.

Rev. 0 | Page 53 of 88

ADV7320/ADV7321

For the length of 16 to 240, the gamma correction curve has to be calculated as follows:

y = xγ

where:

y = gamma corrected output x = linear input signal

γ = gamma power factor

To program the gamma correction registers, calculate the seven values for

y using the following formula:

x

⎡

=

y

n

⎢ ⎣

⎤

)16(

−n

⎥

)16240(

−

⎦

16)16240(

+−×γ

where:

= Value for x along x axis at points

x

(n − 16)

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224

= value for y along the y axis, which must be written into the

y

n

gamma correction register

For example,

= [(8/224)0.5 × 224] + 16 = 58

y

24

= [(16/224)0.5 × 224] + 16 = 76

y

32

= [(32/224)0.5 × 224] + 16 = 101

y

48

= [(48/224)0.5 × 224] + 16 = 120

y

64

= [(64/224)0.5 × 224] + 16 = 136

y

80

= [(80/224)0.5 × 224] + 16 = 150

y

96

= [(112/224)0.5 × 224] + 16 = 174

y

128

= [(144/224)0.5 × 224] + 16 = 195

y

160

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

300

250

200

150

100

GAMMA CORRECTED AMPLITUDE

50

0

SIGNAL INPUT

0

50 100 150 200 250

SIGNAL OUTPUT

0.5

LOCATION

Figure 71. Signal Input (Ramp) and Signal Output for Gamma 0.5

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

300

250

200

150

100

GAMMA CORRECTED AMPLITUDE

50

0

VARIOUS GAMMA VALUES

0.3

0.5

T

U

P

1.5

N

I

L

A

N

G

I

S

50 100 150 200 250

1.8

LOCATION

Figure 72. Signal Input (Ramp) and Selectable Output Curves

05067-071

05067-072

= [(176/224)0.5 × 224] + 16 = 214

y

192

= [(208/224)0.5 × 224] + 16 = 232

y

224

where the sum of each equation is rounded to the nearest integer.

The gamma curves in Figure 71 and Figure 72 are examples only; any user-defined curve is acceptable in the range of 16 to 240.

Rev. 0 | Page 54 of 88

ADV7320/ADV7321

S

HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS

[Subaddresses 0x20, 0x38 to 0x3D]

There are three filter modes available on the ADV7320/ ADV7321: sharpness filter mode and two adaptive filter modes.

HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges shown in Figure 73, the HD sharpness filter must be enabled and the HD adaptive filter enable must be disabled.

To select one of the 256 individual responses, the corresponding gain values, which range from –8 to +7, for each filter must be programmed into the HD sharpness filter gain register at Address 0x20.

HD Adaptive Filter Mode

The HD adaptive filter threshold A, B, and C registers, the HD adaptive filter gain 1, 2, and 3 registers, and the HD sharpness gain register are used in adaptive filter mode. To activate the adaptive filter control, the HD sharpness filter and the HD adaptive filter must be enabled.

The derivative of the incoming signal is compared to the three programmable threshold values: HD Adaptive Filter Threshold A, B, and C. The recommended threshold range is from 16 to 235, although any value in the range of 0 to 255 can be used.

The edges can then be attenuated with the settings in HD adaptive filter gain 1, 2, and 3 registers, and HD sharpness filter gain register.

According to the settings of the HD adaptive filter mode control, there are two adaptive filter modes available:

Mode A is used when adaptive filter mode is set to 0.

1. In this case, Filter B (LPF) will be used in the adaptive filter block. Also, only the programmed values for Gain B in the HD sharpness filter gain and HD Adaptive Filter Gain 1, 2, and 3 are applied when needed. The Gain A values are fixed and cannot be changed.

Mode B is used when adaptive filter mode is set to 1.

2. In this mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the HD sharpness filter gain and HD Adaptive Filter Gain 1, 2, and 3 become active when needed.

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

FREQUENCY (MHz)

FILTER A RESPONSE (Gain Ka)

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5

Figure 73. Sharpness and Adaptive Filter Control Block

FREQUENCY (MHz)

FILTER B RESPONSE (Gain Kb)

1.6

1.5

1.4

1.3

1.2

1.1

MAGNITUDE RESPONSE (Linear Scale)

1.0 0

24

FREQUENCY RESPONSE IN SHARPNESS

FILTER MODE WITH Ka = 3 AND Kb = 7

6

FREQUENCY (MHz)

8

10 12

05067-073

INPUT

IGNAL:

STEP

1.5

1.4

1.3

1.2

1.1



1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5

Rev. 0 | Page 55 of 88

ADV7320/ADV7321

HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES

HD Sharpness Filter Application

The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in Figure 74. Input data was generated by an external signal source.

Table 34. Sharpness Control

Address Register Setting Reference

0x00 0xFC 0x01 0x10 0x02 0x20 0x10 0x00 0x11 0x81 0x20 0x00 a 0x20 0x08 b 0x20 0x04 c 0x20 0x40 d 0x20 0x80 e 0x20 0x22 f

1

See Figure 74.

1

d

e

f

05067-074

R2

R4

1

CH1 500mV M 4.00µs CH1

REF A 500mV 4.00µs 1

Figure 74. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Values

9.99978ms

ALL FIELDS

a

1

b

R1

c

R2

CH1 500mV M 4.00µs CH1

REF A 500mV 4.00µs 1

9.99978ms

ALL FIELDS

Rev. 0 | Page 56 of 88

ADV7320/ADV7321

Adaptive Filter Control Application

Figure 75 and Figure 76 show typical signals to be processed by the adaptive filter control block.

When changing the adaptive filter mode to Mode B [Address 0x15, Bit 6], the output shown in Figure 77 can be obtained.

05067-075

Figure 75. Input Signal to Adaptive Filter Control

05067-076

Figure 76. Output Signal after Adaptive Filter Control

The register settings in Table 35 were used to obtain the results shown in Figure 76, i.e., to remove the ringing on the Y signal. Input data was generated by an external signal source.

Table 35. Register Settings for Figure 76

Address Register Setting

0x00 0xFC 0x01 0x38 0x02 0x20 0x10 0x00 0x11 0x81 0x15 0x80 0x20 0x00 0x38 0xAC 0x39 0x9A 0x3A 0x88 0x3B 0x28 0x3C 0x3F 0x3D 0x64

05067-077

Figure 77. Output Signal from Adaptive Filter Control

SD DIGITAL NOISE REDUCTION

[Subaddresses 0x63, 0x64, 0x65]

DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). There are two DNR modes available: DNR mode and DNR sharpness mode.

In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal will be subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) will be added to the original signal to boost high frequency components and sharpen the video image.

In MPEG systems, it is common to process the video information in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels × 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area).

It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset.

The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing.

Rev. 0 | Page 57 of 88

ADV7320/ADV7321

Y

A

Y DATA

INPUT

DNR MODE

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

< THRESHOLD?

FILTER OUTPUT

> THRESHOLD

GAIN

SUBTRACTSIGNAL IN THRESHOLD RANGE FROM ORIGINALSIGNAL

–

+

DNR OUT

In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal.

APPLY BORDER CORING GAIN

OFFSET CAUSED BY VARIATIONS IN INPUT TIMING

DNR27 – DNR24 = 0x01

APPLY DATA CORING GAIN

OXXXXXXOOXXXXXXO

Figure 79. DNR Offset Control

05067-079

DAT INPUT

DNR SHARPNESS MODE

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

> THRESHOLD?

FILTER OUTPUT < THRESHOLD

ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL

+

DNR OUT

Figure 78. DNR Block Diagram

CORING GAIN BORDER

[Address 0x63, Bits 3 to 0]

These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal.

CORING GAIN DATA

[Address 0x63, Bits 7 to 4]

These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal.

05067-078

DNR THRESHOLD

[Address 0x64, Bits 5 to 0]

These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value.

BORDER AREA

[Address 0x64, Bit 6]

When this bit is set to Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.

720 × 485 PIXELS

(NTSC)

8 × 8 PIXEL BLOCK

Figure 80. DNR Border Area

2-PIXEL

BORDER

8 × 8 PIXEL BLOCK

DATA

05067-080

BLOCK SIZE CONTROL

[Address 0x64, Bit 7]

This bit is used to select the size of the data blocks to be processed. Setting the block size control function to Logic 1 defines a 16 pixel × 16 pixel data block, and Logic 0 defines an 8 pixel × 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz.

DNR INPUT SELECT CONTROL

[Address 0x65, Bits 2 to 0]

Three bits are assigned to select the filter, which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that will be DNR processed. Figure 81 shows the filter responses selectable with this control.

Rev. 0 | Page 58 of 88

ADV7320/ADV7321

1.0

0.8

0.6

FILTER D

FILTER C

original signal, since this data is assumed to be valid data and not noise. The overall effect is that the signal will be boosted (similar to using Extended SSAF filter).

BLOCK OFFSET CONTROL

[Address 0x65, Bits 7 to 4]

MAGNITUDE

0.4

0.2

0

1

0

FILTER B

FILTER A

23

FREQUENCY (Hz)

Figure 81. DNR Input Select

45

05067-081

6

DNR MODE CONTROL

[Address 0x65, Bit 4]

This bit controls the DNR mode selected. Logic 0 selects DNR mode; Logic 1 selects DNR sharpness mode.

DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal.

In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1.

When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the

LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED

100 IRE

0 IRE

Figure 82. Example of Active Video Edge Functionality

Four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.

SD ACTIVE VIDEO EDGE

[Subaddress 0x42, Bit 7]

When the active video edge feature is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. The scaling factors are ×1/8, ×1/2, and ×7/8. All other active video passes through unprocessed.

SAV/EAV STEP EDGE CONTROL

The ADV7320/ADV7321 have the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing.

An algorithm monitors SAV and EAV and determines when the edges are rising or falling too fast. The result is reduced ringing at the start and end of active video for fast transitions. Subaddress 0x42, Bit 7 = 1, enables this feature.

LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED

100 IRE

87.5 IRE

50 IRE

12.5 IRE 0 IRE

05067-082

Rev. 0 | Page 59 of 88

ADV7320/ADV7321

VOLTS

024

0.5

IRE:FLT

100

50

0

–50

0

F2 L135

6 8 10 12

05067-083

Figure 83. Address 0x42, Bit 7 = 0

VOLTS

IRE:FLT

100

0.5

50

0

F2

–50

02–2 4 6 8 10 12

Figure 84. Address 0x42, Bit 7 = 1

L135

05067-084

Rev. 0 | Page 60 of 88

ADV7320/ADV7321

/

HSYNC

VSYNC

The ADV7320/21 has the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on P_HSYNC

Table 36. Hsync Output Control1

HD/ED2 Slave Mode (0x10, bit 2)

x 0 0 x Tristate – x 0 1 x Pipelined SD

External &

VSYNC

HSYNC

/Field Mode EAV/SAV Mode 1 x 0

x 1 x 1

______________________________

1

In all HD/ED standards where there is an

2

ED = enhanced definition.

Table 37.

VSYNC

HD/ED2 Slave Mode (0x10, Bit 2)

x 0 0 x x Tristate x 0 1 x Interlaced

External &

VSYNC

HSYNC

/Field Mode EAV/SAV Mode 1 x 0

EAV/SAV Mode 1 x 0

x 1 x 1

x 1 x 1 525p

1

In all HD/ED standards where there is an

2

ED = enhanced definition.

OUTPUT CONTROL

/

P_VSYNC

HD/ED Sync Out Enable (0x02, Bit 7)

1 x 0 Pipelined Ext HD/ED

Output Control1

HD/ED Sync out Enable (0x02, Bit 7)

1 x 0 x

, outputting the respective signals on the

SD Sync Out Enable (0x02, Bit 6)

HSYNC

o/p, the start of the

HSYNC

SD Sync Out Enable (0x02, Bit 6)

HSYNC

o/p, the start of the

I2C_ (0x14, Bit 2)

HSYNC

P_HSYNC

I2C_

and

HSYNC

(0x14, Bit 1)

P_VSYNC

_gen_sel

pins.

Signal on

S_HSYNC

HSYNC

Pipelined HD/ED based on AV code H bit Pipelined HD/ED based on horizontal counter

pulse is aligned with the falling edge of the embedded

VSYNC

_gen_sel

Video Standard

Signal on S_VSYNC

Pipelined SD VSYNC

Pipelined EXT HD/ED

field signal

All HD interlace standards

External pipelined field signal based on AV code F bit

All HD/ED progressive standards

All HD/ED standards except 525p

Pipelined based on AV code

V bit External pipelined

HD/ED based on vertical

counter External pipelined

HD/ED based on vertical

counter

pulse is aligned with the falling edge of the embedded

HSYNC

/ field

VSYNC

HSYNC

VSYNC

Duration

See Appendix 5—SD Timing Modes

As per

HSYNC

timing

Same as line blanking interval

Same as embedded HSYNC

in the output video.

Duration

See Appendix 5—SD Timing Modes

As per Ext

or

or field signal

Field

Vertical blanking interval

Aligned with serration lines

Vertical blanking interval

in the output video.

VSYNC

Rev. 0 | Page 61 of 88

ADV7320/ADV7321

BOARD DESIGN AND LAYOUT

DAC TERMINATION AND LAYOUT CONSIDERATIONS

The ADV7320/ADV7321 contain an on-board voltage reference. The ADV7320/ADV7321 can be used with an external V

The R AGND and are used to control the full-scale output current and, therefore, the DAC voltage output levels. For full-scale output, R not be changed. R

VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER

Output buffering on all six DACs is necessary to drive output devices, such as SD or HD monitors. Analog Devices produces a range of suitable op amps for this application, e.g., the AD8061. More information on line driver buffering circuits is given in the relevant op amps’ data sheets.

An optional analog reconstruction low-pass filter (LPF) may be required as an anti-imaging filter if the ADV7320/ADV7321 are connected to devices that require this filtering.

The filter specifications vary with the application.

Table 38. External Filter Requirements

Application Oversampling

SD 2× >6.5 20.5 SD 16× >6.5 209.5 PS 1× >12.5 14.5 PS 8× >12.5 203.5 HDTV 1× >30 44.25 HDTV 2× >30 118.5

DAC

OUTPUT

(AD1580).

REF

resistors are connected between the R

SET

must have a value of 3040 Ω. The R

SET

has a value of 300 Ω for full-scale output.

LOAD

pins and

SET

values should

SET

Cutoff Frequency (MHz)

10µH

600

22pF600

Ω

3

Ω

4

560

Ω

1

Attenuation –50 dB @ (MHz)

75

Ω

Figure 85. Example of Output Filter for S D, 16× Over sampling

BNC OUTPUT

05067-085

0

–10

–20

–30

–40

GAIN (dB)

–50

GROUP DELAY (Seconds)

–60

–70

–80

1M 10M 100M

CIRCUIT FREQUENCY RESPONSE

PHASE (Degrees)

FREQUENCY (Hz)

MAGNITUDE (dB)

1G

0

–30

–60

–90

–120

–150

–180

–210

–240

24n

21n

18n

15n

12n

9n

6n

3n

0

05067-086

Figure 86. Filter Plot for Output Filter for SD, 16× Oversampling

Ω

4.7µH

6.8pF 600

6.8pF600

Ω

560

3

4

560

Ω

75

Ω

1

Ω

BNC OUTPUT

05067-087

DAC

OUTPUT

Figure 87. Example of Output Filter for PS, 8× Oversampling

DAC

OUTPUT

300Ω

3

4

75Ω

1

220nH470nH

82pF33pF

75Ω

3

4

500Ω

1

BNC

OUTPUT

05067-088

Figure 88. Example of Output Filter for HDTV, 2× Oversampling

Table 39. Possible Output Rates from the ADV7320/ADV7321

Input Mode Address 0x01, Bits 6 to 4

PLL Address 0x00, Bit 1

Output Rate (MHz)

Off 27 (2×) SD Only On 216 (16×) Off 27 (1×) PS Only On 216 (8×)

HDTV Only Off On

74.25 (1×)

148.5 (2×)

Rev. 0 | Page 62 of 88

ADV7320/ADV7321

0

–10

–20

–30

GROUP DELAY (Seconds)

–40

–50

GAIN (dB)

–60

–70

–80

–90

1M 10M 100M 1G

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

FREQUENCY (Hz)

PHASE

(Degrees)

480

400

320

240

160

80

0

–80

–160

–240

18n

16n

14n

12n

10n

8n

6n

4n

2n 0

Figure 89. Filter Plot for Output Filter for PS, 8× Oversampling

0

–10

–20

GROUP DELAY (Seconds)

–30

GAIN (dB)

–40

PHASE (Degrees)

–50

–60

1M 10M 100M 1G

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

FREQUENCY (Hz)

480

360

240

120

0

–120

–240

18n

15n

12n

9n

6n

3n

0

Figure 90. Filter Plot for Output Filter for HDTV, 2× Oversampling

PCB BOARD LAYOUT

The ADV7320/ADV7321 are optimally designed for lowest noise performance of both radiated and conducted noise. To complement the excellent noise performance of the ADV7320/ ADV7321, it is imperative that great care be given to the PC board layout.

The layout should be optimized for lowest noise on the ADV7320/ ADV7321 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of V

and DGND, and V

V

DD

and GND_IO pins should be kept

DD_IO

as short as possible to minimized inductive ringing.

It is recommended that a 4-layer printed circuit board is used, with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. Component placement should be carefully considered in order to separate noisy circuits, such as crystal clocks, high speed logic circuitry, and analog circuitry.

and AGND,

AA

05067-089

05067-090

There should be a separate analog ground plane and a separate digital ground plane.

Power planes should encompass a digital power plane and an analog power plane. The analog power plane should contain the DACs and all associated circuitry, V

circuitry. The digital

REF

power plane should contain all logic circuitry.

The analog and digital power planes should be individually connected to the common power plane at a single point through a suitable filtering device, such as a ferrite bead.

DAC output traces on a PCB should be treated as transmission lines. It is recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the DAC outputs and should overlay the PCB’s ground plane. As well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry.

To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the tracks of the individual DAC output pins. The addition of ground tracks between outputs is also recommended.

Supply Decoupling

Noise on the analog power plane can be further reduced by the use of decoupling capacitors.

Optimum performance is achieved by the use of 10 nF and

0.1 µF ceramic capacitors. Each group of V

, VDD, or V

AA

DD_IO

pins should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance.

A 1 µF tantalum capacitor is recommended across the V

AA

supply in addition to 10 nF ceramic. See the circuit layout in Figure 91.

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane.

Due to the high clock rates used, avoid long clock lines to the ADV7320/ADV7321 to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane.

Analog Signal Interconnect

Locate the ADV7320/ADV7321 as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch.

Rev. 0 | Page 63 of 88

ADV7320/ADV7321

For optimum performance, the analog outputs should each be source- and load-terminated, as shown in Figure 91. The termination resistors should be as close as possible to the ADV7320/ADV7321 to minimize reflections.

For optimum performance, it is recommended that all decoupling and external components relating to the ADV7320/ADV7321 are located on the same side of the PCB and as close as possible to the ADV7320/ADV7321. Any unused inputs should be tied to ground.

POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP

V

AA

0.1µF

V

DD_IO

5k

Ω

19

50 49 48

0.1µF

36

COMP1, 245V

I2C

ADV7320/

ADV7321

S0–S9

S_HSYNC S_VSYNC S_BLANK

10, 56

41

VDDV

AA

DAC A

DAC B

1

DD_IO

V

REF

46

44

43

+

10nF 1µF

10nF 0.1µF

300

Ω

300

Ω

V

100nF

AA

DD

DD_IO

1.1k

V

AA

Ω

RECOMMENDED EXTERNAL AD1580 FOR OPTIMUM PERFORMANCE

42

UNUSED

INPUTS

SHOULD BE

GROUNDED

V

AA

Ω

4.7k

+

4.7µF

ALL COMPONENTS IN DASHED BOXES MUST BE LOCATED ON THE SAME SIDE OF THE PCB AS THE ADV7320/21 AND AS CLOSE AS POSSIBLE TO THE ADV7320/21.

V

AA

820pF

3.9nF

680

Ω

C0–C9

Y0–Y9

63

CLKIN_B

23

P_HSYNC

24

P_VSYNC

25

P_BLANK

33

RESET

32

CLKIN_A

34

EXT_LF

GND_ IO64AGND40DGND

Figure 91. ADV7320/ADV7321 Circuit Layout

DAC C

DAC D

DAC E

DAC F

SCLK

SDA

ALSB R

SET2

R

SET1

11, 57

300

Ω

39

300

Ω

38

300

Ω

37

300

Ω

100

22

21

20

35

47

100

3040

Ω

V

DD_IO

V

DD_IO

5k

Ω

V

DD_IO

5k

Ω

2

C BUS

I

Ω

SELECTION HERE DETERMINES DEVICE ADDRESS

05067-091

Rev. 0 | Page 64 of 88

ADV7320/ADV7321

=

APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM

PS CGMS

Data Registers 2 to 0

[Subaddresses 0x21, 0x22, 0x23]

525p

Using the vertical blanking interval 525p system, 525p CGMS conforms to the CGMS-A EIA-J CPR1204-1 (March 1998) transfer method of video identification information and to the IEC61880 (1998) 525p/60 video system’s analog interface for the video and accompanying data.

When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS data is inserted on Line 41. The 525p CGMS data registers are at Addresses 0x21, 0x22, and 0x23.

FUNCTION OF CGMS BITS

For Word 0 to 6 bits, Word 1 to 4 bits, and Word 2 to 6 bits CRC 6 bits,

xxPolynomialCRC

16 ++

where default is preset to 111111.

720p System

CGMS data is applied to Line 24 of the luminance vertical blanking interval.

1080i System

CGMS data is applied to Line 19 and Line 582 of the luminance vertical blanking interval.

625p

The 625p CGMS conforms to the IEC62375 (2004) 625p/50 video system’s analog interface for the video and accompanying data using the vertical blanking interval.

When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS data is inserted on Line 43. The 625p CGMS data registers are at Addresses 0x22, and 0x23.

HD CGMS

[Address 0x12, Bit 6]

The ADV7320/ADV7321 support copy generation management system (CGMS) in HDTV mode (720p and 1080i) in accordance with EIAJ CPR-1204-2.

The HD CGMS data registers are found at Addresses 0x021, 0x22, and 0x23.

SD CGMS

Data Registers 2 to 0

[Subaddresses 0x59, 0x5A, 0x5B]

The ADV7320/ADV7321 support copy generation management system (CGMS), conforming to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether CGMS data is output on odd and even fields. CGMS data can be transmitted only when the ADV7320/ADV7321 is configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit; see Figure 94.

CGMS FUNCTIONALITY

If SD CGMS CRC [Address 0x59, Bit 4] or PS/HD CGMS CRC [Subaddress 0x12, Bit 7] is set to Logic 1, the last six bits, C19 to C14, which comprise the 6-bit CRC check sequence, are automatically calculated on the ADV7320/ADV7321. This calculation is based on the lower 14 bits (C0 to C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial ×6 + x + 1 with a preset value of 111111. If SD CGMS CRC [Address 0x59, Bit 4] and PS/HD CGMS CRC [Address 0x12, Bit 7] are set to Logic 0, all 20 bits (C0 to C19) are output directly from the CGMS registers (CRC must be calculated by the user manually).

Rev. 0 | Page 65 of 88

ADV7320/ADV7321

5

70%

+700mV

± 10%

0mV

–300mV

µs ± 0.15µs

5.8 6T

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

21.2µs ± 0.22µs 22T

T = 1/(f

f

= HORIZONTAL SCAN FREQUENCY

H

± 30ns

T

H

CRC SEQUENCE

C13 C14 C15 C16 C17 C18 C19

× 33) = 963ns

05067-092

Figure 92. Progressive Scan 525p CGMS Waveform (Line 41)

PEAK WHITE

00mV ± 25mV

SYNC LEVEL

5.5µs ± 0.125µs

R = RUN-IN S = START CODE

C0

R S

LSB

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

13.7µs

C13 MSB

05067-093

Figure 93. Progressive Scan 625p CGMS-A Waveform (Line 43)

+100 IRE

+70 IRE

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17

CRC SEQUENCE

C18 C19

0 IRE

–40 IRE

11.2µs

2.235µs ± 20ns

Figure 94. Standard Definition CGMS Waveform

49.1µs ± 0.5µs

05067-094

Rev. 0 | Page 66 of 88

ADV7320/ADV7321

CRC SEQUENCE

C18 C19

70%

+700mV

±

10%

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17

0mV

–300mV

3.128

4T

µs±

90ns

±

30ns

T

17.2

µs±

160ns

22T

T = 1/(

f

×

1650/58) = 781.93ns

H

f

= HORIZONTAL SCAN FREQUENCY

H

1H

05067-095

Figure 95. HDTV 720p CGMS Waveform

CRC SEQUENCE

×

2200/77) = 1.038µs

C18 C19

05067-096

70%

+700mV

±

10%

0mV

–300mV

4.15

µs±

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17

±

30ns

T

4T

60ns

22.84

µs±

22T

1H

210ns

T = 1/(f

H

f

= HORIZONTAL SCAN FREQUENCY

H

Figure 96. HDTV 1080i CGMS Waveform

Rev. 0 | Page 67 of 88

ADV7320/ADV7321

APPENDIX 2—SD WIDE SCREEN SIGNALING

[Subaddresses 0x59, 0x5A, 0x5B]

The ADV7320/ADV7321 support wide screen signaling (WSS) conforming to the ETS 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long, and the function of each of these bits is shown in Table 40.

Table 40. Function of WSS Bits

Bit Description

Bit 0 to Bit 2 Aspect Ratio/Format/Position Bit 3 Odd Parity Check of Bit 0 to Bit 2

B0 B1 B2 B3 Aspect Ratio Format Position

0 0 0 1 4:3 Full Format N/A 1 0 0 0 14:9 Letterbox Center 0 1 0 0 14:9 Letterbox Top 1 1 0 1 16:9 Letterbox Center 0 0 1 0 16:9 Letterbox Top 1 0 1 1 >16:9 Letterbox Center 0 1 1 1 14:9 Full Format Center 1 1 1 0 16:9 N/A N/A 1 1 1 0 16:9

B4

0 Camera Mode 1 Film Mode

B5

0 Standard Coding 1 Motion Adaptive Color Plus

B6

0 No Helper 1 Modulated Helper

B7 B9 B10

Reserved

0 0 No Open Subtitles 1 0 Subtitles in Active Image Area 0 1 Subtitles out of Active Image Area 1 1 Reserved B11 0 No Surround Sound Information 1 Surround Sound Mode

B12 B13

Reserved Reserved

The WSS data is preceded by a run-in sequence and a start code; see Figure 97. If SD WSS [Address 0x59, Bit 7] is set to Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 s from the falling edge of HSYNC

) is available for the insertion of video. It is possible to

blank the WSS portion of Line 23 with Subaddress 0x61, Bit 7.

500mV

11.0µs

RUN-IN

SEQUENCE

START

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

CODE

38.4µs

42.5µs

Figure 97. WSS Waveform Diagram

Rev. 0 | Page 68 of 88

ACTIVE

VIDEO

05067-097

ADV7320/ADV7321

APPENDIX 3—SD CLOSED CAPTIONING

[Subaddresses 0x51 to 0x54]

The ADV7320/ADV7321 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by Logic 1 start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in the SD closed captioning registers [Addresses 0x53 to 0x54].

The ADV7320/ADV7321 also support the extended closed captioning operation, which is active during even fields and encoded on Scan Line 284. The data for this operation is stored in the SD closed captioning registers [Addresses 0x51 to 0x52].

FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA608 describe the closed captioning information for Line 21 and Line 284.

The ADV7320/ADV7321 use a single buffering method. This means that the closed captioning buffer is only 1 byte deep; therefore, there will be no frame delay in outputting the closed captioning data, unlike other 2-byte-deep buffering systems. The data must be loaded one line before it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC

to interrupt a microprocessor, which in turn will load

the new data (2 bytes) in every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes, on Line 21, or a TV will not recognize them. If there is a message such as “Hello World” that has an odd number of characters, it is important to add a blank character at the end so that the end-of-caption, 2-byte control code lands in the same field.

All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7320/ ADV7321. All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled.

10.5±0.25µs 12.91µs 7CYCLESOF

CLOCK RUN-IN

50 IRE

40 IRE

REFERENCE COLOR BURST

FREQUENCY = F

(9 CYCLES)

= 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003µs

27.382µs 33.764µs

Figure 98. Closed Captioning Waveform, NTSC

0.5035MHz

TWO 7-BIT + PARITY ASCII CHARACTERS

(DATA)

S T A

D0–D6 D0–D6 R T

P A R

I T Y

P A R

I T Y

BYTE 1BYTE 0

05067-098

Rev. 0 | Page 69 of 88

ADV7320/ADV7321

APPENDIX 4—TEST PATTERNS

The ADV7320/ADV7321 can generate SD and HD test patterns.

T

2

CH2 200mV M 10.0µs A CH2 1.20V

T

30.6000µs

05067-099

Figure 99. NTSC Color Bars

2

CH2 100mV M 10.0µs CH2 EVEN

T

1.82600ms

05067-102

Figure 102. PAL Black Bar

(–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)

T

2

CH2 200mV M 10.0µs A CH2 1.21V

T

30.6000µs

05067-100

Figure 100. PAL Color Bars

T

2

CH2 200mV M 4.0µs CH2 EVEN

T

1.82944ms

05067-103

Figure 103. 525p Hatch Pattern

T

2

CH2 100mV M 10.0µs CH2 EVEN

T

1.82380ms

Figure 101. NTSC Black Bar

(–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV,18 mV, 23 mV)

05067-101

Rev. 0 | Page 70 of 88

2

CH2 200mV M 4.0µs CH2 EVEN

T

1.84208ms

05067-104

Figure 104. 625p Hatch Pattern

ADV7320/ADV7321

T

2

CH2 200mV M 4.0µs CH2 EVEN

T

1.82872ms

05067-105

Figure 105. 525p Field Pattern

T

2

CH2 100mV M 4.0µs CH2 EVEN

T

1.82936ms

Figure 107. 525p Black Bar

(−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 35 mV)

T

05067-107

2

CH2 200mV M 4.0µs CH2 EVEN

T

1.84176ms

Figure 106. 625p Field Pattern

05067-106

2

CH2 100mV M 4.0µs CH2 EVEN

T

1.84176ms

Figure 108. 625p Black Bar

05067-108

(−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 5 mV)

Rev. 0 | Page 71 of 88

ADV7320/ADV7321

The register settings in Table 41 are used to generate an SD NTSC CVBS output on DAC A, S-video on DACs B and C, and YPrPb on DACs D, E, and F. Upon power-up, the subcarrier registers are programmed with the appropriate values for NTSC. All other registers are set as normal/default.

Table 41. NTSC Test Pattern Register Writes

Subaddress Register Setting

0x00 0xFC 0x40 0x10 0x42 0x40 0x44 0x40 (internal test pattern on) 0x4A 0x08

For PAL CVBS output on DAC A, the same settings are used, except that Subaddress 0x40 is programmed to 0x11 and the F registers are programmed as shown in Table 42.

Table 42. PAL FSC Register Writes

Subaddress Description Register Setting

0x4C FSC0 0xCB 0x4D FSC1 0x8A 0x4E FSC2 0x09 0x4F FSC3 0x2A

Note that when programming the FSC registers, the user must write the values in the sequence F

value to be written is only accepted after the FSC3 write is

F

SC

0, FSC1, FSC2, FSC3. The full

SC

complete.

SC

The register settings in Table 43 are used to generate a 525p hatch pattern on DAC D, E, and F. All other registers are set as normal/default.

Table 43. 525p Test Pattern Register Writes.

Subaddress Register Setting

Ox00 0xFC 0x01 0x10 0x10 0x00 0x11 0x05 0x16 0xA0 0x17 0x80 0x18 0x80

For 625p hatch pattern on DAC D, the same register settings are used except that Subaddress 0x10 = 0x18.

Rev. 0 | Page 72 of 88

ADV7320/ADV7321

APPENDIX 5—SD TIMING MODES

[Subaddress 0x4A]

MODE 0 (CCIR-656)—SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 0)

The ADV7320/ADV7321 are controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. If Pins

S_VSYNC

,

S_HSYNC

used, they should be tied high during this mode. Blank output is available.

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

, and

S_BLANK

EAV CODE

C

FF0000X

Y

r

4 CLOCK

END OF ACTIVE

VIDEO LINE

are not

8

10801

0

Y

0

Figure 109. SD Slave Mode 0

FF00FFABABA

ANCILLARY DATA

268 CLOCK

280 CLOCK

B

(HANC)

801

0

SAV CODE

8

10FF0

0

XYC

Y

0

b

4 CLOCK

START OF ACTIVE

VIDEO LINE

C

Y

b

r

1440 CLOCK

C

Y

b

r

05067-109

Rev. 0 | Page 73 of 88

ADV7320/ADV7321

V

MODE 0 (CCIR-656)—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 1)

The ADV7320/ADV7321 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on S_HSYNC output on

, the V bit is output on

S_VSYNC

.

DISPLAY

S_BLANK

, and the F bit is

VERTICAL BLANK

DISPLAY

522 523 524 525 8

H

F

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

H

F

1

EVEN FIELD

ODD FIELD

4

32

ODD FIELD

EVEN FIELD

765

VERTICAL BLANK

9

Figure 110. SD Master Mode 0, NTSC

10 11 20 21 22

DISPLAY

283

284

285

05067-110

Rev. 0 | Page 74 of 88

ADV7320/ADV7321

V

A

G

DISPLAY

622 623 624 625

H

F

DISPLAY

309 310 311 312 314 315 316 317

H

F

EVEN FIELD

ODD FIELD

1

ODD FIELD

313

EVEN FIELD

VERTICAL BLANK

4

32

VERTICAL BLANK

318

765

319 320

21

22 23

334

DISPLAY

335 336

DISPLAY

05067-111

Figure 111. SD Master Mode 0, PAL

NALO

VIDEO

H

F

V

05067-112

Figure 112. SD Master Mode 0, Data Transitions

Rev. 0 | Page 75 of 88

ADV7320/ADV7321

MODE 1—SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 1 0)

In this mode, the ADV7320/ADV7321 accept horizontal sync and odd/even field signals. When

HSYNC the field input indicates a new frame, i.e., vertical retrace. The BLANK

signal is optional. When the

ADV7320/ADV7321 automatically blank all normally blank

, and

,

BLANK

S_VSYNC

lines as per CCIR-624. on

S_HSYNC

,

S_BLANK

HSYNC

DISPLAY

is low, a transition of

BLANK

input is disabled,

, and FIELD are input

.

VERTICAL BLANK

DISPLAY

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

522 523 524 525

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1

2

EVEN FIELD

ODD FIELD EVEN FIELD

3

4

59

ODD FIELD

VERTICAL BLANK

7

6

8

10 11

Figure 113. SD Slave Mode 1 (NTSC)

20 21 22

DISPLAY

283

284

285

05067-113

Rev. 0 | Page 76 of 88

ADV7320/ADV7321

MODE 1—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 1 1)

In this mode, the ADV7320/ADV7321 can generate horizontal sync and odd/even field signals. When

HSYNC

transition of the field input indicates a new frame, i.e., vertical retrace. The

BLANK

signal is optional. When the

is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions.

,

HSYNC S_BLANK

BLANK

, and FIELD are output on

, and

S_VSYNC

DISPLAY

.

is low, a

BLANK

S_HSYNC

input

,

VERTICAL BLANK

DISPLAY

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

622 623 624 625

EVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD

1

ODD FIELD

EVEN FIELD

3

2

VERTICAL BLANK

Figure 114. SD Slave Mode 1 (PAL)

HSYNC

FIELD

×

CLOCK/2

×

CLOCK/2

BLANK

PAL = 12

NTSC = 16

4

5

317

7

6

318 319

320

21 22 23

334 335 336

DISPLAY

05067-114

PIXEL DATA

PAL = 132×CLOCK/2

NTSC = 122

Figure 115. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave

Rev. 0 | Page 77 of 88

Cb Y

×

CLOCK/2

Cr Y

05067-115

ADV7320/ADV7321

MODE 2— SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 0 0)

In this mode, the ADV7320/ADV7321 accept horizontal and vertical sync signals. A coincident low transition of both

and low transition when field. The

inputs indicates the start of an odd field. A

VSYNC

is high indicates the start of an even

BLANK

HSYNC

signal is optional. When the

disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624.

input on

S_HSYNC

DISPLAY

,

S_BLANK

HSYNC

, and

,

BLANK

S_VSYNC

, and

, respectively.

BLANK

VSYNC

HSYNC

VSYNC

input is

are

VERTICAL BLANK

DISPLAY

HSYNC

BLANK

VSYNC

HSYNC

BLANK

VSYNC

4

522 523 524 525

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1

3

2

EVEN FIELD

ODD FIELD

5

VERTICAL BLANK

6

ODD FIELD

EVEN FIELD

7

8

9

10 11

Figure 116. SD Slave Mode 2 (NTSC)

HSYNC

DISPLAY

622 623 624 625

1

VERTICAL BLANK

4

32

765

DISPLAY

21 22 23

20 21 22

DISPLAY

283

284

285

05067-116

BLANK

VSYNC

HSYNC

BLANK

VSYNC

EVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD

VERTICAL BLANK

EVEN FIELD

Figure 117. SD Slave Mode 2 (PAL)

Rev. 0 | Page 78 of 88

317

318 319

320

DISPLAY

334 335 336

05067-117

ADV7320/ADV7321

MODE 2—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7320/ADV7321 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC

and

inputs indicates the start of an odd field.

VSYNC

A

VSYNC

low transition when

start of an even field. The

input is disabled, the ADV7320/ADV7321

BLANK

HSYNC

BLANK

is high indicates the

signal is optional. When the

automatically blank all normally blank lines as per CCIR-624.

,

HSYNC S_BLANK

BLANK

, and

VSYNC

S_VSYNC

HSYNC

VSYNC

BLANK

PIXEL

DATA

HSYNC

are output on

, respectively.

PAL = 12×CLOCK/2

NTSC = 16

,

×

CLOCK/2

S_HSYNC

Figure 118. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave

PAL = 132

NTSC = 122

×

CLOCK/2

Cb

Cr

Y

05067-118

VSYNC

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

Cb

Y

Cr

Cb

05067-119

BLANK

PIXEL

DATA

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 119. SD Timing Mode 2 Odd-to-Even Field Transition

Rev. 0 | Page 79 of 88

ADV7320/ADV7321

MODE 3—MASTER/SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 1 0 OR X X X X X 1 1 1)

In this mode, the ADV7320/ADV7321 accept or generate hori-

BLANK

,

BLANK

is high, a

input

, and

zontal sync and odd/even field signals. When

HSYNC

transition of the field input indicates a new frame, i.e., vertical retrace. The

BLANK

signal is optional. When the

is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624.

VSYNC S_VSYNC

are output in master mode and input in slave mode on

,

S_BLANK

, and

S_VSYNC

HSYNC

, respectively.

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

284

DISPLAY

285

DISPLAY

522 523 524 525

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1

ODD FIELD EVEN FIELD

4

32

ODD FIELDEVEN FIELD

VERTICAL BLANK

765

VERTICAL BLANK

9

10 11

8

20 21 22

283

Figure 120. SD Timing Mode 3 (NTSC)

DISPLAY

VERTICAL BLANK

DISPLAY

05067-120

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

622 623 624 625

DISPLAY

309 310 311 312 313 314 315 316

1

ODD FIELDEVEN FIELD

32

VERTICAL BLANK

Figure 121. SD Timing Mode 3 (PAL)

Rev. 0 | Page 80 of 88

5

4

317

7

6212223

DISPLAY

318 319

320

334 335 336

05067-121

ADV7320/ADV7321

APPENDIX 6—HD TIMING

DISPLAY

FIELD 1

P_VSYNC

P_HSYNC

FIELD 2

P_VSYNC

P_HSYNC

VERTICAL BLANKING INTERVAL

1124 1125 1 2 5 6 7 8

VERTICAL BLANKING INTERVAL

561 562 563 564 567 568 569 570

Figure 122. 1080i

566565

43

HSYNC

and

VSYNC

Input Timing

21

20 22 560

DISPLAY

584

583 585 1123

05067-122

Rev. 0 | Page 81 of 88

ADV7320/ADV7321

APPENDIX 7—VIDEO OUTPUT LEVELS

HD YPrPb OUTPUT LEVELS

INPUT CODE

EIA-770.2, STANDARD FOR Y

OUTPUT VOLTAGE

INPUT CODE

EIA-770.3, STANDARD FOR Y

OUTPUT VOLTAGE

940

700mV

64

300mV

EIA-770.2, STANDARD FOR Pr/Pb

960

512

64

OUTPUT VOLTAGE

700mV

Figure 123. EIA 770.2 Standard Output Signals (525p/625p)

INPUT CODE

EIA-770.1, STANDARD FOR Y

940

OUTPUT VOLTAGE

782mV

05067-123

940

700mV

64

300mV

EIA-770.3, STANDARD FOR Pr/Pb

960

600mV

512

64

OUTPUT VOLTAGE

700mV

Figure 125. EIA 770.3 Standard Output Signals (1080i/720p)

INPUT CODE

1023

Y–OUTPUT LEVELS FOR FULL INPUT SELECTION

OUTPUT VOLTAGE

05067-125

64

EIA-770.1, STANDARD FOR Pr/Pb

960

512

64

Figure 124. EIA 770.1 Standard Output Signals (525p/625p)

714mV

286mV

OUTPUT VOLTAGE

700mV

05067-124

64

INPUT CODE

1023

Pr/Pb–OUTPUT LEVELS FOR

FULL INPUT SELECTION

64

Figure 126. Output Levels for Full Input Selection

700mV

300mV

OUTPUT VOLTAGE

700mV

300mV

05067-126

Rev. 0 | Page 82 of 88

ADV7320/ADV7321

3

RGB OUTPUT LEVELS

Pattern: 100%/75% Color Bars

700mV

00mV

700mV

00mV

700mV

00mV

Figure 127. PS RGB Output Levels

700mV 525mV

525mV

05067-127

700mV

300mV

700mV

300mV

700mV

300mV

525mV

05067-129

Figure 129. SD RGB Output Levels—RGB Sync Disabled

700mV 525mV

00mV

0mV

700mV

00mV

0mV

700mV

00mV

0mV

525mV

Figure 128. PS RGB Output Levels—RGB Sync Enabled

05067-128

300mV

0mV

700mV

300mV

0mV

700mV

300mV

0mV

525mV

Figure 130. SD RGB Output Levels—RGB Sync Enabled

05067-130

Rev. 0 | Page 83 of 88

ADV7320/ADV7321

YPrPb LEVELS—SMPTE/EBU N10

Pattern: 100% Color Bars

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

WHITE

YELLOW

CYAN

GREEN

MAGENTARED

BLUE

BLACK

700mV

Figure 131. Pb Levels—NTSC

WHITE

YELLOW

CYAN

GREEN

MAGENTA

700mV

05067-134

05067-131

Figure 134. Pr Levels—PAL

WHITE

YELLOW

CYAN

GREEN

MAGENTARED

BLUE

RED

BLUE

BLACK

300mV

2 3 1

7 6 0 5 0

700mV

BLACK

05067-135

700mV

Figure 132. Pb Levels—PAL

WHITE

YELLOW

CYAN

GREEN

MAGENTARED

Figure 133. Pr Levels—NTSC

BLUE

BLACK

05067-133

Rev. 0 | Page 84 of 88

300mV

Figure 135. Y Levels—NTSC

WHITE

YELLOW

CYAN

GREEN

700mV

MAGENTARED

Figure 136. Y Levels—PAL

BLUE

BLACK

05067-136

ADV7320/ADV7321

VOLTS IRE:FLT

100

0.5 50

VOLTS

0.6

0.4

0.2

0

F1

–50

L76

0

10 20

APL = 44.5% 525 LINE NTSC SLOW CLAMP TO 0.00V AT 6.72µs

MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = A FRAMES SELECTED 1, 2

Figure 137. NTSC Color Bars 75%

VOLTS IRE:FLT

0.4 50

0.2

0

–0.2

–50

–0.4

F1 L76

0

NOISE REDUCTION: 15.05dB APL NEEDS SYNC SOURCE. 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72

10 20

µ

Figure 138. NTSC Chroma

VOLTS IRE:FLT

0.6

0.4

50

0

0.2

0

30 40 50 60

30 40 50 60 MICROSECONDS

PRECISION MODE OFF SYNCHRONOUS SYNC = B FRAMES SELECTED 1, 2

s

05067-137

05067-138

0

–0.2

L608

NOISE REDUCTION: 0.00dB APL = 39.1% 625 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72

10020

30 40 50 60

MICROSECONDS PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

µs

FRAMES SELECTED 1, 2, 3, 4

05067-140

Figure 140. PAL Color Bars 75%

VOLTS

0.5

0

–0.5

L575

10 20

APL NEEDS SYNC SOURCE. 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 AT 6.72

30 40 50 60

MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

µ

s

FRAMES SELECTED 1

05067-141

Figure 141. PAL Chroma

VOLTS

0.5

0

–0.2

NOISE REDUCTION: 15.05dB APL = 44.3% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72

F2 L238

10 20

30 40 50 60

MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED 1, 2

µ

s

Figure 139. NTSC Luma

05067-139

Rev. 0 | Page 85 of 88

L575

10020

APL NEEDS SYNC SOURCE. 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 AT 6.72

Figure 142. PAL Luma

30 40 50 60

MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

µ

s

70

05067-142

ADV7320/ADV7321

A

M

APPENDIX 8—VIDEO STANDARDS

SMPTE 274M

ANALOG WAVEFORM

*1

4T

EAV CODE

F

INPUT PIXELS

SAMPLE NUMBER

FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1 SAV/EAV: LINE 21–560; 584–1123: V = 0

FOR A FRAME RATE OF 30Hz: 40 SAMPLES FOR A FRAME RATE OF 25Hz: 480 SAMPLES

000

V

F

0

H*

4 CLOCK 4 CLOCK

2112 2116 2156 2199

Figure 143. EAV/SAV Input Data Timing Diagram—SMPTE 274M

0

DATUM

H

DIGITAL HORIZONTAL BLANKING

272T

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

0

44 188 192 2111

4T 1920T

SAV CODE

F

C

000

F

V

bCr

0

F

H*

DIGITAL

ACTIVE LINE

Y

C

Y

r

05067-143

SMPTE 293M

NALOG WAVEFOR

INPUT PIXELS

SAMPLE NUMBER

EAV CODE

F

000

V

F

0

H*

4 CLOCK 4 CLOCK

719 723 736 799 853 0

FVH* = FVH AND PARITY BITS SAV: LINE 43–525 = 200H SAV: LINE 1–42 = 2AC EAV: LINE 43–525 = 274H EAV: LINE 1–42 = 2D8

0HDATUM

DIGITAL HORIZONTAL BLANKING

ANCILLARY DATA

(OPTIONAL)

SAV CODE

F

000

F

Figure 144. EAV/SAV Input Data Timing Diagram—SMPTE 293M

DIGITAL

ACTIVE LINE

F

CbC

V

Y

0

H*

857 719

r

C

Y

r

05067-144

Rev. 0 | Page 86 of 88

ADV7320/ADV7321

ACTIVE

VIDEO

VERTICAL BLANK

ACTIVE

VIDEO

52252352452512567891213141516424344

05067-145

Figure 145. SMPTE 293M (525p)

ACTIVE

VIDEO

622 623 624 625 10 11

12 56789

4

VERTICAL BLANK

Figure 146. ITU-R BT.1358 (625p)

12

13

ACTIVE

VIDEO

43 44 45

05067-146

DISPLAY

VERTICAL BLANKING INTERVAL

45

747 748 749 750 26 2725744 745

12

3

67

8

05067-147

Figure 147. SMPTE 296M (720p)

DISPLAY

VERTICAL BLANKING INTERVAL

FIELD 1

560

22

21

20

DISPLAY

584

583 585 1123

05067-148

FIELD 2

1124 1125

561 562 563 564 567 568 569 570

12 5678

VERTICAL BLANKING INTERVAL

43

566565

Figure 148. SMPTE 274M (1080i)

Rev. 0 | Page 87 of 88

ADV7320/ADV7321

OUTLINE DIMENSIONS

0.75

0.60

0.45

SEATING

PLANE

1.60 MAX

12.00

BSC SQ

1

PIN 1

4964

48

10.00

BSC SQ

33

1.45

1.40

1.35

0.15

0.05

ROTATED 90° CCW

SEATING PLANE

VIEW A

10°

6° 2°

0.20

0.09 7°

3.5° 0°

0.08 MAX COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026BCD

VIEW A

TOP VIEW

(PINS DOWN)

16

17

0.50 BSC

0.27

0.22

0.17

32

Figure 149. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7320KSTZ1 0°C to 70°C

64-Lead Low Profile Quad Flat Package [LQFP]

ADV7321KSTZ1 0°C to 70°C

64-Lead Low Profile Quad Flat

Package [LQFP] EVAL-ADV7320EB Evaluation Board EVAL-ADV7321EB Evaluation Board

1

Z = Pb-free part.

ST-64-2

D05067–0–10/04(0)

Rev. 0 | Page 88 of 88

Datasheet ADV7320 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL FEATURES

APPLICATIONS

GENERAL DESCRIPTION

SPECIFICATIONS

DYNAMIC SPECIFICATIONS

TIMING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

MPU PORT DESCRIPTION

REGISTER ACCESS

REGISTER PROGRAMMING

SUBADDRESS REGISTER (SR7 TO SR0)

INPUT CONFIGURATION

STANDARD DEFINITION ONLY

16-/20-Bit Mode Operation

PROGRESSIVE SCAN ONLY OR HDTV ONLY

FEATURES

OUTPUT CONFIGURATION

HD ASYNC TIMING MODE

HD TIMING RESET

SD REAL-TIME CONTROL, SUBCARRIER RESET, AND TIMING RESET

RESET SEQUENCE

SD VCR FF/RW SYNC

VERTICAL BLANKING INTERVAL

SUBCARRIER FREQUENCY REGISTERS

Programming the FSC

SQUARE PIXEL TIMING MODE

FILTERS

SD Internal Filter Response

PS/HD Sinc Filter

COLOR CONTROLS AND RGB MATRIX

HD Y Level, HD Cr Level, HD Cb Level

RGB Matrix

Manual RGB Matrix Adjust Feature

Programming the RGB Matrix

SD Luma and Color Control

SD Hue Adjust Value

SD Brightness Control

SD Brightness Detect

Double Buffering

PROGRAMMABLE DAC GAIN CONTROL

GAMMA CORRECTION

HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS

HD Sharpness Filter Mode

HD Adaptive Filter Mode

HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES

HD Sharpness Filter Application

Adaptive Filter Control Application

SD DIGITAL NOISE REDUCTION

BLOCK SIZE CONTROL

BORDER AREA

CORING GAIN DATA

CORING GAIN BORDER

DNR THRESHOLD

DNR INPUT SELECT CONTROL

BLOCK OFFSET CONTROL

DNR MODE CONTROL

SD ACTIVE VIDEO EDGE

SAV/EAV STEP EDGE CONTROL

BOARD DESIGN AND LAYOUT

DAC TERMINATION AND LAYOUT CONSIDERATIONS

VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER

PCB BOARD LAYOUT

Supply Decoupling

Digital Signal Interconnect

Analog Signal Interconnect

APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM

PS CGMS

Data Registers 2 to 0

525p

FUNCTION OF CGMS BITS