Analog Devices ADV7310 1 a Datasheet

Multiformat 216 MHz

Video Encoder with Six NSV

™

ADV7310/ADV7311

12-Bit DACs

FEATURES
High Definition Input Formats

8-/10-, 16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:

SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3ⴛ10-Bit 4:4:4 Input Format

HDTV RGB Supported:

RGB, RGBHV
Other High Definition Formats Using Async

Timing Mode

High Definition Output Formats

YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)*
CGMS-A (525p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1*

CGMS/WSS
Closed Captioning

GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling up to 216 MHz
Programmable DAC Gain Control
Sync Outputs in All Modes
On-Board Voltage Reference

Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.

*ADV7310 Only

Six 12-Bit NSV Precision Video DACs
2-Wire Serial I

2C®

Interface
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product

APPLICATIONS
High End DVD
High End PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
Professional Video Systems

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

Y9–Y0
C9–C0
S9–S0

HSYNC
VSYNC
BLANK

CLKIN_A
CLKIN_B

D
E
M
U
X

TIMING

GENERATOR

PLL

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

PROGRAMMABLE

RGB MATRIX

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

ADV7310/
ADV7311

12-BIT

DAC

12-BIT

O
V

DAC
E
R

12-BIT

S

DAC
A

M

12-BIT

P
L

DAC

I

N

12-BIT

G

DAC

12-BIT

DAC

I2C

INTERFACE

GENERAL DESCRIPTION

The ADV®7310/ADV7311 is a high speed, digital-to-analog
encoder on a single monolithic chip. It includes six high speed
NSV video D/A converters with TTL compatible inputs.

The ADV7310/ADV7311 has separate 8-/10-/16-/20-bit input
ports that accept data in high definition and/or standard definition
video format. For all standards, external horizontal, vertical,
and blanking signals or EAV/SAV timing codes control the
insertion of appropriate synchronization signals into the digi­tal data stream and therefore the output signal.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADV7310/ADV7311

P

P
P

S

S
S

DETAILED FEATURES
High Definition Programmable Features (720p 1080i)

2 Oversampling (148.5 MHz)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)

High Definition Programmable Features (525p/625p)

8 Oversampling (216 MHz Output)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)*
CGMS-A (525p)

Standard Definition Programmable Features

16 Oversampling (216 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)

Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction
Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable

Gain/Attenuation
PrPb SSAF™
Separate Pedestal Control on Component and
Composite/S-Video Output
VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1*
CGMS/WSS
Closed Captioning

Standards Directly Supported

Frame Clk

Resolution Rate (Hz) Input (MHz) Standard

720  480 29.97 27 ITU-R BT.656
720  576 25 27 ITU-R BT.656
720  483 59.94 27 SMPTE 293M
720  480 59.94 27 BTA T-1004
720  576 50 27 ITU-R BT.1362
1280  720 60 74.25 SMPTE 296M
1920  1080 30 74.25 SMPTE 274M
1920  1080 25 74.25 SMPTE 274M*

Other standards are supported in Async Timing Mode.
*SMPTE 274M-1998: System no. 6

DETAILED FUNCTIONAL BLOCK DIAGRAM

HD PIXEL

INPUT

CLKIN_B

_HSYNC
_VSYNC
_BLANK

_HSYNC
_VSYNC
_BLANK

CLKIN_A

SD PIXEL

INPUT

TERMINOLOGY

SD Standard Definition Video, conforming to

ITU-R BT.601/ITU-R BT.656.

HD High Definition Video, i.e., Progressive Scan or HDTV.

DE­INTER­LEAVE

DE­INTER­LEAVE

Y

TEST

CR

PAT T ERN

CB

CB

TEST

CR

PATTERN

Y

TIMING

GENERATOR

TIMING

GENERATOR

SHARPNESS

AND

ADAPTIVE

FILTER

CONT

ROL

DNR

GAMMA

Y COLOR
CR COLOR
CB COLOR

COLOR

CONTROL

CLOCK

CONTROL

AND PLL

INSERTION

4:2:2

TO

4:4:4

SYNC

U

UV SSAF

V

CHROMA

FILTERS

LUMA

AND

2 OVER-

SAMPLING

RGB

MATRIX

F

SC

MODULATION

CGMS

WSS

PS 8

HDTV 2

SD 16

DAC

DAC

DAC

DAC

DAC

DAC

HDTV High Definition Television Video, conforming to

SMPTE 274M or SMPTE 296M.

YCrCb SD, PS, or HD Component Digital Video.

YPrPb SD, PS, or HD Component Analog Video.

PS Progressive Scan Video, conforming to SMPTE 293M,

ITU-R BT.1358, BTAT-1004EDTV2, or BTA1362.

*ADV7310 Only

REV. A–2–

CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 14

THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 14

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 15

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 16

REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 17

INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 30

Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . . 30

Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . . 30

Simultaneous Standard Definition and Progressive Scan

or HDTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz . . . 31

OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 33

TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 34

HD TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SD Real-Time Control, Subcarrier Reset,

and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 38

Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . . 38

Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 40

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 41

COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 45

HD Y Level, HD Cr Level, HD Cb Level . . . . . . . . . . . . 45

HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 45

SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 45

SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

ADV7310/ADV7311

PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 47

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

HD SHARPNESS FILTER CONTROL AND ADAPTIVE

FILTER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . . 49

HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . 49

HD Sharpness Filter and Adaptive Filter Application

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

SD Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . 52

Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . . 53

DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . . 54

SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . . 54

BOARD DESIGN AND LAYOUT CONSIDERATIONS . 55

DAC Termination and Layout Considerations . . . . . . . . 55

Video Output Buffer and Optional Output Filter . . . . . . . 55

PCB Board Layout Considerations . . . . . . . . . . . . . . . . . 57

Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 57

Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 57

APPENDIX 1—COPY GENERATION MANAGEMENT

SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

PS CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . . 59

SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . . 59

HD/PS CGMS [Address 12h, Bit 6] . . . . . . . . . . . . . . . . 59

Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 59

CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . . 61

APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . . 62

APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . . 63

APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . . 66

Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . . 66

Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . . 67

Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 69

Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 71

Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . . 72

APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . . 73

APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . . 74

HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . 74

RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

YUV Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . . 80

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 82

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

REV. A

–3–

ADV7310/ADV7311–SPECIFICATIONS

= 2.375–3.6 V, V

V

DD_IO

= 1.235 V, R

REF

= 3040 , R

SET

= 300 . All specifications T

LOAD

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V;

MIN

to T

(0C to 70C), unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

1

Resolution 12 Bits
Integral Nonlinearity 1.5 LSB
Differential Nonlinearity

2

, +ve 0.25 LSB

Differential Nonlinearity2, –ve 1.5 LSB

DIGITAL OUTPUTS

Output Low Voltage, V
Output High Voltage, V

OL

OH

2.4[2.0]

3

Three-State Leakage Current ±1.0 µAV

0.4 [0.4]3VI

VI

= 3.2 mA

SINK

SOURCE

= 0.4 V, 2.4 V

IN

= 400 µA

Three-State Output Capacitance 2 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V

IH

IL

Input Leakage Current 3 µAV
Input Capacitance, C

IN

2V

0.8 V

= 2.4 V

IN

2pF

ANALOG OUTPUTS

Full-Scale Output Current 4.1 4.33 4.6 mA
Output Current Range 4.1 4.33 4.6 mA

DAC-to-DAC Matching 1.0 %

Output Compliance Range, V
Output Capacitance, C

OC

OUT

0 1.0 1.4 V

7pF

VOLTAGE REFERENCE

Internal Reference Range, V
External Reference Range, V
V

Current

REF

4

REF

REF

1.15 1.235 1.3 V

1.15 1.235 1.3 V

±10 µA

POWER REQUIREMENTS

Normal Power Mode

5

I

DD

170 mA SD Only [16]
110 mA PS Only [8]

I

DD_IO

I

AA

6, 7

95 mA HDTV Only [2]
172 190

1.0 mA
39 45 mA

8

mA SD[16, 10-bit] + PS[8, 20-bit]

Sleep Mode

I

DD

I

AA

I

DD_IO

200 µA
10 µA
250 µA

POWER SUPPLY REJECTION RATIO 0.01 % / %

NOTES

1

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

2

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL,
the actual step value lies below the ideal step value.

3

Value in brackets for V

4

External current required to overdrive internal V

5

IDD, the circuit current, is the continuous current required to drive the digital core.

6

IAA is the total current required to supply all DACs including the V

7

All DACs on.

8

Guaranteed maximum by characterization.

Specifications subject to change without notice.

= 2.375 V–2.75 V.

DD_IO

REF

.

circuitry and the PLL circuitry.

REF

REV. A–4–

ADV7310/ADV7311

DYNAMIC SPECIFICATIONS

3040 , R

= 300 . All specifications T

LOAD

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; V

to T

MIN

(0C to 70C), unless otherwise noted.)

MAX

= 2.375 V–3.6 V, V

DD_IO

= 1.235 V, R

REF

SET

Parameter Min Typ Max Unit Test Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth 12.5 MHz
Chroma Bandwidth 5.8 MHz
SNR 65.6 dB Luma ramp unweighted

72 dB Flat field full bandwidth

HDTV MODE

Luma Bandwidth 30 MHz
Chroma Bandwidth 13.75 MHz

STANDARD DEFINITION MODE

Hue Accuracy 0.2

o

Color Saturation Accuracy 0.20 %
Chroma Nonlinear Gain 0.84 ±%Referenced to 40 IRE
Chroma Nonlinear Phase –0.2 ±

o

Chroma/Luma Intermodulation 0 ±%
Chroma/Luma Gain Inequality 96.7 ±%
Chroma/Luma Delay Inequality –1.0 ns
Luminance Nonlinearity 0.2 ±%
Chroma AM Noise 84 dB
Chroma PM Noise 75.3 dB
Differential Gain 0.25 % NTSC
Differential Phase 0.2

o

NTSC

SNR 63.5 dB Luma ramp

77.7 dB Flat field full bandwidth

=

Specifications subject to change without notice.

REV. A

–5–

ADV7310/ADV7311

TIMING SPECIFICATIONS

R

= 300 . All specifications T

LOAD

MIN

to T

(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; V

(0C to 70C), unless otherwise noted.)

MAX

= 2.375 V–3.6 V, V

DD_IO

= 1.235 V, R

REF

Parameter Min Typ Max Unit Test Conditions

MPU PORT

1

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

1

2

3

4

6

7

8

0.6 µs

1.3 µs

0.6 µs First clock generated after this period

0.6 µs relevant for repeated start condition
100 ns

300 ns
300 ns

0.6 µs

RESET Low Time 100 ns

ANALOG OUTPUTS

Analog Output Delay

2

7ns

Output Skew 1 ns

CLOCK CONTROL AND PIXEL PORT

f

CLK

f

CLK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
SD Output Access Time, t
SD Output Hold Time, t
HD Output Access Time, t
HD Output Hold Time, t

PIPELINE DELAY

9

10

1

11

1

12

13

14

13

14

4

3

27 MHz Progressive scan mode

81 MHz HDTV mode/async mode
40 % of one clk cycle
40 % of one clk cycle

2.0 ns

2.0 ns

15 ns

5.0 ns

14 ns

5.0 ns

63 clk cycles SD [2, 16]

76 clk cycles SD component mode [16]

35 clk cycles PS [1]

41 clk cycles PS [8]

36 clk cycles HD[2, 1]

NOTES

1

Guaranteed by characterization.

2

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3

Data: C[9:0]; Y[9:0], S[9:0]
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.

4

SD, PS = 27 MHz, HD = 74.25 MHz.

Specifications subject to change without notice.

= 3040 ,

SET

REV. A–6–

CLKIN_A

ADV7310/ADV7311

t

12

t

13

t

14

CONTROL

INPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

C9–C0

CONTROL

OUTPUTS

t

t

9

10

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

t11

Figure 1. HD Only 4:2:2 Input Mode [Input Mode 010]; PS Only 4:2:2 Input Mode [Input Mode 001]

CLKIN_A

t

12

CONTROL

INPUTS

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

t

t

9

10

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cb1 Cb2 Cb3 Cb4 Cb5

t

11

Cr 0 Cr1 Cr 2 Cr3 Cr 4 Cr5

t

13

t

14

CONTROL

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

C9–C0

S9–S0

OUTPUTS

Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001]

REV. A

–7–

ADV7310/ADV7311

CONTROL

INPUTS

CLKIN_A

P_HSYNC,
P_VSYNC,
P_BLANK

t

t

9

10

t

12

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

CONTROL

INPUTS

Y9–Y0

C9–C0

S9–S0

G0 G1 G2 G3 G4 G5

B0 B1 B2 B3 B4 B5

t

11

R0 R1 R2 R3 R4 R5

Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010]

CLKIN_B*

t

t

10

t

12

t

11

t

P_HSYNC,

P_VSYNC,

P_BLANK

Y9–Y

CONTROL

OUTPUTS

9

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

0

t

12

t

11

t

13

t

14

13

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

*CLKIN_B MUST BE USED IN THIS PS MODE.

Figure 4. PS 4:2:2 10-Bit Interleaved at 27 MHz

t

14

HSYNC/VSYNC

Input Mode [Input Mode 100]

REV. A–8–

CONTROL

INPUTS

CLKIN_A

P_VSYNC,
P_HSYN
P_BLANK

ADV7310/ADV7311

t10

t9

C,

Y9–Y0

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Figure 5. PS 4:2:2 1  10-Bit Interleaved at 54 MHz

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

t11

CLKIN_B*

Y9–Y

CONTROL

OUTPUTS

t12

t

t

9

3FF 00 00 XY Cb0 Y0 Cr0 Y1

0

t

12

t

11

*CLKIN_B USED IN THIS PS ONLY MODE.

10

t13

t14

HSYNC/VSYNC

t

12

t

11

t

13

t

14

Input Mode [Input Mode 111]

Figure 6. PS Only 4:2:2 1  10-Bit Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100]

REV. A

CLKIN_A

t10

t9

CONTROL

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Y9–Y0

OUTPUTS

3FF 00 00 XY Cb0 Y0 Cr0 Y1

t11

t12

NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0  01 BIT-1

t13

t14

Figure 7. PS Only 4:2:2 1  10-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]

–9–

ADV7310/ADV7311

CLKIN_B

CONTROL

INPUTS

P_HSYNC,
P_VSYNC,
P_BLANK

t9

t10

t12

CONTROL

INPUTS

Y9–Y0

C9–C0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

Y0 Y1

Cb0 Cr0 Cb2

t11

t9

t10

Cb0 Y0 Cr0

Y2

Y3 Y4 Y5

Cr2

t12

Y1

t11

Cb4 Cr4

Cb1 Y2

Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101: SD Oversampled]
[Input Mode 110: HD Oversampled]

CLKIN_B

t12

Y2

Y3 Y4 Y5

CONTROL

INPUTS

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

t10

t9

Y0 Y1

HD INPUT

SD INPUT

PS INPUT

CONTROL

INPUTS

C9–C0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

Cb0 Cr0 Cb2

t11

t9

t10

Cb0 Y0 Cr0

t11

Cr2

Y1

Cb4 Cr4

t12

Cb1 Y2

Figure 9. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode [Input Mode 011]

SD INPUT

REV. A–10–

CONTROL

INPUTS

CONTROL

INPUTS

CONTROL

INPUTS

ADV7310/ADV7311

CLKIN_B

t

t

P_HSYNC,
P_VSYNC,
P_BLANK

Y9–Y0

CLKIN_A

S_HSYNC,
S_VSYNC,
S_BLANK

S9–S0

9

Cb0 Y0 Cr0 Y1

t

12

t

11

t

9

Cb0 Y0 Cr0

Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100]

CLKIN_A

t

t

9

10

S_HSYNC,
S_VSYNC,
S_BLANK

10

PS INPUT

Crxxx Yxxx

t

12

t

11

t

t

10

t

12

12

Y1

t

11

Cb1 Y2

SD INPUT

IN SLAVE MODE

S9–S0/Y9–Y0*

CONTROL
OUTPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000]

t

11

t

13

IN MASTER/SLAVE MODE

t

14

REV. A

–11–

ADV7310/ADV7311

P

CLKIN_A

CONTROL

INPUTS

S_HSYNC,
S_VSYNC,
S_BLANK

t

t

9

10

t

12

IN SLAVE MODE

S9–S0/Y9–Y0*

C9–C0

CONTROL

OUTPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000]

_HSYNC

P_VSYNC

P_BLANK

Y9–Y0

C9–C0

Y0 Y2 Y3

Cb0 Cr0 Cb2 Cr2

t

11

a

Y1

t

13

t

14

IN MASTER/SLAVE MODE

Y0 Y1

Cb0 Cr0 Cr1 Cb1

Y2 Y3

b

a = 16 CLKCYCLES FOR 525p
a = 12 CLKCYCLES FOR 626p
a = 44 CLKCYCLES FOR 1080i @ 30Hz, 25Hz
a = 70 CLKCYCLES FOR 720p
AS RECOMMENDED BY STANDARD

b(MIN) = 122 CLKCYCLES FOR 525p
b(MIN) = 132 CLKCYCLES FOR 625p
b(MIN) = 236 CLKCYCLES FOR 1080i @ 30Hz, 25Hz
b(MIN) = 300 CLKCYCLES FOR 720p

Figure 13. HD 4:2:2 Input Timing Diagram

REV. A–12–

P

_HSYNC

P_VSYNC

P_BLANK

ADV7310/ADV7311

a

Y9–Y0

a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p

Figure 14. PS 4:2:2 1  10-Bit Interleaved Input Timing Diagram

S_HSYNC

S_VSYNC

PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES

S_BLANK

S9–S0/Y9–Y0*

*SELECTED BY ADDRESS 0x01 BIT 7

b

Figure 15. SD Timing Input for Timing Mode 1

Cb Y

Cb Y

PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES

Cr Y

Cr Y

t

3

SDA

t

6

SCLK

t

2

Figure 16. MPU Port Timing Diagram

REV. A

t

5

t

1

t

7

–13–

t

3

t

4

t

8

ADV7310/ADV7311

K

ABSOLUTE MAXIMUM RATINGS*

VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

V

DD

V

to IO_GND . . . . . . . . . . . . –0.3 V to V

DD_IO

Ambient Operating Temperature (T
Storage Temperature (T

) . . . . . . . . . . . . . . .–65°C to +150°C

S

A

) . . . . . . . . . 0°C to 70°C

DD_IO

to +0.3 V

Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . . 260°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

θJC = 11°C/W
θJA = 47°C/W

PIN CONFIGURATION

The ADV7310/ADV7311 is a Pb-free environmentally friendly
product. It is manufactured using the most up-to-date materials
and processes. The coating on the leads of each device is 100%
pure Sn electroplate. The device is suitable for Pb-free applica­tions, and is able to withstand surface-mount soldering at up to
255°C (±5°C).

In addition it is backward compatible with conventional SnPb
soldering processes. This means that the electroplated Sn coating
can be soldered with Sn/Pb solder pastes at conventional reflow
temperatures of 220°C to 235°C.

ORDERING GUIDE*

Package Package

Model Description Option

ADV7310KST Plastic Quad Flat Package ST-64
ADV7311KST Plastic Quad Flat Package ST-64
EVAL-ADV7310EB Evaluation Board
EVAL-ADV7311EB Evaluation Board

*Analog output short circuit to any power supply or common can be of an

indefinite duration.

DD

V

V

DD_IO

V

DGND

P_VSYNC

P_BLANK

P_HSYNC

S4S3S2S1S0

C5C6C7C8C9

GND_IO

CLKIN_BS9S8S7S6S5DGND

1

PIN 1

2

Y0

IDENTIFIER

3

Y1

4

Y2

5

Y3

6

Y4

7

Y5

8

Y6

9

Y7

10

DD

11

12

Y8

13

Y9

14

C0

15

C1

16

C2

C3

ADV7310/ADV7311

TOP VIEW

(Not to Scale)

C

2

C4

I

SDA

ALSB

SCLK

S_HSYNCS_VSYNC

49505152535455565758596061626364

48

S_BLAN

47

R

46

V

45

COMP1

44

DAC A

43

DAC B

42

DAC C

41

V

40

AGND

39

DAC D

38

DAC E

37

DAC F

36

COMP2

35

R

34

EXT_LF

33

RESET

32313029282726252423222120191817

CLKIN_A

RTC_SCR_TR

SET1

REF

AA

SET2

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7310/ADV7311 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. A–14–

ADV7310/ADV7311

PIN FUNCTION DESCRIPTIONS

Mnemonic Input/Output Function

DGND G Digital Ground.

AGND G Analog Ground.

CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz).

CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz

(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.

COMP1,2 O Compensation Pin for DACs. Connect 0.1 F capacitor from COMP pin to V

DAC A O CVBS/Green/Y/Y Analog Output.

DAC B O Chroma/Blue/U/Pb Analog Output.

DAC C O Luma/Red/V/Pr Analog Output.

DAC D O In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Y/Green [HD] Analog Output.

DAC E O In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Pr/Red Analog Output.

DAC F O In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Pb/Blue [HD] Analog Output.

P_HSYNC I Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
P_VSYNC IVideo Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
P_BLANK IVideo Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
S_BLANK I/O Video Blanking Control Signal for SD Only.
S_HSYNC I/O Video Horizontal Sync Control Signal for SD Only.
S_VSYNC I/O Video Vertical Sync Control Signal for SD Only.

Y9–Y0 I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan

data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2.

C9–C0 I Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data.

The LSB is set up on pin C0. For 8-bit data input, LSB is set up on C2.

S9–S0 I SD or Progressive Scan/HDTV Input Port for Cr[Red/V] data in 4:4:4 input mode. LSB is set up

on pin S0. For 8-bit data input, LSB is set up on S2.

RESET I This input resets the on-chip timing generator and sets the ADV7310/ADV7311 into default register

setting. RESET is an active low signal.

R

SET1,2

IA 3040 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes

of the DAC outputs.

SCLK I I

SDA I/O I

ALSB I TTL Address Input. This signal sets up the LSB of the I

V

DD_IO

V

DD

V

AA

V

REF

PPower Supply for Digital Inputs and Outputs.

PDigital Power Supply.

PAnalog Power Supply.

I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

2

C Port Serial Interface Clock Input.

2

C Port Serial Data Input/Output.

2

C filter is activated, which reduces noise on the I2C interface.

the I

2

C address. When this pin is tied low,

EXT_LF I External Loop Filter for the Internal PLL.

RTC_SCR_TR I Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input.

2

I

CI This input pin must be tied high (V

) for the ADV7310/ADV7311 to interface over the I2C port.

DD_IO

GND_IO Digital Input/Output Ground.

AA

.

REV. A

–15–

ADV7310/ADV7311

MPU PORT DESCRIPTION

The ADV7310/ADV7311 support a 2-wire serial (I2C compat­ible) microprocessor bus driving multiple peripherals. Two inputs,
serial data (SDA) and serial clock (SCL), carry information
between any device connected to the bus and the ADV7310/
ADV7311. Each slave device is recognized by a unique address.
The ADV7310/ADV7311 have four possible slave addresses for
both read and write operations. These are unique addresses for
each device and are illustrated in Figure 17. The LSB sets
either a read or write operation. Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation. A1 is
set by setting the ALSB pin of the ADV7310/ADV7311 to
Logic 0 or Logic 1. When ALSB is set to 1, there is greater
input bandwidth on the I
transfers on this bus. When ALSB is set to 0, there is reduced
input bandwidth on the I

2

C lines, which allows high speed data

2

C lines, which means that pulses of
less than 50 ns will not pass into the I2C internal controller.
This mode is recommended for noisy systems.

1 1 0 1 0 1 A1 X

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 17. ADV7310 Slave Address = D4h

0 1 0 1 0 1 A1 X

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 18. ADV7311 Slave Address = 54h

To control the various devices on the bus, the following protocol
must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transi­tion on SDA while SCL remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted address.
The R/W bit determines the direction of the data.

A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.

The ADV7310/ADV7311 acts as a standard slave device on
the bus. The data on the SDA pin is 8 bits long, supporting the
7-bit addresses plus the R/W bit. It interprets the first byte as
the device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.

Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then they cause an
immediate jump to the idle condition. During a given SCL high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7310/ADV7311 will not issue an acknowledge and will return
to the idle condition. If in auto-increment mode the user exceeds
the highest subaddress, the following action will be taken:

1. In read mode, the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read.
A no-acknowledge condition is when the SDA line is not
pulled low on the ninth pulse.

2. In write mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7310/ADV7311, and the part will return to the
idle condition.

Before writing to the subcarrier frequency registers, it is a require­ment that the ADV7310/ADV7311 has been reset at least once
after power-up.

The four subcarrier frequency registers must be updated, starting
with subcarrier frequency register 0 through subcarrier frequency
register 3. The subcarrier frequency will not update until the last
subcarrier frequency register byte has been received by the
ADV7310/ADV7311.

Figure 19 illustrates an example of data transfer for a write
sequence and the start and stop conditions. Figure 20 shows
bus write and read sequences.

SDATA

SCLOCK

S

1–7 8

START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP

9

1–7 8 9

1–7

89

P

Figure 19. Bus Data Transfer

REV. A–16–

WRITE

SEQUENCE

READ

SEQUENCE

ADV7310/ADV7311

S SLAVE ADDR A(S) SUBADDR A(S) DATA A(S) DATA A(S) P

LSB = 0

S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT
P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER

Figure 20. Read and Write Sequence

LSB = 1

A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the
ADV7310/ADV7311 except the subaddress registers, which are
write only registers. The subaddress register determines which
register the next read or write operation accesses. All communi­cations with the part through the bus start with an access to the
subaddress register. A read/write operation is then performed
from/to the target address, which increments to the next address
until a stop command is performed on the bus.

Register Programming

The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless other­wise stated.

Subaddress Register (SR7–SR0)

The communications register is an 8-bit write only register. After
the part has been accessed over the bus and a read/write opera­tion is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.

REV. A

–17–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

Power Mode

00h

01h

Register

Mode Select
Register

Sleep Mode. With this
control enabled, the
current consumption is
reduced to µA level. All
DACs and the internal
PLL cct are disabled. I
registers can be read from
and written to in Sleep
Mode.

PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the over-sampling to be
switched off.

DAC F: Power On/Off

DAC E: Power On/Off

DAC D: Power On/Off

DAC C: Power On/Off

DAC B: Power On/Off

DAC A: Power On/Off

BTA T-1004 or BT.1362
Compatibility

Clock Edge Only for PS interleaved input at

Reserved 0

Clock Align

Input Mode

Y/S Bus Swap 0 10-bit data on S bus

2

C

0 DAC F off

1 DAC F on

0 DAC E off

1 DAC E on

0 DAC D off

1 DAC D on

0 DAC D off

1 DAC C on

0 DAC B off

1 DAC B on

0 DAC A off

1 DAC A on

0

1Must be set if the phase

00 0SD input only 38h

00 1 PS input only

01 0 HDTV input only

01 1SD and PS [20-bit]

10 0SD and PS [10-bit]

10 1SD and HDTV [SD

11 0SD and HDTV [HDTV

11 1 PS only [at 54 MHz]

1 10-bit data on Y bus

0 Sleep Mode off FCh

1 Sleep Mode on

0 PLL on

1 PLL off

0Disabled

1 Enabled

0 Cb clocked on rising edge

1Y clocked on rising edge

delay between the two input
clocks is <9.25 ns or
>27.75 ns.

oversampled]

oversampled]

Register Reset Values
(Shaded)

Only for PS dual edge clk mode

27 MHz

Only if two input clocks are used

SD Mode 10-bit/20-bit Modes

REV. A–18–

ADV7310/ADV7311

1

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

02h Mode Register 0

03h RGB Matrix 0 xxLSB for GY 03h
04h

RGB Matrix 1 x x LSB for RV F0h

05h RGB Matrix 2 x x x x x x x x Bit 9–2 for GY 4Eh
06h RGB Matrix 3 x x x x x x x x Bit 9–2 for GU 0Eh

07h RGB Matrix 4 x x x x x x x x Bit 9–2 for GV 24h
08h RGB Matrix 5 x x x x x x x x Bit 9–2 for BU 92h

09h RGB Matrix 6 x x x x x x x x Bit 9–2 for RV 7Ch
0Ah DAC A, B, C

Output Level

0Bh DAC D, E, F

Output Level

0Ch Reserved 00h

0Dh Reserved 00h
0Eh Reserved 00h

0Fh Reserved 00h

NOTES

1

For more detail, refer to Appendix 7.

2

For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

Reserved 00Zero must be written to

Test Pattern Black Bar

RGB Matrix

Sync on RGB

RGB/YUV Output

SD Sync

HD Sync 0 No Sync output

Positive Gain to DAC Output

2

Voltage

Negative Gain to DAC Output
Voltage

Positive Gain to DAC Output
Voltage

Negative Gain to DAC Output
Voltage

0No Sync output

1Output SD Syncs on

1Output HD Syncs on

xx LSB for GU

000000000% 00h

0000 0001+0.018%

0000 00100.036%

0011 1111+7.382%
0100 0000+7.5%

1100 0000–7.5%

1100 0001–7.382%

1000 0010–7.364%

1111 1111–0.018%
000000000% 00h

0000 0001+0.018%

0000 00100.036%

0011 1111+7.382%
0100 0000+7.5%

1100 0000–7.5%

1100 0001–7.382%

1000 0010–7.364%

1111 1111–0.018%

0No Sync

1 Sync on all RGB outputs
0RGB component outputs

1YUV component outputs

xx LSB for GV

0Disabled
1 Enabled 0x11h, Bit 2

0Disable Programmable

1 Enable Programmable RGB

xx LSB for BU

these bits

RGB matrix

matrix

HSYNC output, VSYNC
output, BLANK output

HSYNC output, VSYNC
output, BLANK output

………

… …….

………

… …….

Reset
Values

20h

must also be
enabled

REV. A

–19–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

HD Mode

10h

Register 1

HD Mode

11h HD Pixel Data Valid 0 Pixel data valid off 00h

Register 2

12h HD Mode

Register 3

HD Output Standard 0 0 EIA770.2 output 00h

HD Input Control Signals 0 0

01 EAV/SAV codes
10 Async Timing Mode

HD 625p 0 525p

HD 720p 0 1080i

HD BLANK Polarity 0

HD Macrovision for
525p/625p

HD Test Pattern Enable 0 HD test pattern off

HD Test Pattern Hatch/Field

HD VBI Open 0 Disabled

HD Undershoot Limiter 0 0 Disabled

HD Sharpness Filter 0 Disabled

HD Y Delay with Respect to
Falling Edge of HSYNC

HD Color Delay with Respect
to Falling Edge of HSYNC

HD CGMS 0 Disabled

HD CGMS CRC

0 Macrovision off

1 Macrovision on

1 Enabled

0 Disabled
1 Enabled

1 720p

1 BLANK active low

01 –11 IRE
10 –6 IRE

11 –1.5 IRE

0000 clk cycles
0011 clk cycle

0102 clk cycles
0113 clk cycles

1004 clk cycles

1 Enabled

11 Reserved

1 625p

0 Hatch

1 Field/frame

1 Enabled

01 EIA770.1 output

10 Output levels for full

11 Reserved

0 Reserved

1 HD test pattern on

0000 clk cycles

0011 clk cycles
0102 clk cycles

0113 clk cycles
1004 clk cycles

input range

HSYNC, VSYNC,
BLANK

BLANK active high

1 Pixel data valid on

Reset
Values

REV. A–20–

ADV7310/ADV7311

g

g

VSYNC

SR7–
SR0 Re

13h HD Cr/Cb Sequence 0 Cb after falling edge of

14h HD Mode

ister Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Settin

HD Mode
Register 4

Register 5

Reserved 00 must be written to this

HD Input Format 0 8-bit input

Sinc Filter on DAC D, E, F

Reserved 0 0 must be written to this

HD Chroma SSAF 0 Disabled

HD Chroma Input 0 4:4:4

HD Double Buffering 0 Disabled

HD Timing Reset xA low-high-low transition

1080i Frame Rate

Reserved 0 0 0 0 0 must be written to these

HD

Lines/Frame

/Field Input 0 0 = Field Input

1

1 Enabled

0 Update field/line counter

1 Enabled

14:2:2

1

1 10-bit input
0Disabled

1 Enabled

00 30 Hz/2200 total

01 25 Hz/2640 total

HSYNC

1Cr after falling edge of

HSYNC

bit

bit

resets the internal HD
timing counters

samples/lines

samples/lines

bits

1 = VSYNC Input

Reset
Values

00h

1Field/line counter free

HD Mode

15h Reserved 00 must be written to this

Register 6

NOTES

1

When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are
free running and wrap around when external sync signals indicate so.

2

Adaptive Filter mode is not available in PS only @ 54 MHz input mode.

HD RGB Input

HD Sync on PrPb

HD Color DAC Swap

HD Gamma Curve A/B

HD Gamma Curve Enable

HD Adaptive Filter Mode

HD Adaptive Filter Enable

0Disabled

1 Enabled
0Disabled

1 Enabled

0 DAC E = Pb;

1 DAC E = Pr;

0 Gamma Curve A
1 Gamma Curve B

0Disabled

2

2

0Disabled
1 Enabled

1 Enabled

0 Mode A
1 Mode B

running

bit

DAC F = Pr

DAC F = Pb

00h

REV. A

–21–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

16h HD Y Level* xxxxxxxxY level value A0h
17h HD Cr Level* xxxxxxxxCr level value 80h

18h HD Cb Level* xxxxxxxxCb level value 80h
19h Reserved 00h

1Ah Reserved 00h
1Bh Reserved 00h

1Ch Reserved 00h
1Dh Reserved 00h

1Eh Reserved 00h
1Fh Reserved 00h

20h HD Sharpness Filter HD Sharpness Filter Gain Value A 0 0 0 0 Gain A = 0 00h

Gain 0001Gain A = +1

HD Sharpness Filter Gain Value B 0 0 0 0 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

21h HD CGMS Data 0 HD CGMS Data Bits 0 0 0 0 C19 C18 C17 C16 CGMS 19–16 00h
22h HD CGMS Data 1 HD CGMS Data Bits C15 C14 C13 C12 C11 C10 C9 C8 CGMS 15–8 00h

23h HD CGMS Data 2 HD CGMS Data Bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS 7–0 00h
24h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A0 00h

25h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A1 00h

26h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A2 00h
27h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A3 00h

28h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A4 00h
29h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A5 00h

2Ah HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A6 00h
2Bh HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A7 00h

2Ch HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A8 00h
2Dh HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A9 00h

2Eh HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B0 00h
2Fh HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B1 00h

30h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B2 00h
31h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B3 00h

32h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B4 00h
33h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B5 00h

34h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B6 00h
35h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B7 00h

36h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B8 00h
37h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B9 00h

.. .. .. .. ……

0111Gain A = +7

1000Gain A = –8

.. .. .. .. ……

1111Gain A = –1

Register
Setting

NOTES
Programmable gamma correction is not available in PS only @ 54 MHz input mode.
*For use with internal test pattern only.

Reset
Values

REV. A–22–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

38h 0 000Gain A = 0 00h

HD Adaptive Filter
Gain 1

39h 0 000Gain A = 0 00h

HD Adaptive Filter
Gain 2

3Ah 0 000Gain A = 0 00h

HD Adaptive Filter
Gain 3

3Bh xxxxxxxxThreshold A 00h

HD Adaptive Filter
Threshold A

3Ch x x x x x x x x Threshold B 00h

HD Adaptive Filter
Threshold B

3Dh x x x x x x x x Threshold C 00h

HD Adaptive Filter
Threshold C

HD Adaptive Filter Gain 1 Value A

HD Adaptive Filter Gain 1 Value B

HD Adaptive Filter Gain 2 Value A

HD Adaptive Filter Gain 2 Value B

HD Adaptive Filter Gain 3 Value A

HD Adaptive Filter Gain 3 Value B

HD Adaptive Filter Threshold A Value

HD Adaptive Filter Threshold B Value

HD Adaptive Filter Threshold C Value

0 001Gain A = +1

.. .. .. .. ……

0 111Gain A = +7

1 000Gain A = –8

.. .. .. .. ……

1 111Gain A = –1
0000 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

0 001Gain A = +1

.. .. .. .. ……

0 111Gain A = +7

1 000Gain A = –8

.. .. .. .. ……

1 111Gain A = –1
0000 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

0 001Gain A = +1

.. .. .. .. ……

0 111Gain A = +7

1 000Gain A = –8

.. .. .. .. ……

1 111Gain A = –1
0000 Gain B = 0

0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7

1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

Register
Setting

Reset
Values

REV. A

–23–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

3Eh Reserved 00h
3Fh Reserved 00h

40h SD Mode Register 0 00NTSC 00h

41h Reserved 00h
42h SD Mode Register 1 SD PrPb SSAF 0 Disabled 08h

43h SD Mode Register 2 SD Pedestal YPrPb Output 0 No pedestal on YUV 00h

SD Standard

SD Luma Filter

SD Chroma Filter

SD DAC Output 1 0

SD DAC Output 2 0

SD Pedestal 0 Disabled

SD Square Pixel 0 Disabled

SD VCR FF/RW Sync 0 Disabled

SD Pixel Data Valid 0 Disabled

SD SAV/EAV Step Edge
Control

SD Output Levels Y 0 Y = 700 mV/300 mV

SD Output Levels PrPb 0 0 700 mV p-p[PAL];

SD VBI Open 0 Disabled

SD CC Field Control 0 0 CC disabled

Reserved 1 Reserved

000 1.3 MHz
001 0.65 MHz

010 1.0 MHz
011 2.0 MHz

100 Reserved
101 Chroma CIF

110 Chroma QCIF
111 3.0 MHz

1 Enabled

0 Disabled
1 Enabled

01 CC on odd field only

10 CC on odd field only
11 CC on both fields

000 LPF NTSC
001 LPF PAL

010 Notch NTSC
011 Notch PAL

100 SSAF Luma
101 Luma CIF

110 Luma QCIF
111 Reserved

1 Enabled

1 Enabled

1 Enabled

01 700 mV p-p
10 1000 mV p-p

11 648 mV p-p

1 Enabled

01PAL B, D, G, H, I

10PAL M
11PAL N

1 Enabled

Refer to output configuration

1

1

1Y = 714 mV/286 mV

section

Refer to output configuration
section

1 7.5 IRE pedestal on YUV

1000 mV p-p[NTSC]

Reset
Values

REV. A–24–

ADV7310/ADV7311

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

SD Mode

44h SD VSYNC-3H 0Disabled 00h

Register 3

SD RTC/TR/SCR 0 0 Genlock disabled

SD Active Video Length 0 720 pixels

SD Chroma 0 Chroma enabled

SD Burst 0 Enabled

SD Color Bars 0 Disabled

SD DAC Swap 0 DAC A = Luma, DAC B =

45h Reserved 00h
46h Reserved 00h

47h SD PrPb Scale 0Disabled 00h

SD Mode
Register 4

SD Y Scale 0Disabled

SD Hue Adjust 0 Disabled

SD Brightness 0 Disabled

SD Luma SSAF Gain 0 Disabled

Reserved 0 0 must be written to this bit

Reserved 0 0 must be written to this bit

48h Reserved 0 00h

SD Mode
Register 5

49h SD Undershoot Limiter 0 0 Disabled 00h

SD Mode
Register 6

Reserved 0 0 must be written to this bit

Reserved 00 must be written to this bit
SD Double Buffering 0 Disabled

SD Input Format 0 0 8-bit Input

SD Digital Noise Reduction 0 Disabled

SD Gamma Control 0 Disabled

SD Gamma Curve 0 Gamma Curve A

Reserved 00 must be written to this bit
SD Black Burst Output on DAC

Luma

SD Chroma Delay 0 0 Disabled

Reserved 0 0 must be written to this bit
Reserved 0 0 must be written to this bit

1 Enabled

1DAC A = Chroma, DAC B =

1 Enabled

1 Gamma Curve B

1 Chroma disabled

1Disabled

1 Enabled

01 16-bit Input

10 10-bit Input
11 20-bit Input

1 Enabled

01 4 clk cycles

10 8 clk cycles
11 Reserved

01 Subcarrier Reset
10 Timing Reset

11 RTC enabled

1 710 [NTSC]/702[PAL]

1 Enabled

1 Enabled

1 Enabled

0Disabled

1 Enabled

1

VSYNC
VSYNC

Chroma

Luma

1 Enabled

1 Enabled

01 – 11 IRE

10 – 6 IRE
11 – 1.5 IRE

= 2.5 lines [PAL]
= 3 lines [NTSC]

Reset
Values

REV. A

–25–

ADV7310/ADV7311

H

SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

SD Timing

4Ah SD Slave/Master Mode 0 Slave Mode 08h

Register 0

SD Timing

4Bh

Register 1

4Ch

SD F

Register 0
4Dh SD F
4Eh

4Fh SD F
50h

51h SD Closed

52h SD Closed

53h SD Closed

54h SD Closed

55h SD Pedestal

56h SD Pedestal

57h SD Pedestal

58h SD Pedestal

SC

Register 1

SC

SD F

Register 2

SC

Register 3

SC

SD F

Phase

SC

Captioning

Captioning

Captioning

Captioning

Register 0

Register 1

Register 2

Register 3

SD Timing Mode 0 0 Mode 0

SD BLANK Input

SD Luma Delay 0 0 No delay

SD Min. Luma Value 0 – 40 IRE

SD Timing Reset x 0 0 00000A low-high-low transition will reset

SD HSYNC Width

SD HSYNC to VSYNC delay

SD HSYNC to VSYNC Rising
Edge Delay [Mode 1 Only]

VSYNC Width [Mode 2 Only]

HSYNC to Pixel Data Adjust

Extended Data on Even Fields x x x xxxxxExtended Data Bit 7–0 00h

Extended Data on Even Fields x x x xxxxxExtended Data Bit 15–8 00h

Data on Odd Fields x x x xxxxxData Bit 7–0 00h

Data on Odd Fields x x x xxxxxData Bit 15–8 00h

Pedestal on Odd Fields 17 16 15 14 13 12 11 10 00h

Pedestal on Odd Fields 25 24 23 22 21 20 19 18 00h

Pedestal on Even Fields 17 16 15 14 13 12 11 10 00h

Pedestal on Even Fields 25 24 23 22 21 20 19 18 00h

00 0 clk cycles

01 1 clk cycle
10 2 clk cycles

11 3 clk cycles
xxxxxxxxSubcarrier Frequency Bit 7–0 16h

xxxxxxxxSubcarrier Frequency Bit 15–8 7Ch
xxxxxxxxSubcarrier Frequency Bit 23–16 F0h

xxxxxxxxSubcarrier Frequency Bit 31–24 21h
xxxxxxxxSubcarrier Phase Bit 9–2 00h

01 2 clk cycles

10 4 clk cycles
11 6 clk cycles

1– 7.5 IRE

x0 Tc = Tb

x1 Tc = Tb + 32 us
00 1 clk cycle

01 4 clk cycles
10 16 clk cycles

11 128 clk cycles

01 Mode 1

10 Mode 2
11 Mode 3

0 Enabled
1 Disabled

00 Tb = 0 clk cycle

01 Tb = 4 clk cycles
10 Tb = 8 clk cycles

11 Tb = 18 clk cycles

1 Master Mode

00 Ta = 1 clk cycle 00h

01 Ta = 4 clk cycles
10 Ta = 16 clk cycles

11 Ta = 128 clk cycles

the internal SD timing counters

Setting any of these bits to 1 will
disable pedestal on the line number
indicated by the bit settings

Reset
Values

LINE 313 LINE 314LINE 1

SYNC

VSYNC

t

A

t

t

B

C

Figure 21. Timing Register 1 in PAL Mode

REV. A–26–