Analog Devices ADV7302A 3A a Datasheet

Multiformat SD, Progressive Scan/HDTV

a

FEATURES
High Definition Input Formats

YCrCb Compliant to SMPTE293M (525 p),

ITU-R.BT1358 (625 p), SMPTE274M (1080 i),
SMPTE296M (720 p), and Any Other High Definition

Standard Using Async Timing Mode
RGB in 3 ⴛ 8-Bit 4:4:4 Format
BTA T-1004 EDTV2 525 p Parallel

High Definition Output Formats (525 p/625 p/720 p/1080 i)

YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB + H/V (HDTV 5-Wire Format)
CGMS-A (720 p/1080 i)
Macrovision Rev 1.0 (525 p/625 p)*

CGMS-A (525 p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-Bit Parallel Input
CCIR-601 4:2:2 16-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M, N;

PAL M, N, B, D, G, H, I, PAL-60
SMPTE170M NTSC Compatible Composite Video
ITU-R.BT470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YUV (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1*

CGMS/WSS

Closed Captioning

GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling (108 MHz/148.5 MHz)
On-Board Voltage Reference
6 Precision Video 11-Bit DACs
2-Wire Serial MPU Interface
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-LQFP Package
Lead-Free Product

Video Encoder with Six 11-Bit DACs

ADV7302A/ADV7303A

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

PROGRAMMABLE

RGB MATRIX

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

S7–S0

Y7–Y0
C7–C0

S_HSYNC
S_VSYNC

S_BLANK

P_HSYNC
P_VSYNC

P_BLANK

CLKIN_A
CLKIN_B

D
E
M
U
X

D
E
M
U
X

TIMING

GENERATOR

PLL

GENERAL DESCRIPTION

The ADV7302A/ADV7303A is a high speed, digital-to-analog
encoder on a single monolithic chip. It includes six high speed
video D/A converters with TTL compatible inputs.

The ADV7302A/ADV7303A has three separate 8-bit wide input
ports that accept data in high definition and/or standard defini­tion video format. For all standards, external horizontal, vertical,
and blanking signals, or EAV/SAV timing codes, control the
insertion of appropriate synchronization signals into the digital
data stream and therefore the output signals.

ADV7302A/

ADV7303A

11-BIT

DAC

11-BIT

O

DAC

V
E
R

11-BIT

S

DAC

A
M

11-BIT

P

DAC

L

I

N

11-BIT

G

DAC

11-BIT

DAC

I2C

INTERFACE

APPLICATIONS
DVD Players
SD/HD Display Devices
SD/HD Set-Top Boxes
SD/HDTV Studio Equipment

*ADV7302A Only

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADV7302A/ADV7303A

P
P

DETAILED FEATURES
High Definition Programmable Features (720 p/1080 i)

2 Oversampling (148.5 MHz)
Internal Test Pattern Generator (Color Hatch, Black

Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control

CGMS-A (720 p/1080 i)

High Definition Programmable Features (525 p/625 p)

4 Oversampling (108 MHz Output)
Internal Test Pattern Generator (Color Hatch, Black

Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter

HD PIXEL

INPUT

CLKIN_B

DE­INTER­LEAVE

CR

CB

Y

TEST

PATTERN

SHARPNESS

AND

ADAPTIVE

FILTER

CONTROL

Y COLOR
CR COLOR
CB COLOR

Macrovision Rev 1.0 (525 p/625 p)*
CGMS-A (525 p)

Standard Definition Programmable Features

8 Oversampling (108 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and UV Output Delay
Gamma Correction
Digital Noise Reduction
Multiple Chroma and Luma Filters
Luma-SSAF

™

Filter with Programmable Gain/

Attenuation
UV SSAF
Separate Pedestal Control on Component and

Composite/S-Video Outputs
VCR FF/RW Sync Mode

Macrovision Rev 7.1*
CGMS/WSS
Closed Captioning

DAC

4:2:2

TO

4:4:4

PS 4

HDTV 2

DAC

_HSYNC
_VSYNC

P_BLANK

S_HSYNC
S_VSYNC
S_BLANK

CLKIN_A

SD PIXEL

INPUT

DE­INTER­LEAVE

TIMING

GENERATOR

TIMING

GENERATOR

CB

CR

Y

TEST

PATTERN

DNR

GAMMA

COLOR

CONTROL

CLOCK

CONTROL

AND PLL

SYNC

INSER-

TION

U

V

UV SSAF

LUMA

AND

CHROMA

FILTERS

RGB

MATRIX

2 OVER-

SAMPLING

SD 8

CGMS

WSS

FSC

MODULATION

DAC

DAC

DAC

DAC

Figure 1. Functional Block Diagram

TERMS USED IN THIS DATA SHEET

SD Standard Definition Video, conforming to

ITU-R.BT601/ITU-R.BT656.

HD High Definition Video, i.e., Progressive Scan or HDTV.

PS Progressive Scan Video, conforming to SMPTE293M

or ITU-R.BT1358.

HDTV High Definition Television Video, conforming to

SMPTE274M or SMPTE296M.

YCrCb SD or HD Component Digital Video

YPrPb HD Component Analog Video

YUV SD Component Analog Video

SSAF is a trademark of Analog Devices, Inc.

*ADV7302A Only

REV. A–2–

ADV7302A/ADV7303A–SPECIFICATIONS

(VAA = VDD = 2.375 V–2.625 V, V

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution 11 Bits
Integral Nonlinearity ±1.0 LSB V
Differential Nonlinearity, +ve
Differential Nonlinearity, –ve

DIGITAL OUTPUTS

Output Low Voltage, V
Output High Voltage, V
Three-State Leakage Current ±1.0 µAV
Three-State Output Capacitance 2 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Leakage Current 1 µAV
Input Capacitance, C

ANALOG OUTPUTS

Full-Scale Output Current 8.2 8.7 9.2 mA
Output Current Range 8.2 8.7 9.2 mA
Full-Scale Output Current 4.1 4.35 4.6 mA R
Output Current Range 4.1 4.35 4.6 mA R
DAC to DAC Matching 2.0 %
Output Compliance Range, V
Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

REF

POWER REQUIREMENTS

Normal Power Mode

4

I

DD

I

DD_IO

5, 6

I

AA

Sleep Mode

I

DD

I

AA

I

DD_IO

Power Supply Rejection Ratio 0.01 %/%

NOTES

1

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

2

DNL measures the deviation of the actual DAC o/p voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL, the
actual step values lie below the ideal step value.

3

Value in brackets for V

4

IDD or the circuit current is the continuous current required to drive the digital core without the I

5

IAA is the total current required to supply all DACs including the V

6

All DACs on.

Specifications subject to change without notice.

= 2.375 V to 2.750 V.

DD_IO

= 2.375 V–3.600 V, V

DD_IO

1

2

2

OL

OH

IH

IL

IN

OC

OUT

= 1.235 V, R

REF

= 760 , R

SET

= 150 , T

LOAD

MIN

to T

(0C to 70C), unless otherwise noted.)

MAX

= 2.5 V

AA

0.125 LSB VAA = 2.5 V

1.0 LSB VAA = 2.5 V

2.4 [2.0]

3

0.4 [0.4]3VI
VI

= 3.2 mA

SINK

= 400 µA

SOURCE

= 0.4 V, 2.4 V

IN

2V

0.8 V

= 2.4 V

IN

2pF

= 1520 Ω

SET1, 2

= 1520 Ω

SET1, 2

0 1.0 1.4 V

7pF

1.15 1.235 1.3 V

93 mA SD Only [8⫻]
52 mA PS Only [4⫻]
84 mA HDTV Only [2⫻]
90 110 mA SD and PS
99 mA SD [8⫻] and HDTV
108 mA SD and HDTV [2⫻]

0.2 mA
70 75 mA
37 45 mA R

SET1, 2

= 1520 Ω

130 µA
10 µA
110 µA

.

circuitry and the PLL circuitry.

REF

PLL

REV. A –3–

ADV7302A/ADV7303A

(VAA = VDD = 2.375 V–2.625 V, V

DYNAMIC SPECIFICATIONS

Parameter Min Typ Max Unit Test Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth 12.5 MHz
Chroma Bandwidth 5.8 MHz
SNR 59 dB Luma Ramp Unweighted
SNR 75 dB Flat Field up to 5 MHz
SNR 70 dB Flat Field Full Bandwidth

HDTV MODE

Luma Bandwidth 30 MHz
Chroma Bandwidth 13.75 MHz
SNR 59 dB Luma Ramp Unweighted
SNR 75 dB Flat Field up to 5 MHz
SNR 70 dB Flat Field Full Bandwidth

STANDARD DEFINITION MODE

Hue Accuracy 0.2 Degrees
Color Saturation Accuracy 0.54 %
Chroma Nonlinear Gain ±0.4 % Referenced to 40 IRE
Chroma Nonlinear Phase ±0.3 Degrees
Chroma/Luma Intermod ±0.05 %
Chroma/Luma Gain Ineq ±98 %
Chroma/Luma Delay Ineq 0.9 ns
Luminance Nonlinearity ±0.4 %
Chroma AM Noise 84 dB
Chroma PM Noise 74 dB
Differential Gain 0.6 % NTSC
Differential Phase 1.4 Degrees NTSC
SNR 59 dB Luma Ramp
SNR 75 dB Flat Field up to 5 MHz
SNR 70 dB Flat Field Full Bandwidth

Specifications subject to change without notice.

R

= 150 , T

LOAD

MIN

to T

(0C to 70C), unless otherwise noted.)

MAX

= 2.375 V–3.600 V, V

DD_IO

= 1.235 V, R

REF

= 760 ,

SET

REV. A–4–

ADV7302A/ADV7303A

TIMING SPECIFICATIONS

(VAA = VDD = 2.375 V–2.625 V, V
T

to T

MIN

(0C to 70C), unless otherwise noted.)

MAX

= 2.375 V–3.600 V, V

DD_IO

= 1.235 V, R

REF

= 760 , R

SET

Parameter Min Typ Max Unit Test Conditions

MPU PORT

1

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t

1

2

3

0.6 µs

1.3 µs

0.6 µs First Clock Generated After

This Period

Setup Time (Start Condition), t

4

0.6 µsRelevant for Repeated Start

Condition
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

5

6

7

8

100 ns

300 ns
300 ns

0.6 µs

RESET Low Time 100 ns

ANALOG OUTPUTS

Analog Output Delay

2

8ns

Output Skew 1 ns

CLOCK CONTROL AND PIXEL PORT

f

CLK

f

CLK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Output Access Time, t
Output Hold Time, t

9

10

11

1

12

13

14

3

27 MHz Progressive Scan Mode

81 MHz HDTV Mode/Async Mode
40 % 1 clkcycle
40 % 1 clkcycle

2.0 ns

2.0 ns

14 ns

4.0 ns

Pipeline Delay 61 clkcycles SD [2⫻]

62.5 clkcycles SD [8⫻]

66.5 clkcycles SD Component Filter [8⫻]

33 clkcycles PS [1⫻], HD [1⫻], Async

Timing Mode

43.5 clkcycles PS [4⫻]

36 clkcycles HD [2⫻]

NOTES

1

Guaranteed by characterization.

2

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3

Data: C[7:0]; S[7:0]; Y[7:0]
Control: P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK

Specifications subject to change without notice.

= 150 ,

LOAD

REV. A

–5–

ADV7302A/ADV7303A

CLKIN_A

I/PS

P_HSYNC,
P_VSYNC,

P_BLANK

CONTROL

t

t

t

9

10

12

CONTROL

t

= CLOCK HIGH TIME,

9

O/PS

S_HSYNC,

S_VSYNC

Y7–Y0

C7–C0

t

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

t

11

= CLOCK LOW TIME,

10

t

= DATA SETUP TIME,

11

t

= DATA HOLD TIME

12

t

13

t

14

Figure 2. HD 4:2:2 Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV
Input Only (Input Mode at Subaddress 01h = 001 or 010)

CLKIN_A

t9

t10

Y0 Y1 Y2 Yxxx Yxxx

Cb0 Cb1 Cb2 Cb3 Cbxxx Cbxxx

Cr0 Cr1 Cr2 Cr3 Crxxx Crxxx

t12

t13

CONTROL

I/PS

P_HSYNC,
P_VSYNC,

P_BLANK

Y7–Y0

C7–C0

S7–S0

t11

CONTROL

t

= CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME

9

O/PS

S_HSYNC,

S_VSYNC

t14

Figure 3. HD 4:4:4 YCrCb Input Data Format Timing Diagram, Input Mode: PS Input Only,
HDTV Input Only (Input Mode at Subaddress 01h = 001 or 010)

REV. A–6–

CONTROL

I/PS

CLKIN_A

P_HSYNC,
P_VSYNC,

P_BLANK

t9

ADV7302A/ADV7303A

t10

Y7–Y0

C7–C0

S7–S0

t11

CONTROL

t

= CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME

9

O/PS

S_HSYNC,

S_VSYNC

G0 G1 G2 Gxxx Gxxx

B0 B1 B2 B3 Bxxx Bxxx

R0 R1 R2

t12

G3

Rxxx Rxxx

t13

t14

Figure 4. HD 4:4:4 RGB Input Data Format Timing Diagram, HD RGB Input Enabled (Input
Mode at Subaddress 01h = 001 or 010)

CLKIN_B

t

t

10

t

11

t

= DATA SETUP TIME,

11

t

12

t

13

t

14

t

= DATA HOLD TIME

12

I/PS

O/PS

P_HSYNC,
P_VSYNC,

P_BLANK

S_HSYNC,

S_VSYNC

CONTROL

CONTROL

t

= CLOCK HIGH TIME,

9

Y7–Y0

t

= CLOCK LOW TIME,

10

9

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

t

12

t

11

Figure 5. PS 4:2:2 1 ⫻ 8-Bit Interleaved @ 27 MHz, Input Mode: PS Input Only (Input
Mode at Subaddress 01h = 100)

REV. A

–7–

ADV7302A/ADV7303A

CLKIN_A

I/PS

P_HSYNC,
P_VSYNC,

P_BLANK

CONTROL

t10

t9

CONTROL

I/PS

CONTROL

O/PS

Y7–Y0

CONTROL

t

= CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME

9

O/PS

S_HSYNC,

S_VSYNC

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

t11

t12

t13

t14

Figure 6. PS 4:2:2 1 ⫻ 8-Bit Interleaved @ 54 MHz, Input Mode: PS 54 MHz Input (Input
Mode at Subaddress 01h = 111)

CLKIN_A

t

t

S_HSYNC,
S_VSYNC,

S_BLANK

S7–S0

S_HSYNC,

S_VSYNC

9

10

Cb Y Cr Y Cb Y

t

12

t

11

t

13

t

14

IN SLAVE
MODE

IN MASTER/SLAVE
MODE WITH
EAV/SAV

Figure 7. 8-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)

REV. A–8–

CONTROL

I/PS

CLKIN_A
@ 27MHz

S_HSYNC,
S_VSYNC,

S_BLANK

ADV7302A/ADV7303A

t

t

t

9

10

12

IN SLAVE
MODE

Y0 Y1 Y2 Y3

Cb0 Cr0 Cb2 Cr2

t

11

t

13

t

14

IN MASTER/SLAVE
MODE WITH
EAV/SAV

CONTROL

O/PS

S7–S0

Y7–Y0

S_HSYNC,

S_VSYNC

Figure 8. 16-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)

CLKIN_B

t

12

Y2

t

11

Y3 Y4 Y5

Cr2

t

12

Cb4 Cr4

HD INPUT

SD INPUT

CONTROL

I/PS

CONTROL

I/PS

P_HSYNC,
P_VSYNC,

P_BLANK

Y7–Y0

C7–C0

CLKIN_A

S_HSYNC,
S_VSYNC,

S_BLANK

t

t

10

9

Y0 Y1

Cb0 Cr0 Cb2

t

t

9

10

S7–S0

Cb0 Y0 Cr0

Y1

t

11

Cb1 Y2

Figure 9. SD and HD Simultaneous Input, Input Mode: SD and PS 16-Bit or SD and HDTV (Input Mode at
Subaddress 01h = 011, 101, or 110)

REV. A

–9–

ADV7302A/ADV7303A

CLKIN_B

t10

t9

I/PS

I/PS

P_HSYNC,
P_VSYNC,

P_BLANK

CLKIN_A

S_HSYNC,
S_VSYNC,

S_BLANK

P_HSYNC

Y7–Y0

S7–S0

Cb0 Y0 Cr0 Y1

t12

t11

t9

t10

Cb0 Y0 Cr0

t11

t12

t11

Crxxx Yxxx

t12

Y1

PS INPUT

SD INPUT

Cb1 Y2

CONTROL

CONTROL

Figure 10. SD and HD Simultaneous Input, Input Mode: SD and PS 8-Bit (Input Mode at Subaddress 01h = 100)

P_VSYNC

a

P_BLANK

Y7–Y0

b

a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p

Figure 11. PS 4:2:2 1 ⫻ 8-Bit Interleaved @ 54 MHz Input Timing Diagram

Cb Y

Cr Y

REV. A–10–

P_HSYNC

H

B

P_VSYNC

P_BLANK

ADV7302A/ADV7303A

a

Y7–Y0

S7–S0

C7–C0

a = 16 CLKCYCLES FOR 525p
a = 12 CLKCYCLES FOR 626p
a = 44 CLKCYCLES FOR 1080i
a = 70 CLKCYCLES FOR 720p
AS RECOMMENDED BY STANDARD

SYNC

FIELD

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

LANK

PIXEL
DATA

b

b(MIN) = 122 CLKCYCLES FOR 525p
b(MIN) = 132 CLKCYCLES FOR 625p
b(MIN) = 236 CLKCYCLES FOR 1080i
b(MIN) = 300 CLKCYCLES FOR 720p

Figure 12. HD Input Timing Diagram

Y0 Y1

Cr0 Cr1 Cr2 Cr3

Cb0 Cb1 Cb2 Cb3

Cb Y

Y2 Y3

Cr Y

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Figure 13. SD Timing Input for Timing Mode 1

t

3

t

4

t

8

SDA

SCLK

t

3

t

6

t

2

t

5

t

1

t

7

Figure 14. MPU Port Timing Diagram

REV. A

–11–

ADV7302A/ADV7303A

ABSOLUTE MAXIMUM RATINGS*

VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

DD

to IO_GND . . . . . . . . . . . . . –0.3 V to V

V

DD_IO

Ambient Operating Temperature (T
Storage Temperature (T

) . . . . . . . . . . . . . . –65°C to +150°C

S

A

) . . . . . . . 0°C to +70°C

DD_IO

+ 0.3 V

Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . . 260°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

The ADV7302A/ADV7303A is a lead-free environmentally
friendly product. It is manufactured using the most up-to-date
materials and processes. The coating on the leads of each device
is 100% pure tin electroplate. The device is suitable for lead-free
applications and is able to withstand surface-mount soldering at
up to 255°C (±5°C). In addition, it is backward compatible with
conventional tin-lead soldering processes. This means that the
electroplated tin coating can be soldered with tin-lead solder
pastes at conventional reflow temperatures of 220°C to 235°C.

device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

θJC = 11°C/W

= 47°C/W

θ

JA

Model Package Description Package Option

ADV7302AKST Plastic Quad Flatpack ST-64B
ADV7303AKST Plastic Quad Flatpack ST-64B

ORDERING GUIDE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7302A/ADV7303A features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATION

DD

V

S2S1S0

GND_IO

GND_IO

S_HSYNC

S_VSYNC

49505152535455565758596061626364

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32313029282726252423222120191817

CLKIN_A

RTC_SCR_TR

S_BLANK

R

SET1

V

REF

COMP1

DAC A

DAC B

DAC C

V

AA

AGND

DAC D

DAC E

DAC F

COMP2

R

SET2

EXT_LF

RESET

V

DD_IO

GND_IO

GND_IO

V

DGND

GND_IO

GND_IO

GND_IO

CLKN_BS7S6S5S4S3DGND

1

PIN 1

2

IDENTIFIER

3

4

Y0

5

Y1

6

Y2

7

Y3

8

Y4

9

Y5

10

DD

11

12

Y6

13

Y7

14

15

16

C0

ADV7302A/ADV7303A

(Not to Scale)

C

2

C1

C2

I

SDA

ALSB

SCLK

TOP VIEW

P_VSYNC

P_HSYNC

C3C4C5C6C7

P_BLANK

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Input/Output Function

1V

DD_IO

PPower Supply for Digital Inputs and Outputs

4–9, 12, 13 Y0–Y7 I 8-Bit Progressive Scan/HDTV Input Port for Y Data. The LSBs are set up on

Pins Y0 and Y1. In default mode, the input on this port is output on DAC D.

16–18, 26–30 C0–C7 I 8-Bit Progressive Scan/HDTV Input Port for CrCb Color Data in 4:2:2 Input

Mode. In 4:4:4 Input Mode, this input port is used for the Cb (Blue/U) data.
The LSBs are set up on Pins C0 and C1. In default mode, the input on this
port is output on DAC E.

REV. A–12–

ADV7302A/ADV7303A

Pin No. Mnemonic Input/Output Function

19 I

20 ALSB I/O TTL Address Input. This signal sets up the LSB of the MPU address. When

21 SDA I/O MPU Port Serial Data Input/Output

22 SCLK I MPU Port Serial Interface Clock Input
23 P_HSYNC IVideo Horizontal Sync Control Signal for HD Sync in Simultaneous SD/HD

24 P_VSYNC IVideo Vertical Sync Control Signal for HD Sync in Simultaneous SD/HD

25 P_BLANK I Video Blanking Control Signal for HD Sync in Simultaneous SD/HD Mode

31 RTC_SCR_TR I Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input,

32 CLKIN_A I Pixel Clock Input for HD Only or SD Only Modes
33 RESET IThis input resets the on-chip timing generator and sets the ADV7302A/

34 EXT_LF I External Loop Filter for the internal PLL

35, 47 R

36, 45 COMP2, 1 O Compensation Pin for DACs. Connect 0.1 µF Capacitor from COMP Pin to V

37 DAC F O In SD Only Mode: Chroma/Red/V Analog Output, in HD Only Mode and

38 DAC E O In SD Only Mode: Luma/Blue/U Analog Output, in HD Only Mode and

39 DAC D O In SD Only Mode: CVBS/Green/Y Analog Output, in HD Only Mode and

40 AGND G Analog Ground

41 V

42 DAC C O Chroma/Red/V SD Analog Output

43 DAC B O Luma/Blue/U SD Analog Output

44 DAC A O CVBS/Green/Y SD Analog Output

46 V

48 S_BLANK I/O Video Blanking Control Signal for SD
49 S_VSYNC I/O Video Vertical Control Signal for SD. Option to output SD VSYNC or SD

50 S_HSYNC I/O Video Horizontal Control Signal for SD. Option to output SD HSYNC or

53–55, 58–62 S0–S7 I 8-Bit Standard Definition Input Port or Progressive Scan/HDTV Input Port

10, 56 V

11, 57 DGND G Digital Ground

63 CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan

2, 3, 14, 15, GND_IO Digital Ground
51, 52, 64

REV. A

2

CI This input pin must be tied high (V

interface over the I

this pin is tied low, the I

2

C port.

2

C filter is activated, which reduces noise on the I2C

interface.

Mode and HD Only Mode

Mode and HD Only Mode

and HD Only Mode

and Subcarrier Reset Input

ADV7303A into default register setting. Reset is an active low signal.

SET2, 1

IA 760 Ω resistor must be connected from this pin to AGND and is used to

control the amplitudes of the DAC outputs.

Simultaneous HD/SD: Pr/Red (HD) Analog Output

Simultaneous HD/SD: Pb/Blue (HD) Analog Output

Simultaneous HD/SD: Y/Green (HD) Analog Output

AA

REF

PAnalog Power Supply

I/O Optional External Voltage Reference Input for DACs or Voltage Reference

Output (1.235 V)

HSYNC in SD Slave Mode 0 and/or any HD Mode.

HD HSYNC in SD Slave Mode 0 and/or any HD Mode.

for Cr (Red/V) color data in 4:4:4 Input Mode. The LSBs are set up on Pins
S0 and S1. In Default Mode, the input on this port is output on DAC F.

DD

PDigital Power Supply

Mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV Mode. This
clock input pin is only used in Simultaneous SD/HD Mode.

–13–

) for the ADV7302A/ADV7303A to

DD_IO

AA

.

ADV7302A/ADV7303A

MPU PORT DESCRIPTION

The ADV7302A/ADV7303A supports a 2-wire serial (I2C com­patible) microprocessor bus driving multiple peripherals. Two
inputs, Serial Data (SDA) and Serial Clock (SCL), carry infor­mation between any device connected to the bus. Each slave
device is recognized by a unique address. The ADV7302A/
ADV7303A has four possible slave addresses for both read and
write operations. These are unique addresses for each device and
are illustrated in Figures 15 and 16. The LSB sets either a read or
write operation. Logic Level “1” corresponds to a read operation,
while Logic Level “0” corresponds to a write operation. A1 is set
by setting the ALSB Pin of the ADV7302A/ADV7303A to Logic
Level “0” or Logic Level “1.” When ALSB is set to “1,” there is
greater input bandwidth on the I
speed data transfers on this bus. When ALSB is set to “0,” there
is reduced input bandwidth on the I
pulses of less than 50 ns will not pass into the I

2

C lines, which allows high

2

C lines, which means that

2

C internal con-

troller. This mode is recommended for noisy systems.

1 1 0 1 0 1 A1 X

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 15. ADV7302A Slave Address = D4h

0 1 0 1 0 1 A1 X

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 16. ADV7303A Slave Address = 54h

To control the various devices on the bus, the following protocol
must be followed. First, the master initiates a data transfer by estab­lishing a start condition, defined by a high-to-low transition on
SDA, while SCLK remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start condition
and shift the next eight bits (7-bit address + R/W Bit). The bits
are transferred from MSB down to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
Acknowledge Bit. All other devices withdraw from the bus at this
point and maintain an idle condition. The idle condition is where
the device monitors the SDA and SCLK lines waiting for the
start condition and the correct transmitted address. The R/W
Bit determines the direction of the data.

A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.

The ADV7302A/ADV7303A acts as a standard slave device on
the bus. The data on the SDA Pin is eight bits long, supporting
the 7-bit addresses plus the R/W Bit. It interprets the first byte
as the device address and the second byte as the starting
subaddress. The subaddress’s autoincrement allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers.

Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, it will cause an imme­diate jump to the idle condition. During a given SCLK high period,
the user should issue only one start condition, one stop condi­tion, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7302A/ADV7303A will not issue an acknowledge and will
return to the idle condition. If in Autoincrement Mode the user
exceeds the highest subaddress, the following action will be taken:

1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no­acknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the ninth
pulse.

2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7302A/ADV7303A, and the part will
return to the idle condition.

Before writing to the subcarrier frequency registers, it is a require­ment that the ADV7302A/ADV7303A has been reset at least
once since power-up.

The four Subcarrier Frequency Registers must be updated
starting with Subcarrier Frequency Register 0. The subcarrier
frequency will not update until the last subcarrier frequency
register byte has been received by the ADV7302A/ADV7303A.

Figure 17 illustrates an example of data transfer for a read sequence
and the start and stop conditions.

Figure 18 shows bus write and read sequences.

SDATA

SCLOCK

S

1–7 8

START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP

9

1–7 8 9

1–7

89

P

Figure 17. Bus Data Transfer

REV. A–14–

WRITE

SEQUENCE

READ

SEQUENCE

ADV7302A/ADV7303A

S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P

LSB = 0 LSB = 1

S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT
P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER

Figure 18. Read and Write Sequence

A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the
ADV7302A/ADV7303A except the subaddress registers that are
write-only registers. The subaddress register determines which
register the next read or write operation accesses. All communica­tions with the part through the bus start with an access to the
subaddress register. Then a read/write operation is performed
from/to the target address which then increments to the next
address until a stop command on the bus is performed.

REGISTER PROGRAMMING

The following section describes the functionality of each regis­ter. All registers can be read from as well as written to, unless
otherwise stated.

Subaddress Register (SR7–SR0)

The Communications Register is an 8-bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation
takes place.

Register Select (SR7–SR0)

These bits are set up to point to the required starting address.

REV. A

–15–

ADV7302A/ADV7303A

C

C

/Off

C

Off

p

Table I. Power Mode Register

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

00h Power Mode Register Sleep Mode

PLL and Oversampling
Control

DAC F: Power On/Off 0 DAC F Off

DA

DAC D: Power On/Off 0 DAC D Off

DAC C: Power On/Off 0 DAC C Off

DAC B: Power On/Off 0 DAC B Off

DAC A: Power On/Off 0 DAC A Off

NOTES

1

When enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled. I2C registers can be read from and written to.

2

This control allows the internal PLL circuit to be powered down and the oversampling to be switched off.

1

2

E: Power On

0 Sleep Mode Off

1 Sleep Mode On

0 PLL On

1 PLL Off

1DA

0DA

1 DAC E On

1 DAC D On

1 DAC C On

1 DAC B On

1 DAC A On

F On

E

Fch

Table II. Input Mode Register

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

01h Input Mode Register 0 Disabled 38h

BTA T-1004 Compatibility

1 Enabled

Reserved 0 Zero must be written

Pixel Align

Clock Align

Input Mode

Reserved 0 Zero must be written

000 SD Input Only

001 PS Input Only

010 HDTV Input Only

011 SD and PS (16-Bit)

100 SD and PS (8-Bit)

101 SD and HDTV (SD

110 SD and HDTV

111 PS 54 MHz Input

0 Video input data starts

1 Video input data starts

0

1 Must be set if the

to this bit.

with a Y0 bit. Only for
PS Interleaved Mode.

with a Cb0 bit.

phase delay between
the two input clocks is
<9.25 ns or >27.75 ns.
Only if two input
clocks are used.

led)

Oversam

(HDTV Oversampled)

to this bit.

REV. A–16–

Table III. Mode Register

p

p

p

ADV7302A/ADV7303A

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R egister Setting

02h Mode Register 0 Reserved 0 0 Zero must be written

Test Pattern Black Bar

RGB Matrix

SYNC on RGB

RGB/YUV Output

SD SYNC

HD SYNC

03h RGB Matrix 0 XXLSB for GY 03h

04h RGB Matrix 1 XXLSB for RV F0h

05h RGB Matrix 2 XXXXXXXXBits 9–2 for GY 4Eh

06h RGB Matrix 3 XXXXXXXXBits 9–2 for GU 0 Eh

07h RGB Matrix 4 XXXXXXXXBits 9–2 for GV 24h

08h RGB Matrix 5 XXXXXXXXBits 9–2 for BU 92h

09h RGB Matrix 6 XXXXXXXXBits 9–2 for RV 7Ch

0Ah Reserved 00h

0Bh Reserved 00h

0Ch Reserved 00h

0Dh Reserved 00h

0Eh Reserved 00h

0Fh Reserved 00h

0 No SYNC Output

1 Output SD SYNCs on

0 No SYNC Output

1 Output HD SYNCs

XX LSB for GU

0No SYNC

1 SYNC on all RGB

0 RGB Component

1YUV Component

XX LSB for GV

0Disabled

1 Enabled. 0x11h, Bit 2

0 Disable Programmable

1 Enable Programmable

XX LSB for BU

to these bits.

must also be enabled.

RGB Matrix

RGB Matrix

uts

Out

uts

Out

uts

Out

S_HSYNC and
S_VSYNC

on S_HSYNC and
S_VSYNC

Reset

20h

REV. A

–17–

ADV7302A/ADV7303A

Subaddress Reg ister Bit Descr iption Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

10h HD Mode Register 1 00EIA770.2 Output 00h

11h HD Mode Register 2 0Pixel Data Valid Off 00h

12h HD Mode Register 3 0 0 0 0 Clock Cycle

Table IV. HD Mode Register

HD Output Standard

HD Input Control Signals

HD 625 p

HD 720 p

HD BLANK Polarity

HD Macrovision for
525 p/625 p

HD Pixel Data Valid

HD Test Pattern Enable

HD Test Pattern
Hatch/Field

HD VBI Open

HD Undershoot Limiter

HD Sharpness Filter

HD Y Delay wrt Falling
Edge of HSYNC

HD Color Delay wrt
Falling Edge of HSYNC

HD CGMS

HD CGMS CRC

01EIA770.1 Output

10Output Levels for Full

11Reserved

00

01 EAV/SAV Codes

10 Async Timing Mode

11 Reserved

0 525 p

1 625 p

0 1080 i

1 720 p

0BLANK Active High

1BLANK Active Low

0Macrovision Off

1Macrovision On

0 Reser ved

0 HD Test Pattern Off

1 HD Test Pattern Off

0Hatch

1Field/Frame

0Disabled

1Enabled

00 Disabled

01 –11 IRE

10 –6 IRE

11 –1.5 IRE

0Disabled

1Enabled

0011 Clock Cycle

0102 Clock Cycle

0113 Clock Cycle

1004 Clock Cycle

000 0 Clock Cycle

001 1 Clock Cycle

010 2 Clock Cycle

011 3 Clock Cycle

100 4 Clock Cycle

0Disabled

1Enabled

0Disabled

1Enabled

Input Range

HSYNC, VSYNC

BLANK

1Pixel Data Valid On

Reset

,

1

REV. A–18–

ADV7302A/ADV7303A

Table IV. HD Mode Register (continued)

Subaddress Register Bit Descr iption Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

13h HD Mode Register 4 0 Cb after Falling

14h HD Mode Register 50000000XA Low-High-Low

15h HD Mode Register 6 Reser ved 0Zero must be written

HD Cr/Cb Sequence

Reserved

Sync Filter on DAC D, E, F

HD Chroma SSAF

HD Chroma Input 0 4:4:4

HD Double Buffering 0 Disabled

HD RGB Input 0 Disabled

HD Sync on PrPb 0 Disabled

HD Color DAC Swap

HD Gamma Curve A/B 0 Gamma Curve A

HD Gamma Curve Enable 0 Disabled

HD Adaptive Filter Mode 0 Mode A

HD Adaptive Filter Enable 0 Disabled

1

1Cr after Falling Edge

0 Reser ved

0

0Disabled

1Enabled

0 Reserved

1

1Enabled

2

1Enabled

0Disabled

1Enabled

1 4:2:2

1Enabled

1Enabled

0DAC E = Pb,

1DAC F = Pb,

1Gamma Curve B

1Enabled

1 Mode B

HSYNC

Edge of

HSYNC

of

.

Reserved

transition resets the
internal HD timing
counters.

to this bit.

DAC F = Pr

DAC E = Pr

Reset

4Ch

00h

00h

REV. A

NOTES

1

4:2:2 Input Format Only

2

4:4:4 Input Format Only

–19–

ADV7302A/ADV7303A

Table V. Register Settings

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

16h HD Y Color XXXXXXXXY Color Value A0h

17h HD Cr Color XXXXXXXXCr Color Value 80h

18h HD Cb Color XXXXXXXXCb Color Value 80h

19h Reserved 00h

1Ah Reserved 00h

1Bh Reserved 00h

1Ch Reserved 00h

1Dh Reserved 00h

1Eh Reserved 00h

1Fh Reserved 00h

20h 0000Gain A = 0

21h HD CGMS Data 0 HD CGMS Data Bits 0000C19C18C17C16CGMS 19–16 00h

22h HD CGMS Data 1 HD CGMS Data Bits C 15 C 14 C 13 C 12 C11 C1 0 C9 C8 CGMS 15–8 00h

23h HD CGMS Data 2 HD CGMS Data Bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS 7–0 00h

24h HD Gamma A HD Gamma Curve A Data

25h HD Gamma A HD Gamma Curve A Data

26h HD Gamma A HD Gamma Curve A Data

27h HD Gamma A HD Gamma Curve A Data

28h HD Gamma A HD Gamma Curve A Data

29h HD Gamma A HD Gamma Curve A Data

2Ah HD Gamma A HD Gamma Curve A Data

2Bh HD Gamma A HD Gamma Curve A Data

2Ch HD Gamma A HD Gamma Curve A Data

2Dh HD Gamma A HD Gamma Curve A Data

2Eh HD Gamma B HD Gamma Curve B Data

2Fh HD Gamma B HD Gamma Curve B Data

30h HD Gamma B HD Gamma Curve B Data

31h HD Gamma B HD Gamma Curve B Data

32h HD Gamma B HD Gamma Curve B Data

33h HD Gamma B HD Gamma Curve B Data

34h HD Gamma B HD Gamma Curve B Data

HD Sharpness Filter
Gain

HD Sharpness Filter Gain
Value A

HD Sharpness Filter Gain
Value B

Points

Points

Points

Points

Points

Points

Points

Points

Points

Points

Points

Points

Points

Points

Points

Points

Points

0001Gain A = +1

……………

0111Gain A = +7

1000Gain A = –8

……………

1111Gain A = –1

0000 Gain B = 0

0001 Gain B = +1

………… …

0111 Gain B = +7

1000 Gain B = –8

………… …

1111 Gain B = –1

XXXXXXXXA0 00h

XXXXXXXXA1 00h

XXXXXXXXA2 00h

XXXXXXXXA3 00h

XXXXXXXXA4 00h

XXXXXXXXA5 00h

XXXXXXXXA6 00h

XXXXXXXXA7 00h

XXXXXXXXA8 00h

XXXXXXXXA9 00h

XXXXXXXXB0 00h

XXXXXXXXB1 00h

XXXXXXXXB2 00h

XXXXXXXXB3 00h

XXXXXXXXB4 00h

XXXXXXXXB5 00h

XXXXXXXXB6 00h

Reset

00h

REV. A–20–

ADV7302A/ADV7303A

Table VI. HD Adaptive Filters

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Register Setting Reset

38h 0000Gain A = 0

39h 0000Gain A = 0

3Ah 0000Gain A = 0

3Bh HD Adaptive Filter

3Ch HD Adaptive Filter

3Dh HD Adaptive Filter

HD Adaptive Filter
Gain 1

HD Adaptive Filter
Gain 2

HD Adaptive Filter
Gain 3

Threshold A

Threshold B

Threshold C

HD Adaptive Filter Gain 1
Value A

HD Adaptive Filter Gain 1
Value B

HD Adaptive Filter Gain 2
Value A

HD Adaptive Filter Gain 2
Value B

HD Adaptive Filter Gain 3
Value A

HD Adaptive Filter Gain 3
Value B

HD Adaptive Filter
Threshold A Value
HD Adaptive Filter
Threshold B Value
HD Adaptive Filter
Threshold C Value

00hex

0001Gain A = +1

0111Gain A = +7

1000Gain A = –8

1111Gain A = –1

0000 Gain B = 0

0001 Gain B = +1

0111 Gain B = +7

1000 Gain B = –8

1111 Gain B = –1

00hex

0001Gain A = +1

0111Gain A = +7

1000Gain A = –8

1111Gain A = –1

0000 Gain B = 0

0001 Gain B = +1

0111 Gain B = +7

1000 Gain B = –8

1111 Gain B = –1

00hex

0001Gain A = +1

0111Gain A = +7

1000Gain A = –8

1111Gain A = –1

0000 Gain B = 0

0001 Gain B = +1

0111 Gain B = +7

1000 Gain B = –8

1111 Gain B = –1

XXXXXXXXThreshold A 00hex

XXXXXXXXThreshold B 00hex

XXXXXXXXThreshold C 00hex

REV. A

–21–