Analog Devices ADV7302A 3A a Datasheet

Download

Multiformat SD, Progressive Scan/HDTV

FEATURES High Definition Input Formats

YCrCb Compliant to SMPTE293M (525 p),

ITU-R.BT1358 (625 p), SMPTE274M (1080 i), SMPTE296M (720 p), and Any Other High Definition

Standard Using Async Timing Mode RGB in 3 ⴛ 8-Bit 4:4:4 Format BTA T-1004 EDTV2 525 p Parallel

High Definition Output Formats (525 p/625 p/720 p/1080 i)

YPrPb Progressive Scan (EIA-770.1, EIA-770.2) YPrPb HDTV (EIA 770.3) RGB + H/V (HDTV 5-Wire Format) CGMS-A (720 p/1080 i) Macrovision Rev 1.0 (525 p/625 p)*

CGMS-A (525 p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-Bit Parallel Input CCIR-601 4:2:2 16-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M, N;

PAL M, N, B, D, G, H, I, PAL-60 SMPTE170M NTSC Compatible Composite Video ITU-R.BT470 PAL Compatible Composite Video S-Video (Y/C) EuroScart RGB Component YUV (Betacam, MII, SMPTE/EBU N10) Macrovision Rev 7.1*

CGMS/WSS

Closed Captioning

GENERAL FEATURES Simultaneous SD and HD Inputs and Outputs Oversampling (108 MHz/148.5 MHz) On-Board Voltage Reference 6 Precision Video 11-Bit DACs 2-Wire Serial MPU Interface Dual I/O Supply 2.5 V/3.3 V Operation Analog and Digital Supply 2.5 V On-Board PLL 64-LQFP Package Lead-Free Product

Video Encoder with Six 11-Bit DACs

ADV7302A/ADV7303A

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

PROGRAMMABLE

RGB MATRIX

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

S7–S0

Y7–Y0 C7–C0

S_HSYNC S_VSYNC

S_BLANK

P_HSYNC P_VSYNC

P_BLANK

CLKIN_A CLKIN_B

D E M U X

TIMING

GENERATOR

PLL

GENERAL DESCRIPTION

The ADV7302A/ADV7303A is a high speed, digital-to-analog encoder on a single monolithic chip. It includes six high speed video D/A converters with TTL compatible inputs.

The ADV7302A/ADV7303A has three separate 8-bit wide input ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical, and blanking signals, or EAV/SAV timing codes, control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals.

ADV7302A/

ADV7303A

11-BIT

DAC

11-BIT

DAC

V E R

11-BIT

DAC

A M

11-BIT

DAC

11-BIT

DAC

11-BIT

DAC

I2C

INTERFACE

APPLICATIONS DVD Players SD/HD Display Devices SD/HD Set-Top Boxes SD/HDTV Studio Equipment

*ADV7302A Only

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

ADV7302A/ADV7303A

P P

DETAILED FEATURES High Definition Programmable Features (720 p/1080 i)

2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black

Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control

CGMS-A (720 p/1080 i)

High Definition Programmable Features (525 p/625 p)

4 Oversampling (108 MHz Output) Internal Test Pattern Generator (Color Hatch, Black

Bar, Flat Frame) Individual Y and PrPb Output Delay Gamma Correction Programmable Adaptive Filter Control Fully Programmable YCrCb to RGB Matrix Undershoot Limiter

HD PIXEL

INPUT

CLKIN_B

DEINTERLEAVE

TEST

PATTERN

SHARPNESS

AND

ADAPTIVE

FILTER

CONTROL

Y COLOR CR COLOR CB COLOR

Macrovision Rev 1.0 (525 p/625 p)* CGMS-A (525 p)

Standard Definition Programmable Features

8 Oversampling (108 MHz) Internal Test Pattern Generator (Color Bars, Black Bar) Controlled Edge Rates for Sync, Active Video Individual Y and UV Output Delay Gamma Correction Digital Noise Reduction Multiple Chroma and Luma Filters Luma-SSAF

™

Filter with Programmable Gain/

Attenuation UV SSAF Separate Pedestal Control on Component and

Composite/S-Video Outputs VCR FF/RW Sync Mode

Macrovision Rev 7.1* CGMS/WSS Closed Captioning

DAC

4:2:2

4:4:4

PS 4

HDTV 2

DAC

_HSYNC _VSYNC

P_BLANK

S_HSYNC S_VSYNC S_BLANK

CLKIN_A

SD PIXEL

INPUT

DEINTERLEAVE

TIMING

GENERATOR

TIMING

GENERATOR

TEST

PATTERN

DNR

GAMMA

COLOR

CONTROL

CLOCK

CONTROL

AND PLL

SYNC

INSER-

TION

UV SSAF

LUMA

AND

CHROMA

FILTERS

RGB

MATRIX

2 OVER-

SAMPLING

SD 8

CGMS

WSS

FSC

MODULATION

DAC

Figure 1. Functional Block Diagram

TERMS USED IN THIS DATA SHEET

SD Standard Definition Video, conforming to

ITU-R.BT601/ITU-R.BT656.

HD High Definition Video, i.e., Progressive Scan or HDTV.

PS Progressive Scan Video, conforming to SMPTE293M

or ITU-R.BT1358.

HDTV High Definition Television Video, conforming to

SMPTE274M or SMPTE296M.

YCrCb SD or HD Component Digital Video

YPrPb HD Component Analog Video

YUV SD Component Analog Video

SSAF is a trademark of Analog Devices, Inc.

*ADV7302A Only

REV. A–2–

ADV7302A/ADV7303A–SPECIFICATIONS

(VAA = VDD = 2.375 V–2.625 V, V

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution 11 Bits Integral Nonlinearity ±1.0 LSB V Differential Nonlinearity, +ve Differential Nonlinearity, –ve

DIGITAL OUTPUTS

Output Low Voltage, V Output High Voltage, V Three-State Leakage Current ±1.0 µAV Three-State Output Capacitance 2 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V Input Low Voltage, V Input Leakage Current 1 µAV Input Capacitance, C

ANALOG OUTPUTS

Full-Scale Output Current 8.2 8.7 9.2 mA Output Current Range 8.2 8.7 9.2 mA Full-Scale Output Current 4.1 4.35 4.6 mA R Output Current Range 4.1 4.35 4.6 mA R DAC to DAC Matching 2.0 % Output Compliance Range, V Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

REF

POWER REQUIREMENTS

Normal Power Mode

DD_IO

5, 6

Sleep Mode

DD_IO

Power Supply Rejection Ratio 0.01 %/%

NOTES

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

DNL measures the deviation of the actual DAC o/p voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL, the actual step values lie below the ideal step value.

Value in brackets for V

IDD or the circuit current is the continuous current required to drive the digital core without the I

IAA is the total current required to supply all DACs including the V

All DACs on.

Specifications subject to change without notice.

= 2.375 V to 2.750 V.

DD_IO

= 2.375 V–3.600 V, V

DD_IO

OUT

= 1.235 V, R

REF

= 760 , R

SET

= 150 , T

LOAD

MIN

to T

(0C to 70C), unless otherwise noted.)

MAX

= 2.5 V

0.125 LSB VAA = 2.5 V

1.0 LSB VAA = 2.5 V

2.4 [2.0]

0.4 [0.4]3VI VI

= 3.2 mA

SINK

= 400 µA

SOURCE

= 0.4 V, 2.4 V

0.8 V

= 2.4 V

2pF

= 1520 Ω

SET1, 2

= 1520 Ω

SET1, 2

0 1.0 1.4 V

7pF

1.15 1.235 1.3 V

93 mA SD Only [8⫻] 52 mA PS Only [4⫻] 84 mA HDTV Only [2⫻] 90 110 mA SD and PS 99 mA SD [8⫻] and HDTV 108 mA SD and HDTV [2⫻]

0.2 mA 70 75 mA 37 45 mA R

SET1, 2

= 1520 Ω

130 µA 10 µA 110 µA

circuitry and the PLL circuitry.

REF

PLL

REV. A –3–

ADV7302A/ADV7303A

(VAA = VDD = 2.375 V–2.625 V, V

DYNAMIC SPECIFICATIONS

Parameter Min Typ Max Unit Test Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth 12.5 MHz Chroma Bandwidth 5.8 MHz SNR 59 dB Luma Ramp Unweighted SNR 75 dB Flat Field up to 5 MHz SNR 70 dB Flat Field Full Bandwidth

HDTV MODE

Luma Bandwidth 30 MHz Chroma Bandwidth 13.75 MHz SNR 59 dB Luma Ramp Unweighted SNR 75 dB Flat Field up to 5 MHz SNR 70 dB Flat Field Full Bandwidth

STANDARD DEFINITION MODE

Hue Accuracy 0.2 Degrees Color Saturation Accuracy 0.54 % Chroma Nonlinear Gain ±0.4 % Referenced to 40 IRE Chroma Nonlinear Phase ±0.3 Degrees Chroma/Luma Intermod ±0.05 % Chroma/Luma Gain Ineq ±98 % Chroma/Luma Delay Ineq 0.9 ns Luminance Nonlinearity ±0.4 % Chroma AM Noise 84 dB Chroma PM Noise 74 dB Differential Gain 0.6 % NTSC Differential Phase 1.4 Degrees NTSC SNR 59 dB Luma Ramp SNR 75 dB Flat Field up to 5 MHz SNR 70 dB Flat Field Full Bandwidth

Specifications subject to change without notice.

= 150 , T

LOAD

MIN

to T

(0C to 70C), unless otherwise noted.)

MAX

= 2.375 V–3.600 V, V

DD_IO

= 1.235 V, R

REF

= 760 ,

SET

REV. A–4–

ADV7302A/ADV7303A

TIMING SPECIFICATIONS

(VAA = VDD = 2.375 V–2.625 V, V T

to T

MIN

(0C to 70C), unless otherwise noted.)

MAX

= 2.375 V–3.600 V, V

DD_IO

= 1.235 V, R

REF

= 760 , R

SET

Parameter Min Typ Max Unit Test Conditions

MPU PORT

SCLOCK Frequency 0 400 kHz SCLOCK High Pulsewidth, t SCLOCK Low Pulsewidth, t Hold Time (Start Condition), t

0.6 µs

1.3 µs

0.6 µs First Clock Generated After

This Period

Setup Time (Start Condition), t

0.6 µsRelevant for Repeated Start

Condition Data Setup Time, t SDATA, SCLOCK Rise Time, t SDATA, SCLOCK Fall Time, t Setup Time (Stop Condition), t

100 ns

300 ns 300 ns

0.6 µs

RESET Low Time 100 ns

ANALOG OUTPUTS

Analog Output Delay

8ns

Output Skew 1 ns

CLOCK CONTROL AND PIXEL PORT

CLK

Clock High Time, t Clock Low Time, t Data Setup Time, t Data Hold Time, t Output Access Time, t Output Hold Time, t

27 MHz Progressive Scan Mode

81 MHz HDTV Mode/Async Mode 40 % 1 clkcycle 40 % 1 clkcycle

2.0 ns

14 ns

4.0 ns

Pipeline Delay 61 clkcycles SD [2⫻]

62.5 clkcycles SD [8⫻]

66.5 clkcycles SD Component Filter [8⫻]

33 clkcycles PS [1⫻], HD [1⫻], Async

Timing Mode

43.5 clkcycles PS [4⫻]

36 clkcycles HD [2⫻]

NOTES

Guaranteed by characterization.

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

Data: C[7:0]; S[7:0]; Y[7:0] Control: P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK

Specifications subject to change without notice.

= 150 ,

LOAD

REV. A

–5–

ADV7302A/ADV7303A

CLKIN_A

I/PS

P_HSYNC, P_VSYNC,

P_BLANK

CONTROL

= CLOCK HIGH TIME,

O/PS

S_HSYNC,

S_VSYNC

Y7–Y0

C7–C0

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

= CLOCK LOW TIME,

= DATA SETUP TIME,

= DATA HOLD TIME

Figure 2. HD 4:2:2 Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV Input Only (Input Mode at Subaddress 01h = 001 or 010)

CLKIN_A

t10

Y0 Y1 Y2 Yxxx Yxxx

Cb0 Cb1 Cb2 Cb3 Cbxxx Cbxxx

Cr0 Cr1 Cr2 Cr3 Crxxx Crxxx

t12

t13

CONTROL

I/PS

P_HSYNC, P_VSYNC,

P_BLANK

Y7–Y0

C7–C0

S7–S0

t11

CONTROL

= CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME

O/PS

S_HSYNC,

S_VSYNC

t14

Figure 3. HD 4:4:4 YCrCb Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV Input Only (Input Mode at Subaddress 01h = 001 or 010)

REV. A–6–

CONTROL

I/PS

CLKIN_A

P_HSYNC, P_VSYNC,

P_BLANK

ADV7302A/ADV7303A

t10

Y7–Y0

C7–C0

S7–S0

t11

CONTROL

= CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME

O/PS

S_HSYNC,

S_VSYNC

G0 G1 G2 Gxxx Gxxx

B0 B1 B2 B3 Bxxx Bxxx

R0 R1 R2

t12

Rxxx Rxxx

t13

t14

Figure 4. HD 4:4:4 RGB Input Data Format Timing Diagram, HD RGB Input Enabled (Input Mode at Subaddress 01h = 001 or 010)

CLKIN_B

= DATA SETUP TIME,

= DATA HOLD TIME

I/PS

O/PS

P_HSYNC, P_VSYNC,

P_BLANK

S_HSYNC,

S_VSYNC

CONTROL

= CLOCK HIGH TIME,

Y7–Y0

= CLOCK LOW TIME,

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

Figure 5. PS 4:2:2 1 ⫻ 8-Bit Interleaved @ 27 MHz, Input Mode: PS Input Only (Input Mode at Subaddress 01h = 100)

REV. A

–7–

ADV7302A/ADV7303A

CLKIN_A

I/PS

P_HSYNC, P_VSYNC,

P_BLANK

CONTROL

t10

CONTROL

I/PS

CONTROL

O/PS

Y7–Y0

CONTROL

= CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME

O/PS

S_HSYNC,

S_VSYNC

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

t11

t12

t13

t14

Figure 6. PS 4:2:2 1 ⫻ 8-Bit Interleaved @ 54 MHz, Input Mode: PS 54 MHz Input (Input Mode at Subaddress 01h = 111)

CLKIN_A

S_HSYNC, S_VSYNC,

S_BLANK

S7–S0

S_HSYNC,

S_VSYNC

Cb Y Cr Y Cb Y

IN SLAVE MODE

IN MASTER/SLAVE MODE WITH EAV/SAV

Figure 7. 8-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)

REV. A–8–

CONTROL

I/PS

CLKIN_A @ 27MHz

S_HSYNC, S_VSYNC,

S_BLANK

ADV7302A/ADV7303A

IN SLAVE MODE

Y0 Y1 Y2 Y3

Cb0 Cr0 Cb2 Cr2

IN MASTER/SLAVE MODE WITH EAV/SAV

CONTROL

O/PS

S7–S0

Y7–Y0

S_HSYNC,

S_VSYNC

Figure 8. 16-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)

CLKIN_B

Y3 Y4 Y5

Cr2

Cb4 Cr4

HD INPUT

SD INPUT

CONTROL

I/PS

CONTROL

I/PS

P_HSYNC, P_VSYNC,

P_BLANK

Y7–Y0

C7–C0

CLKIN_A

S_HSYNC, S_VSYNC,

S_BLANK

Y0 Y1

Cb0 Cr0 Cb2

S7–S0

Cb0 Y0 Cr0

Cb1 Y2

Figure 9. SD and HD Simultaneous Input, Input Mode: SD and PS 16-Bit or SD and HDTV (Input Mode at Subaddress 01h = 011, 101, or 110)

REV. A

–9–

ADV7302A/ADV7303A

CLKIN_B

t10

I/PS

P_HSYNC, P_VSYNC,

P_BLANK

CLKIN_A

S_HSYNC, S_VSYNC,

S_BLANK

P_HSYNC

Y7–Y0

S7–S0

Cb0 Y0 Cr0 Y1

t12

t11

t10

Cb0 Y0 Cr0

t11

t12

t11

Crxxx Yxxx

t12

PS INPUT

SD INPUT

Cb1 Y2

CONTROL

Figure 10. SD and HD Simultaneous Input, Input Mode: SD and PS 8-Bit (Input Mode at Subaddress 01h = 100)

P_VSYNC

P_BLANK

Y7–Y0

a = 32 CLKCYCLES FOR 525p a = 24 CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p

Figure 11. PS 4:2:2 1 ⫻ 8-Bit Interleaved @ 54 MHz Input Timing Diagram

Cb Y

Cr Y

REV. A–10–

P_HSYNC

P_VSYNC

P_BLANK

ADV7302A/ADV7303A

Y7–Y0

S7–S0

C7–C0

a = 16 CLKCYCLES FOR 525p a = 12 CLKCYCLES FOR 626p a = 44 CLKCYCLES FOR 1080i a = 70 CLKCYCLES FOR 720p AS RECOMMENDED BY STANDARD

SYNC

FIELD

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

LANK

PIXEL DATA

b(MIN) = 122 CLKCYCLES FOR 525p b(MIN) = 132 CLKCYCLES FOR 625p b(MIN) = 236 CLKCYCLES FOR 1080i b(MIN) = 300 CLKCYCLES FOR 720p

Figure 12. HD Input Timing Diagram

Y0 Y1

Cr0 Cr1 Cr2 Cr3

Cb0 Cb1 Cb2 Cb3

Cb Y

Y2 Y3

Cr Y

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Figure 13. SD Timing Input for Timing Mode 1

SDA

SCLK

Figure 14. MPU Port Timing Diagram

REV. A

–11–

ADV7302A/ADV7303A

ABSOLUTE MAXIMUM RATINGS*

VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V

to IO_GND . . . . . . . . . . . . . –0.3 V to V

DD_IO

Ambient Operating Temperature (T Storage Temperature (T

) . . . . . . . . . . . . . . –65°C to +150°C

) . . . . . . . 0°C to +70°C

DD_IO

+ 0.3 V

Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . . 260°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

The ADV7302A/ADV7303A is a lead-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure tin electroplate. The device is suitable for lead-free applications and is able to withstand surface-mount soldering at up to 255°C (±5°C). In addition, it is backward compatible with conventional tin-lead soldering processes. This means that the electroplated tin coating can be soldered with tin-lead solder pastes at conventional reflow temperatures of 220°C to 235°C.

device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

θJC = 11°C/W

= 47°C/W

Model Package Description Package Option

ADV7302AKST Plastic Quad Flatpack ST-64B ADV7303AKST Plastic Quad Flatpack ST-64B

ORDERING GUIDE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7302A/ADV7303A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATION

S2S1S0

GND_IO

S_HSYNC

S_VSYNC

49505152535455565758596061626364

32313029282726252423222120191817

CLKIN_A

RTC_SCR_TR

S_BLANK

SET1

REF

COMP1

DAC A

DAC B

DAC C

AGND

DAC D

DAC E

DAC F

COMP2

SET2

EXT_LF

RESET

DD_IO

GND_IO

DGND

GND_IO

CLKN_BS7S6S5S4S3DGND

PIN 1

IDENTIFIER

ADV7302A/ADV7303A

(Not to Scale)

SDA

ALSB

SCLK

TOP VIEW

P_VSYNC

P_HSYNC

C3C4C5C6C7

P_BLANK

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Input/Output Function

DD_IO

PPower Supply for Digital Inputs and Outputs

4–9, 12, 13 Y0–Y7 I 8-Bit Progressive Scan/HDTV Input Port for Y Data. The LSBs are set up on

Pins Y0 and Y1. In default mode, the input on this port is output on DAC D.

16–18, 26–30 C0–C7 I 8-Bit Progressive Scan/HDTV Input Port for CrCb Color Data in 4:2:2 Input

Mode. In 4:4:4 Input Mode, this input port is used for the Cb (Blue/U) data. The LSBs are set up on Pins C0 and C1. In default mode, the input on this port is output on DAC E.

REV. A–12–

ADV7302A/ADV7303A

Pin No. Mnemonic Input/Output Function

19 I

20 ALSB I/O TTL Address Input. This signal sets up the LSB of the MPU address. When

21 SDA I/O MPU Port Serial Data Input/Output

22 SCLK I MPU Port Serial Interface Clock Input 23 P_HSYNC IVideo Horizontal Sync Control Signal for HD Sync in Simultaneous SD/HD

24 P_VSYNC IVideo Vertical Sync Control Signal for HD Sync in Simultaneous SD/HD

25 P_BLANK I Video Blanking Control Signal for HD Sync in Simultaneous SD/HD Mode

31 RTC_SCR_TR I Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input,

32 CLKIN_A I Pixel Clock Input for HD Only or SD Only Modes 33 RESET IThis input resets the on-chip timing generator and sets the ADV7302A/

34 EXT_LF I External Loop Filter for the internal PLL

35, 47 R

36, 45 COMP2, 1 O Compensation Pin for DACs. Connect 0.1 µF Capacitor from COMP Pin to V

37 DAC F O In SD Only Mode: Chroma/Red/V Analog Output, in HD Only Mode and

38 DAC E O In SD Only Mode: Luma/Blue/U Analog Output, in HD Only Mode and

39 DAC D O In SD Only Mode: CVBS/Green/Y Analog Output, in HD Only Mode and

40 AGND G Analog Ground

41 V

42 DAC C O Chroma/Red/V SD Analog Output

43 DAC B O Luma/Blue/U SD Analog Output

44 DAC A O CVBS/Green/Y SD Analog Output

46 V

48 S_BLANK I/O Video Blanking Control Signal for SD 49 S_VSYNC I/O Video Vertical Control Signal for SD. Option to output SD VSYNC or SD

50 S_HSYNC I/O Video Horizontal Control Signal for SD. Option to output SD HSYNC or

53–55, 58–62 S0–S7 I 8-Bit Standard Definition Input Port or Progressive Scan/HDTV Input Port

10, 56 V

11, 57 DGND G Digital Ground

63 CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan

2, 3, 14, 15, GND_IO Digital Ground 51, 52, 64

REV. A

CI This input pin must be tied high (V

interface over the I

this pin is tied low, the I

C port.

C filter is activated, which reduces noise on the I2C

interface.

Mode and HD Only Mode

and HD Only Mode

and Subcarrier Reset Input

ADV7303A into default register setting. Reset is an active low signal.

SET2, 1

IA 760 Ω resistor must be connected from this pin to AGND and is used to

control the amplitudes of the DAC outputs.

Simultaneous HD/SD: Pr/Red (HD) Analog Output

Simultaneous HD/SD: Pb/Blue (HD) Analog Output

Simultaneous HD/SD: Y/Green (HD) Analog Output

REF

PAnalog Power Supply

I/O Optional External Voltage Reference Input for DACs or Voltage Reference

Output (1.235 V)

HSYNC in SD Slave Mode 0 and/or any HD Mode.

HD HSYNC in SD Slave Mode 0 and/or any HD Mode.

for Cr (Red/V) color data in 4:4:4 Input Mode. The LSBs are set up on Pins S0 and S1. In Default Mode, the input on this port is output on DAC F.

PDigital Power Supply

Mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV Mode. This clock input pin is only used in Simultaneous SD/HD Mode.

–13–

) for the ADV7302A/ADV7303A to

DD_IO

ADV7302A/ADV7303A

MPU PORT DESCRIPTION

The ADV7302A/ADV7303A supports a 2-wire serial (I2C compatible) microprocessor bus driving multiple peripherals. Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7302A/ ADV7303A has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figures 15 and 16. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation, while Logic Level “0” corresponds to a write operation. A1 is set by setting the ALSB Pin of the ADV7302A/ADV7303A to Logic Level “0” or Logic Level “1.” When ALSB is set to “1,” there is greater input bandwidth on the I speed data transfers on this bus. When ALSB is set to “0,” there is reduced input bandwidth on the I pulses of less than 50 ns will not pass into the I

C lines, which allows high

C lines, which means that

C internal con-

troller. This mode is recommended for noisy systems.

1 1 0 1 0 1 A1 X

ADDRESS CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE 1 READ

Figure 15. ADV7302A Slave Address = D4h

0 1 0 1 0 1 A1 X

ADDRESS CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE 1 READ

Figure 16. ADV7303A Slave Address = 54h

To control the various devices on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA, while SCLK remains high. This indicates that an address/ data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W Bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an Acknowledge Bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCLK lines waiting for the start condition and the correct transmitted address. The R/W Bit determines the direction of the data.

A Logic “0” on the LSB of the first byte means that the master will write information to the peripheral. A Logic “1” on the LSB of the first byte means that the master will read information from the peripheral.

The ADV7302A/ADV7303A acts as a standard slave device on the bus. The data on the SDA Pin is eight bits long, supporting the 7-bit addresses plus the R/W Bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddress’s autoincrement allows data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers.

Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, it will cause an immediate jump to the idle condition. During a given SCLK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7302A/ADV7303A will not issue an acknowledge and will return to the idle condition. If in Autoincrement Mode the user exceeds the highest subaddress, the following action will be taken:

1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A no-acknowledge condition is where the SDA line is not pulled low on the ninth pulse.

2. In Write Mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7302A/ADV7303A, and the part will return to the idle condition.

Before writing to the subcarrier frequency registers, it is a requirement that the ADV7302A/ADV7303A has been reset at least once since power-up.

The four Subcarrier Frequency Registers must be updated starting with Subcarrier Frequency Register 0. The subcarrier frequency will not update until the last subcarrier frequency register byte has been received by the ADV7302A/ADV7303A.

Figure 17 illustrates an example of data transfer for a read sequence and the start and stop conditions.

Figure 18 shows bus write and read sequences.

SDATA

SCLOCK

1–7 8

START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP

1–7 8 9

1–7

Figure 17. Bus Data Transfer

REV. A–14–

WRITE

SEQUENCE

READ

SEQUENCE

ADV7302A/ADV7303A

S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P

LSB = 0 LSB = 1

S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER

Figure 18. Read and Write Sequence

A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the ADV7302A/ADV7303A except the subaddress registers that are write-only registers. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. Then a read/write operation is performed from/to the target address which then increments to the next address until a stop command on the bus is performed.

REGISTER PROGRAMMING

The following section describes the functionality of each register. All registers can be read from as well as written to, unless otherwise stated.

Subaddress Register (SR7–SR0)

The Communications Register is an 8-bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place.

Register Select (SR7–SR0)

These bits are set up to point to the required starting address.

REV. A

–15–

ADV7302A/ADV7303A

/Off

Off

Table I. Power Mode Register

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

00h Power Mode Register Sleep Mode

PLL and Oversampling Control

DAC F: Power On/Off 0 DAC F Off

DAC D: Power On/Off 0 DAC D Off

DAC C: Power On/Off 0 DAC C Off

DAC B: Power On/Off 0 DAC B Off

DAC A: Power On/Off 0 DAC A Off

NOTES

When enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled. I2C registers can be read from and written to.

This control allows the internal PLL circuit to be powered down and the oversampling to be switched off.

E: Power On

0 Sleep Mode Off

1 Sleep Mode On

0 PLL On

1 PLL Off

1DA

0DA

1 DAC E On

1 DAC D On

1 DAC C On

1 DAC B On

1 DAC A On

F On

Fch

Table II. Input Mode Register

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

01h Input Mode Register 0 Disabled 38h

BTA T-1004 Compatibility

1 Enabled

Reserved 0 Zero must be written

Pixel Align

Clock Align

Input Mode

Reserved 0 Zero must be written

000 SD Input Only

001 PS Input Only

010 HDTV Input Only

011 SD and PS (16-Bit)

100 SD and PS (8-Bit)

101 SD and HDTV (SD

110 SD and HDTV

111 PS 54 MHz Input

0 Video input data starts

1 Video input data starts

1 Must be set if the

to this bit.

with a Y0 bit. Only for PS Interleaved Mode.

with a Cb0 bit.

phase delay between the two input clocks is <9.25 ns or >27.75 ns. Only if two input clocks are used.

led)

Oversam

(HDTV Oversampled)

to this bit.

REV. A–16–

Table III. Mode Register

ADV7302A/ADV7303A

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R egister Setting

02h Mode Register 0 Reserved 0 0 Zero must be written

Test Pattern Black Bar

RGB Matrix

SYNC on RGB

RGB/YUV Output

SD SYNC

HD SYNC

03h RGB Matrix 0 XXLSB for GY 03h

04h RGB Matrix 1 XXLSB for RV F0h

05h RGB Matrix 2 XXXXXXXXBits 9–2 for GY 4Eh

06h RGB Matrix 3 XXXXXXXXBits 9–2 for GU 0 Eh

07h RGB Matrix 4 XXXXXXXXBits 9–2 for GV 24h

08h RGB Matrix 5 XXXXXXXXBits 9–2 for BU 92h

09h RGB Matrix 6 XXXXXXXXBits 9–2 for RV 7Ch

0Ah Reserved 00h

0Bh Reserved 00h

0Ch Reserved 00h

0Dh Reserved 00h

0Eh Reserved 00h

0Fh Reserved 00h

0 No SYNC Output

1 Output SD SYNCs on

0 No SYNC Output

1 Output HD SYNCs

XX LSB for GU

0No SYNC

1 SYNC on all RGB

0 RGB Component

1YUV Component

XX LSB for GV

0Disabled

1 Enabled. 0x11h, Bit 2

0 Disable Programmable

1 Enable Programmable

XX LSB for BU

to these bits.

must also be enabled.

RGB Matrix

uts

Out

uts

Out

uts

Out

S_HSYNC and S_VSYNC

on S_HSYNC and S_VSYNC

Reset

20h

REV. A

–17–

ADV7302A/ADV7303A

Subaddress Reg ister Bit Descr iption Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

10h HD Mode Register 1 00EIA770.2 Output 00h

11h HD Mode Register 2 0Pixel Data Valid Off 00h

12h HD Mode Register 3 0 0 0 0 Clock Cycle

Table IV. HD Mode Register

HD Output Standard

HD Input Control Signals

HD 625 p

HD 720 p

HD BLANK Polarity

HD Macrovision for 525 p/625 p

HD Pixel Data Valid

HD Test Pattern Enable

HD Test Pattern Hatch/Field

HD VBI Open

HD Undershoot Limiter

HD Sharpness Filter

HD Y Delay wrt Falling Edge of HSYNC

HD Color Delay wrt Falling Edge of HSYNC

HD CGMS

HD CGMS CRC

01EIA770.1 Output

10Output Levels for Full

11Reserved

01 EAV/SAV Codes

10 Async Timing Mode

11 Reserved

0 525 p

1 625 p

0 1080 i

1 720 p

0BLANK Active High

1BLANK Active Low

0Macrovision Off

1Macrovision On

0 Reser ved

0 HD Test Pattern Off

1 HD Test Pattern Off

0Hatch

1Field/Frame

0Disabled

1Enabled

00 Disabled

01 –11 IRE

10 –6 IRE

11 –1.5 IRE

0Disabled

1Enabled

0011 Clock Cycle

0102 Clock Cycle

0113 Clock Cycle

1004 Clock Cycle

000 0 Clock Cycle

001 1 Clock Cycle

010 2 Clock Cycle

011 3 Clock Cycle

100 4 Clock Cycle

0Disabled

1Enabled

0Disabled

1Enabled

Input Range

HSYNC, VSYNC

BLANK

1Pixel Data Valid On

Reset

REV. A–18–

ADV7302A/ADV7303A

Table IV. HD Mode Register (continued)

Subaddress Register Bit Descr iption Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

13h HD Mode Register 4 0 Cb after Falling

14h HD Mode Register 50000000XA Low-High-Low

15h HD Mode Register 6 Reser ved 0Zero must be written

HD Cr/Cb Sequence

Reserved

Sync Filter on DAC D, E, F

HD Chroma SSAF

HD Chroma Input 0 4:4:4

HD Double Buffering 0 Disabled

HD RGB Input 0 Disabled

HD Sync on PrPb 0 Disabled

HD Color DAC Swap

HD Gamma Curve A/B 0 Gamma Curve A

HD Gamma Curve Enable 0 Disabled

HD Adaptive Filter Mode 0 Mode A

HD Adaptive Filter Enable 0 Disabled

1Cr after Falling Edge

0 Reser ved

0Disabled

1Enabled

0 Reserved

1Enabled

0Disabled

1Enabled

1 4:2:2

1Enabled

0DAC E = Pb,

1DAC F = Pb,

1Gamma Curve B

1Enabled

1 Mode B

HSYNC

Edge of

HSYNC

Reserved

transition resets the internal HD timing counters.

to this bit.

DAC F = Pr

DAC E = Pr

Reset

4Ch

00h

REV. A

NOTES

4:2:2 Input Format Only

4:4:4 Input Format Only

–19–

ADV7302A/ADV7303A

Table V. Register Settings

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

16h HD Y Color XXXXXXXXY Color Value A0h

17h HD Cr Color XXXXXXXXCr Color Value 80h

18h HD Cb Color XXXXXXXXCb Color Value 80h

19h Reserved 00h

1Ah Reserved 00h

1Bh Reserved 00h

1Ch Reserved 00h

1Dh Reserved 00h

1Eh Reserved 00h

1Fh Reserved 00h

20h 0000Gain A = 0

21h HD CGMS Data 0 HD CGMS Data Bits 0000C19C18C17C16CGMS 19–16 00h

22h HD CGMS Data 1 HD CGMS Data Bits C 15 C 14 C 13 C 12 C11 C1 0 C9 C8 CGMS 15–8 00h

23h HD CGMS Data 2 HD CGMS Data Bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS 7–0 00h

24h HD Gamma A HD Gamma Curve A Data

25h HD Gamma A HD Gamma Curve A Data

26h HD Gamma A HD Gamma Curve A Data

27h HD Gamma A HD Gamma Curve A Data

28h HD Gamma A HD Gamma Curve A Data

29h HD Gamma A HD Gamma Curve A Data

2Ah HD Gamma A HD Gamma Curve A Data

2Bh HD Gamma A HD Gamma Curve A Data

2Ch HD Gamma A HD Gamma Curve A Data

2Dh HD Gamma A HD Gamma Curve A Data

2Eh HD Gamma B HD Gamma Curve B Data

2Fh HD Gamma B HD Gamma Curve B Data

30h HD Gamma B HD Gamma Curve B Data

31h HD Gamma B HD Gamma Curve B Data

32h HD Gamma B HD Gamma Curve B Data

33h HD Gamma B HD Gamma Curve B Data

34h HD Gamma B HD Gamma Curve B Data

HD Sharpness Filter Gain

HD Sharpness Filter Gain Value A

HD Sharpness Filter Gain Value B

Points

0001Gain A = +1

……………

0111Gain A = +7

1000Gain A = –8

……………

1111Gain A = –1

0000 Gain B = 0

0001 Gain B = +1

………… …

0111 Gain B = +7

1000 Gain B = –8

………… …

1111 Gain B = –1

XXXXXXXXA0 00h

XXXXXXXXA1 00h

XXXXXXXXA2 00h

XXXXXXXXA3 00h

XXXXXXXXA4 00h

XXXXXXXXA5 00h

XXXXXXXXA6 00h

XXXXXXXXA7 00h

XXXXXXXXA8 00h

XXXXXXXXA9 00h

XXXXXXXXB0 00h

XXXXXXXXB1 00h

XXXXXXXXB2 00h

XXXXXXXXB3 00h

XXXXXXXXB4 00h

XXXXXXXXB5 00h

XXXXXXXXB6 00h

Reset

00h

REV. A–20–

ADV7302A/ADV7303A

Table VI. HD Adaptive Filters

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Register Setting Reset

38h 0000Gain A = 0

39h 0000Gain A = 0

3Ah 0000Gain A = 0

3Bh HD Adaptive Filter

3Ch HD Adaptive Filter

3Dh HD Adaptive Filter

HD Adaptive Filter Gain 1

HD Adaptive Filter Gain 2

HD Adaptive Filter Gain 3

Threshold A

Threshold B

Threshold C

HD Adaptive Filter Gain 1 Value A

HD Adaptive Filter Gain 1 Value B

HD Adaptive Filter Gain 2 Value A

HD Adaptive Filter Gain 2 Value B

HD Adaptive Filter Gain 3 Value A

HD Adaptive Filter Gain 3 Value B

HD Adaptive Filter Threshold A Value HD Adaptive Filter Threshold B Value HD Adaptive Filter Threshold C Value

00hex

0001Gain A = +1

0111Gain A = +7

1000Gain A = –8

1111Gain A = –1

0000 Gain B = 0

0001 Gain B = +1

0111 Gain B = +7

1000 Gain B = –8

1111 Gain B = –1

00hex

0001Gain A = +1

0111Gain A = +7

1000Gain A = –8

1111Gain A = –1

0000 Gain B = 0

0001 Gain B = +1

0111 Gain B = +7

1000 Gain B = –8

1111 Gain B = –1

00hex

0001Gain A = +1

0111Gain A = +7

1000Gain A = –8

1111Gain A = –1

0000 Gain B = 0

0001 Gain B = +1

0111 Gain B = +7

1000 Gain B = –8

1111 Gain B = –1

XXXXXXXXThreshold A 00hex

XXXXXXXXThreshold B 00hex

XXXXXXXXThreshold C 00hex

REV. A

–21–

ADV7302A/ADV7303A

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

3Eh Reserved 00h

3Fh Reserved 00h

40h SD Mode Register 0 00NTSC

41h Reserved 00h

42h SD Mode Register 1 0 Disabled

Table VII. SD Mode Registers

SD Standard

SD Luma Filter

SD Chroma Filter

SD UV SSAF

SD DAC Output 1*

SD DAC Output 2

SD Pedestal

SD Square Pixel

SD VCR FF/R

SD Pixel Data Valid

SD Active Video Edge

Sync

01PAL B, D, G, H, I

10PAL M

11PAL N

000 LPF NTSC

001 LPF PAL

010 Notch NTSC

011 Notch PAL

100 SSAF Luma

101 Luma CIF

110 Luma QCIF

111 Reserved

000 1.3 MHz

001 0.65 MHz

010 1.0 MHz

011 2.0 MHz

100 Reserved

101 Chroma CIF

110 Chroma QCIF

111 3.0 MHz

1 Enabled

0 DAC A, B, C: CVBS,

1 DAC A, B, C: GBR or

0 Swap DAC A and

0 Disabled

1 Enabled

0 Disabled

1 Enabled

0 Disabled

1 Enabled

0 Disabled

1 Enabled

0 Disabled

1 Enabled

L, C; DAC D, E, F: GBR or YUV

YUV; DAC D, E, F: CVBS, L, C

DAC D Out

00h

08h

uts

REV. A–22–

ADV7302A/ADV7303A

[

]

(

)

Table VII. SD Mode Registers (continued)

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Register Setting Reset

43h SD Mode Register 2 SD Pedestal YUV Output 0 No Pedestal on YUV

1 7.5 IRE Pedestal on

SD Output Levels Y 0 Y = 700 mV/300 mV

1Y = 714 mV/286 mV

SD Output Levels UV 0 0 700 mV p-p [PAL];

01 700 mV p-p

10 1000 mV p-p

11 648 mV p-p

SD VBI Open 0 Disabled

1 Enabled

SD CC Field Control

44h

45h Reserved 00h

46h Reserved 00h

SD Mode Register 3

SD VSYNC-3H 00h

SD RTC/TR/SCR

SD Active Video Length

SD Chroma

SD Burst

SD Color Bars

Reserved 0 Zero must be written

SD UV Scale

SD Y Scale

SD Hue Adjust

SD Brightness

SD Luma SSAF Gain

Reserved 0 Zero must be written

00 CC Disabled

01 CC on Odd Field Only

10 CC on Even Field

11 CC on Both Fields

1 Reserved

00 Genlock Disabled

01 Subcarrier Reset

10 Timing Reset

11 RTC Enabled

0 720 Pixels

1 710 (NTSC);

0 Chroma Enabled

1 Chroma Disabled

0 Enabled

1Disabled

0Disabled

1 Enabled

0Disabled

1 Enabled

0Disabled

1 Enabled

0Disabled

1 Enabled

0Disabled

1 Enabled

YUV

1000 mV p-p [NTSC]

Onl

0Disabled

1 VSYNC = 2.5 lines

[PAL]; VSYNC = 3

NTSC

lines

PAL

702

to this bit.

0Disabled

1 Enabled

to this bit.

00h

00hSD Mode Register 447h

REV. A

–23–

ADV7302A/ADV7303A

Table VII. SD Mode Registers (continued)

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

SD Mode Register 548h

*For more detail, see Input and Output Configuration section.

Reserved 0 Zero must be written

SD Double Buffering

SD Input Format

Reserved 0 Zero must be written

SD Digital Noise Reduction

SD Gamma Control

SD Gamma Curve

SD Black Burst Output on DAC Y

SD Black Burst Output on DAC Luma

SD Chroma Delay

Reserved 0 Zero must be written

0 Gamma Curve A

1 Gamma Curve B

0 Disabled

1 Enabled

0 Disabled

1 Enabled

00 Disabled

01 4 Clock Cycles

10 8 Clock Cycles

11 Reserved

0 Disabled

1 Enabled

0 8-Bit Input

1 16-Bit Input

00Disabled

01–11 IRE

10–6 IRE

11–1.5 IRE

0 Disabled

1 Enabled

0 Disabled

1 Enabled

to this bit.

00h

00h49h SD Mode Register 6 SD Undershoot Limiter

REV. A–24–

Mod

BLANK

Enabled

Disabled

HSYNC

VSYNC

HSYNC

VSYNC

HSYNC

ADV7302A/ADV7303A

Table VIII. SD Registers

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

4Ah SD Timing Register 0 SD Slave/Master Mode 0 Slave Mode

1 Master Mode

SD Timing Mode 0 0 Mode 0

01 Mode 1

10 Mode 2

SD Luma Delay 0 0 No Delay

SD Min. Luma Value 0 –40 IRE

SD Timing Reset X 0000000A low-high-low

4Bh SD Timing Register 1 00Ta = 1 Clock Cycle

4Ch SD F

4Dh SD F

4Eh SD F

4Fh SD F

50h SD F

51h SD Closed Captioning Extended Data on Even

52h SD Closed Captioning Extended Data on Even

53h SD Closed Captioning Data on Odd Fields XXXXXXXXData Bits 7–0 00h

54h SD Closed Captioning Data on Odd Fields XXXXXXXXData Bits 15–8 00h

55h SD Pedestal Register 0 Pedestal on Odd Fields 17 16 15 14 13 12 11 10 00h

56h SD Pedestal Register 1 Pedestal on Odd Fields 25 24 23 22 21 20 19 18 00h

57h SD Pedestal Register 2 Pedestal on Even Fields 17 16 15 14 13 12 11 10 00h

58h SD Pedestal Register 3 Pedestal on Even Fields 25 24 23 22 21 20 19 18 00h

Phase XXXXXXXXSubcarrier Phase Bits

SD Delay

SD Rising Edge Delay (Mode 1

Only); VSYNC Width (Mode 2 Only)

Adjust

Fields

Input

Width

to Pixel Data

01 2 Clock Cycles

10 4 Clock Cycles

11 6 Clock Cycles

1 –7.5 IRE

X0 Tc = T

X1 Tc = Tb + 32 µs

00 1 Clock Cycle

01 4 Clock Cycles

10 16 Clock Cycles

11 128 Clock Cycles

00 0 Clock Cycle

01 1 Clock Cycle

10 2 Clock Cycles

11 3 Clock Cycles

XXXXXXXXExtended Data Bits 7–0 00h

XXXXXXXXExtended Data Bits

01Ta = 4 Clock Cycles

10Ta = 16 Clock Cycles

11Ta = 128 Clock Cycles

00 Tb = 0 Clock Cycle

01 Tb = 4 Clock Cycles

10 Tb = 8 Clock Cycles

11 Tb = 18 Clock Cycles

e 3

transistion will reset the internal SD timing counters.

Bits 7–0

Bits 15–8

Bits 23–16

Bits 31–24

9–2

15–8

Setting any of these bits to 1 will disable

pedestal on the line number indicated by

the bit settings.

08h

00h

16h

7Ch

F0h

21h

00h

REV. A

–25–

ADV7302A/ADV7303A

)

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

59h SD CGMS/WSS 0 SD CGMS Data 1 9 18 1 7 1 6 CGMS Data Bits

5Ah SD CGMS/WSS 1 SD CGMS/WSS Data 13 12 11 1 0 9 8 CGMS Data Bits

5Bh SD CGMS/WSS 2 SD CGMS/WSS Data 76543210CGMS/WSS Data Bits

5Ch SD LSB Register SD LSB for Y Scale Value X X SD Y Scale Bits 1–0

5Dh SD Y Scale Register SD Y Scale Value XXXXXXXXSD Y Scale Bits 7–2 00h

5Eh SD V Scale Register SD V Scale Value XXXXXXXXSD V Scale Bits 7–2 00h

5Fh SD U Scale Register SD U Scale Value XXXXXXXXSD U Scale Bits 7–2 00h

60h SD Hue Register SD Hue Adjust Value XXXXXXXXSD Hue Adjust Bits

61h SD Brightness/WSS SD Brightness Value XXXXXXXSD Brightness Bits 6–0

62h SD Luma SSAF SD Luma SSAF

63h SD DNR 0 Coring Gain Border 0000No Gain

Table VIII. SD Registers (continued)

SD CGMS CRC 0 Disabled

1 Enabled

SD CGMS on Odd Fields 0 Disabled

1 Enabled

SD CGMS on Even Fields 0 Disabled

1 Enabled

SD WSS 0 Disabled

1 Enabled

15 14 CGMS Data Bits

SD LSB for U Scale Value X X SD U Scale Bits 1–0

SD LSB for V Scale Value X X SD V Scale Bits 1–0

SD LSB for F

SD Blank WSS Data* 0 Disabled

Gain/Attenuation

Coring Gain Data 0000 No Gain

Phase X X Subcarrier Phase Bits

1 Enabled

00000000–4 dB

000001100 dB

00001100+4 dB

0001+1/16 (–1/8 in DNR

0010+2/16 (–2/8 in DNR

0011+3/16 (–3/8 in DNR

0100+4/16 (–4/8 in DNR

0101+5/16 (–5/8 in DNR

0110+6/16 (–6/8 in DNR

0111+7/16 (–7/8 in DNR

1000+8/16 (–1 in DNR

0001 +1/16 (–1/8 in DNR

0010 +2/16 (–2/8 in DNR

0011 +3/16 (–3/8 in DNR

0100 +4/16 (–4/8 in DNR

0101 +5/16 (–5/8 in DNR

0110 +6/16 (–6/8 in DNR

0111 +7/16 (–7/8 in DNR

1000 +8/16 (–1 in DNR

C19–C16

C13–C8 or WSS Data Bits C13–C8

C15–C14

C7–C0

1–0

7–0

Mode

Mode)

Mode

00h

REV. A–26–

ADV7302A/ADV7303A

Table VIII. SD Registers (continued)

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Register Setting Reset

64h SD DNR 1 DNR Threshold 0000000

0000011

11111062

11111163

Border Area 0 2 Pixels

14 Pixels

Block Size Control 08 Pixels

1 16 Pixels

SD DNR 265h

DNR Mode

DNR Block Offset

66h SD Gamma A SD Gamma Curve A Data

67h SD Gamma A SD Gamma Curve A Data

68h SD Gamma A SD Gamma Curve A Data

69h SD Gamma A SD Gamma Curve A Data

6Ah SD Gamma A SD Gamma Curve A Data

6Bh SD Gamma A SD Gamma Curve A Data

6Ch SD Gamma A SD Gamma Curve A Data

6Dh SD Gamma A SD Gamma Curve A Data

6Eh SD Gamma A SD Gamma Curve A Data

6Fh SD Gamma A SD Gamma Curve A Data

70h SD Gamma B SD Gamma Curve B Data

71h SD Gamma B SD Gamma Curve B Data

72h SD Gamma B SD Gamma Curve B Data

73h SD Gamma B SD Gamma Curve B Data

74h SD Gamma B SD Gamma Curve B Data

75h SD Gamma B SD Gamma Curve B Data

76h SD Gamma B SD Gamma Curve B Data

77h SD Gamma B SD Gamma Curve B Data

78h SD Gamma B SD Gamma Curve B Data

79h SD Gamma B SD Gamma Curve B Data

7Ah SD Brightness Detect SD Brightness Value XXXXXXXXRead-Only

7Bh Field Count Register Field Count XXXRead-Only

Points

Reserved 0 Zero must be written

Reserved Code X X Read-Only

0000 0 Pixel Offset

0001 1 Pixel Offset

1110 14 Pixel Offset

1111 15 Pixel Offset

XXXXXXXXA0 00h

XXXXXXXXA1 00h

XXXXXXXXA2 00h

XXXXXXXXA3 00h

XXXXXXXXA4 00h

XXXXXXXXA5 00h

XXXXXXXXA6 00h

XXXXXXXXA7 00h

XXXXXXXXA8 00h

XXXXXXXXA9 00h

XXXXXXXXB0 00h

XXXXXXXXB1 00h

XXXXXXXXB2 00h

XXXXXXXXB3 00h

XXXXXXXXB4 00h

XXXXXXXXB5 00h

XXXXXXXXB6 00h

XXXXXXXXB7 00h

XXXXXXXXB8 00h

XXXXXXXXB9 00h

001Filter A

010Filter B

011Filter C

100Filter D

0DNR Mode

1 DNR Sharpness Mode

to this bit.

00h

00hDNR Input Select

REV. A

–27–

ADV7302A/ADV7303A

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

7Ch Reset Register Timing Reset 0 No reset of Timing

*Line 23

HSYNC

VSYNC

Table VIII. SD Registers (continued)

Generator in Subcarrier Reset Mode. 44h, Bits

1 and 2 must be set to Subcarrier Reset.

1 Reset Timing

Generator in Subcarrier Reset Mode

Reserved 0 Zero must be written to

LINE 313 LINE 314LINE 1

this bit.

00h

Figure 19. Timing Register 1 in PAL Mode

Table IX. Macrovision Registers*

Subaddress Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

7Dh Reserved

7Eh Reserved

7Fh Reserved

80h Macrovision MV Control Bits XXXXXXXXMV 3a [7:0] 00h

81h Macrovision MV Control Bits XXXXXXXXMV 3b [15:8] 00h

82h Macrovision MV Control Bits XXXXXXXXMV 3c [23:16] 00h

83h Macrovision MV Control Bits XXXXXXXXMV 3d [31:24] 00h

84h Macrovision MV Control Bits XXXXXXXXMV 3e [39:32] 00h

85h Macrovision MV Control Bits XXXXXXXXMV 3f [47:40] 00h

86h Macrovision MV Control Bits XXXXXXXXMV 40 [55:48] 00h

87h Macrovision MV Control Bits XXXXXXXXMV 41 [63:56] 00h

88h Macrovision MV Control Bits XXXXXXXXMV 42 [71:64] 00h

89h Macrovision MV Control Bits XXXXXXXXMV 43 [79:72] 00h

8Ah Macrovision MV Control Bits XXXXXXXXMV 44 [87:80] 00h

8Bh Macrovision MV Control Bits XXXXXXXXMV 45 [95:88] 00h

8Ch Macrovision MV Control Bits XXXXXXXXMV 46 [103:96] 00h

8Dh Macrovision MV Control Bits XXXXXXXXMV 47 [111:104] 00h

8Eh Macrovision MV Control Bits XXXXXXXXMV 48 [119:112] 00h

8Fh Macrovision MV Control Bits XXXXXXXXMV 49 [127:120] 00h

90h Macrovision MV Control Bits XXXXXXXXMV 4A [135:128] 00h

MV Control BitMacrovision91h 00h

0000000 Zero must be written

*Macrovision Registers are only available on the ADV7302A.

X MV 4B [136]

to these bits.

REV. A–28–

ADV7302A/ADV7303A

DELAY

9.25ns OR

DELAY

27.75ns

INPUT AND OUTPUT CONFIGURATION STANDARD DEFINITION ONLY

The 8-bit multiplexed input data is input on Pins S7–S0, with S0 being the LSB. ITU-R.BT601/ITU-R.BT656 input standards are supported. In 16-bit Input Mode, the Y pixel data is input on Pins S7–S0 and CrCb data on Pins Y7–Y0. The 27 MHz clock input must be input on Pin CLKIN_A. Input sync signals are optional and are input on the S_VSYNC, S_HSYNC, and S_BLANK pins.

ADV7302A/

ADV7303A

S_VSYNC

MPEG2

DECODER

YCrCb

27MHz

S_HSYNC S_BLANK

CLKIN_A

S7–S0

Figure 20. Standard Definition Only Input Mode

PROGRESSIVE SCAN ONLY OR HDTV ONLY

YCrCb Progressive Scan, HDTV, or any other HD YCrCb data can be input in 4:2:2 or 4:4:4 format. In 4:2:2 Input Mode, the Y data is input on Pins Y7–Y0 and the CrCb data on Pins C7– C0. In 4:4:4 Input Mode, Y data is input on Pins Y7–Y0, Cb data on Pins C7–C0, and Cr data on Pins S7–S0. If the YCrCb data does not conform to SMPTE293M (525 p), ITU-R.BT1358M (625 p), SMPTE274M (1080 i), SMPTE296M (720 p), or BTA-T1004, the Async Timing Mode must be used. RGB data can only be input in 4:4:4 format in PS Input Mode only, or HDTV Input Mode only, when HD RGB input is enabled. G data is input on Pins Y7–Y0, R data on S7–S0, and B data on Pins C7–C0. The clock signal must be input on Pin CLKIN_A. Synchronization signals are optional and are input on Pins P_VSYNC, P_HSYNC, and P_BLANK.

MPEG2

DECODER

YCrCb

INTERLACED

PROGRESSIVE

27MHz

ADV7302A/

ADV7303A

CLKIN_A

S7–S0

C7–C0

Y7–Y0

P_VSYNC P_HSYNC

P_BLANK

Figure 21. Progressive Scan Only Input Mode

SIMULTANEOUS STANDARD DEFINITION AND PROGRESSIVE SCAN OR HDTV

YCrCb PS, HDTV, or any other HD data must be input in 4:2:2 format. In 4:2:2 Input Mode, the Y data is input on Pins Y7–Y0 and the CrCb data on C7–C0. If PS 4:2:2 data is interleaved onto a single 8-bit bus, Pins Y7–Y0 are used for the input port. The interleaved data is to be input at 27 MHz in setting the Input Mode Register at Address 01h accordingly. If the YCrCb data does not conform to SMPTE293M (525 p), ITU-R.BT1358M (625 p),

SMPTE274M (1080 i), SMPTE296M (720 p), or BTA-T1004, the Async Timing Mode must be used.

The 8-bit standard definition data must be compliant to ITUR.BT601/ITU-R.BT656 in 4:2:2 format. Standard definition data is input on Pins S7–S0, with S0 being the LSB. The clock input for SD must be input on CLKIN_A, and the clock input for HD must be input on CLKIN_B. Synchronization signals are optional. SD syncs are input on Pins S_VSYNC, S_HSYNC, and S_BLANK; the HD syncs on Pins P_VSYNC, P_HSYNC, and P_BLANK.

ADV7302A/

ADV7303A

S_VSYNC

27MHz

CrCb

27MHz

S_HSYNC S_BLANK

CLKIN_A

S7–S0

C7–C0

Y7–Y0

P_VSYNC P_HSYNC

P_BLANK

CLKIN_B

MPEG2

DECODER

YCrCb

INTERLACED

PROGRESSIVE

Figure 22. Simultaneous Progressive Scan and SD Input

ADV7302A/

ADV7303A

S_VSYNC

S_HSYNC S_BLANK

CLKIN_A

S7–S0

C7–C0

Y7–Y0

P_VSYNC P_HSYNC

P_BLANK

CLKIN_B

SDTV

DECODER

HDTV



DECODER

1080 i

720 p

27MHz

YCrCb

CrCb

74MHz

Figure 23. Simultaneous HDTV and SD Input

If in Simultaneous Input Mode the two clock phases differ by less than 9.25 ns or more than 27.75 ns, the Clock Align Bit must be set accordingly. This also applies if the Pixel Align Bit is set. If the application uses the same clock source for both SD and PS, the Clock Align Bit must be set since the phase difference between both inputs is less than 9.25 ns.

Figure 24. Clock Phase with Two Input Clocks

REV. A

–29–

ADV7302A/ADV7303A

PROGRESSIVE SCAN AT 27 MHz OR 54 MHz

YCrCb progressive scan data can be input at 27 MHz or 54 MHz. The input data is interleaved onto a single 8-bit bus and is input on Pins Y7–Y0. For PS Input Only Mode, the input clock must be input on CLKIN_A. In Simultaneous SD/HD Mode, the input clock is input on CLKIN_B.

MPEG2

DECODER

YCrCb

INTERLACED

PROGRESSIVE

27MHz OR

54MHz

YCrCb

ADV7302A/

ADV7303A

CLKIN_A

Y7–Y0

P_VSYNC P_HSYNC

P_BLANK

Figure 25. 1 ⫻ 8-Bit PS @ 27 MHz or 54 MHz

When the input sequence of the PS data, i.e., 8-bit interleaved at 27 MHz, starts with Y0 data as shown in Figure 26, PIXEL ALIGN [Subaddress 01h] must be set to “0.” In this case, the timing information embedded in the data stream is recognized and the video data is transferred to the according Y channel and CrCb channel processing blocks.

CLKIN_A

PIXEL INPUT

DATA

3FF 00 00 XY Y0 Cb0 Y1 Cr0

Figure 26. Input Sequence in PS 8-Bit Interleaved Mode, EAV/SAV Followed by Y0 Data

If the input sequence starts with Cb0 data as shown in Figure 27, initially PIXEL ALIGN [Subaddress 01h] must be set to “0.” This ensures that the ADV7302A/ADV7303A locks to the input sequence in decoding the embedded timing information correctly. For correct color decoding, the Pixel Align Bit [Subaddress 01h] must then be set to “l” after a delay of one field. The ADV7302A/ADV7303A is now in free run mode, any changes in the timing information are ignored.

CLKIN_A

PIXEL INPUT

DATA

3FF 00 00 XY Cb0 Y0 Cr0 Y1

Figure 27. Input Sequence in PS 8-Bit Interleaved Mode, EAV/SAV Followed by Cb0 Data

PS 8-bit interleaved at 54 MHz must be input with separate timing signals. EAV/SAV codes cannot be used in this mode.

REV. A–30–

ADV7302A/ADV7303A

Table X. Overview of All Possible Input Configurations

Input Format Total Bits Input Video Input Pins Subaddress Reg ister Setting

ITU-R.BT656 8 4:2:2 YCrCb S7–S0 [MSB = S7] 01h, 48h 00h, 00h

4:2:216

Y S7–S0 [MSB = S7]

CrCb Y7–Y0 [MSB = Y7]

PS Only 8 (27 MHz Clock) 4:2:2 YCrCb Y7–Y0 [MSB = Y7] 01h, 13h 10h, 40h

8 (54 MHz Clock) 4:2:2 YCrCb Y7–Y0 [MSB = Y7] 01h, 13h 70h, 40h

4:2:216

Y Y7–Y0 [MSB = Y7]

CrCb C7–C0 [MSB = C7]

24 4:4:4

HDTV Only 8 4:2:2 YCrCb Y7–Y0 [MSB = Y7] 01h, 13h 20h, 40h

24 4:4:4

HD RGB G Y7–Y0 [MSB = Y7]

ITU-R.BT656 and PS

ITU-R.BT656 and PS or HDTV

24 4:4:4

84:2:2 YCrCb S7–S0 [MSB = S7] 01h 40h

84:2:2 YCrCb Y7–Y0 [MSB = Y7] 13h, 48h 40h, 00h

84:2:2 YCrCb S7–S0 [MSB = S7] 01h 30h, 50h, or

16 4:2:2 13h, 48h 40h, 00h

Y Y7–Y0 [MSB = Y7]

Cb C7–C0 [MSB = C7]

Cr S7–S0 [MSB = S7]

4:2:2

Y Y7–Y0 [MSB = Y7]

CrCb C7–Y0 [MSB = C7]

Y Y7–Y0 [MSB = Y7]

Cb C7–Y0 [MSB = C7]

Cr S7–S0 [MSB = S7]

B C7–C0 [MSB = C7]

R S7–S0 [MSB = S7]

Y Y7–Y0 [MSB = Y7]

CrCb C7–C0 [MSB = C7]

01h, 48h 00h, 08h

01h, 13h 10h, 40h

01h, 13h 10h, 00h

01h, 13h 20h, 40h

01h, 13h 20h, 00h

01h, 13h, 15h

10h or 20h, 00h, 02h

60h

REV. A

–31–

ADV7302A/ADV7303A

OUTPUT CONFIGURATION

Tables XI–XIII demonstrate what output signals are assigned to the DACs when corresponding control bits are set.

Table XI. Output Configuration in SD Only Mode

RGB/YUV O/P SD DAC O/P 1 SD DAC O/P 2 Addr 02h, Bit 5 Addr 42h, Bit 2 Addr 42h, Bit 1 DAC A DAC B DAC C DAC D DAC E DAC F

00 0CVBS Luma Chroma G B R 00 1GBRCVBS Luma Chroma 01 0GLuma Chroma CVBS B R 01 1CVBS B R G Luma Chroma 10 0CVBS Luma Chroma Y U V 10 1YUV CVBS Luma Chroma 11 0YLuma Chroma CVBS U V 11 1CVBS U V Y Luma Chroma

Table XII. Output Configuration in HD Only Mode

HD I/P HD RGB I/P RGB/YUV O/P HD Color Swap Format Addr 15h, Bit 1 Addr 02h, Bit 5 Addr 15h, Bit 3 DAC A DAC B DAC C DAC D DAC E DAC F

YCrCb 4:2:2 N/A 0 0 N/A N/A N/A G B R YCrCb 4:2:2 N/A 0 1 N/A N/A N/A G R B YCrCb 4:2:2 N/A 1 0 N/A N/A N/A Y Pb Pr YCrCb 4:2:2 N/A 1 1 N/A N/A N/A Y Pr Pb YCrCb 4:4:4 N/A 0 0 N/A N/A N/A G B R YCrCb 4:4:4 N/A 0 1 N/A N/A N/A G R B YCrCb 4:4:4 N/A 1 0 N/A N/A N/A Y Pb Pr YCrCb 4:4:4 N/A 1 1 N/A N/A N/A Y Pr Pb RGB 4:4:4 100N/AN/A N/A G B R RGB 4:4:4 101N/AN/A N/A G R B RGB 4:4:4 110N/AN/A N/A G B R RGB 4:4:4 111N/AN/A N/A G R B

Table XIII. Output Configuration in Simultaneous SD/HD Mode

RGB/YUV O/P HD Color Swap

Input Formats Addr 02h, Bit 5 Addr 15h, Bit 3 DAC A DAC B DAC C DAC D DAC E DAC F

SD YCrCb in 4:2:2 and HD YCrCb in 4:2:2 0 0 CVBS Luma Chroma G B R

SD YCrCb in 4:2:2 and HD YCrCb in 4:2:2 0 1 CVBS Luma Chroma G R B

SD YCrCb in 4:2:2 and HD YCrCb in 4:2:2 1 0 CVBS Luma Chroma Y Pb Pr

SD YCrCb in 4:2:2 and HD YCrCb in 4:2:2 1 1 CVBS Luma Chroma Y Pr Pb

REV. A–32–

ADV7302A/ADV7303A

TIMING MODES HD Async Timing Mode [Subaddress 10h, Bits 3–2]

For any input data that does not conform to SMPTE293M, SMPTE274M, SMPTE296M, or ITU-R.BT1358 standards, an Asynchronous Timing Mode can be used to interface to the ADV7302A/ADV7303A. Timing control signals for HSYNC, VSYNC, and BLANK have to be programmed by the user. Macrovision is not available in Async Timing Mode.

Figure 28 shows an example of how to program the ADV7302A/ ADV7303A to accept a different high definition standard other than SMPTE293M, SMPTE274M, SMPTE296M, or ITU-R.BT1358 standards.

Table XIV must be followed when programming the control signals in Async Timing Mode.

HD Timing Reset

A timing reset is achieved in setting the HD Timing Reset Control Bit at Address 14h from “0” to “1.” In this state, the horizontal and vertical counters will remain reset. On setting this bit back to “0,” the internal counters will again commence counting. The minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the HD timing counters only.

SD Timing Real-time Control, Subcarrier Reset, Timing Reset [Subaddress 44h, Bits 2–1]

Together with the RTC_SCR_TR Pin and SD Mode Register 3 [Address 44h, Bits 1–2] the ADV7302A/ADV7303A can be used in Timing Reset Mode, Subcarrier Phase Reset Mode, or RTC Mode.

a. A timing reset is achieved in a low-to-high transition on the

RTC_SCR_TR Pin (Pin 31). In this state, the horizontal and vertical counters will remain reset. On releasing this pin (set to low), the internal counters will again commence counting. The minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the SD timing counters only.

b. Subcarrier phase reset, a low-to-high transition on the

RTC_SCR_TR pin (Pin 31), will reset the subcarrier phase to zero when the SD RTC/TR/SCR control bits at Address 44h are set to “01.” This reset signal will have to be held high for a minimum of one clock cycle. Since the Field Counter is not reset, it is recommended to apply the reset in Field 7 (PAL). The reset of the phase will then occur on the next field by being correctly lined up with the internal counters. The Field Count Register at Address 7Bh can be used to identify the number of the active field.

c. In RTC Mode, the ADV7302A/ADV7303A can be used to

lock to an external video source. The Real-time Control Mode allows the ADV7302A/ADV7303A to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device that outputs a digital data stream in the RTC format (such as a ADV7185 video decoder, see Figure 29), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00h should be written into all four Subcarrier Frequency Registers when using this mode.

CLK

P_HSYNC

P_VSYNC

P_BLANK*

81 66 66 243 1920

*SET ADDRESS 10h, BIT 6 TO “1”

Figure 28. Async Timing Mode, Programming Input Control Signals for SMPTE295M Compatibility

HORIZONTAL SYNC

ab c d

ACTIVE VIDEO

PROGRAMMABLE INPUT TIMING

ANALOG OUTPUT

REV. A

–33–

ADV7302A/ADV7303A

Table XIV. Truth Table

P_HSYNC P_VSYNC

P_BLANK

1 → 0 0 0 or 1 50% point of falling edge of tri-level horizontal sync signal a 00 → 1 0 or 1 25% point of rising edge of tri-level horizontal sync signal b 0 → 1 0 or 1 0 50% point of falling edge of tri-level horizontal sync signal c 10 or 1 0 → 1 50% start of active video d 10 or 1 1 → 0 50% end of active video e

NOTES For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.

When Async Timing Mode is enabled, P_BLANK, Pin 25 becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.

See Figure 28.

ADV7302A/

ADV7303A

Reference

CLKIN_A

LCC1

COMPOSITE

VIDEO

H/L TRANSITION

COUNT START

RTC

TIME SLOT 01

NOTES

i.e., VCR OR CABLE

PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7302A/ADV7303A FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0

PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7302A/ADV7303A.

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE

RESET ADV7302A/ADV7303A DDS

128

ADV7185

VIDEO

DECODER

RESERVED

LOW

13 0

P19–P12

14 BITS

NOT USED

GLL

4 BITS

RESERVED

142119

RTC_SCR_TR

S7–S0

Figure 29. RTC Timing and Connections

SD VCR FF/RW Sync [Subaddress 42h, Bit 5]

In DVD record applications where the encoder is used with a decoder, the VCR FF/RW Sync Control Bit can be used for nonstandard input video, i.e., in Fast Forward or Rewind Modes. In Fast Forward Mode, the sync information for the start of a new field in the incoming video usually occurs before the total number of lines/fields are reached; in Rewind Mode, this sync signal occurs usually after the total number of lines/fields are reached. Conventionally, this means that the output video will have an erroneous start of new field signals, one generated by the incoming video and one when the internal lines/field counters reach the end of a field. When VCR FF/RW sync control is enabled

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

PLL INCREMENT

VALID

INVALID

SAMPLE

SEQUENCE

BIT

8/LINE

LOCKED

CLOCK

6768

5 BITS

RESERVED

RESET

BIT

RESERVED

[Subaddress 42h, Bit 5] the lines/field counters are updated according to the incoming VSYNC signal, and the analog output matches the incoming VSYNC signal.

This control is available in all slave timing modes except Slave Mode 0.

RESET SEQUENCE

A reset is activated with a high-to-low transition on the RESET Pin (Pin 33) according to the timing specifications. The ADV7302A/ADV7303A will revert to the default output configuration. Figure 30 illustrates the RESET sequence timing.

RESET

DACs

DIGITAL TIMING

PIXEL DATA

VALID

DIGITAL TIMING SIGNALS SUPPRESSED

Figure 30.

OFF

RESET

Timing Sequence

VALID VIDEO

TIMING ACTIVE

REV. A–34–

ADV7302A/ADV7303A

FREQUENCY – MHz

0.5

–0.5

0305

GAIN – dB

10 15 20 25

0.4

0.1

–0.2

–0.3

–0.4

0.3

0.2

–0.1

VERTICAL BLANKING INTERVAL

The ADV7302A/ADV7303A accepts input data that contains VBI data [CGMS, WSS, VITS, etc.] in SD and HD Modes.

For SMPTE293M (525 p) standards, VBI data can be inserted on Lines 13 to 42 of each frame, or Lines 6 to 43 for ITU-R.BT1358 (625 p) standard.

For SD NTSC this data can be present on Lines 10 to 20, in PAL on Lines 7 to 22.

If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h, Bit 4 for SD] VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave modes.

In Slave Mode 0, if VBI is enabled, the Blanking Bit in the EAV/SAV code is overwritten and it is possible to use VBI in this timing mode as well.

In Slave Mode 1 or 2, the BLANK Control Bit must be set to enabled [Address 4Ah, Bit 3] to allow VBI data to pass through the ADV7302A/ADV7303A. Otherwise the ADV7302A/ ADV7303A automatically blanks the VBI to standard.

If CGMS is enabled and VBI disabled, the CGMS data will nevertheless be available at the output.

SUBCARRIER FREQUENCY REGISTER [Subaddress 4Ch–4Fh]

Four 8-bit wide registers are used to set up the subcarrier frequency. The value of these registers is calculated in using the equation:

FILTERS

Table XV shows an overview of the programmable filters available on the ADV7302A/ADV7303A.

Table XV. Selectable Filters

Filter Subaddress

SD Luma LPF NTSC 40h SD Luma LPF PAL 40h SD Luma Notch NTSC 40h SD Luma Notch PAL 40h SD Luma SSAF 40h SD Luma CIF 40h SD Luma QCIF 40h SD Chroma 0.65 MHz 40h SD Chroma 1.0 MHz 40h SD Chroma 1.3 MHz 40h SD Chroma 2.0 MHz 40h SD Chroma 3.0 MHz 40h SD Chroma CIF 40h SD Chroma QCIF 40h SD UV SSAF 42h HD Chroma Input 13h HD Sync Filter 13h HD Chroma SSAF 13h

HD Sync Filter

Subcarrier Frequency Register =

##of Subcarrier Frequency Cycles in One Video Line

of MHz Clock Cycles in One Video Line27

Example: NTSC Mode

227 5

Subcarrier Frequency =

1716

2 569408542

×= *

Subcarrier Register Value = 21F07C1Eh

SD F SD F SD F SD F

Refer to the MPU Port Description section for more detail on how to access the Subcarrier Frequency Registers.

SUBCARRIER PHASE REGISTER [Subaddress 50h, 5Ch, Bits 7, 6]

Ten bits are used to set up the subcarrier phase. Each bit represents 0.352°. For normal operation, this register is set to 00h.

*Rounded to the nearest integer

REV. A

–35–

Figure 31. HD Sync Filter Enabled

0.5

0.4

0.3

0.2

0.1

GAIN – dB

–0.1

–0.2

–0.3

–0.4

–0.5

10 15 20 25

FREQUENCY – MHz

Figure 32. HD Sync Filter Disabled

305

ADV7302A/ADV7303A

HD 4:2:2 to 4:4:4 Interpolation Filters and Chroma SSAF

It is recommended to input data in 4:2:2 Input Mode to make use of the HD chroma SSAFs on the ADV7302A/ADV7303A. This filter has a 0 dB pass-band response and prevents signal components from being folded back into the frequency band. In 4:4:4 Input Mode, the video data is already interpolated by the external input device and the chroma SSAFs of the ADV7302A/ ADV7303A are bypassed.

–10

–20

–30

–40

GAIN – dB

–50

–60

–70

–80

0 11010

20 30 40 50 60 70 80 90 100

FREQUENCY – MHz

Figure 33. Y – PS 4⫻ Oversampling Filter

The chroma SSAF is controlled with Address 13h, Bit 5. When the HD input format is 4:2:2, the HD Chroma Input Bit [Address 13h, Bit 6] must be set to “1.”

2/4/8 Oversampling Filters

The oversampling filters are enabled in setting the PLL ON control [Subaddress 00h, Bit 1] to “1.” If enabled, PS and ITU-R.BT656 data is output at a rate of 108 MHz, HDTV at a rate of 148 MHz.

–10

–20

–30

–40

GAIN – dB

–50

–60

–70

–80

0 16020

40 60 80 100 120 140

FREQUENCY – MHz

Figure 35. Y – HDTV 2⫻ Oversampling Filter

1.0

0.5

–0.5

–1.0

GAIN – dB

–1.5

–2.0

–2.5

–3.0

4681012 14

FREQUENCY – MHz

Figure 34. Y – PS 4⫻ Oversampling Filter in the Pass Band

1.0

0.5

–0.5

–1.0

GAIN – dB

–1.5

–2.0

–2.5

–3.0

10 15 20 25 30 35

FREQUENCY – MHz

Figure 36. Y – HDTV 2⫻ Oversampling Filter in the Pass Band

REV. A–36–

ADV7302A/ADV7303A

–10

–20

–30

–40

GAIN – dB

–50

–60

–70

–80

0 11010

20 30 40 50 60 70 80 90 100

FREQUENCY – MHz

Figure 37. UV – HDTV 2⫻ Oversampling Filter

–10

–20

–30

–40

GAIN – dB

–50

1.0

0.5

–0.5

–1.0

GAIN – dB

–1.5

–2.0

–2.5

–3.0

0182

4681012 14 16

FREQUENCY – MHz

Figure 39. UV – HDTV 2⫻ Oversampling Filter, Pass Band

–10

–20

–30

–40

GAIN – dB

–50

–60

–70

–80

0 11010

20 30 40 50 60 70 80 90 100

FREQUENCY – MHz

Figure 38. UV – PS 4⫻ Oversampling Filter, Linear

–60

–70

–80

0 11010

20 30 40 50 60 70 80 90 100

FREQUENCY – MHz

Figure 40. UV – PS 4⫻ Oversampling Filter, SSAF

REV. A

–37–

ADV7302A/ADV7303A

SD Internal Filter Response [Subaddress 42h, Bit 0]

The Y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost/attenuation, a CIF response, and a QCIF response. The UV filter supports several different frequency responses including six low-pass responses, a CIF response, and a QCIF response, as can be seen in Figures 41–59.

If SD SSAF gain is enabled, there is the option of 12 responses in the range from –4 dB to +4 dB. The desired response can be chosen by the user by programming the correct value via the I2C. The variation of frequency responses can be seen in Figures 41–59.

In addition to the chroma filters listed above, the ADV7302A/ ADV7303A contains an SSAF filter specifically designed for and applicable to the color difference component outputs U and V. This filter has a cutoff frequency of approximately 2.7 MHz and –40 dB at 3.8 MHz, as shown in Figure 41. This filter can be controlled via Address 42h, Bit 0. If this filter is disabled, the selectable chroma filters shown in Table XVI can be used for the CVBS or chroma signal.

Table XVI. Internal Filter Specifications

Pass-Band 3 dB

Filter Ripple1 (dB) Bandwidth2 (MHz)

Luma LPF NTSC 0.16 4.24 Luma LPF PAL 0.1 4.81 Luma Notch NTSC 0.09 2.3/4.9/6.6 Luma Notch PAL 0.1 3.1/5.6/6.4 Luma SSAF 0.04 6.45 Luma CIF 0.127 3.02 Luma QCIF Monotonic 1.5 Chroma 0.65 MHz Monotonic 0.65 Chroma 1.0 MHz Monotonic 1 Chroma 1.3 MHz 0.09 1.395 Chroma 2.0 MHz 0.048 2.2 Chroma 3.0 MHz Monotonic 3.2 Chroma CIF Monotonic 0.65 Chroma QCIF Monotonic 0.5

NOTES

Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter, 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the –3 dB points.

3 dB bandwidth refers to the –3 dB cutoff frequency.

–10

–20

–30

GAIN – dB

–40

–50

–60

02345

FREQUENCY – MHz

Figure 41. UV SSAF Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 42. Luma NTSC Low-Pass Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 43. Luma PAL Low-Pass Filter

REV. A–38–

ADV7302A/ADV7303A

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 44. Luma NTSC Notch Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 47. Luma SSAF Filter up to 12 MHz

–2

–4

–6

MAGNITUDE – dB

–8

–10

–12

01234 7

FREQUENCY – MHz

Figure 45. Luma PAL Notch Filter

–10

–20

–30

–40

GAIN – dB

–50

–60

–70

–80

0 11010

20 30 40 50 60 70 80 90 100

FREQUENCY – MHz

Figure 46. Luma SSAF Filter up to 108 MHz

Figure 48. Luma SSAF Filter, Programmable Responses

MAGNITUDE – dB

–1

01234 7

FREQUENCY – MHz

Figure 49. Luma SSAF Filter, Programmable Gain

REV. A

–39–

ADV7302A/ADV7303A

–1

–2

MAGNITUDE – dB

–3

–4

–5

01234 7

FREQUENCY – MHz

Figure 50. Luma SSAF Filter, Programmable Attenuation

–10

–20

–30

–40

MAGNITUDE – dB

–50

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 53. Chroma 3.0 MHz LP Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 51. Luma CIF LP Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 52. Luma QCIF LP Filter

–60

–70

02468 12

FREQUENCY – MHz

Figure 54. Chroma 2.0 MHz LP Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 55. Chroma 1.3 MHz LP Filter

REV. A–40–

ADV7302A/ADV7303A

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 56. Chroma 1.0 MHz LP Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 58. Chroma CIF LP Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02468 12

FREQUENCY – MHz

Figure 57. Chroma 0.65 MHz LP Filter

–60

–70

02468 12

FREQUENCY – MHz

Figure 59. Chroma QCIF LP Filter

REV. A

–41–

ADV7302A/ADV7303A

COLOR CONTROLS AND RGB MATRIX HD Y Color, HD Cr Color, HD Cb Color [Subaddresses 16h–18h]

Three 8-bit wide registers at Addresses 16h, 17h, and 18h are used to program the output color of the internal HD test pattern generator, be it the lines of the cross hatch pattern or the uniform field test pattern. They are not functional as color controls on external pixel data input. For this purpose, the RGB matrix is used.

The standard used for the values for Y and the color difference signals to obtain white, black, and the saturated primary and complementary colors conforms to the ITU-R.BT601– ITU-R.BT604 standards. Table XVII shows sample color values to be programmed into the color registers when Output Standard Selection is set to EIA 770.2.

Table XVII. Sample Color Values for EIA 770.2 Output Standard Selection

Sample Color Y Color Cr Color Cb Color Value Value Value

White 235 (EB) 128 (80) 128 (80) Black 16 (10) 128 (80) 128 (80) Red 81 (51) 240 (F0) 90 (5A) Green 145 (91) 34 (22) 54 (36) Blue 41 (29) 110 (6E) 240 (F0) Yellow 210 (D2) 146 (92) 16 (10) Cyan 170 (AA) 16 (10) 166 (A6) Magenta 106 (6A) 222 (DE) 202 (CA)

HD RGB Matrix [Subaddresses 03h–09h]

When the programmable RGB matrix is disabled [Address 02h, Bit 3], the internal RGB matrix takes care of all YCrCb to YUV or RGB scaling according to the input standard programmed into the device.

When the programmable RGB matrix is enabled, the color components are converted according to the SMPTE274M standard (1080 i):

YRG B

0 2126 0 7152 0 0722

'. ' . '. '

=×

()

This is reflected in the preprogrammed values for GY = 13Bh, RV = 1F0h, BU = 248h, GV = 93h, and GU = 3Bh.

If another input standard is used the scale values for GY, GU, GV, BU, and RV have to be adjusted according to this input standard. It must be considered by the user that the color component conversion might use different scale values. For example, SMPTE293M uses the following conversion:

YR G B

0 299 0 587 0 114

'. ' . '. '

=×

()

The programmable RGB matrix can be used to control the HD output levels in cases where the video output does not conform to

+×

()

Cb B Y

−

100722

−

102126

+×

()

Cb B Y

−

10114

−

10299

+×

×−

()

×−

()

+×

×−

()

×−

()

standards due to altering the DAC output stages, such as termination resistors. The programmable RGB matrix is used for external HD data and is not functional when the HD test pattern is enabled.

To make use of the programmable RGB matrix, the YCrCb data should contain the HSYNC signal on the Y channel only. The RGB matrix should be enabled [Address 02h, Bit 3], the output should be set to RGB [Address 02h, Bit 3], Sync on PrPb should be disabled [Address 15h, Bit 2], and Sync on RGB is optional [Address 02h, Bit 4].

GY at Addresses 03h and 05h control the output levels on the green signal, BU at 04h and 08h the blue signal output levels and RV at 04h and 09h the red output levels. To control YPrPb output levels, YUV output should be enabled [Address 02h, Bit 5]. In this case GY [Address 05h; Address 03, Bits 0–1] is used for the Y output, RV [Address 09; Address 04, Bits 0–1] is used for the Pr output, and BU [Address 08h; Address 04h, Bits 2–3] is used for the Pb output.

If RGB output is selected, the RGB matrix scaler uses the following equations:

RGYYRV

=×+×

GGYYGUCb GV

=×−×−×

B=GY Y+BU Cb

If YUV output is selected the following equations are used:

On power-up, the RGB matrix is programmed with default values:

Address 03h: 03h Address 04h: F0h Address 05h: 4Eh Address 06h: 0Eh Address 07h: 24h Address 08h: 92h Address 09h: 7Ch

When the programmable RGB matrix is not functional, the ADV7302A/ADV7303A automatically scales YCrCb inputs to all standards supported. For SMPTE293M, the register values are as follows:

Address 03h: 03h Address 04h: 1Eh Address 05h: 4Eh Address 06h: 1Bh Address 07h: 38h Address 08h: 8Bh Address 09h: 6Eh

Address 15h, Bit 3 must be set to “1” in this mode.

SD Color Control [Subaddresses 5Ch, 5Dh, 5Eh, and 5Fh]

SD Y SCALE, SD Cr SCALE, and SD Cb SCALE are three 10-bit wide control registers to scale the Y, U, and V output levels.

Each of these registers represents the value required to scale the U or V level from 0 to 2.0 and the Y level from 0 to 1.5 of its initial level. The value of these 10 bits is calculated using the equation:

Y, U, or V Scalar Value = Scale Factor ⫻ 512

××

RRV

=×

GGYY

=×

BBUCb

=×

REV. A–42–

ADV7302A/ADV7303A

Example: Scale Factor = 1.18

Y, U, or V Scale Value = 1.18 ⫻ 512 = 665.6

Y, U, or V Scale Value = 665 (rounded to nearest integer)

Y, U, or V Scale Value = 1010011001

Address 5Ch, SD LSB Register = 15h Address 5Dh, SD Y Scale Register = A6h Address 5Eh, SD V Scale Register = A6h Address 5Fh, SD U Scale Register = A6h

SD Hue Adjust Value [Subaddress 60h]

The Hue Adjust Value is used to adjust the hue on the composite and chroma outputs.

These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7302A/ADV7303A provides a range of ±22.5° in increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 80h. FFh and 00h represent the attainable upper and lower limit (respectively) of adjustment.

For a positive hue adjust value:

0.17578125° ⫻ (HCR – 128)

Example: To adjust the hue by +4°, write 97h to the Hue Adjust Value Register:

0 17578125

where 151 is rounded to the nearest integer. To adjust the hue by –4°,

write 69h to the Hue Adjust Value Register:

–.4

0 17578125

128 151 97.h

+==

128 105 69+==h

where 105 is rounded to the nearest integer.

SD Brightness Control [Subaddress 61h]

The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added

onto the scaled Y data. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and for PAL, the setup can vary from –7.5 IRE to +15 IRE.

The Brightness Control Register is an 8-bit wide register. Seven bits are used to control the brightness level. This brightness level can be a positive or negative value.

Example: Standard: NTSC with pedestal. To add +20 IRE brightness level, write 28h to Address 61h, SD Brightness:

SD Brightness Value (hex) = (IRE Value ⫻ 2.015631)

28h = (20 ⫻ 2.015631) = 40.31262

Standard: PAL. To add –7 IRE brightness level, write 72h to Address 61h, SD Brightness:

SD Brightness Value (hex) = (IRE Value ⫻ 2.015631)

0001110

= (7 ⫻ 2.015631) = 14.109417

0001110 in twos complement equals 1110010, or 72h.

SD Brightness Detect [Subaddress 7Ah]

The ADV7302A/ADV7303A allows monitoring of the brightness level of the incoming video data. The Brightness Detect Register is a read-only register.

Double Buffering [Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]

Double buffered registers are updated once per field on the falling edge of the VSYNC signal. Double buffering improves the overall performance since modifications to register settings will not be made during active video but take effect on the start of the active video.

Double buffering can be activated on the following HD registers: HD Gamma A and Gamma B curves and HD CGMS Registers. Double buffering can be activated on the following SD Registers: SD Gamma A and Gamma B Curves, SD Y Scale, SD U Scale, SD V Scale, SD Brightness, SD Closed Captioning, and SD Macrovision Bits 5–0.

REV. A

Table XVIII. Brightness Control Values

Setup Level— Setup Level— Setup Level— SD Brightness NTSC w/Pedestal (IRE) NTSC w/o Pedestal (IRE) PAL (IRE) Value

22.5 +15 +15 1Eh 15 +7.5 +7.5 0Fh

7.5 0 0 00h 0 –7.5 –7.5 71h

Values in the range from 3Fh to 44h might result in an invalid output signal.

NTSC WITHOUT PEDESTAL

100 IRE

0 IRE

NO SETUP

VALUE ADDED

POSITIVE SETUP

VALUE ADDED

NEGATIVE SETUP

VALUE ADDED

+7.5 IRE

–7.5 IRE

Figure 60. Examples for Brightness Control Values

–43–

ADV7302A/ADV7303A

Gamma Correction [Subaddresses 21h–37h for HD; Subaddresses 66h–79h for SD]

Gamma correction is available for SD and HD video. For each standard there are 20 8-bit wide registers. They are used to program the gamma correction curves A and B. HD Gamma Curve A is programmed at Addresses 24h–2Dh, HD Gamma Curve B at 2Eh–37h. SD Gamma Curve A is programmed at Addresses 66h–6Fh, and SD Gamma Curve B at Addresses 70h–79h.

Generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used.

Gamma correction uses the function:

Signal Signal

()

OUT IN

where ␥ equals the gamma power factor.

Gamma correction is performed on the luma data only. The user has the choice to use two different curves, Curve A or Curve B. At any one time only one of these curves can be used. The response of the curve is programmed at 10 predefined locations. In changing the values at these locations, the gamma curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the 10 locations are at: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed.

For the length of 16 to 240, the gamma correction curve must be calculated as:

yx=

where y = gamma corrected output, x = linear input signal, and ␥ = the gamma power factor.

To program the Gamma Correction Registers, the values for y must be calculated using the formula:





240 16



()

where x

= the value for x along the x-axis at points n = 24,

(n–16)

32, 48, 64, 80, 96, 128, 160, 192, or 224; y



−

240 16 16

×−

()





= the value for y

along the y-axis, which has to be written into the Gamma Correction Register.

Example:

 



 



 



 



 



 



224



112



224





144



224





176



224



 



208 224



224 16 58

 



224 16 76

 



224 16 101

 



224 16 120

 



224 16 136

 



224 16 150

 



224 16 174

 



224 16

 



224 16 214

 



224 16 232

 



  



  



  



  



  



  



  



  



  



  

195





 





 





 





 





 





 





128

 





160

 





192

 





224

 

The gamma curves shown in Figures 61 and 62 are examples. Any user defined curve is acceptable in the range of 16–240.

300

250

200

SIGNAL OUTPUT

150

100

0.5

*Rounded to the nearest integer

GAMMA CORRECTED AMPLITUDE

SIGNAL INPUT

50 100 150 200 250

LOCATION

Figure 61. Signal Input (Ramp) and Signal Output for Gamma 0.5

REV. A–44–

ADV7302A/ADV7303A

300

250

SIGNAL INPUT

200

150

100

GAMMA CORRECTED AMPLITUDE

50 100 150 200 250

0.3

0.5

1.5

1.8

LOCATION

Figure 62. Signal Input (Ramp) and Selectable Gamma Output

HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddresses 20h and 38h-3Dh]

There are three filter modes available on the ADV7302A/ ADV7303A: Sharpness Filter Mode and two adaptive filter modes.

HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges shown in Figure 63, the following register settings must be used: HD Sharpness Filter must be enabled and HD Adaptive Filter Enable must be set to disabled.

To select one of the 256 individual responses, the corresponding gain values for each filter, which range from –8 to +7, must be programmed into the HD Sharpness Filter Gain Register at Address 20h.

HD Adaptive Filter Mode

The HD Adaptive Filter Threshold A, B, C Registers, the HD Adaptive Filter Gain 1, 2, and 3 Registers, and the HD Sharpness Filter Gain Register are used in Adaptive Filter Mode. To activate the adaptive filter control, HD Sharpness Filter and HD Adaptive Filter Enable must be enabled.

The derivative of the incoming signal is compared to the three programmable threshold values: HD Adaptive Filter Threshold A, B, C. The recommended threshold range is from 16–235, although any value in the range of 0–255 can be used.

The edges can then be attenuated with the settings in HD Adaptive Filter Gain 1, 2, 3 Registers and HD Sharpness Filter Gain Register.

According to the settings of the HD Adaptive Filter Mode control, there are two adaptive filter modes available:

1. Mode A is used when Adaptive Filter Mode is set to “0.” In this case, Filter B (LPF) will be used in the adaptive filter block. Also, only the programmed values for Gain B in the HD Sharpness Filter Gain, HD Adaptive Filter Gain 1, 2, 3 are applied when needed. The Gain A values are fixed and cannot be changed.

2. Mode B is used when Adaptive Filter Mode is set to “1.” In this mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the HD Sharpness Filter Gain, HD Adaptive Filter Gain 1, 2, 3 become active when needed.

INPUT SIGNAL:

STEP

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5 FREQUENCY – MHz

FILTER A RESPONSE – Gain Ka

Figure 63. Sharpness and Adaptive Filter Control Block

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5 FREQUENCY – MHz

FILTER B RESPONSE – Gain Kb

1.6

1.5

1.4

1.3

1.2

MAGNITUDE – Linear Scale

1.1

1.0 024681012

FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb = 7

FREQUENCY – MHz

REV. A

–45–

ADV7302A/ADV7303A

Figure 64. HD Sharpness Filter Control with Different Gain Settings for HD Sharpness Filter Gain Value

HD Sharpness Filter and Adaptive Filter Application Examples

HD Sharpness Filter Application

The HD sharpness filter can be used to enhance or attenuate the Y video output signal.

The register settings in Tables XIX and XX are used to achieve the results shown in Figure 64. Input data was generated by an external signal source.

Table XIX. Sharpness Filter on Frequency Sweep

Address Register Setting Reference*

00h FCh 01h 10h 02h 20h 10h 00h 11h 81h 20h 00h a 20h 08h b 20h 04h c 20h 40h d 20h 80h e 20h 22h f

*See Figure 64.

The effect of the sharpness filter can also be seen when using the internally generated cross hatch pattern.

Adaptive Filter Control Application

Figure 65 shows a typical signal to be processed by the adaptive filter control block.

: 692mV @: 446mV

: 332ns @: 12.8ms

Figure 65. Input Signal to Adaptive Filter Control

: 690mV @: 446mV

: 332ns @: 12.8ms

Table XX. Sharpness Filter on Internal Test Pattern

Address Register Setting

00h FCh 01h 10h 02h 20h 10h 00h 11h 85h 20h 99h

In toggling the Sharpness Filter Enable Bit [Address 11h, Bit 8], it can be seen that the line contours of the crosshatch pattern change their sharpness.

Figure 66. Output Signal After Adaptive Filter Control

The register settings in Table XXI are used to obtain the results shown in Figure 66, i.e., to remove the ringing on the Y signal. Input data was generated by an external signal source.

REV. A–46–

ADV7302A/ADV7303A

Table XXI. Adaptive Filter Control on Step Input Signal

Address Register Setting

00h FCh 01h 38h 02h 20h 10h 00h 11h 81h 15h 80h 20h 00h 38h ACh 39h 9Ah 3Ah 88h 3Bh 28h 3Ch 3Fh 3Dh 64h

All other register settings are 00h.

When changing the Adaptive Filter Mode to Mode B [Address 15h, Bit 6], the output in Figure 67 can be obtained.

: 674mV @: 446mV

: 332ns

@: 12.8ms

SD DIGITAL NOISE REDUCTION [Subaddresses 63h, 64h, and 65h]

DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). There are two DNR modes available: DNR Mode and DNR Sharpness Mode.

In DNR Mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal will be subtracted from the original signal.

In DNR Sharpness Mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) will be added to the original signal in order to boost high frequency components and to sharpen the video image.

In MPEG systems it is common to process the video information in blocks of 8 ⫻ 8 pixels for MPEG2 systems, or 16 ⫻ 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area.)

It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset.

Figure 67. Output Signal from Adaptive Filter Control

The adaptive filter control can also be demonstrated using the internally generated crosshatch test pattern and toggling the Adaptive Filter Control Bit [Address 15h, Bit 7], shown in Table XXII.

Table XXII. Adaptive Filter Control on Internal Test Pattern

Address Register Setting

00h FCh 01h 38h 02h 20h 10h 00h 11h 85h 15h 80h 20h 00h 38h ACh 39h 9Ah 3Ah 88h 3Bh 28h 3Ch 3Fh 3Dh 64h

Y DATA

INPUT

Y DATA

INPUT

DNR MODE

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR SHARPNESS MODE

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

< THRESHOLD ?

FILTER OUTPUT

> THRESHOLD

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

> THRESHOLD ?

FILTER OUTPUT

< THRESHOLD

SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL

DNR OUT

ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL

DNR OUT

REV. A

Figure 68. DNR Block Diagram

–47–

ADV7302A/ADV7303A

The Digital Noise Reduction Registers are three 8-bit wide registers. They are used to control the DNR processing.

Coring Gain Border [Address 63h, Bits 3–0]

These four bits are assigned to the gain factor applied to border areas. In DNR Mode, the range of gain values is 0–1, in increments of 0.125. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal.

In DNR Sharpness Mode, the range of gain values is 0 to 0.5, in increments of 0.0625. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal.

Coring Gain Data [Address 63h, Bits 7–4]

These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block.

In DNR Mode, the range of gain values is 0–1, in increments of

0.125. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal.

In DNR Sharpness Mode, the range of gain values is 0–0.5, in increments of 0.0625. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal.

APPLY BORDER CORING GAIN

OFFSET CAUSED BY VARIATIONS IN INPUT TIMING

DNR27 – DNR24 = 01HEX

APPLY DATA CORING GAIN

O X X X X X X O O X X X X X X O

Figure 69. DNR Block Offset Control

DNR Threshold [Address 64h, Bits 5–0]

These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value.

Border Area [Address 64h, Bit 6]

In setting this bit to a Logic “1,” the block transition area can be defined to consist of four pixels. If this bit is set to a Logic “0,” the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.

720ⴛ485 PIXELS

(NTSC)

2 PIXEL

BORDER

DATA

Block Size Control [Address 64h, Bit 7]

This bit is used to select the size of the data blocks to be processed. Setting the block size control function to a Logic “1” defines a 16 ⫻ 16 pixel data block, a Logic “0” defines an 8 ⫻ 8 pixel data block, where 1 pixel refers to 2 clock cycles at 27 MHz.

DNR Input Select Control [Address 65h, Bits 2–0]

Three bits are assigned to select the filter that is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that will be DNR processed. The figure below shows the filter responses selectable with this control.

1.0 FILTER D

0.8

FILTER C

0.6

0.4

0.2

012 3456

FILTER B

FILTER A

FREQUENCY – Hz

Figure 71. DNR Input Select

DNR Mode Control [Address 65h, Bit 3]

This bit controls the DNR mode selected. A Logic “0” selects DNR mode, a Logic “1” selects DNR Sharpness Mode. DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal.

In DNR Mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1.

When DNR Sharpness Mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. The overall effect is that the signal will be boosted (similar to using extended SSAF filter).

Block Offset Control [Address 65h, Bits 7–4]

Four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.

8ⴛ8 PIXEL BLOCK 8ⴛ8 PIXEL BLOCK

Figure 70. DNR Border Area

REV. A–48–

SD ACTIVE VIDEO EDGE

600R

300R47pF300R

DAC O/P

75R

BNC O/P

6.8␮H 6.8␮H

600R

CIRCUIT FREQUENCY RESPONSE – MHz

–60

110100

–240

–120

12n

18n

120

24n

240

30n

360

36n

480

–50

–40

–30

–20

–10

GROUP DELAY (sec)

PHASE (Deg)

MAGNITUDE (dB)

THIRD ORDER LOW-PASS BUTTERWORTH

[Subaddress 42h, Bit 7]

When the active video edge is enabled, the first three pixels and the last three pixels of the active video on the Luma Channel are scaled in such a way that maximum transitions on these pixels are not possible. The scaling factors are 1/8⫻, 1/2⫻, and 7/8⫻. All other active video passes through unprocessed.

ADV7302A/ADV7303A

LUMA CHANNEL WITH ACT IVE VIDEO EDGE DISABLED

100 IRE

0 IRE

Figure 72. Active Video Edge Functionality Example

BOARD DESIGN AND LAYOUT CONSIDERATIONS DAC Termination and Layout Considerations

The ADV7302A/ADV7303A contain an on-board voltage reference. The V

0.1 µF capacitor when the internal V the ADV7302A/ADV7303A can be used with an external V AD1580). The R

Pin is normally terminated to VAA through a

REF

resistors are connected between the R

SET

is used. Alternatively,

REF

(e.g.,

SET

Pins and AGND and are used to control the full-scale output current and, therefore, the DAC voltage output levels. For full-scale output, R values should not be changed. R

must have a value of 760 Ω. The R

SET

has a value of 150 Ω for

LOAD

SET

full-scale output.

Video Output Buffer and Optional Output Filter

Output buffering on all six DACs is necessary in order to drive output devices, such as SD or HD monitors. Analog Devices produces a range of suitable op amps for this application, for example the AD8061. More information on line driver buffering circuits is given in the relevant op amp data sheets.

An optional analog reconstruction LPF might be required as an antialias filter if the ADV7302A/ADV7303A is connected to a device that requires this filtering. The filter specifications vary with the application, see Table XXIII.

LUMA CHANNEL WITH ACT IVE VIDEO EDGE ENABLED

100 IRE

87.5 IRE

50 IRE

12.5 IRE 0 IRE

Figure 73. Example for Output Filter for SD,

⫻

Oversampling

Table XXIII. External Filter Requirements

Input External Filter Cutoff Mode Oversampling Frequency Attenuation

SD 2⫻ >6.5 MHz –50 dB @ 20.5 MHz SD 8⫻ >6.5 MHz –50 dB @ 101.5 MHz PS 1⫻ >12.5 MHz –50 dB @ 14.5 MHz PS 4⫻ >12.5 MHz –50 dB @ 95.5 MHz HDTV 1⫻ >30 MHz –50 dB @ 44.25 MHz HDTV 2⫻ >30 MHz –50 dB @ 118.5 MHz

REV. A

–49–

Figure 74. Filter Plot for Output Filter for SD,

⫻

Oversampling

ADV7302A/ADV7303A

6.8H 2.2H

DAC O/P

300R

6.8pF

18pF

300R

600R

75R

600R

Figure 75. Example of Output for Output Filter for PS, 4

⫻

Oversampling

–10

GROUP DELAY (sec)

–20

–30

–40

–50

FOURTH ORDER LOW-PASS BUTTERWORTH

–60

PHASE (Deg)

10M

CIRCUIT FREQUENCY RESPONSE – Hz

MAGNITUDE (dB)

100M

Figure 76. Filter Plot for Output Filter for PS, 4 Oversampling

470nH 220nH

82pF

75R

500R

33pF

75R

DAC O/P

300R

Figure 77. Example for Output Filter HDTV, 2 Oversampling

–8.6

–17.1

–25.7

–34.3

–42.9

–51.4

FOURTH ORDER LOW-PASS BUTTERWORTH

–60.0

110100

GROUP DELAY (sec)

PHASE (Deg)

CIRCUIT FREQUENCY RESPONSE – MHz

MAGNITUDE (dB)

Figure 78. Filter Plot for Output Filter for HDTV,

⫻

Oversampling

BNC O/P

30n

25n

20n

15n

10n

–120

–240

⫻

BNC O/P

⫻

14n

12n

10n

480

360

240

120

198

97.6

–102

–203

498

398

298

Table XXIII. Possible Output Rates

Input Mode PLL Addr 01h, Bits 6–4 Addr 00h, Bit 1 Output Rate

SD Off 27 MHz (2⫻)

On 108 MHz (8⫻)

PS Off 27 MHz (1⫻)

On 108 MHz (4⫻)

HDTV Off 74.25 MHz (1⫻)

On 148.5 MHz (2⫻)

SD and Off 27 MHz (2⫻)

On 108 MHz (8⫻)

PS Off 27 MHz (1⫻)

On 108 MHz (4⫻)

SD* and Off 27 MHz (2⫻)

On 108 MHz (8⫻)

HDTV Off 74.25 MHz (1⫻)

On 74.25 MHz (1⫻)

SD and Off 27 MHz (2⫻)

On 27 MHz (2⫻)

HDTV* Off 74.25 MHz (1⫻)

On 148.5 MHz (2⫻)

*Oversampled

PCB Board Layout Considerations

The ADV7302A/ADV7303A is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7302A/ADV7303A, it is imperative that great care be given to the PC board layout and the ADV7302A/ADV7303A power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of V AGND, V

and DGND, and V

and GND_IO Pins should

DD_IO

and

be kept as short as possible to minimize inductive ringing.

It is recommended that a four-layer printed circuit board be used with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. Placement of components should take into account noisy circuits such as crystal clocks, high speed logic circuitry, and analog circuitry.

There should be a separate analog ground plane and a separate digital ground plane.

Power planes should encompass a digital and an analog power plane. The analog power plane should contain the DACs and all associated circuitry, V

circuitry. The digital power plane

REF

should contain all logic circuitry. The analog and digital power planes should be individually connected to the common power plane at one single point through a suitable filtering device, such as a ferrite bead.

DAC output traces on a PCB should be treated as transmission lines. It is recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than three inches). The DAC termination resistors should be placed as close as possible to the DAC outputs and should overlay the PCB’s ground plane. As well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry.

REV. A–50–

ADV7302A/ADV7303A

To avoid crosstalk between the DAC outputs, it is recommended to leave as much space as possible between the tracks of the individual DAC output pins.

Supply Decoupling

Noise on the analog power plane can be further reduced by the use of decoupling capacitors. Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the group of

, V

DD,

or V

Pins should be individually decoupled to

DD_IO

ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance.

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to

POWER SUPPLY DECOUPLING FOR

EACH POWER SUPPLY GROUP

AAVAA

0.1F 0.1F

COMP1

S0–S7

S_HSYNC

S_VSYNC

BLANK

C0–C7

Y0–Y7

COMP2

ADV7302A/

10, 56

VDDV

DD_IO

REF

DAC A

DAC B

DAC C

DAC D

ADV7303A

P_HSYNC

P_VSYNC

47k

4.7F

6.3V

820pF

3.9nF680R 15, 51, 52, 64

UNUSED INPUTS SHOULD BE GROUNDED

P_BLANK

RESET

CLKIN_B

CLKIN_A

EXT_LF

GND_IO AGND DGND

2, 3, 14,

DAC E

DAC F

SCLK

ALSB

11, 57

SDA

SET1

SET2

Figure 79. Circuit Layout

the high clock rates used, long clock lines to the ADV7302A/ ADV7303A should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane.

Analog Signal Interconnect

The ADV7302A/ADV7303A should be located as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. For optimum performance, the analog outputs should each be source and load terminated, as shown in Figure 79. The termination resistors should be as close as possible to the ADV7302A/ADV7303A to minimize reflections.

Any unused inputs should be tied to ground.

10nF

0.1F

10nF

10nF 0.1F

150

760

0.1F

DD_IO

SD CVBS/GREEN/Y

SD LUMA/BLUE/U

SD CHROMA/RED/V

HD Y/GREEN

HD Pb/BLUE

HD Pr/RED

DD_IO

5k

DD_IO

5k

DD_IO

5k

I2C BUS

REV. A

–51–

ADV7302A/ADV7303A

Appendix A

COPY GENERATION MANAGEMENT SYSTEM HD CGMS DATA Registers 2–0 [Subaddress 12h]

HD CGMS is available in 525 p Mode only, conforming to “CGMS-A EIA-J CPR1204-1, Transfer Method of Video ID information using vertical blanking interval (525 p System),

+700mV

70% 10%

0mV

–300mV

5.8s 0.15s

 33) = 963ns

T = 1/(f

= HORIZONTAL SCAN FREQUENCY

T 30ns

REF

BIT 1

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

Figure 80. CGMS Waveform

SD CGMS Data Registers 2–0 [Subaddresses 59h, 5Ah, and 5Bh]

The ADV7302A/ADV7303A supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is output on odd and even fields. CGMS data can only be transmitted when the ADV7302A/ADV7303A is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit, see Figure 81.

If SD CGMS CRC [Address 59h, Bit 4] is set to a Logic “1,” the last six bits, C19–C14, that comprise the 6-bit CRC check sequence are calculated automatically on the ADV7302A/ ADV7303A based on the lower 14 bits (C0–C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial:

March 1998” and IEC61880, 1998, video systems (525/60)— video and accompanied data using the vertical blanking interval—analog interface.

When HD CGMS is enabled, CGMS data is inserted on Line 41. The HD CGMS Data Registers are to be found at Addresses 21h, 22h, and 23h.

CRC SEQUENCE

BIT 20

21.2s 0.22s 22T

output directly from the CGMS registers (no CRC calculated; must be calculated by the user).

Table XXIV. Function of CGMS Bits

Word Bit Function

0B1Aspect Ratio 0 = 4:3

1 = 16:9

B2 Display Format 0 = Normal

1 = Letterbox B3 Undefined B4–B6 Identification Information about Video

and Other Signals (i.e., Audio)

1 B7–B10 Identification Signal. Incidental to Word 0.

2 B11–B14 Identification Signal and Information.

Incidental to Word 0.

xx61++

with a preset value of 111111. If SD CGMS CRC [Address 59h, Bit 4] is set to a Logic “0,” then all 20 bits (C0–C19) are

+100 IRE

+70 IRE

0 IRE

–40 IRE

11.2s

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

2.235s 20ns

Figure 81. CGMS Waveform

CRC SEQUENCE

49.1s 0.5s

REV. A–52–

Appendix B

ADV7302A/ADV7303A

SD WIDE SCREEN SIGNALING [Subaddresses 59h, 5Ah, and 5Bh]

The ADV7302A/ADV7303A supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7302A/ ADV7303A is configured in PAL Mode. The WSS data is 14 bits long. The function of each of these bits is as shown in Table XXV. The WSS data is preceded by a run-in sequence and a start code (see Figure 82). If SD WSS [Address 59h, Bit 7] is set to a Logic “1,” it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 µs from the falling edge of HSYNC) is available for the insertion of video.

It is possible to blank the WSS portion of Line 23 with Subaddress 61h, Bit 7.

Table XXV. Function of WSS Bits

Bit Function

0Aspect Ratio

1 Format

2 Position

3Odd Parity Check of Bits 0–2

40 = Camera Mode

1 = Film Mode

50 = Standard Coding

1 = Motion Adaptive Color Plus

60 = No Helper

1 = Modulated Helper

7Reserved

8Reserved

9–10 00 = No Open Subtitles

10 = Subtitles Inside Active Image Area 01 = Subtitles Outside Active Image Area 11 = Reserved

11 0 = No Surround Sound Information

1 = Surround Sound Mode

12–13 Reserved

Table XXVI. Function of WSS Bits 0–3

B0 B1 B2 B3 Aspect Ratio Format Position

0001 4:3 Full Format N/A 1000 14:9 Letterbox Center 0100 14:9 Letterbox Top 1101 16:9 Letterbox Center 0010 16:9 Letterbox Top 1011 >16:9 Letterbox Center 0111 14:9 Full Format Center 1110 16:9 N/A N/A

REV. A

500mV

11.0␮s

RUN- IN

SEQUENCE

START

CODE

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10

38.4␮s

42.5␮s

Figure 82. WSS Waveform

–53–

W11

W12

W13

ACTIVE

VIDEO

ADV7302A/ADV7303A

Appendix C

SD CLOSED CAPTIONING [Subaddresses 51h–54h]

The ADV7302A/ADV7303A supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase-locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in the SD Closed Captioning Registers [Addresses 53h–54h].

The ADV7302A/ADV7303A also supports the extended closed captioning operation that is active during even fields and is encoded on Line 284. The data for this operation is stored in the SD Closed Captioning Registers [Addresses 51h–52h].

All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7302A/

10.5  0.25s 12.91s

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

50 IRE

40 IRE

REFERENCE COLOR BURST

FREQUENCY = F

(9 CYCLES)

= 3.579545MHz

AMPLITUDE = 40 IRE

10.003s

27.382s 33.764s

ADV7303A. All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled.

FCC Code of Federal Regulations (CFR) 47, Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284.

The ADV7302A/ADV7303A uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data must be loaded one line before (Line 20 or Line 283) it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, that in turn will load the new data (two bytes) every field. If no new data is required for transmission, “0” must be inserted in both data registers; this is called nulling. It is also important to load “control codes,” all of which are double bytes on Line 21, or a TV will not recognize them. If there is a message like “Hello World” that has an odd number of characters, it is important to pad it out to even to get the “end of caption” 2-byte control code to land in the same field.

TWO 7-BIT + PARITY ASCII CHARACTERS

(DATA)

S T

D0–D6 D0–D6

A R T

P A R

I T

P A R

I T Y

BYTE 1BYTE 0

Figure 83. Closed Captioning Waveform, NTSC

REV. A–54–

Appendix D

TEST PATTERNS

The ADV7302A/ADV7303A can generate SD and HD test patterns.

ADV7302A/ADV7303A

Figure 84. NTSC Color Bars

Figure 85. NTSC Black Bar (–21 mV, 0 mV, +3.5 mV, +7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV)

Figure 87. PAL Color Bars

Figure 88. PAL Black Bar

+7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV)

(–21 mV, 0 mV, +3.5 mV,

REV. A

Figure 86. 525 p Hatch Pattern

Figure 89. 625 p Hatch Pattern

–55–

ADV7302A/ADV7303A

Figure 90. 525 p Field Pattern

Figure 91. 525 p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV)

Figure 92. 625 p Field Pattern

Figure 93. 625 p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV)

REV. A–56–

ADV7302A/ADV7303A

Table XXVII. NTSC CVBS Output on DAC A

Subaddress Register Setting

00h 82h 11h 01h 40h 10h 42h 40h 44h 40h 4Ah 08h 4Ch 16h 4Dh 7Ch 4Eh F0h 4Fh 21h

All other registers are set to 00h.

For PAL CVBS output on DAC A, the same settings in Table XXVII are used except those listed in Table XXVIII.

Table XXVIII. PAL CVBS Output on DAC A

Subaddress Register Setting

40h 11h 4Ch CBh 4Dh 8Ah 4Eh 09h 4Fh 2Ah

Table XXIX. NTSC Black Bar Pattern Output on DAC A

Subaddress Register Setting

00h 82h 02h 04h 11h 01h 40h 10h 42h 40h 44h 40h 4Ah 08h 4Ch 16h 4Dh 7Ch 4Eh F0h 4Fh 21h

All other registers are set to 00h. The subcarrier frequency registers 4Ch–4Fh will be needed to generate the correct color burst signal.

For PAL black bar pattern output on DAC A, the same settings in Table XXIX are used except those listed in Table XXX.

Table XXXI. 525 p Hatch Pattern on DAC D

Subaddress Register Setting

00h 12h 01h 10h 02h 20h 10h 40h 11h 05h 16h A0h 17h 80h 18h 80h

All other registers are set to 00h.

For a 625 p Hatch Pattern on DAC D, the same settings in Table XXXI are used except for Subaddress 10h, which has a register setting of 50h.

Table XXXII. 525 p Field Pattern*

Subaddress Register Setting

00h 12h 01h 10h 02h 20h 10h 40h 11h 0Dh 16h A0h 17h 80h 18h 80h

NOTES All other registers are set to 00h. *See Figure 90.

For a 625 p Field Pattern on DAC D, the same settings in Table XXXII are used except for Subaddress 10 h, which has a register setting of 50h.

For a 525 p Black Bar Pattern Output on DAC D, the same settings in Table XXXII are used except for Subaddresses 02h, which has a register setting of 24h.

For a 625 p Black Bar Pattern Output on DAC D, the same settings in Table XXXII are used except for Subaddresses 02h, and 10h, which have register settings of 24h and 50h, respectively.

Table XXX. PAL Black Bar Pattern Output on DAC A

Subaddress Register Setting

40h 11h 4Ch CBh 4Dh 8Ah 4Eh 09h 4Fh 2Ah

REV. A

–57–

ADV7302A/ADV7303A

Appendix E

SD TIMING MODES [Subaddress 4Ah] Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7302A/ADV7303A is controlled by the start active video (SAV) and end active video (EAV) time codes in the pixel data. All

ANALOG

VIDEO

EAV CODE

INPUT PIXELS

NTSC /PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

FF0000X

4 CLOCK

END OF ACTIVE

VIDEO LINE

10801

Figure 94. SD Slave Mode 0

Mode 0 (CCIR-656): Master Option (Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7302A/ADV7303A generates H, V, and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H Bit is output on the S_HSYNC pin, the V Bit is output on the S_BLANK pin, and the F Bit is output on the S_VSYNC pin.

timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. S_VSYNC, S_HSYNC, and S_BLANK (if not used) pins should be tied high during this mode. Blank output is available.

SAV CODE

FF00FFABABA

ANCILLARY DATA

268 CLOCK

280 CLOCK

(HANC)

801

10FF0

XYC

4 CLOCK

START OF ACTIVE

VIDEO LINE

1440 CLOCK

DISPLAY

522 523 524 525 1 2 3 4

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

EVEN FIELD

ODD FIELD

EVEN FIELD

VERTICAL BLANK

Figure 95. SD Master Mode 0, NTSC

DISPLAY

10 11 20 21 22

283

284

285

DISPLAY

REV. A–58–

ADV7302A/ADV7303A

DISPLAY

622 623 624 625 1 2 3 4

DISPLAY

309 310 311 312 314 315 316 317

EVEN FIELD

ODD FIELD

313

EVEN FIELD

Figure 96. SD Master Mode 0, PAL

VERTICAL BLANK

318

319 320

DISPLAY

22 23

DISPLAY

335 336

334

ANALOG

VIDEO

Figure 97. SD Master Mode 0 Data Transitions

REV. A

–59–

ADV7302A/ADV7303A

Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode the ADV7302A/ADV7303A accepts horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical

DISPLAY

522 523 524 525

SYNC

LANK

FIELD

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

HSYNC

1234

EVEN FIELD

ODD FIELD

VERTICAL BLANK

retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7302A/ADV7303A automatically blanks all normally blank lines as per CCIR-624. HSYNC is input on the S_HSYNC Pin, BLANK on the S_BLANK Pin, and FIELD on the S_VSYNC Pin.

284

DISPLAY

285

VERTICAL BLANK

678

10 11

20 21 22

283

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 98. SD Slave Mode 1, NTSC

DISPLAY

622 623 624 625 1234

HSYNC

BLANK

FIELD

DISPLAY

309 310 311 312 313 314 315 316

SYNC

EVEN FIELD

ODD FIELD

VERTICAL BLANK

317

318 319

21 22 23

320

DISPLAY

334 335 336

LANK

FIELD

ODD FIELD

EVEN FIELD

Figure 99. SD Slave Mode 1, PAL

REV. A–60–

ADV7302A/ADV7303A

Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7302A/ADV7303A can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e.,

HSYNC

FIELD

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

BLANK

PIXEL

DATA

Figure 100. SD Timing Mode 1 Odd/Even Field Transitions, Master/Slave

vertical retrace. The blank signal is optional. When the BLANK input is disabled, the ADV7302A/ADV7303A automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC is output on the S_HSYNC Pin, BLANK on the S_BLANK Pin, and FIELD on the S_VSYNC Pin.

Cb Y

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Cr Y

REV. A

–61–

ADV7302A/ADV7303A

Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode the ADV7302A/ADV7303A accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field.

HSYNC

BLANK

VSYNC

HSYNC

BLANK

DISPLAY

522 523 524 525

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

EVEN FIELD

VERTICAL BLANK

A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7302A/ADV7303A automatically blanks all normally blank lines as per CCIR-624.

HSYNC is input on the S_HSYNC Pin, BLANK on the S_BLANK Pin, and FIELD on the S_VSYNC Pin.

DISPLAY

678

ODD FIELD

10 11

20 21 22

DISPLAY

283

284

285

VSYNC

HSYNC

BLANK

VSYNC

HSYNC

BLANK

VSYNC

ODD FIELD

Figure 101. SD Slave Mode 2, NTSC

DISPLAY

622 623 624 625 1234

EVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD

VERTICAL BLANK

ODD FIELD

VERTICAL BLANK

EVEN FIELD

318 319

317

320

DISPLAY

21 22 23

DISPLAY

334 335 336

Figure 102. SD Slave Mode 2, PAL

REV. A–62–

ADV7302A/ADV7303A

Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode the ADV7302A/ADV7303A can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd

SYNC

VSYNC

PAL = 12  CLOCK/2

LANK

PIXEL

DATA

NTSC = 16  CLOCK/2

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Figure 103. SD Timing Mode 2 Even to Odd Field Transition, Master/Slave

HSYNC

VSYNC

PAL = 12  CLOCK/2

LANK

NTSC = 16  CLOCK/2

field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7302A/ADV7303A automatically blanks all normally blank lines as per CCIR-624.

HSYNC is output on the S_HSYNC Pin, BLANK on the S_BLANK Pin, and FIELD on the S_VSYNC Pin.

PAL = 864  CLOCK/2

NTSC = 858  CLOCK/2

Cb Y Cr

PIXEL

DATA

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Cb Y Cr Y Cb

Figure 104. SD Timing Mode 2 Odd to Even Field Transition, Master/Slave

REV. A

–63–

ADV7302A/ADV7303A

Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode the ADV7302A/ADV7303A accepts or generates horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame,

HSYNC

BLANK

FIELD

HSYNC

DISPLAY

522 523 524 525

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

VERTICAL BLANK

i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7302A/ADV7303A automati-

cally blanks all normally blank lines as per CCIR-624. HSYNC is interfaced on the S_HSYNC Pin, BLANK on the S_BLANK Pin, and FIELD on the S_VSYNC Pin.

DISPLAY

678

10 11

20 21 22

283

284

285

BLANK

FIELD

HSYNC

BLANK

FIELD

HSYNC

BLANK

ODD FIELD EVEN FIELD

Figure 105. SD Timing Mode 3, NTSC

DISPLAY

622 623 624 625 1234

ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

VERTICAL BLANK

317

318 319

320

DISPLAY

21 22 23

DISPLAY

334 335 336

FIELD

ODD FIELDEVEN FIELD

Figure 106. SD Timing Mode 3, PAL

REV. A–64–

Appendix F

INPUT CODE

940

EIA-770.3, STANDARD FOR Y

+700mV

OUTPUT VOLTAGE

0mV

–300mV

VIDEO ACTIVE

+300mV

960

EIA-770.3, STANDARD FOR Pr/Pb

+350mV

OUTPUT VOLTAGE

0mV

–350mV

VIDEO ACTIVE

512

–300mV

+300mV

VIDEO OUTPUT LEVELS

ADV7302A/ADV7303A

INPUT CODE

EIA-770.2, STANDARD FOR Y

940

EIA-770.2, STANDARD FOR Pr/Pb

960

512

OUTPUT VOLTAGE

+700mV

VIDEO ACTIVE

0mV

–300mV

OUTPUT VOLTAGE

+350mV

VIDEO ACTIVE

0mV

–300mV

–350mV

Figure 107. EIA 770.2 Standard Output Signals (525 p)

INPUT CODE

EIA-770.1, STANDARD FOR Y

940

OUTPUT VOLTAGE

+782mV

+714mV

Figure 109. EIA 770.3 Standard Output Signals (1080 i, 720 p)

INPUT CODE

1023

Y–OUTPUT LEVELS FOR

FULL I/P SELECTION

OUTPUT VOLTAGE

+700mV

VIDEO ACTIVE

EIA-770.1, STANDARD FOR Pr/Pb

960

512

Figure 108. EIA 770.1 Standard Output Signals (525 p)

0mV

–286mV

OUTPUT VOLTAGE

+350mV

VIDEO ACTIVE

0mV

–300mV

–350mV

INPUT CODE

1023

Pr/Pb–OUTPUT LEVELS FOR

FULL I/P SELECTION

0mV

–300mV

OUTPUT VOLTAGE

+700mV

VIDEO ACTIVE

0mV

–300mV

Figure 110. Output Levels for Full Input Selection

REV. A

–65–

ADV7302A/ADV7303A

Appendix G

VIDEO STANDARDS

SMPTE274M

ANALOG WAVEFORM

DATUM

DIGITAL HORIZONTAL BLANKING

INPUT PIXELS

SAMPLE NUMBER

SMPTE293M

ANALOG WAVEFORM

INPUT PIXELS

4T 4T 1920T

EAV CODE

000

4 CLOCK 4 CLOCK

2112 2116 2156 2199

FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE1–20; 561–583; 1124–1125: V = 1 SAV/EAV: LINE 21–560; 584–1123: V = 0

(OPTIONAL) OR BLANKING CODE

Figure 111. EAV/SAV Input Data Timing Diagram, SMPTE274M

EAV CODE

000

4 CLOCK 4 CLOCK

272T

ANCILLARY DATA

44 188 192 2111

ANCILLARY DATA

(OPTIONAL)

SAV CODE

F F

SAV CODE

000

F F

000

DIGITAL

ACTIVE LINE

CbC

DIGITAL

ACTIVE LINE

CbC

SAMPLE NUMBER

719 723 736 799 853 0

FVH* = FVH AND PARITY BITS SAV: LINE 43–525 = 200H SAV: LINE 1–42 = 2AC EAV: LINE43–525 = 274H EAV: LINE 1–42 = 2D8

0HDATUM

DIGITAL HORIZONTAL BLANKING

Figure 112. EAV/SAV Input Data Timing Diagram, SMPTE293M

857 719

REV. A–66–

ADV7302A/ADV7303A

ACTIVE

VIDEO

522 523 524 525 1 2 5 6 7 8 9 12 13 14 15 16 43 4442

VERTICAL BLANK

Figure 113. SMPTE293M

ACTIVE

VIDEO

622 623 624 625 1 2 5 6 7 8 9 12 1310 11 43 44 454

VERTICAL BLANK

Figure 114. ITU-R.BT1358 (625 p)

VERTICAL BLANKING INTERVAL

747 748 749 750 1 2 5 6 7 8 26 2725744 7454

Figure 115. SMPTE296M (720 p)

ACTIVE

VIDEO

DISPLAY

ACTIVE

VIDEO

FIELD 1

FIELD 2

VERTICAL BLANKING INTERVAL

1124 1125 1 2 5 6 7 8

VERTICAL BLANKING INTERVAL

561 562 563 564 567 568 569 570

566565

Figure 116. SMPTE274M (1080 i)

20 22 560

DISPLAY

583 585 1123

584

REV. A

–67–

ADV7302A/ADV7303A

OUTLINE DIMENSIONS

64-Lead Thin Plastic Quad Flatpack [LQFP]

(ST-64B)

Dimensions shown in millimeters

1.45

1.40

1.35

0.15

0.05

SEATING

PLANE

ROTATED 90ⴗ CCW

VIEW A

0.08 MAX COPLANARITY

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7ⴗ

3.5ⴗ 0ⴗ

COMPLIANT TO JEDEC STANDARDS MS-026BCD

1.60 MAX

VIEW A

0.50 BSC

12.00 BSC

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

4964

C02863–0–11/02(A)

10.00 BSC

Revision History

Location Page

11/02—Data Sheet changed from REV. 0 to REV. A.

Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Changes to TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Added Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Changes to Table IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Changes to Table XII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Changes to Table XIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Changes to the Realtime Control, Subcarrier Reset, Timing Reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Changes to SD SUBCARRIER FREQUENCY REGISTERS [Subaddress 4Ch–4Fh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Changes to Figure 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Changes to Figure 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Changes to Figure 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Changes to Figure 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

PRINTED IN U.S.A.

–68–

REV. A

Analog Devices ADV7302A 3A a Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TERMS USED IN THIS DATA SHEET

DYNAMIC SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS*

THERMAL CHARACTERISTICS

ORDERING GUIDE

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

MPU PORT DESCRIPTION

REGISTER ACCESSES

REGISTER PROGRAMMING

Subaddress Register (SR7–SR0)

Register Select (SR7–SR0)

PROGRESSIVE SCAN ONLY OR HDTV ONLY

SIMULTANEOUS STANDARD DEFINITION AND PROGRESSIVE SCAN OR HDTV

PROGRESSIVE SCAN AT 27 MHz OR 54 MHz

OUTPUT CONFIGURATION

HD Timing Reset

RESET SEQUENCE

VERTICAL BLANKING INTERVAL

FILTERS

HD Sync Filter

HD 4:2:2 to 4:4:4 Interpolation Filters and Chroma SSAF

HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddresses 20h and 38h-3Dh]

HD Sharpness Filter Mode

HD Adaptive Filter Mode

SD ACTIVE VIDEO EDGE

Video Output Buffer and Optional Output Filter

PCB Board Layout Considerations

Supply Decoupling

Digital Signal Interconnect

Analog Signal Interconnect

TEST PATTERNS

VIDEO OUTPUT LEVELS

VIDEO STANDARDS

OUTLINE DIMENSIONS

Revision History