Analog Devices ADV7192 Datasheet

Video Encoder with Six 10-Bit DACs, 54 MHz

a

Oversampling and Progressive Scan Inputs

FEATURES
Six High-Quality 10-Bit Video DACs
10-Bit Internal Digital Video Processing
Multistandard Video Input
Multistandard Video Output
4 Oversampling with Internal 54 MHz PLL
Programmable Video Control Includes:

Digital Noise Reduction
Gamma Correction
Black Burst
LUMA Delay
CHROMA Delay
Multiple Luma and Chroma Filters

Luma SSAF™ (Super Subalias Filter)
Average Brightness Detection
Field Counter
Macrovision Rev. 7.1
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support.
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface (I

and Fast I

2

C Interface

I

2

C)

2C®

-Compatible

Supply Voltage 5 V and 3.3 V Operation
80-Lead LQFP Package

ADV7192

APPLICATIONS
DVD Playback Systems
PC Video/Multimedia Playback Systems
Progressive Scan Playback Systems

GENERAL DESCRIPTION

The ADV7192 is part of the new generation of video encoders
from Analog Devices. The device builds on the performance of
previous video encoders and provides new features like interfac­ing progressive scan devices, Digital Noise Reduction, Gamma

×

Correction, 4
Brightness Detection, Black Burst Signal Generation, Chroma
Delay, an additional Chroma Filter, and other features.

The ADV7192 supports NTSC-M, NTSC-N (Japan), PAL N,
PAL M, PAL-B/D/G/H/I and PAL-60 standards. Input standards
supported include ITU-R.BT656 4:2:2 YCrCb in 8-Bit or 16-Bit
format and 3

The ADV7192 can output Composite Video (CVBS), S-Video
(Y/C), Component YUV
YPrPb format. The analog component output is also compatible
with Betacam, MII, and SMPTE/EBU N10 levels, SMPTE
170 M NTSC, and ITU–R.BT 470 PAL.

Please see Detailed Description of Features for more informa­tion about the ADV7192.

Oversampling and 54 MHz operation, Average

×

10-Bit YCrCb progressive scan format.

or RGB and analog progressive scan in

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

DIGITAL

INPUT

27MHz

CLOCK

ITU–R.BT

656/601

8-BIT YCrCb

IN 4:2:2 FORMAT

SSAF is a trademark of Analog Devices Inc.
This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
I2C is a registered trademark of Philips Corporation.
Throughout the document YUV refers to digital or analog component video.

VIDEO
INPUT
PROCESSING

PLL

AND

54MHz

DEMUX

AND

YCrCb-

TO-

YUV

MATRIX

VIDEO
SIGNAL
PROCESSING

COLOR CONTROL
DNR
GAMMA
CORRECTION

VBI
TELETEXT
CLOSED CAPTION
CGMS/WSS

CHROMA
LPF

SSAF
LPF

LUMA
LPF

I2C INTERFACE

VIDEO
OUTPUT
PROCESSING

2

OVERSAMPLING

OR

4

OVERSAMPLING

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

ADV7192

ANALOG
OUTPUT

COMPOSITE VIDEO
Y [S-VIDEO]
C [S-VIDEO]
RGB
YUV
YPrPb

TV SCREEN
OR
PROGRESSIVE
SCAN DISPLAY

ADV7192

CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1

SPECIFICATIONS

Static Performance 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Static Performance 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Dynamic Specifications 5 V . . . . . . . . . . . . . . . . . . . . . . . . 5

Dynamic Specifications 3.3 V . . . . . . . . . . . . . . . . . . . . . . . 5

Timing Characteristics 5 V . . . . . . . . . . . . . . . . . . . . . . . . 6

Timing Characteristics 3.3 V . . . . . . . . . . . . . . . . . . . . . . . 7

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10

DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 11

DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12

INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 13

FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17

BLACK BURST OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . 17

BRIGHTNESS DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CHROMA/LUMA DELAY . . . . . . . . . . . . . . . . . . . . . . . . 17

CLAMP OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CSO, HSO AND VSO OUTPUTS . . . . . . . . . . . . . . . . . . . 17

COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 17

COLOR BURST SIGNAL CONTROL . . . . . . . . . . . . . . . 17

COLOR CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CHROMINANCE CONTROL . . . . . . . . . . . . . . . . . . . . . 17

UNDERSHOOT LIMITER . . . . . . . . . . . . . . . . . . . . . . . . 18

DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . . . . . 18

DOUBLE BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

GAMMA CORRECTION CONTROL . . . . . . . . . . . . . . . 18

NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 18

POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PROGRESSIVE SCAN INPUT . . . . . . . . . . . . . . . . . . . . . 18

REAL-TIME CONTROL, SUBCARRIER RESET, AND

TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SCH PHASE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 19

VERTICAL BLANKING DATA INSERTION

AND BLANK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

YUV LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16-BIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4× OVERSAMPLING AND INTERNAL PLL . . . . . . . . . 20

VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 20

RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 28

REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 29

MODE REGISTERS 0–9 . . . . . . . . . . . . . . . . . . . . . . . 30–35

TIMING REGISTERS 0–17 . . . . . . . . . . . . . . . . . . . . . . . 36

SUBCARRIER FREQUENCY AND

PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 37

NTSC PEDESTAL/PAL TELETEXT CONTROL

REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

TELETEXT CONTROL REGISTER . . . . . . . . . . . . . . . . 38

CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 38

CONTRAST CONTROL REGISTERS . . . . . . . . . . . . . . . 39

HUE ADJUST CONTROL REGISTER (HCR) . . . . . . . . 40

HCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40

BRIGHTNESS CONTROL REGISTER (BCR) . . . . . . . . 40

BCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40

SHARPNESS RESPONSE REGISTER (PR) . . . . . . . . . . . 41

PR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DNR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 41

GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 43

BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 44

OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 44

OCR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 44

APPENDIX 1

Board Design and Layout Considerations . . . . . . . . . . . . 45

APPENDIX 2

Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

APPENDIX 3

Copy Generation Management System (CGMS) . . . . . . . 48

APPENDIX 4

Wide Screen Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

APPENDIX 5

Teletext Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

APPENDIX 6

Optional Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

APPENDIX 7

DAC Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

APPENDIX 8

Recommended Register Values . . . . . . . . . . . . . . . . . . . . 53

APPENDIX 9

NTSC Waveforms (With Pedestal) . . . . . . . . . . . . . . . . . 57

NTSC Waveforms (Without Pedestal) . . . . . . . . . . . . . . . 58

PAL Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Video Measurement Plots . . . . . . . . . . . . . . . . . . . . . . . . 60

UV Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

APPENDIX 10

Vector Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 69

–2–

REV. 0

ADV7192

SPECIFICATIONS

2

to T

MAX

= 400 µA

= 2400 Ω

5 V SPECIFICATIONS

(VAA = 5 V, V

1

unless otherwise noted.)

= 1.235 V, R

REF

= 1200  unless otherwise noted. All specifications T

SET1,2

MIN

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity

3

3

1.0 LSB

1.0 LSB Guaranteed Monotonic

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INH

INL

IN

IN

Input Leakage Current
Input Leakage Current

4

5

2.0 V

0.8 V
0 ± 1 µAV
610 pF
1 µA
200 µA

= 0.4 V or 2.4 V

IN

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Three-State Leakage Current
Three-State Leakage Current

OL

OH

6

7

2.4 V I

0.8 0.4 V I
10 µA
200 µA

SOURCE

= 3.2 mA

SINK

Three-State Output Capacitance 6 10 pF

ANALOG OUTPUTS

Output Current (Max) 4.125 4.33 4.625 mA RL = 300 Ω
Output Current (Min) 2.16 mA R

REF

OC

OUT

OUT

8

3

0.4 2.5 %

0 1.4 V

100 kΩ
6pFI

1.112 1.235 1.359 V

DAC-to-DAC Matching
Output Compliance, V
Output Impedance, R
Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

= 600 Ω

L

R

SET1, RSET2

= 0 mA

OUT

POWER REQUIREMENTS

V

AA

Normal Power Mode

I

DAC

I

CCT

I

CCT

I

PLL

9

(Max)
(2× Oversampling)
(4× Oversampling)

10, 11

10, 11

4.75 5.0 5.25 V

29 35 mA
80 120 mA
120 170 mA
610 mA

Sleep Mode

I

DAC

I

CCT

NOTES

1

All measurements are made in 4× Oversampling Mode unless otherwise specified.

2

Temperature range T

3

Guaranteed by characterization.

4

For all inputs but PAL_NTSC and ALSB.

5

For PAL_NTSC and ALSB inputs.

6

For all outputs but VSO/TTX/CLAMP.

7

For VSO/TTX/CLAMP output.

8

Measurement made in 2× Oversampling Mode.

9

I

is the total current required to supply all DACs including the V

DAC

10

All six DACs ON.

11

I

or the circuit current, is the continuous current required to drive the digital core without I

CCT

Specifications subject to change without notice.

MIN

to T

: 0°C to 70°C.

MAX

0.01 µA
85 µA

Circuitry.

REF

.

PLL

REV. 0

–3–

ADV7192–SPECIFICATIONS

3.3 V SPECIFICATIONS

(VAA = 3.3 V, V

1

unless otherwise noted.)

= 1.235 V, R

REF

= 1200  unless otherwise noted. All specifications T

SET1,2

MIN

to T

MAX

2

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity 1.0 LSB
Differential Nonlinearity 1.0 LSB Guaranteed Monotonic

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INH

INL

Input Leakage Current
Input Leakage Current
Input Current, I
Input Capacitance, C

IN

IN

3

4

2V

0.8 V
1 µA
200 µA

± 1 µAV

= 0.4 V or 2.4 V

IN

610 pF

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Three-State Leakage Current
Three-State Leakage Current

OL

OH

5

6

2.4 V I

0.4 V I
10 µA
200 µA

SOURCE

= 3.2 mA

SINK

= 400 µA

Three-State Output Capacitance 6 10 pF

ANALOG OUTPUTS

Output Current (Max) 4.125 4.33 4.625 mA RL = 300 Ω
Output Current (Min) 2.16 mA R

= 600 Ω, R

L

SET1,2

= 2400 Ω
DAC-to-DAC Matching 0.4 2.5 %
Output Compliance, V
Output Impedance, R
Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

REF

OC

OUT

OUT

7

100 kΩ
6pFI

1.235 V I

1.4 V

= 0 mA

OUT

VREFOUT

= 20 µA

POWER REQUIREMENTS

V

AA

Normal Power Mode

I

DAC

I

CCT

I

CCT

I

PLL

Sleep Mode

I

DAC

I

CCT

NOTES

1

All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. In 2 × Oversampling Mode, power require­ment for the ADV7192 is typically 3.0 V.

2

Temperature range T

3

For all inputs but PAL_NTSC and ALSB.

4

For PAL_NTSC and ALSB inputs.

5

For all outputs but VSO/TTX/CLAMP.

6

For VSO/TTX/CLAMP output.

7

Measurement made in 2× Oversampling Mode.

8

I

is the total current required to supply all DACs including the V

DAC

9

All six DACs ON.

10

I

or the circuit current, is the continuous current required to drive the digital core without I

CCT

Specifications subject to change without notice.

8

(Max)
(2× Oversampling)
(4× Oversampling)

10

to T

MIN

MAX

9, 10

9, 10

: 0°C to 70°C.

3.15 3.3 3.6 V

29 mA
42 54 mA
68 86 mA
6mA

0.01 µA
85 µA

Circuitry.

REF

.

PLL

–4–

REV. 0

ADV7192

(VAA = 5 V  250 mV, V

1

5 V DYNAMIC–SPECIFICATIONS

specifications T

MIN

Parameter Min Typ Max Unit Test Conditions

Hue Accuracy 0.5 Degrees
Color Saturation Accuracy 0.7 %
Chroma Nonlinear Gain 0.7 0.9 ±% Referenced to 40 IRE
Chroma Nonlinear Phase 0.5 ± Degrees
Chroma/Luma Intermod 0.1 ±%
Chroma/Luma Gain Ineq 1.7 ± %
Chroma/Luma Delay Ineq 2.2 ns
Luminance Nonlinearity 0.6 0.7 ±%
Chroma AM Noise 82 dB
Chroma PM Noise 72 dB
Differential Gain
Differential Phase
SNR (Pedestal)

SNR (Ramp)

3

3

3

3

0.1 (0.4) 0.3 (0.5) %

0.4 (0.15) 0.5 (0.3) Degrees

78.5 (78) dB rms RMS
78 (78) dB p-p Peak Periodic

61.7 (61.7) dB rms RMS
62 (63) dB p-p Peak Periodic

NOTES

1

All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization.

2

Temperature range T

3

Values in parentheses apply to 2× Oversampling Mode.

Specifications subject to change without notice.

MIN

to T

: 0°C to 70°C.

MAX

= 1.235 V, R

REF

2

to T

unless otherwise noted.)

MAX

= 1200  unless otherwise noted. All

SET1,2

3.3 V DYNAMIC–SPECIFICATIONS

(VAA = 3.3 V  150 mV, V

1

specifications T

MIN

to T

= 1.235 V, R

REF

2

unless otherwise noted.)

MAX

SET1,2

= 1200  unless otherwise noted. All

Parameter Min Typ Max Unit Test Conditions

Hue Accuracy 0.5 Degrees
Color Saturation Accuracy 0.8 %
Luminance Nonlinearity 0.6 ± %
Chroma AM Noise 83 dB
Chroma PM Noise 71 dB
Chroma Nonlinear Gain 0.7 ± % Referenced to 40 IRE
Chroma Nonlinear Phase 0.5 ± Degrees
Chroma/Luma Intermod 0.1 ±%
Differential Gain
Differential Phase
SNR (Pedestal)

SNR (Ramp)

3

3

3

3

0.2 (0.5) %

0.5 (0.2) Degrees

78.5 (78) dB rms RMS
78 (78) dB p-p Peak Periodic

62.3 (62) dB rms RMS
61 (62.5) dB p-p Peak Periodic

NOTES

1

All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization.

2

Temperature range T

3

Values in parentheses apply to 2× Oversampling Mode.

Specifications subject to change without notice.

MIN

to T

: 0°C to 70°C.

MAX

REV. 0

–5–

ADV7192
5 V TIMING CHARACTERISTICS

(VAA = 5 V  250 mV, V
specifications T

MIN

= 1.235 V, R

REF

1

to T

unless otherwise noted.)

MAX

= 1200 V unless otherwise noted. All

SET1,2

Parameter Min Typ Max Unit Test Conditions

MPU PORT

2

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

ANALOG OUTPUTS

2

1

2

3

4

6

7

8

0.6 µs

1.3 µs

0.6 µs After This Period the First Clock Is Generated

0.6 µs Relevant for Repeated Start Condition
100 ns

300 ns
300 ns

0.6 µs

Analog Output Delay 8 ns
DAC Analog Output Skew 0.1 ns

CLOCK CONTROL AND PIXEL

3

PORT

f

CLOCK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t

9

10

11

12

11

12

Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t

(2× Oversampling) 57 Clock Cycles

15

27 MHz
82 ns
83 ns
6 2.5 ns
5 2.0 ns
6ns
4ns

13

14

13 ns

12 ns

Pipeline Delay, t15 (4× Oversampling) 67 Clock Cycles

TELETEXT PORT

Digital Output Access Time, t
Data Setup Time, t
Data Hold Time, t

4

16

17

18

11 ns

3ns

6ns

RESET CONTROL

RESET Low Time 3 20 ns

2

PLL

PLL Output Frequency 54 MHz

NOTES

1

Temperature range T

2

Guaranteed by characterization.

3

Pixel Port consists of:

Data: P7–P0, Y0/P8–Y7/P15 Pixel Inputs
Control: HSYNC, VSYNC, BLANK
Clock: CLKIN

4

Teletext Port consists of:

Digital Output: TTXRQ
Data: TTX

Specifications subject to change without notice.

MIN

to T

: 0°C to 70°C.

MAX

–6–

REV. 0

ADV7192

3.3 V TIMING CHARACTERISTICS

(VAA = 3.3 V  150 mV, V
specifications T

MIN

to T

= 1.235 V, R

REF

1

unless otherwise noted.)

MAX

SET1,2

= 1200  unless otherwise noted. All

2

Parameter Min Typ Max Unit Test Conditions

MPU PORT

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

1

2

3

4

6

7

8

0.6 µs

1.3 µs

0.6 µs After This Period the First Clock Is Generated

0.6 µs Relevant for Repeated Start Condition
100 ns

300 ns
300 ns

0.6 2 µs

ANALOG OUTPUTS

Analog Output Delay 8 ns
DAC Analog Output Skew 0.1 ns

CLOCK CONTROL AND PIXEL

TELETEXT PORT

3

PORT

f

CLOCK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t

9

10

11

12

11

12

Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t

Digital Output Access Time, t
Data Setup Time, t
Data Hold Time, t

(2× Oversampling) 37 Clock Cycles

15

4

16

17

18

27 MHz
82 ns
83 ns
64 ns
4 2.0 ns
2, 5 ns
3ns

13

14

13 ns

12 ns

11 ns

3ns

6ns

RESET CONTROL

RESET Low Time 3 20 ns

PLL

PLL Output Frequency 54 MHz

NOTES

1

Temperature range T

2

Guaranteed by characterization.

3

Pixel Port consists of:
Data: P7–P0, Y0/P8–Y7/P15 Pixel Inputs
Control: HSYNC, VSYNC, BLANK
Clock: CLKIN

4

Teletext Port consists of:
Digital Output: TTXRQ
Data: TTX

Specifications subject to change without notice.

MIN

to T

: 0°C to 70°C.

MAX

REV. 0

–7–

ADV7192

SDA

SCL

CLOCK

t

t

3

t

6

t

2

5

t

1

t

7

Figure 1. MPU Port Timing Diagram

t

3

t

4

t

8

TXTREQ

CLOCK

TXT

CONTROL

t

16

CONTROL

I/PS

O/PS

HSYNC,
VSYNC,

BLANK

PIXEL INPUT

DATA

HSYNC,

VSYNC,

BLANK,

CSO_HSO,

VSO, CLAMP

t

17

t

18

4 CLOCK

CYCLES

t

t

9

10

Cb Y Cr Y Cb Y

t

12

t

11

t

13

t

14

Figure 2. Pixel and Control Data Timing Diagram

4 CLOCK

CYCLES

4 CLOCK
CYCLES

3 CLOCK

CYCLES

Figure 3. Teletext Timing Diagram

4 CLOCK

CYCLES

PROGRESSIVE

SCAN INPUT

CLOCK

Y0–Y9

INCLUDING

SYNC

INFORMATION

Cb0–Cb9

Cr0–Cr9

t

t9t

10

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cb1 Cb2 Cb3 Cb4 Cb5

Cr0 Cr1 Cr2 Cr3 Cr4 Cr5

12

t

11

Figure 4. Progressive Scan Input Timing

–8–

REV. 0

ADV7192

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

AA

Voltage on any Digital Input Pin . . GND – 0.5 V to V
Storage Temperature (T
Junction Temperature (T

Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220°C

Analog Outputs to GND

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

) . . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . . . 150°C

J

2

. . . . . . . . . . . . GND – 0.5 V to V

1

+ 0.5 V

AA

AA

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Analog Output Short Circuit to any Power Supply or Common can be of an

indefinite duration.

PIN CONFIGURATION

DGND

VDDCb[3]

Cb[2]

Cb[1]

Cb[0]

Cr[9]

Cr[8]

Cr[7]

ADV7192

LQFP

TOP VIEW

(Not to Scale)

Cb[5]

Cb[6]

Cb[7]

Cr[6]

Cb[8]

NC

NC

P0
P1

P2

P3
P4

P5

P6
P7

Y[0]/P8

Y[1]/P9

Y[2] /P10

Y[3] /P11

Y[4] /P12

Y[5] /P13

Y[6] /P14

Y[7] /P15

Y[8]

Y[9]

NC = NO CONNECT

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

DD

V

DGND

VSYNC

HSYNC

Cb[4]

BLANK

PACKAGE THERMAL PERFORMANCE

The 80-lead package is used for this device. The junction-to­ambient (θ

) thermal resistance in still air on a four-layer PCB

JA

is 24.7°C.

To reduce power consumption when using this part the user
can run the part on a 3.3 V supply, turn off any unused DACs.

The user must at all times stay below the maximum junction
temperature of 110°C. The following equation shows how to
calculate this junction temperature:

Junction Temperature = (V

I

= 10 mA + (sum of the average currents consumed by

DAC

AA

× (I

DAC

+ I

)) × θJA + 70°C T

CCT

AMB

each powered-on DAC)

Average current consumed by each powered-on DAC =

(V

× K )/R

REF

V

REF

= 1.235 V

SET

K = 4.2146

DGND

Cr[5]

VDDCr[4]

Cr[3]

Cr[2]

Cr[1]

VSO/ TTX/CLAMP

CSO_HSO

Cr[0]

60

RESET

59

PAL_NTSC

58

R

SET1

57

V

REF

56

COMP 1

55

DAC A

54

DAC B

53

V

AA

52

AGND

51

DAC C

50

DAC D

49

AGND

48

V

AA

47

DAC E

46

DAC F

45

COMP 2
R

44

SET2

43

DGND

42

ALSB

41

SCRESET/ RTC/TR

Cb[9]

DGND

TTXREQ

DD

V

AGND

CLKIN

AA

V

CLKOUT

SCL

SDA

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7192KST 0°C to 70°C 80-Lead Quad Flatpack ST-80

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7192 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. 0

–9–

ADV7192

PIN FUNCTION DESCRIPTIONS

Pin Input/
No. Mnemonic Output Function

1, 2 NC No Connect.
3–10 P0–P7 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on Pin P0

(Pin Number 3).

11–18 Y0/P8–Y7/P15 I 16-Bit 4:2:2 Multiplexed YCrCb Pixel Port (Bits 8–15). 1 × 10-bit progressive scan input for

Ydata (Bits 0–7).

19, 20 Y8–Y9 1 × 10-bit progressive scan input is Ydata (Bits 8 and 9).
21, 34, 68, 79 V

DD

22, 33, 43, 69, DGND G Digital Ground.
80

23 HSYNC I/O HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output

24 VSYNC I/O VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an

25 BLANK I/O Video Blanking Control Signal. This signal is optional. For further information see

26–31, 75–78 Cb4–Cb9, Cb0–Cb3 I 1 × 10-Bit Progressive Scan Input Port for Cb data.
32 TTXREQ O Teletext Data Request Output Signal, used to control teletext data transfer.
35, 49, 52 AGND G Analog Ground.
36 CLKIN I TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation.

37 CLKOUT O Clock Output pin.
38, 48, 53 V

AA

39 SCL I MPU Port Serial Interface Clock Input.
40 SDA I/O MPU Port Serial Data Input/Output.
41 SCRESET/ I Multifunctional Input: Real Time Control (RTC) input, Timing Reset input, Subcarrier

RTC/TR Reset input.

42 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.
44 R

SET2

45 COMP 2 O Compensation Pin for DACs D, E, and F. Connect a 0.1 µF Capacitor from COMP2

46 DAC F O S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
47 DAC E O S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
50 DAC D O Composite/Y (progressive scan)/Y/Green Analog Output. This DAC is capable of providing

51 DAC C O S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
54 DAC B O S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
55 DAC A O Composite/Y(progressive scan)/Y/Green Analog Output. This DAC is capable of providing

56 COMP 1 O Compensation Pin for DACs A, B, and C. Connect a 0.1 µF Capacitor from COMP1 to V
57 V

58 R

REF

SET1

59 PAL_NTSC I Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL.
60 RESET I The input resets the on-chip timing generator and sets the ADV7192 into default mode.

61 CSO_HSO O Dual function CSO or HSO Output Sync Signal at TTL Level.
62 VSO/TTX/CLAMP I/O Multifunctional Pin. VSO Output Sync Signal at TTL level. Teletext Data Input pin.

63–67, 70–74 Cr0–Cr4, Cr5–Cr9 I 1 × 10-Bit progressive scan input port for Cr data.

P Digital Power Supply (3.3 V to 5 V).

(Master Mode) or an input (Slave Mode) and accept Sync Signals.

input (Slave Mode) and accept VSYNC as a Control Signal.

Vertical Blanking and Data Insertion Blanking Input section.

Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel
operation.

P Analog Power Supply (3.3 V to 5 V).

I A 1200 Ω resistor connected from this pin to GND is used to control full-scale amplitudes

of the Video Signals from the DAC D, E, F.

to VAA.

4.33 mA output.

4.33 mA output.
.

AA

I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external

V

cannot be used in 4× Oversampling Mode.

REF

I A 1200 Ω resistor connected from this pin to GND is used to control full-scale amplitudes

of the Video Signals from the DAC A, B, C.

See Appendix 8 for Default Register settings.

CLAMP TTL output signals can be used to drive external circuitry to enable clamping
of all video signals.

–10–

REV. 0

ADV7192

DETAILED DESCRIPTION OF FEATURES
Clocking:

Single 27 MHz Clock Required to Run the Device
4 Oversampling with Internal 54 MHz PLL

Square Pixel Operation
Advanced Power Management
Programmable Video Control Features:

Digital Noise Reduction

Black Burst Signal Generation

Pedestal Level

Hue, Brightness, Contrast, and Saturation

Clamping Output Signal

VBI (Vertical Blanking Interval)

Subcarrier Frequency and Phase

LUMA Delay

CHROMA Delay

Gamma Correction

Luma And Chroma Filters

Luma SSAF (Super Subalias Filter)
Average Brightness Detection
Field Counter
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision Rev 7.1
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface

2

C-Compatible And Fast I2C)

(I

2

C Registers Synchronized to VSYNC

I

GENERAL DESCRIPTION

The ADV7192 is an integrated Digital Video Encoder that
converts digital CCIR-601/656 4:2:2 8-bit or 16-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards. Additionally, it is possible

HSYNC

VSYNC

BLANK

RESET

TTX

TTXRQ

P15

CLKIN

CLKOUT

PAL_NTSC

YCrCb-

MATRIX

10 1010

P0

DEMUX

VSO/CLAMP

VIDEO TIMING

GENERATOR

INSERTION

10

Y

TO-

10

YUV

U

10

V

TELETEXT

BLOCK

CORRECTION

PLL

DNR
AND

GAMMA

CSO_HSO

CLOSED CAPTIONING

10

INTERPOLATOR

Y

10

U

10

V

INTERPOLATOR

ADV7192

CGMS/WSS

AND

CONTROL

BRIGHTNESS

CONTROL

AND

ADD SYNC

AND

SATURATION

CONTROL

AND

ADD BURST

AND

I2C MPU PORT

PROGRAMMABLE

LUMA FILTER

AND

SHARPNESS

FILTER

PROGRAMMABLE

CHROMA

FILTER

REAL-TIME

CONTROL

CIRCUIT

SCRESET/RTC/TR

Figure 5. Detailed Functional Block Diagram

REV. 0

–11–

to input video data in 3⫻ 10-bit YCrCb progressive scan format
to facilitate interfacing devices such as progressive scan systems.

Six DACs are available on the ADV7192, each of which is capable
of providing 4.33 mA of current. In addition to the composite
output signal there is the facility to output S-Video (Y/C Video),
RGB Video and YUV Video. All YUV formats (SMPTRE/EBU
N10, MII or Betacam) are supported.

The on-board SSAF (Super Subalias Filter) with extended lumi­nance frequency response and sharp stopband attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness
control feature allows high-frequency enhancement on the
luminance signal.

DNR MODE

Y DATA

INPUT

DNR CONTROL

BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

FILTER OUTPUT

<THRESHOLD?

FILTER OUTPUT>

THRESHOLD

GAIN

CORING GAIN DATA
CORING GAIN BORDER

SUBTRACT SIGNAL IN THRESHOLD
RANGE FROM ORIGINAL SIGNAL

DNR OUT

DNR SHARPNESS MODE

Y DATA

INPUT

DNR CONTROL

BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

FILTER OUTPUT

>THRESHOLD?

FILTER OUTPUT<

THRESHOLD

GAIN

CORING GAIN DATA
CORING GAIN BORDER

ADD SIGNAL ABOVE THRESHOLD
RANGE TO ORIGINAL SIGNAL

DNR OUT

Figure 6. Block Diagram for DNR Mode and DNR Sharpness
Mode

ALSBSDASCL

MODULATOR

HUE CONTROL

YUV-TO-RGB

MATRIX

AND

YUV LEVEL

CONTROL

BLOCK

AND

SIN/COS

DDS

BLOCK

Y0–Y9Cb0–Cb9Cr0–Cr9

M
U
L
T

I
P
L
E
X
E
R

I

10-BIT

N

DAC

T
E

10-BIT

R

DAC

P
O

10-BIT

L

DAC
A
T
O
R

DAC

CONTROL

BLOCK

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

DAC

CONTROL

BLOCK

I
N
T
E
R
P

O
L
A
T
O
R

DAC A

DAC B

DAC C

V

REF

R

SET2

COMP2

DAC D

DAC F

DAC E

R

SET1

COMP1

ADV7192

Digital Noise Reduction allows improved picture quality in remov­ing low amplitude, high frequency noise. Figure 6 shows the DNR
functionality in the two modes available.

Programmable gamma correction is also available. The figure below
shows the response of different gamma values to a ramp signal.

300

GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT FOR VARIOUS GAMMA VALUES

250

200

150

100

GAMMA-CORRECTED AMPLITUDE

50

0

0 50 100 150 200 250

SIGNAL OUTPUTS

0.3

0.5

1.5

SIGNAL INPUT

LOCATION

1.8

Figure 7. Signal Input (Ramp) and Selectable Gamma
Output Curves

The device is driven by a 27 MHz clock. Data can be output at
27 MHz or 54 MHz (on-board PLL) when 4
enabled. Also, the output filter requirements in 4

⫻

oversampling is

⫻

oversampling

and 2⫻ oversampling differ, as can be seen in Figure 8.

0dB

–30dB

2 FILTER
REQUIREMENTS

4 FILTER
REQUIREMENTS

6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz

Figure 8. Output Filter Requirements in 4×Oversampling
Mode

54MHz

2



6

I

D

N

A

T

C

E
R
P
O
L
A
T

I
O
N

54MHz

O

OUTPUT

U

RATE

T
P
U
T
S

MPEG2

PIXEL BUS

27MHz

ADV7192

ENCODER

CORE

PLL

Figure 9. PLL and 4× Oversampling Block Diagram

The ADV7192 also supports both PAL and NTSC square pixel
operation. In this case the encoder requires a 24.5454 MHz Clock
for NTSC or 29.5 MHz Clock for PAL square pixel mode opera­tion. All internal timing is generated on-chip.

An advanced power management circuit enables optimal control
of power consumption in normal operating modes or sleep modes.

The Output Video Frames are synchronized with the incoming
data Timing Reference Codes. Optionally, the Encoder accepts
(and can generate) HSYNC, VSYNC, and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in master mode.

HSO/CSO and VSO TTL outputs are also available and are timed
to the analog output video.

A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.

The ADV7192 also incorporates WSS and CGMS-A data control
generation.

The ADV7192 modes are set up over a 2-wire serial bidirectional

2

port (I

C-compatible) with two slave addresses, and the device

is register-compatible with the ADV7172.

The ADV7192 is packaged in an 80-lead LQFP package.

DATA PATH DESCRIPTION

For PAL B, D, G, H, I, M, N, and NTSCM, N modes, YCrCb
4:2:2 data is input via the CCIR-656/601-compatible Pixel Port
at a 27 MHz Data Rate. The Pixel Data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr and Cb
typically have a range of 128⫾112; however, it is possible to
input data from 1 to 254 on both Y, Cb, and Cr. The ADV7192
supports PAL (B, D, G, H, I, N, M) and NTSCM, N (with
and without Pedestal) and PAL60 standards.

Digital noise reduction can be applied to the Y signal. Pro­grammable gamma correction can also be applied to the Y
signal if required.

The Y data can be manipulated for contrast control and a setup
level can be added for brightness control. The Cr, Cb data can
be scaled to achieve color saturation control. All settings become
effective at the start of the next field when double buffering is
enabled.

The appropriate sync, blank, and burst levels are added to the
YCrCb data. Macrovision antitaping, closed-captioning and
teletext levels are also added to Y and the resultant data is inter­polated to 54 MHz (4⫻ Oversampling Mode). The interpolated
data is filtered and scaled by three digital FIR filters.

The U and V signals are modulated by the appropriate Subcarrier
Sine/Cosine waveforms and a phase offset may be added onto
the color subcarrier during active video to allow hue adjustment.
The resulting U and V signals are added together to make up
the Chrominance signal. The Luma (Y) signal can be delayed
by up to six clock cycles (at 27 MHz) and the Chroma signal
can be delayed by up to eight clock cycles (at 27 MHz).

The Luma and Chroma signals are added together to make up
the Composite Video Signal. All timing signals are controlled.

The YCrCb data is also used to generate RGB data with appropri­ate sync and blank levels. The YUV levels are scaled to output
the suitable SMPTE/EBU N10, MII, or Betacam levels.

Each DAC can be individually powered off if not required. A
complete description of DAC output configurations is given in
the Mode Register 2 section.

Video output levels are illustrated in Appendix 9.

–12–

REV. 0

ADV7192

When used to interface progressive scan systems, the ADV7192
allows input to YCrCb signals in Progressive Scan format
(3

⫻

10-bit) before these signals are routed to the interpolation

filters and the DACs.

INTERNAL FILTER RESPONSE

The Y Filter supports several different frequency responses
including two low-pass responses, two notch responses, an
Extended (SSAF) response with or without gain boost/attenuation,
a CIF response, and a QCIF response. The UV/filter supports

several different frequency responses including five low-pass
responses, a CIF response, and a QCIF response, as can be seen in

⫻

the following figures. All filter plots show the 4

Oversampling

responses.

In Extended Mode there is the option of 12 responses in the range
from –4 dB to +4 dB. The desired response can be chosen by the
user by programming the correct value via the I

2

C. The variation
of frequency responses can be seen in the Tables I and II. For
more detailed filter plots refer to Analog Devices’ Application
Note AN-562.

Table I. Luminance Internal Filter Specifications (4 Oversampling)

Passband 3 dB Bandwidth2Stopband Stopband

Filter Type Filter Selection Ripple1 (dB) (MHz) Cutoff 3 (MHz) Attentuation4 (dB)

MR04 MR03 MR02

Low-Pass (NTSC) 0 0 0 0.16 4.24 6.05 –75.2
Low-Pass (PAL) 0 0 1 0.1 4.81 6.41 –64.6
Notch (NTSC) 0 1 0 0.09 2.3/4.9/6.6 8.03 –87.3
Notch (PAL) 0 1 1 0.1 3.1/5.6/6.4 8.02 –79.7
Extended (SSAF) 1 0 0 0.04 6.45 8.03 –86.6
CIF 1 0 1 0.127 3.02 5.04 –62.6
QCIF 1 1 0 Monotonic 1.5 3.74 –88.2

NOTES

1

Passband Ripple is defined as the fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0–fc frequency limits for a
low-pass filter, 0–f1 and f2–infinity for a notch filter, where fc, f1, f2 are the –3 dB points.

2

3 dB bandwidth refers to the –3 dB cutoff frequency.

3

Stopband Cutoff refers to the frequency at the attenuation point referred to under Note 4.

4

Stopband Attenuation refers to the attenuation point (dB) at the frequency referred to under Note 3.

Table II. Chrominance Internal Filter Specifications (4 Oversampling)

Passband 3 dB Bandwidth2Stopband Stopband

Filter Type Filter Selection Ripple1 (dB) (MHz) Cutoff 3 (MHz) Attentuation4 (dB)

MR07 MR06 MR05

1.3 MHz Low-Pass 0 0 0 0.09 1.395 2.46 –83.9

0.65 MHz Low-Pass 0 0 1 Monotonic 0.65 2.41 –71.1

1.0 MHz Low-Pass 0 1 0 Monotonic 1.0 1.89 –64.43

2.0 MHz Low-Pass 0 1 1 0.048 2.2 3.1 –65.9

3.0 MHz Low-Pass 1 0 0 Monotonic 3.2 5.3 –84.5
CIF 1 0 1 Monotonic 0.65 2.41 –71.1
QCIF 1 1 0 Monotonic 0.5 1.75 –33.1

NOTES

1

Passband Ripple is defined as the fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0–fc frequency limits for a
low-pass filter, 0–f1 and f2–infinity for a notch filter, where fc, f1, f2 are the –3 dB points.

2

3 dB bandwidth refers to the –3 dB cutoff frequency.

3

Stopband Cutoff refers to the frequency at the attenuation point referred to under Note 4.

4

Stopband Attenuation refers to the attenuation point (dB) at the frequency referred to under Note 3.

REV. 0

–13–

ADV7192

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 10. NTSC Low-Pass Luma Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 13. PAL Notch Luma Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 11. PAL Low-Pass Luma Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 12. NTSC Notch Luma Filter

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 14. Extended Mode (SSAF) Luma Filter

4

2

0

–2

–4

–6

MAGNITUDE – dB

–8

–10

–12

0

1

2

FREQUENCY – MHz

4

3

5

67

Figure 15. Extended SSAF Luma Filter and Programmable
Gain/Attenuation Showing

+

4 dB/–12 dB Range

–14–

REV. 0

MAGNITUDE – dB

0

–20

0

–50

–60

–30

–10

24 101268

–70

–40

MAGNITUDE – dB

FREQUENCY – MHz

0

–20

0

–50

–60

–30

–10

24 101268

–70

–40

MAGNITUDE – dB

FREQUENCY – MHz

0

–20

0

–50

–60

–30

–10

24 101268

–70

–40

MAGNITUDE – dB

FREQUENCY – MHz

ADV7192

1

0

–1

–2

–3

–4

–5

0

1

2

FREQUENCY – MHz

4

3

5

67

Figure 16. Extended SSAF and Programmable Attenuation,
Showing Range 0 dB/–4dB

5

4

3

2

MAGNITUDE – dB

1

0

–1

0

1

2

FREQUENCY – MHz

4

3

5

67

Figure 17. Extended SSAF and Programmable Gain,
Showing Range 0 dB/+4 dB

0

Figure 19. Luma QCIF Filter

Figure 20. Chroma 0.65 MHz Low-Pass Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

REV. 0

–60

–70

0

2 4 10 1268

Figure 18. Luma CIF Filter

FREQUENCY – MHz

Figure 21. Chroma 1.0 MHz Low-Pass Filter

–15–

ADV7192

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 22. Chroma 1.3 MHz Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

MAGNITUDE – dB

MAGNITUDE – dB

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

0

0

2 4 10 1268

FREQUENCY – MHz

Figure 25. Chroma CIF Filter

0

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 23. Chroma 2 MHz Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 24. Chroma 3 MHz Low-Pass Filter

–60

–70

0

2 4 10 1268

FREQUENCY – MHz

Figure 26. Chroma QCIF Filter

–16–

REV. 0

ADV7192

FEATURES: FUNCTIONAL DESCRIPTION

BLACK BURST OUTPUT

It is possible to output a black burst signal from two DACs. This
signal output is very useful for professional video equipment
since it enables two video sources to be locked together. (Mode
Register 9.)

DIGITAL DATA

GENERATOR

BLACK BURST OUTPUT

DIGITAL DATA

GENERATOR

ADV7192

CVBS

CVBS

ADV7192

Figure 27. Possible Application for the Black Burst Output
Signal

BRIGHTNESS DETECT

This feature is used to monitor the average brightness of the
incoming Y video signal on a field by field basis. The information
is read from the I

2

C and based on this information the color
saturation, contrast and brightness controls can be adjusted (for
example to compensate for very dark pictures). (Brightness Detect
Register.)

CHROMA/LUMA DELAY

The luminance data can be delayed by maximum of six clock
cycles. Additionally the Chroma can be delayed by a maximum
of eight clock cycles (one clock cycle at 27 MHz). (Timing Reg­ister 0 and Mode Register 9.)

CHROMA DELAY

LUMA DELAY

Figure 28. Chroma Delay Figure 29. Luma Delay

CLAMP OUTPUT

The ADV7192 has a programmable clamp TTL output signal.
This clamp signal is programmable to the front and back porch.
The clamp signal can be varied by one to three clock cycles in a
positive and negative direction from the default position.
(Mode Register 5, Mode Register 7.)

CLAMP O/P SIGNALS

CVBS
OUTPUT PIN

MR57 = 1

MR57 = 0

CLAMP
OUTPUT PIN

Figure 30. Clamp Output Timing

CSO, HSO AND VSO OUTPUTS

The ADV7192 supports three output timing signals, CSO
(composite sync signal), HSO (Horizontal Sync Signal) and
VSO (Vertical Sync Signal). These output TTL signals are aligned
with the analog video outputs. See Figure 31 for an example
of these waveforms. (Mode Register 7.)

EXAMPLE:- NTSC

OUTPUT

5251234567891011–19

VIDEO

CSO

HSO

VSO

Figure 31.

CSO, HSO, VSO

Timing Diagram

COLOR BAR GENERATION

The ADV7192 can be configured to generate 100/7.5/75/7.5 color
bars for NTSC or 100/0/75/0 color bars for PAL.
(Mode Register 4.)

COLOR BURST SIGNAL CONTROL

The burst information can be switched on and off the composite
and chroma video output. (Mode Register 4.)

COLOR CONTROLS

The ADV7192 allows the user to control the brightness, contrast,
hue and saturation of the color. The control registers may be
double-buffered, meaning that any modification to the registers
will be done outside the active video region and, therefore, changes
made will not be visible during active video.

Contrast Control

Contrast adjustment is achieved by scaling the Y input data by a
factor programmed by the user. This factor allows the data to be
scaled between 0% and 150%. (Contrast Control Register.)

Brightness Control

The brightness is controlled by adding a programmable setup level
onto the scaled Y data. This brightness level may be added onto
the Y data. For NTSC with pedestal, the setup can vary from
0 IRE to 22.5 IRE. For NTSC without pedestal and PAL, the
setup can vary from –7.5 IRE to +15 IRE. (Brightness Control
Register.)

Color Saturation

Color adjustment is achieved by scaling the Cr and Cb input
data by a factor programmed by the user. This factor allows the
data to be scaled between 0% and 200%. (U Scale Register and
V Scale Register.)

Hue Adjust Control

The hue adjustment is achieved on the composite and chroma
outputs by adding a phase offset onto the color subcarrier in the
active video but leaving the color burst unmodified, i.e., only
the phase between the video and the colorburst is modified and
hence the hue is shifted. The ADV7192 provides a range of
± 22° in increments of 0.17578125°. (Hue Adjust Register.)

CHROMINANCE CONTROL

The color information can be switched on and off the com­posite, chroma and color component video outputs. (Mode
Register 4.)

REV. 0

–17–

ADV7192

UNDERSHOOT LIMITER

A limiter is placed after the digital filters. This prevents any
synchronization problems for TVs. The level of undershoot is
programmable between –1.5 IRE, –6 IRE, –11 IRE when oper­ating in 4× Oversampling Mode. In 2× Oversampling Mode the
limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing
Register 0.)

DIGITAL NOISE REDUCTION

DNR is applied to the Y data only. A filter block selects the
high frequency, low amplitude components of the incoming
signal (DNR Input Select). The absolute value of the filter output
is compared to a programmable threshold value (DNR Thresh­old Control). There are two DNR modes available: DNR Mode
and DNR Sharpness Mode.

In DNR Mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (Coring Gain Control) of this noise signal will be sub­tracted from the original signal.

In DNR Sharpness Mode, if the absolute value of the filter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (Coring
Gain Control) will be added to the original signal in order to boost
high frequency components and to sharpen the video image.

In MPEG systems it is common to process the video information
in blocks of 8 × 8 pixels for MPEG2 systems, or 16 × 16 pixels
for MPEG1 systems ('Block Size Control'). DNR can be applied
to the resulting block transition areas that are known to contain
noise. Generally the block transition area contains two pixels. It
is possible to define this area to contain four pixels (Border Area
Control).

It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the Block Offset
Control. (Mode Register 8, DNR Registers 0–2.)

POWER-ON RESET

After power-up, it is necessary to execute a RESET operation. A
reset occurs on the falling edge of a high-to-low transition on the
RESET pin. This initializes the pixel port such that the data on
the pixel inputs pins is ignored. See Appendix 8 for the register
settings after RESET is applied.

PROGRESSIVE SCAN INPUT

It is possible to input data to the ADV7192 in progressive scan
format. For this purpose the input pins Y0/P8–Y7/P15, Y8–Y9,
Cr0–Cr9 and Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data
and 10-bit Cr data. The data is clocked into the part at 27 MHz.
The data is then filtered and sinc corrected in an 2⫻ Interpo­lation filter and then output to three video DACs at 54 MHz
(to interface to a progressive scan monitor).

0

–10

–20

–30

–40

AMPLITUDE – dB

–50

–60

–70

0305

10 15 20 25

FREQUENCY – MHz

Figure 32. Plot of the Interpolation Filter for the Y Data

0

–10

DOUBLE BUFFERING

Double buffering can be enabled or disabled on the following
registers: Closed Captioning Registers, Brightness Control Reg­ister, V-Scale, U-Scale Contrast Control Register, Hue Adjust
Register, Macrovision Registers, and the Gamma Curve Select
bit. These registers are updated once per field on the falling
edge of the VSYNC signal. Double Buffering improves the overall
performance of the ADV7192, since modifications to register
settings will not be made during active video, but take effect on
the start of the active video. (Mode Register 8.)

GAMMA CORRECTION CONTROL

Gamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if
gamma correction is enabled. Gamma correction allows the
mapping of the luma data to a user-defined function. (Mode
Register 8, Gamma Correction Registers 0–13.)

NTSC PEDESTAL CONTROL

In NTSC mode it is possible to have the pedestal signal gener­ated on the output video signal. (Mode Register 2.)

–18–

–20

–30

–40

AMPLITUDE – dB

–50

–60

–70

0305

10 15 20 25

FREQUENCY – MHz

Figure 33. Plot of the Interpolation Filter for the CrCb Data

It is assumed that there is no color space conversion or any other
such operation to be performed on the incoming data. Thus if
these DAC outputs are to drive a TV, all relevant timing and
synchronization data should be contained in the incoming digital
Y data.

The block diagram below shows a possible configuration for
progressive scan mode using the ADV7192.

REV. 0

ADV7192

ENCODER
ADV7192

54MHz

MPEG2

27MHz

PIXEL BUS

PROGRESSIVE

SCAN

DECODER

PLL

ENCODER

CORE

30-BIT INTERFACE

I

N

O

T

U

6

E

T

R

P

D

P

2



U

A

O

T

C

L

S

A

T

I
O
N

Figure 34. Block Diagram Using the ADV7192 in Progres­sive Scan Mode

The progressive scan decoder deinterlaces the data from the
MPEG2 decoder. This now means that there are 525 video lines
per field in NTSC mode and 625 video lines per field in PAL
mode. The duration of the video line is now 32 µs.

It is important to note that the data from the MPEG2 decoder
is in 4:2:2 format. The data output from the progressive scan
decoder is in 4:4:4 format. Thus it is assumed that some form of
interpolation on the color component data is performed in the
progressive scan decoder IC. (Mode Register 8.)

REAL-TIME CONTROL, SUBCARRIER RESET, AND
TIMING RESET

Together with the SCRESET/RTC/TR pin and Mode Register 4
(Genlock Control), the ADV7192 can be used in (a) Timing
Reset Mode, (b) Subcarrier Phase Reset Mode or (c) RTC Mode.

(a) A TIMING RESET is achieved in holding this pin high. In

this state the horizontal and vertical counters will remain reset.
On releasing this pin (set to low), the internal counters will
commence counting again. The minimum time the pin has
to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise
the reset signal might not be recognized.

(b) The SUBCARRIER PHASE will reset to that of Field 0 at

the start of the following field when a low to high transition
occurs on this input pin.

(c) In RTC MODE, the ADV7192 can be used to lock to an ex-

ternal video source.

The real-time control mode allows the ADV7192 to auto­matically alter the subcarrier frequency to compensate for line
length variations. When the part is connected to a device
that outputs a digital datastream in the RTC format (such as
a ADV7185 video decoder, see Figure 38), the part will
automatically change to the compensated subcarrier frequency
on a line-by-line basis. This digital datastream is 67 bits
wide and the subcarrier is contained in Bits 0 to 21. Each bit
is two clock cycles long. 00Hex should be written into all four
Subcarrier Frequency registers when using this mode. (Mode
Register 4.)

SCH PHASE MODE

The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos­sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.

Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor SCH
phase jumps at the start of the four or eight field sequence.

Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7192 is configured in RTC
mode. Under these conditions (unstable video) the Subcarrier
Phase Reset should be enabled but no reset applied. In this
configuration the SCH Phase will never be reset; this means that
the output video will now track the unstable input video. The Sub­carrier Phase Reset when applied will reset the SCH phase to Field
0 at the start of the next field (e.g., Subcarrier Phase Reset applied
in Field 5 (PAL) on the start of the next field SCH phase will be
reset to Field 0). (Mode Register 4.)

SLEEP MODE

If, after RESET, the SCRESET/RTC/TR and NTSC_PAL pins
are both set high, the ADV7192 will power up in Sleep Mode to
facilitate low power consumption before all registers have been
initialized.

If Power-up in Sleep Mode is disabled, Sleep Mode control
passes to the Sleep Mode control in Mode Register 2 (i.e., con­trol via I

2

C). (Mode Register 2 and Mode Register 6.)

SQUARE PIXEL MODE

The ADV7192 can be used to operate in square pixel mode. For
NTSC operation an input clock of 24.5454 MHz is required.
Alternatively, for PAL operation, an input clock of 29.5 MHz
is required. The internal timing logic adjusts accordingly for
square pixel mode operation. Square pixel mode is not available
in 4× Oversampling mode. (Mode Register 2.)

VERTICAL BLANKING DATA INSERTION AND BLANK
INPUT

It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not have line sync or pre-/post-equal­ization pulses . This mode of operation is called Partial Blanking. It
allows the insertion of any VBI data (Opened VBI) into the
encoded output waveform, this data is present in digitized
incoming YCbCr data stream (e.g., WSS data, CGMS, VPS
etc.). Alternatively the entire VBI may be blanked (no VBI data
inserted) on these lines. VBI is available in all timing modes.

The complete VBI is comprised of the following lines:

525/60 systems, Lines 525 to 21 for field one and Lines 262 to
Line 284 for field two.

625/50 systems, Lines 624 to Line 22 and Lines 311 to 335.
The “Opened VBI” consists of:

525/60 systems, Lines 10 to 21 for field one and second half of
Line 273 to Line 284 for field two.

625/50 systems, Lines 7 to 22 and Lines 319 to 335.
(Mode Register 3.)

It is possible to allow control over the BLANK signal using
Timing Register 0. When the BLANK input is enabled (TR03 =
0 and input pin tied low), the BLANK input can be used to
input externally generated blank signals in Slave Mode 1, 2, or

3. When the BLANK input is disabled (TR03 = 1 and input pin
tied low or tied high) the BLANK input is not used and the
ADV7192 automatically blanks all normally blank lines as per
CCIR-624. (Timing Register 0.)

REV. 0

–19–

ADV7192

YUV LEVELS

This functionality allows the ADV7192 to output SMPTE levels
or Betacam levels on the Y output when configured in PAL or
NTSC mode.

Sync Video

Betacam 286 mV 714 mV
SMPTE 300 mV 700 mV
MII 300 mV 700 mV

As the data path is branched at the output of the filters, the luma
signal relating to the CVBS or S-Video Y/C output is unaltered.
Only the Y output of the YCrCb outputs is scaled. This control
allows color component levels to have a peak-peak amplitude of
700 mV, 1000 mV or the default values of 934 mV in NTSC and
700 mV in PAL. (Mode Register 5.)

16-BIT INTERFACE

It is possible to input data in 16-bit format. In this case, the
interface only operates if the data is accompanied by separate
HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not
available in Slave Mode 0 since EAV/SAV timing codes are
used. (Mode Register 8.)

4 OVERSAMPLING AND INTERNAL PLL

It is possible to operate all six DACs at 27 MHz (2× Oversam­pling) or 54 MHz (4× Oversampling).

The ADV7192 is supplied with a 27 MHz clock synced with the
incoming data. Two options are available: to run the device
throughout at 27 MHz or to enable the PLL. In the latter case,
even if the incoming data runs at 27 MHz, 4× Oversampling and
the internal PLL will output the data at 54 MHz.

NOTE
In 4× Oversampling Mode the requirements for the optional
output filters are different from those in 2× Oversampling. (Mode
Register 1, Mode Register 6.) See Appendix 6.

54MHz

2



6

I

D

N

A

T

C

E
R
P
O
L
A
T

I
O
N

54MHz

O

OUTPUT

U

T
P
U

T
S

MPEG2

PIXEL BUS

27MHz

ENCODE
ADV7192

ENCODER

CORE

PLL

Figure 35. PLL and 4× Oversampling Block Diagram

0dB

–30dB

2 FILTER
REQUIREMENTS

4 FILTER
REQUIREMENTS

6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz

Figure 36. Output Filter Requirements in 2× and 4× Over­sampling Mode

VIDEO TIMING DESCRIPTION

The ADV7192 is intended to interface to off-the-shelf MPEG1
and MPEG2 Decoders. As a consequence, the ADV7192 accepts
4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has
several Video Timing Modes of operation that allow it to be
configured as either System Master Video Timing Generator or
a Slave to the System Video Timing Generator. The ADV7192
generates all of the required horizontal and vertical timing periods
and levels for the analog video outputs.

The ADV7192 calculates the width and placement of analog
sync pulses, blanking levels, and color burst envelopes. Color
bursts are disabled on appropriate lines and serration and equal­ization pulses are inserted where required.

In addition the ADV7192 supports a PAL or NTSC square pixel
operation. The part requires an input pixel clock of 24.5454 MHz
for NTSC square pixel operation and an input pixel clock of

29.5 MHz for PAL square pixel operation. The internal horizontal
line counters place the various video waveform sections in the cor­rect location for the new clock frequencies.

The ADV7192 has four distinct Master and four distinct Slave
timing configurations. Timing Control is established with
the bidirectional HSYNC, BLANK and VSYNC pins. Tim­ing Register 1 can also be used to vary the timing pulsewidths
and where they occur in relation to each other. (Mode Regis­ter 2, Timing Register 0, 1.)

RESET SEQUENCE

When RESET becomes active the ADV7192 reverts to the default
output configuration (see Appendix 8 for register settings). The
ADV7192 internal timing is under the control of the logic level
on the NTSC_PAL pin.

When RESET is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7192. Output timing signals
are still suppressed at this stage. DACs A, B, C are switched off
and DACs D, E, F are switched on.

When the user requires valid data, Pixel Data Valid Control is
enabled (MR26 = 1) to allow the valid pixel data to pass through
the encoder. Digital output timing signals become active and the
encoder timing is now under the control of the Timing Regis­ters. If at this stage, the user wishes to select a different video
standard to that on the NTSC_PAL pin, Standard I

2

C Control
should be enabled (MR25 = 1) and the video standard required
is selected by programming Mode Register 0 (Output Video Stan­dard Selection). Figure 37 illustrates the RESET sequence timing.

–20–

REV. 0

RESET

ADV7192

DAC D,
DAC E

DAC F

DAC A,
DAC B,
DAC C

PIXEL_DATA_VALID

DIGITAL TIMING

MR26

COMPOSITE

e.g., VCR

OR CABLE

H/L TRANSITION

COUNT START

128

XXXXXXX XXXXXXX

XXXXXXX XXXXXXX

XXXXXXX

XXXXXXX

XXXXXXX

Figure 37.

VIDEO

LOW

VIDEO

DECODER

ADV7185

14 BITS

RESERVED

LCC1

P19–P12

MPEG

DECODER

4 BITS

RESERVED

BLACK VALUE WITH SYNC

BLACK VALUE

OFF

0

DIGITAL TIMING SIGNALS SUPPRESSED

RESET

Sequence Timing Diagram

CLOCK

M
U
X

SCRESET/RTC/TR

P7–P0

HSYNC
VSYNC

PLL INCREMENT

F

SC

GLL

21013

ADV7192

GREEN/ COMPOSITE/Y

BLUE/LUMA/U

RED/ CHROMA/V

GREEN/ COMPOSITE/Y

BLUE/LUMA/U

RED/ CHROMA/V

1

1

SEQUENCE

5 BITS

RESERVED

0

VALID VIDEO

VALID VIDEO

VALID VIDEO

TIMING ACTIVE

2

BIT

RESET

3

BIT

RESERVED

RTC

TIME SLOT: 01

NOTES:

1

FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7192 FSC DDS REGISTER IS FSC PLL INCREMENTS

BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE
SUBCARRIER FREQUENCY REGISTERS OF THE ADV7192.

2

SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE

3

RESET BIT
RESET ADV7192’s DDS

NOT USED IN

ADV7192

19

14

VALID

SAMPLE

INVALID
SAMPLE

8/ LINE

LOCKED CLOCK

Figure 38. RTC Timing and Connections

67 68

REV. 0

–21–