Analog Devices ADV7190 1 b Datasheet

Video Encoders with Six 10-Bit DACs and

a

FEATURES
Six High Quality 10-Bit Video DACs
Multistandard Video Input
Multistandard Video Output
4 Oversampling with Internal 54 MHz PLL
Programmable Video Control Includes:

Digital Noise Reduction
Gamma Correction
LUMA Delay

CHROMA Delay
Multiple Luma and Chroma Filters
Luma SSAF™ (Super Subalias Filter)
Average Brightness Detection
Field Counter
Macrovision Rev 7.1 (ADV7190 Only)
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface
Supply Voltage 5 V and 3.3 V Operation
64-Lead LQFP Package

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

54 MHz Oversampling

ADV7190/ADV7191

APPLICATIONS
DVD Playback Systems,
PC Video/Multimedia Playback Systems

GENERAL DESCRIPTION

The ADV7190/ADV7191 is part of the new generation of video
encoders from Analog Devices. The device builds on the perfor­mance of previous video encoders and provides new features such
as Digital Noise Reduction, Gamma Correction, 4¥ Oversam-
pling and 54 MHz operation, Average Brightness Detection,
Chroma Delay, an additional Chroma Filter, and so on.

The ADV7190/ADV7191 supports NTSC-M, NTSC-N (Japan),
PAL N, PAL M, PAL-B/D/G/H/I, and PAL-60 standards. Input
standards supported include ITU-R.BT656/601 4:2:2 YCrCb
in 8- or 16-bit format.

The ADV7190/ADV7191 can output Composite Video (CVBS),
S-Video (Y/C), Component YUV
component output is also compatible with Betacam, MII and
SMPTE/EBU N10 levels, SMPTE 170M NTSC, and ITU­R.BT 470 PAL.

For more information about the ADV7190/ADV7191’s features,
refer to Detailed Description.

1

, or RGB. The analog

Continued on page 11

*

DIGITAL

INPUT

27MHz

CLOCK

ITU–R.BT

656/601

8-BIT YCrCb

IN 4:2:2 FORMAT

*This device is protected by U.S. Patent Numbers 4631603, 4577216, and 4819098, and other intellectual property rights.

1

Throughout the document, YUV refers to digital or analog component video.
The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest available Macrovision version.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
SSAF is a trademark of Analog Devices Inc.
I2C is a registered trademark of Philips Corporation.

VIDEO
INPUT
PROCESSING

PLL

AND

54MHz

DEMUX

AND

YCrCb–

TO–

YUV

MATRIX

VIDEO
SIGNAL
PROCESSING

COLOR CONTROL
DNR
GAMMA
CORRECTION

VBI
TELETEXT
CLOSED CAPTION
CGMS/WSS
MACROVISION

CHROMA
LPF

SSAF
LPF

LUMA
LPF

I2C INTERFACE

VIDEO
OUTPUT
PROCESSING

2

OVERSAMPLING

OR

4

OVERSAMPLING

ADV7190/ADV7191

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

ANALOG
OUTPUT

COMPOSITE VIDEO
Y [S-VIDEO]
C [S-VIDEO]
RGB
YUV

TVSCREEN

REV.B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADV7190/ADV7191

CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS

5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 V DYNAMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.3 V DYNAMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 V TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . 6

3.3 V TIMING CHARACTERISTICS . . . . . . . . . . . . . . .. 7

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9

PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10

DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 11

DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12

INTERNAL FILTER RESPONSE.. . . . . . . . . . . . . . . . . . . 13

FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17

Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chroma/Luma Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clamp Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CSO, HSO, and VSO Outputs . . . . . . . . . . . . . . . . . . . . . 17

Color Bar Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Color Burst Signal Control . . . . . . . . . . . . . . . . . . . . . . . 17

Color Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chrominance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Gamma Correction Control . . . . . . . . . . . . . . . . . . . . . . . 18

NTSC Pedestal Control . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Real-Time Control, Subcarrier Reset,

and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SCH Phase Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Square Pixel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Vertical Blanking Data Insertion And BLANK Input . . . . 19

YUV Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

16-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4¥ Oversampling and Internal PLL . . . . . . . . . . . . . . . . . 19

VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 19

RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 27

REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 28

MODE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

TIMING REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SUBCARRIER FREQUENCY AND

PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 36

NTSC PEDESTAL REGISTERS . . . . . . . . . . . . . . . . . . . . 37

TELETEXT REQUEST CONTROL REGISTER . . . . . . 37

CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 37

CONTRAST CONTROL REGISTER . . . . . . . . . . . . . . . . 38

COLOR CONTROL REGISTERS . . . . . . . . . . . . . . . . . . 38

HUE ADJUST CONTROL REGISTER . . . . . . . . . . . . . . 39

BRIGHTNESS CONTROL REGISTERS . . . . . . . . . . . . . 39

SHARPNESS CONTROL REGISTER . . . . . . . . . . . . . . . 40

DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 42

BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 43

OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX 1

BOARD DESIGN AND LAYOUT

CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44

APPENDIX 2

CLOSED CAPTIONING . . . . . . . . . . . . . . . . . . . . . . . . 46

APPENDIX 3

COPY GENERATION MANAGEMENT

SYSTEM (CGMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

APPENDIX 4

WISE SCREEN SIGNALING (WSS) . . . . . . . . . . . . . . . 48

APPENDIX 5

TELETEXT INSERTION . . . . . . . . . . . . . . . . . . . . . . . 49

APPENDIX 6

OPTIONAL OUTPUT FILTER . . . . . . . . . . . . . . . . . . 50

APPENDIX 7

DAC BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

APPENDIX 8

RECOMMENDED REGISTER VALUES . . . . . . . . . . . 52

APPENDIX 9

NTSC WAVEFORMS (WITH PEDESTAL) . . . . . . . . . 56

NTSC WAVEFORMS (WITHOUT PEDESTAL) . . . . . 57

PAL WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

UV WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . 60

VIDEO MEASUREMENT PLOTS . . . . . . . . . . . . . . . . 64

APPENDIX 10

VECTOR PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 69

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

–2–

REV. B

ADV7190/ADV7191

SPECIFICATIONS

(VAA = 5 V, V

5 V SPECIFICATIONS

1

unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity

3

3

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INH

INL

IN

IN

Input Leakage Current 1 mA

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OH

OL

Three-State Leakage Current 10 mA
Three-State Output Capacitance 6 10 pF

ANALOG OUTPUTS

Output Current (Max) 4.125 4.33 4.625 mA RL = 300 W, R
Output Current (Min) 2.16 mA R
DAC-to-DAC Matching
Output Compliance, V
Output Impedance, R
Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

3

OC

OUT

OUT

4

REF

POWER REQUIREMENTS

V

AA

Normal Power Mode

5

I

DAC

I

(2¥ Oversampling)

CCT

I

(4¥ Oversampling)

CCT

I

PLL

6, 7

6, 7

Sleep Mode

I

DAC

I

CCT

NOTES

1

All measurements are made in 4¥ Oversampling Mode unless otherwise specified.

2

Temperature range T

3

Guaranteed by characterization.

4

Measurement made in 2¥ oversampling mode.

5

I

is the total current required to supply all DACs including the V

DAC

6

All six DACs ON.

7

I

, or the circuit current, is the continuous current required to drive the digital core without I

CCT

Specifications subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

= 1.235 V, R

REF

= 1200 , unless otherwise noted. All specifications T

SET1,2

± 1.0 LSB
± 1.0 LSB Guaranteed Monotonic

2V

0.8 V

0 ± 1 mAV

= 0.4 V or 2.4 V

IN

610 pF

2.4 V I

0.8 0.4 V I

= 400 mA

SOURCE

= 3.2 mA

SINK

= 600 W, R

L

SET1,2

SET1,2

0.4 2.5 %

0 1.4 V

100 kW
6pFI

OUT

= 0 mA

1.112 1.235 1.359 V

4.75 5.0 5.25 V

29 35 mA
80 120 mA
120 170 mA
610 mA

0.01 mA
85 mA

circuitry.

REF

.

PLL

to T

MIN

= 1200 W
= 2400 W

MAX

2

,

REV. B

–3–

ADV7190/ADV7191–SPECIFICATIONS

(

3.3 V SPECIFICATIONS

VAA = 3.3 V, V

1

unless otherwise noted.)

= 1.235 V, R

REF

= 1200 , unless otherwise noted. All specifications T

SET1,2

MIN

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity ± 1.0 LSB
Differential Nonlinearity ± 1.0 LSB Guaranteed Monotonic

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

2V

0.8 V
± 1 mAV

= 0.4 V or 2.4 V

IN

610pF

Input Leakage Current 1 mA

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

2.4 V I

0.4 V I

SOURCE

= 3.2 mA

SINK

= 400 mA

Three-State Leakage Current 10 mA
Three-State Output Capacitance 6 10 pF

ANALOG OUTPUTS

Output Current (Max) 4.25 4.33 4.625 mA R
Output Current (Min) 2.16 mA R

= 1200 W, RL = 300 W

SET1,2

= 600 W, R

L

SET1,2

DAC-to-DAC Matching 0.4 %
Output Compliance, V
Output Impedance, R

OC

OUT

Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

REF

OUT

3

100 kW
630pFI

1.235 V I

1.4 V

= 0 mA

OUT

VREFOUT

= 20 mA

POWER REQUIREMENTS

V

AA

Normal Power Mode

4

I

DAC

I

(2¥ Oversampling)

CCT

I

(4¥ Oversampling)

CCT

I

PLL

5, 6

5, 6

3.15 3.3 3.45 V

29 mA
42 54 mA
68 86 mA
6mA

Sleep Mode

I

DAC

I

CCT

NOTES

1

All measurements are made in 4¥ Oversampling Mode unless otherwise specified and are guaranteed by characterization. In 2 ¥ Oversampling Mode, the power re­quirement for the ADV7190/ADV7191 are typically 3.0 V.

2

Temperature range T

3

Measurement made in 2¥ oversampling mode.

4

I

is the total current required to supply all DACs including the V

DAC

5

All six DACs ON.

6

I

, or the circuit current, is the continuous current required to drive the digital core without I

CCT

Specifications subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

0.01 mA

85 mA

circuitry.

REF

.

PLL

2

to T

MAX

= 2400 W

,

–4–

REV. B

ADV7190/ADV7191

(VAA = 5 V  250 mV, V

1

5 V DYNAMIC–SPECIFICATIONS

specifications T

MIN

Parameter Min Typ Max Unit Test Conditions

Differential Gain
Differential Phase
SNR (Pedestal)

SNR (Ramp)

3

3

3

3

61.7 (61.7) dB rms RMS

0.1 (0.4) 0.3 (0.5) %

0.4 (0.15) 0.5 (0.3) Degrees

78.5 (78) dB rms RMS
78 (78) dB p-p Peak Periodic

62 (63) dB p-p Peak Periodic
Hue Accuracy 0.5 Degrees
Color Saturation Accuracy 0.7 %
Chroma Nonlinear Gain 0.7 0.9 ± %Referenced to 40 IRE
Chroma Nonlinear Phase 0.5 ±Degrees
Chroma/Luma Intermod 0.1 ± %
Chroma/Luma Gain Ineq 1.7 ± %
Chroma/Luma Delay Ineq 2.2 ns
Luminance Nonlinearity 0.6 0.7 ± %
Chroma AM Noise 82 dB
Chroma PM Noise 72 dB

NOTES

1

All measurements are made in 4¥ Oversampling Mode unless otherwise specified.

2

Temperature range T

3

Values in parentheses apply to 2¥ Oversampling Mode.

Specifications subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

= 1.235 V, R

REF

2

to T

, unless otherwise noted.)

MAX

= 1200 , unless otherwise noted. All

SET1,2

3.3 V DYNAMIC–SPECIFICATIONS

(VAA = 3.3 V  150 mV, V

1

specifications T

MIN

to T

= 1.235 V, R

REF

2

, unless otherwise noted.)

MAX

SET1,2

= 1200 , unless otherwise noted. All

Parameter Min Typ Max Unit Test Conditions

Differential Gain
Differential Phase
SNR (Pedestal)

SNR (Ramp)

3

3

3

3

62.3 (62) dB rms RMS

0.2 (0.5) %

0.5 (0.2) Degrees

78.5 (78) dB rms RMS
78 (78) dB p-p Peak Periodic

61 (62.5) dB p-p Peak Periodic
Hue Accuracy 0.5 Degrees
Color Saturation Accuracy 0.8 %
Chroma Nonlinear Gain 0.6 ±%Referenced to 40 IRE
Chroma Nonlinear Phase 0.5 ±Degrees
Chroma/Luma Intermod 0.1 ± %
Luminance Nonlinearity 0.6 ±%
Chroma AM Noise 83 dB
Chroma PM Noise 71 dB

NOTES

1

All measurements are made in 4¥ Oversampling Mode unless otherwise specified.

2

Temperature range T

3

Values in parentheses apply to 2¥ Oversample Mode.

Specifications subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

REV. B

–5–

ADV7190/ADV7191

5 V TIMING CHARACTERISTICS

(VAA = 5 V  250 mV, V
T

MIN

1

to T

, unless otherwise noted.)

MAX

= 1.235 V, R

REF

= 1200 , unless otherwise noted. All specifications

SET1,2

Parameter Min Typ Max Unit Test Conditions

MPU PORT

2

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

ANALOG OUTPUTS

2

1

2

3

4

6

7

8

0.6 ms

1.3 ms

0.6 ms

After This Period, the First Clock is Generated

0.6 msRelevant for Repeated Start Condition
100 ns

300 ns
300 ns

0.6 ms

Analog Output Delay 8 ns
DAC Analog Output Skew 0.1 ns

CLOCK CONTROL AND PIXEL PORT

f

CLOCK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t

9

10

11

12

11

12

13

(2¥ Oversampling) 57 Clock Cycles

15

14

3

27 MHz
8ns
8ns
6ns
5ns
6ns
4ns

13 ns

12 ns

Pipeline Delay, t15 (4¥ Oversampling) 67 Clock Cycles

TELETEXT PORT

Digital Output Access Time, t
Data Setup Time, t
Data Hold Time, t

4

16

17

18

11 ns

3ns

6ns

RESET CONTROL

RESET Low Time 3 20 ns

2

PLL

PLL Output Frequency 54 MHz

NOTES

1

Temperature range T

2

Guaranteed by characterization.

3

Pixel Port consists of:
Data: P15–P0 Pixel Inputs,
Control: HSYNC, VSYNC, BLANK,
Clock: CLKIN Input.

4

Teletext Port consists of:
Digital Output: TTXREQ,
Data: TTX.

Specifications subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

–6–

REV. B

ADV7190/ADV7191

3.3 V TIMING CHARACTERISTICS

(VAA = 3.3 V  150 mV, V
specifications T

MIN

to T

= 1.235 V, R

REF

1

, unless otherwise noted2.)

MAX

SET1,2

= 1200 , unless otherwise noted. All

Parameter Min Typ Max Unit Test Conditions

MPU PORT

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

1

2

3

4

6

7

8

0.6 ms

1.3 ms

0.6 msAfter This Period, the First Clock is Generated

0.6 msRelevant for Repeated Start Condition
100 ns

300 ns
300 ns

0.6 2 ms

ANALOG OUTPUTS

Analog Output Delay 8 ns
DAC Analog Output Skew 0.1 ns

CLOCK CONTROL AND PIXEL PORT

f

CLOCK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t

9

10

11

12

11

12

13

(2¥ Oversampling) 57 Clock Cycles

15

14

3

27 MHz
8ns
8ns
6ns
4ns

2.5 ns
3ns

13 ns

12 ns

Pipeline Delay, t15 (4¥ Oversampling) 67 Clock Cycles

TELETEXT PORT

Digital Output Access Time, t
Data Setup Time, t
Data Hold Time, t

4

16

17

18

11 ns

3ns

6ns

RESET CONTROL

RESET Low Time 3 20 ns

PLL

PLL Output Frequency 54 MHz

NOTES

1

Temperature range T

2

Guaranteed by characterization.

3

Pixel Port consists of:
Data: P15–P0 Pixel Inputs,
Control: HSYNC, VSYNC , BLANK,
Clock: CLKIN Input.

4

Teletext Port consists of:
Digital Output: TTXREQ,
Data: TTX.

Specifications subject to change without notice.

MIN

to T

: 0∞C to 70∞C.

MAX

REV. B

–7–

ADV7190/ADV7191

SDA

SCL

CLOCK

t

t

3

t

6

t

2

5

t

1

t

7

Figure 1. MPU Port Timing Diagram

t

3

t

4

t

8

TTXREQ

CLOCK

TTX

CONTROL

CONTROL

t

16

I/PS

O/PS

HSYNC,
VSYNC,

BLANK

PIXEL INPUT

DATA

HSYNC,

VSYNC,

BLANK,

CSO_HSO,

VSO, CLAMP

t

17

t

4 CLOCK

CYCLES

t

t

9

10

Cb Y Cr Y Cb Y

t

12

t

11

t

13

t

14

Figure 2. Pixel and Control Data Timing Diagram

18

4 CLOCK

CYCLES

4 CLOCK

CYCLES

Figure 3. Teletext Timing Diagram

3 CLOCK

CYCLES

4 CLOCK

CYCLES

–8–

REV. B

ADV7190/ADV7191

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Input Pin . . . . GND – 0.5 V to V

Storage Temperature (T
Junction Temperature (T

) . . . . . . . . . . . . . . –65∞C to +150∞C

S

) . . . . . . . . . . . . . . . . . . . . . 150∞C

J

+ 0.5 V

AA

Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . 220∞C

Analog Outputs to GND2 . . . . . . . . . . . . GND – 0.5 to V

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Analog output short circuit to any power supply or common can be of an indefinite

duration.

AA

PIN CONFIGURATION

AA

V

NC

NC

AGND

64 63 62 61 60 55 54 53 52 51 50 4959 58 57 56

1

P0
P1

P2

P3
P4

P5

P6
P7

P8
P9

P10

P11
P12

P13

P14
P15

NC = NO CONNECT

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AA

V

AGND

VSYNC

HSYNC

NC

NC

NC

NC

ADV7190/ADV7191

LQFP

TOP VIEW

(Not to Scale)

ALSB

AGND

BLANK

TTXREQ

PACKAGE THERMAL PERFORMANCE

The 64-lead package is used for this device. The junction-to­ambient (q

) thermal resistance in still air on a four-layer PCB

JA

is 38∞C/W.

To reduce power consumption when using this part, the user can
run the part on a 3.3 V supply, and turn off any unused DACs.

The user must at all times stay below the maximum junction
temperature of 110∞C. The following equation shows how to
calculate this junction temperature:

Junction Temperature = (V

I

= 10 mA + (sum of the average currents consumed by

DAC

AA

¥ (I

DAC

+ I

)) ¥ qJA + 70∞C T

CCT

AMB

each powered-on DAC)

Average current consumed by each powered-on DAC =

(V

¥ K )/R

REF

V

REF

= 1.235 V

SET

K = 4.2146

NTSC

AA

VSO/CLAMP

V

TTX

AA

V

AGND

AGND

CLKIN

NC

CLKOUT

PAL

AA

V

SCL

RESET

CSO_HSO

R

48

SET1

V

47

REF

46

COMP 1

45

DAC A

44

DAC B
V

43

AA

42

AGND

41

DAC C

40

DAC D

39

AGND

38

V

AA

37

DAC E

36

DAC F

35

COMP 2

34

R

SET2

33

AGND

SDA

SCRESET/RTC/TR

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7190KST 0∞C to 70∞C 64-Lead Quad Flatpack ST-64
ADV7191KST 0∞C to 70∞C 64-Lead Quad Flatpack ST-64

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7190/ADV7191 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–9–

ADV7190/ADV7191

PIN FUNCTION DESCRIPTIONS

Pin Input/
No. Mnemonic Output Function

1–16 P0–P15 I 8-Bit or 16-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on

Pin P0.

17, 25, 29, V

AA

38, 43, 54,
63

18, 24, 26, AGND G Analog Ground.
33, 39, 42,
55, 64

19 HSYNC I/O HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output

20 VSYNC I/O VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an

21 BLANK I/O Video Blanking Control Signal. This signal is optional. For further information see Vertical

22 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.
23 TTXREQ O Teletext Data Request Output Signal, used to control teletext data transfer.
27 CLKIN I TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alterna-

28 CLKOUT O Clock Output Pin.
30 SCL I MPU Port Serial Interface Clock Input.
31 SDA I/O MPU Port Serial Data Input/Output.
32 SCRESET/ I Multifunctional Input: Real-Time Control (RTC) Input, Timing Reset Input, Subcarrier Reset

RTC/TR Input.

34 R

SET2

35 COMP 2 O Compensation Pin for DACs D, E, and F. Connect a 0.1 mF Capacitor from COMP2 to V
36 DAC F O S-Video C/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
37 DAC E O S-Video Y/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
40 DAC D O Composite/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.
41 DAC C O S-Video C/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
44 DAC B O S-Video Y/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
45 DAC A O Composite/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.
46 COMP 1 O Compensation Pin for DACs A, B, and C. Connect a 0.1 mF Capacitor from COMP1 to V
47 V

48 R

REF

SET1

49 RESET IThe input resets the on-chip timing generator and sets the ADV7190/ADV7191 into default

50 CSO_HSO ODual Function CSO or HSO Output Sync Signal at TTL Level.
51 VSO/CLAMP I/O Multifunction Pin. VSO Output Sync Signal at TTL level. CLAMP TTL Output Signals

52 PAL_NTSC I Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL.
53, 57–62 NC No Connect.
56 TTX I Teletext Data Input Pin.

PAnalog Power Supply (3.3 V to 5 V).

(Master Mode) or an input (Slave Mode) and accept Sync Signals.

input (Slave Mode) and accept VSYNC as a Control Signal.

Blanking Data Insertion and BLANK Input section.

tively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.

IA 1200 W resistor connected from this pin to ground is used to control full-scale amplitudes

of the Video Signals from DACs D, E, and F.

.

AA

.

AA

I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external

V

cannot be used in 4¥ oversampling mode.

REF

IA 1200 W resistor connected from this pin to ground is used to control full-scale amplitudes

of the Video Signals from DACs A, B, and C.

mode. See Appendix 8 for Default Register settings.

can be used to drive external circuitry to enable clamping of all Video Signals.

–10–

REV. B

ADV7190/ADV7191

DETAILED DESCRIPTION OF FEATURES
Clocking:

Single 27 MHz Clock Required to Run the Device
4 Oversampling with Internal 54 MHz PLL

Square Pixel Operation
Advanced Power Management
Programmable Video Control Features:

Digital Noise Reduction

Pedestal level

Hue, Brightness, Contrast and Saturation

Clamping Output Signal

VBI (Vertical Blanking Interval)

Subcarrier Frequency and Phase

LUMA Delay

CHROMA Delay

Gamma Correction

Luma and Chroma Filters

Luma SSAF (Super Subalias Filter)
Average Brightness Detection
Field Counter
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Macrovision 7.1 Rev (ADV7190 Only)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface

2

C Registers Synchronized to VSYNC

I

(continued from page 1)

GENERAL DESCRIPTION

The ADV7190/ADV7191 is an integrated Digital Video Encoder
that converts digital CCIR-601/656 4:2:2 8-bit or 16-bit com­ponent video data into a standard analog baseband television
signal compatible with worldwide standards.

Six DACs are available on the ADV7190/ADV7191, each of which
is capable of providing 4.33 mA of current. In addition to the
composite output signal there is the facility to output S-Video
(Y/C Video), RGB Video and YUV Video. All YUV formats
(Betacam, MII and (SMPTE/EBU N10) are supported.

Digital Noise Reduction allows improved picture quality in remov­ing low amplitude, high frequency noise. The block diagram below
shows the DNR functionality in the two modes available.

DNR MODE

Y DATA

INPUT

DNR CONTROL

BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

FILTER OUTPUT

<THRESHOLD?

FILTER OUTPUT>

THRESHOLD

GAIN

CORING GAIN DATA
CORING GAIN BORDER

SUBTRACT SIGNAL IN THRESHOLD
RANGE FROM ORIGINAL SIGNAL

DNR OUT

DNR SHARPNESS MODE

Y DATA

INPUT

DNR CONTROL

BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

FILTER OUTPUT

>THRESHOLD?

FILTER OUTPUT<

THRESHOLD

GAIN

CORING GAIN DATA
CORING GAIN BORDER

ADD SIGNAL ABOVE THRESHOLD
RANGE TO ORIGINAL SIGNAL

DNR OUT

Figure 5. Block Diagram for DNR Mode and DNR Sharpness
Mode

HSYNC

VSYNC

BLANK

RESET

TTXREQ

CLKIN

CLKOUT

REV. B

TTX

P15

PAL_NTSC

YCrCb

YUV

MATRIX

10 1010

P0

DEMUX

VSO/CLAMP

VIDEO TIMING

GENERATOR

TELETEXT

INSERTION

10

Y

TO

10

U

10

V

BLOCK

CORRECTION

PLL

DNR
AND

GAMMA

CSO_HSO

CLOSED CAPTIONING

BRIGHTNESS

CONTROL

ADD SYNC

10

INTERPOLATOR

Y

10

SATURATION

U

CONTROL

10

V

ADD BURST

INTERPOLATOR

ADV7190/ADV7191

CGMS/WSS

AND

CONTROL

AND

AND

AND

AND

I2C MPU PORT

PROGRAMMABLE

LUMA FILTER

AND

SHARPNESS

FILTER

PROGRAMMABLE

CHROMA

FILTER

REAL-TIME

CONTROL

CIRCUIT

SCRESET/RTC/TR

ALSBSDASCL

MODULATOR

HUE CONTROL

YUV-TO-RGB

MATRIX

AND

YUV LEVEL

CONTROL

BLOCK

AND

SIN/COS

DDS

BLOCK

M
U
L
T

I
P
L
E
X
E
R

I

10-BIT

N

DAC

T
E

10-BIT

R

DAC

P
O

10-BIT

L

DAC
A
T
O
R

DAC

CONTROL

BLOCK

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

DAC

CONTROL

BLOCK

I
N
T
E
R
P
O
L
A
T
O
R

DAC A

DAC B

DAC C

V

REF

R

SET2

COMP2

DAC D

DAC F

DAC E

R

SET1

COMP1

Figure 4. Detailed Functional Block Diagram

–11–

ADV7190/ADV7191

Programmable gamma correction is also available. Figure 6 shows
the response of different gamma values to a ramp signal.

300

GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT FOR VARIOUS GAMMA VALUES

250

200

150

100

50

GAMMA–CORRECTED AMPLITUDE

0

050100 150 200 250

SIGNAL OUTPUTS

0.3

0.5

1.5

SIGNAL INPUT

LOCATION

1.8

Figure 6. Signal Input (Ramp) and Selectable Gamma
Output Curves

The on-board SSAF (Super Subalias Filter) with extended
luminance frequency response and sharp stopband attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness
control feature allows high-frequency enhancement on the lumi­nance signal.

The device is driven by a 27 MHz clock. Data can be output at
27 MHz or 54 MHz (on-board PLL) when 4
enabled. Also, the output filter requirements in 4

⫻

oversampling is

⫻

oversampling

and 2⫻ oversampling differ, as can be seen in Figure 7.

0dB

–30dB

2 FILTER
REQUIREMENTS

4 FILTER
REQUIREMENTS

6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz

Figure 7. Output Filter Requirements in 4¥Oversampling
Mode

54MHz

2



6

I

D

N

A

T

C

E
R
P
O
L
A
T

I
O
N

54MHz

O

OUTPUT

U

RATE

T
P
U
T
S

MPEG2

PIXEL BUS

27MHz

ADV7190/ADV7191

ENCODER

CORE

PLL

Figure 8. PLL and 4¥ Oversampling Block Diagram

The ADV7190/ADV7191 also supports both PAL and NTSC
square pixel operation. In this case the encoder requires a

24.5454 MHz Clock for NTSC or 29.5 MHz Clock for PAL
square pixel mode operation. All internal timing is generated
on-chip.

An advanced power management circuit enables optimal control
of power consumption in normal operating modes or sleep modes.

The Output Video Frames are synchronized with the incoming
data Timing Reference Codes. Optionally, the Encoder accepts
(and can generate) HSYNC, VSYNC, and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in master mode.

HSO/CSO and VSO TTL outputs are also available and are timed
to the analog output video.

A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.

The ADV7190/ADV7191 also incorporates WSS and CGMS-A
data control generation. The ADV7190 incorporates Macrovision
Rev 7.1.

The ADV7190/ADV7191 modes are set up over a 2-wire
serial bidirectional port (I

2

C-compatible) with two slave
addresses, and the device is register-compatible with the
ADV7172/ADV7173.

The ADV7190ADV7191 is packaged in a 64-lead LQFP
package.

DATA PATH DESCRIPTION

For PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb
4:2:2 Data is input via the CCIR-656/601-compatible Pixel
Port at a 27 MHz data rate. The pixel data is demultiplexed to
form three data paths. Y typically has a range of 16 to 235, Cr
and Cb typically have a range of 128+/–112; however, it is
possible to input data from 1 to 254 on both Y, Cb, and Cr.
The ADV7190/ADV7191 supports PAL (B, D, G, H, I, N) and
NTSC M, N (with and without Pedestal) PAL.M (ADV7190
only) and PAL60 standards. Digital Noise Reduction can be
applied to the Y signal. Programmable gamma correction can also
be applied to the Y signal if required.

The Y data can be manipulated for contrast control and a set-up
level can be added for brightness control. The Cr, Cb data can
be scaled to achieve color saturation control. All settings become
effective at the start of the next field when double buffering is
enabled.

The appropriate sync, blank, and burst levels are added to the
YCrCb data. Macrovision antitaping, (ADV7190 only) Closed­Captioning, and Teletext levels are also added to Y and the
resultant data is interpolated to 54 MHz when 4¥ Oversampling
is enabled. The interpolated data is filtered and scaled by three
digital FIR filters.

The U and V signals are modulated by the appropriate Subcarrier
Sine/Cosine waveforms and a phase offset may be added onto
the color subcarrier during active video to allow hue adjustment.
The resulting U and V signals are added together to make up
the Chrominance Signal. The Luma (Y) signal can be delayed
by up to six clock cycles (at 27 MHz) and the Chroma signal
can be delayed by up to eight clock cycles (at 27 MHz). The

–12–

REV. B

ADV7190/ADV7191

Luma and Chroma Signals are added together to make up the
Composite Video Signal. All timing signals are controlled.

The YCrCb data is also used to generate RGB data with appropri­ate sync and blank levels. The YUV levels are scaled to output
the suitable SMPTE/EBU N10, MII, or Betacam levels.

Each DAC can be individually powered off if not required. A
complete description of DAC output configurations is given in
the MR2 Bit Description section.

Video output levels are illustrated in Appendix 9.

Table I. Luminance Internal Filter Specifications (4 Oversampling)

Filter Type Filter Selection Ripple1 (dB) (MHz)

MR04 MR03 MR02

Low-Pass (NTSC) 0 0 0 0.16 4.24
Low-Pass (PAL) 0 0 1 0.1 4.81
Notch (NTSC) 0 1 0 0.09 2.3/4.9/6.6
Notch (PAL) 0 1 1 0.1 3.1/5.6/6.4
Extended (SSAF) 1 0 0 0.04 6.45
CIF 1 0 1 0.127 3.02
QCIF 1 1 0 Monotonic 1.5

NOTES

1

Passband ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). The
passband is defined to have 0-fc frequency limits for a low-pass filter, 0–f1 and f2–infinity for a notch filter,
where fc, f1, f2 are the –3 dB points.

2

3 dB bandwidth refers to the –3 dB cutoff frequency.

INTERNAL FILTER RESPONSE

The Y Filter supports several different frequency responses
including two low-pass responses, two notch responses, an
Extended (SSAF) response with or without gain boost/attenuation,
a CIF response and a QCIF response. The UV Filter supports
several different frequency responses including five low-pass
responses, a CIF response and a QCIF response, as can be seen on
the following pages.

In Extended Mode there is the option of twelve responses in
the range from –4 dB to +4 dB. The desired response can be
chosen by the user by programming the correct value via the
I2C. The variation of frequency responses can be seen on the
following pages. For more detailed plots refer to AN-562
Analog Devices’ Application note.

Passband 3 dB Bandwidth

2

Table II. Chrominance Internal Filter Specifications (4 Oversampling)

Passband 3 dB Bandwidth

2

Filter Type Filter Selection Ripple1 (dB) (MHz)

MR07 MR06 MR05

1.3 MHz Low-Pass 0 0 0 0.09 1.395

0.65 MHz Low-Pass 0 0 1 Monotonic 0.65

1.0 MHz Low-Pass 0 1 0 Monotonic 1.0

2.0 MHz Low-Pass 0 1 1 0.048 2.2

3.0 MHz Low-Pass 1 1 1 Monotonic 3.2
CIF 1 0 1 Monotonic 0.65
QCIF 1 1 0 Monotonic 0.5

NOTES

1

Passband ripple is defined to be fluctuations from the 0 dB response in the passband, measured in (dB). The
passband is defined to have 0-fc frequency limits for a low-pass filter, 0–f1 and f2–infinity for a notch filter,
where fc, f1, f2 are the –3 dB points.

2

3 dB bandwidth refers to the –3 dB cutoff frequency.

REV. B

–13–

ADV7190/ADV7191

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

0

68

FREQUENCY – MHz

Figure 9. NTSC Low-Pass Luma Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

12

–70

24 10

0

68

FREQUENCY – MHz

12

Figure 12. NTSC Notch Luma Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

0

68

FREQUENCY – MHz

Figure 10. PAL Low-Pass Luma Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

0

68

FREQUENCY – MHz

Figure 11. Extended Mode (SSAF) Luma Filter

–60

12

–70

24 10

0

68

FREQUENCY – MHz

12

Figure 13. PAL Notch Luma Filter

5

4

3

2

MAGNITUDE – dB

1

0

12

–1

0

12

FREQUENCY – MHz

4

6

5

73

Figure 14. Extended SSAF and Programmable Gain,
Showing Range 0 dB/+4 dB Range

–14–

REV. B

ADV7190/ADV7191

1

0

–1

–2

MAGNITUDE – dB

–3

–4

–5

0

12

FREQUENCY – MHz

4

6

5

Figure 15. Extended SSAF and Programmable
Attenuation, Showing Range 0 dB/–4 dB

4

2

0

–2

–4

–6

MAGNITUDE – dB

–8

–10

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

73

0

24 10

68

FREQUENCY – MHz

12

Figure 18. QCIF Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–12

0

12

FREQUENCY – MHz

4

6

5

Figure 16. Extended SSAF and Programmable
Attenuation, Showing Range +4 dB/–12 dB

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

0

68

FREQUENCY – MHz

12

Figure 17. Luma CIF Filter

73

–70

0

24 10

68

FREQUENCY – MHz

12

Figure 19. Chroma 0.65 MHz Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

24 10

0

68

FREQUENCY – MHz

12

Figure 20. Chroma 1.0 MHz Low-Pass Filter

REV. B

–15–

ADV7190/ADV7191

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

24 10

68

FREQUENCY – MHz

Figure 21. Chroma 1.3 MHz Low-Pass Filter

0

–10

–20

–30

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

12

–70

24 10

0

68

FREQUENCY – MHz

12

Figure 24. Chroma CIF Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

24 10

68

FREQUENCY – MHz

Figure 22. Chroma 2 MHz Low-Pass Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

24 10

68

FREQUENCY – MHz

–40

MAGNITUDE – dB

–50

–60

12

–70

24 10

0

68

FREQUENCY – MHz

12

Figure 25. Chroma QCIF Filter

12

Figure 23. Chroma 3 MHz Low-Pass Filter

–16–

REV. B

ADV7190/ADV7191

FEATURES: FUNCTIONAL DESCRIPTION
Brightness Detect

This feature is used to monitor the average brightness of the
incoming Y signal on a field-by-field basis. The information is
read from the I

2

C and based on this information, the color
saturation, contrast and brightness controls can be adjusted (for
example to compensate for very dark pictures). (Brightness Detect
Register.)

Chroma/Luma Delay

The luminance data can be delayed by maximum of six clock
cycles. Additionally the Chroma can be delayed by a maximum
of eight clock cycles (one clock cycle at 27 MHz). (Timing
Register 0 and Mode Register 9.)

CHROMA DELAY

LUMA DELAY

Figure 26. Chroma Delay Figure 27. Luma Delay

Clamp Output

The ADV7190/ADV7191 has a programmable clamp TTL
output signal. This clamp signal is programmable to the front
and back porch. The clamp signal can be varied by one to
three clock cycles in a positive and negative direction from the
default position. (Mode Register 5, Mode Register 7.)

CLAMP O/P SIGNALS

CVBS
OUTPUT PIN

MR57 = 1

MR57 = 0

CLAMP
OUTPUT PIN

Figure 28. Clamp Output Timing

CSO, HSO, and VSO Outputs

The ADV7190/ADV7191 supports three output timing sig­nals, CSO (Composite Sync Signal), HSO (Horizontal Sync
Signal) and VSO (Vertical Sync Signal). These output TTL sig­nals are aligned with the analog video outputs. See Figure 29 for
an example of these waveforms. (Mode Register 7.)

EXAMPLE:- NTSC

OUTPUT

525 1 234567891011–19

VIDEO

CSO

HSO

VSO

Figure 29.

CSO, HSO, VSO

Timing Diagram

Color Bar Generation

The ADV7190/ADV7191 can be configured to generate 100/

7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for
PAL. (Mode Register 4.)

Color Burst Signal Control

The burst information can be switched on and off the composite
and chroma video output. (Mode Register 4.)

Color Controls

The ADV7190/ADV7191 allows the user to control the brightness,
contrast, hue, and saturation of the color. The control regis­ters may be double-buffered, meaning that any modification to
the registers will be done outside the active video region and,
therefore, changes made will not be visible during active video.

Contrast Control

Contrast adjustment is achieved by scaling the Y input data by a
factor programmed by the user. This factor allows the data to be
scaled between 0% and 150%. (Contrast Control Register.)

Brightness Control

The brightness is controlled by adding a programmable setup level
onto the scaled Y data.

For NTSC with pedestal, the setup can vary from 0 IRE to

22.5 IRE. For NTSC without pedestal and PAL, the setup can
vary from –7.5 IRE to +15 IRE. (Brightness Control Register.)

Color Saturation

Color adjustment is achieved by scaling the Cr and Cb input
data by a factor programmed by the user. This factor allows the
data to be scaled between 0% and 200%. (U Scale Register and
V Scale Register.)

Hue Adjust Control

The hue adjustment is achieved on the composite and chroma
outputs by adding a phase offset onto the color subcarrier in the
active video but leaving the color burst unmodified, i.e., only
the phase between the video and the colorburst is modified and
thus the hue is shifted. The ADV7190/ADV7191 provides a
range of ± 22∞ in increments of 0.17578125∞. (Hue Adjust
Register.)

Chrominance Control

The color information can be switched on and off the com­posite, chroma and color component video outputs. (Mode
Register 4.)

Undershoot Limiter

A limiter is placed after the digital filters. This prevents any
synchronization problems for TVs. The level of undershoot is
programmable between –1.5 IRE, –6 IRE, –11 IRE when operat­ing in 4¥ Oversampling. In 2¥ Oversampling mode the limits are
–7.5 IRE and 0 IRE. (Mode Register 9 and Timing Register 0.)

Digital Noise Reduction

DNR is applied to the Y data only. A filter block selects the
high frequency, low amplitude components of the incoming
signal (DNR Input Select). The absolute value of the filter output
is compared to a programmable threshold value (DNR Thresh­old Control).

Two DNR modes are available: DNR Mode and DNR Sharp­ness Mode.

REV. B

–17–

ADV7190/ADV7191

In DNR Mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (Coring Gain Control) of this noise signal will be sub­tracted from the original signal.

In DNR Sharpness Mode, if the absolute value of the filter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (Coring
Gain Control) will be added to the original signal in order to boost
high frequency components and to sharpen the video image.

In MPEG systems it is common to process the video information
in blocks of 8 ¥ 8 pixels for MPEG2 systems, or 16 ¥ 16 pixels for
MPEG1 systems (Block Size Control). DNR can be applied to
the resulting block transition areas that are known to contain
noise. Generally the block transition area contains two pixels.
It is possible to define this area to contain four pixels (Border
Area Control).

It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the (Block Offset
Control). See Figure 82 for further information. (Mode Register 8,
DNR Registers 0–2.)

Double Buffering

Double buffering can be enabled or disabled on the following
registers: Closed Captioning Registers, Brightness Control,
V Scale, U Scale, Contrast Control, Hue Adjust, the Gamma
Curve Select bit, and Macrovision Registers (ADV7190 only).
These registers are updated once per field on the falling edge of
the VSYNC signal. Double buffering improves the overall
performance of the ADV7190/ADV7191, since modifications to
register settings will not be made during active video, but
take effect on the start of the active video. (Mode Register 8.)

Gamma Correction Control

Gamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if
gamma correction is enabled. Gamma correction allows the
mapping of the luma data to a user-defined function. (See Gamma
Correction Registers 0–13 section.) (Mode Register 8, Gamma
Correction Registers 0–13.)

NTSC Pedestal Control

In NTSC mode it is possible to have the pedestal signal gener­ated on the output video signal. (Mode Register 2.)

Power-On Reset

After power-up, it is necessary to execute a RESET operation. A
reset occurs on the falling edge of a high-to-low transition on the
RESET pin. This initializes the pixel port such that the data on
the pixel input pins is ignored. See Appendix 8 for the register
settings after RESET is applied.

Real-Time Control, Subcarrier Reset, and Timing Reset

Together with the SCRESET/RTC/TR pin of Mode Register 4
(Genlock Control), the ADV7190/ADV7191 can be used in
(a) Timing Reset Mode, (b) Subcarrier Phase Reset Mode or
(c) RTC Mode.

(a) A TIMING RESET is achieved in holding this pin high. In

this state the horizontal and vertical counters will remain reset.
On releasing this pin (set to low), the internal counters will

(b) The SUBCARRIER PHASE will reset to that of Field 0 at

(c) In RTC MODE, the ADV7190/ADV7191 can be used to

SCH Phase Mode

The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos­sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.

Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor SCH
phase jumps at the start of the four or eight field sequence.

Automatically resetting the SCH phase should not be done if
the video source does not have stable timing or the ADV7190/
ADV7191 is configured in RTC mode. Under these conditions
(unstable video) the Subcarrier Phase Reset should be en­abled but no reset applied. In this configuration the SCH
Phase will never be reset; this means that the output video will
now track the unstable input video.

The Subcarrier Phase Reset, when applied, will reset the SCH
phase to Field 0 at the start of the next field (e.g., Subcarrier
Phase Reset applied in Field 5 (PAL) on the start of the next
field SCH phase will be reset to Field 0). (Mode Register 4.)

Sleep Mode

If, after RESET, the SCRESET/RTC/TR and NTSC_PAL pins
are both set high, the ADV7190/ADV7191 will power up in
Sleep Mode to facilitate low power consumption before all
registers have been initialized. If Power-Up in Sleep Mode is
disabled, Sleep Mode control passes to the Sleep Mode control
in Mode Register 2 (i.e., control via I
and Mode Register 6.)

Square Pixel Mode

The ADV7190/ADV7191 can be used to operate in square pixel
mode. For NTSC operation an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of

29.5 MHz is required. The internal timing logic adjusts accord­ingly for square pixel mode operation. Square pixel mode is not
available in 4¥ Oversampling mode. (Mode Register 2.)

commence counting again. The minimum time the pin has
to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise
the reset signal might not be recognized.

the start of the following field when a low-to-high transition
occurs on this input pin.

lock to an external video source.

The real-time control mode allows the ADV7190/ADV7191
to automatically alter the subcarrier frequency to compen­sate for line length variations. When the part is connected to
a device that outputs a digital datastream in the RTC format
such as an ADV7185 video decoder (see Figure 32), the part
will automatically change to the compensated subcarrier
frequency on a line-by-line basis. This digital datastream is
67 bits wide and the subcarrier is contained in Bits 0 to 21.
Each bit is two clock cycles long. 00Hex should be written
into all four Subcarrier Frequency registers when using this
mode. It is recommended to use the ADV7185 in this mode.
(Mode Register 4.)

2

C). (Mode Register 2

–18–

REV. B

ADV7190/ADV7191

Vertical Blanking Data Insertion and BLANK Input

It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not have line sync or pre-/post­equalization pulses (see Figures 34 to 45). This mode of operation
is called Partial Blanking. It allows the insertion of any VBI
data (Opened VBI) into the encoded output waveform. This data
is present in digitized incoming YCbCr data stream (e.g., WSS
data, CGMS, VPS etc.). Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines. VBI is available
in all timing modes.

It is possible to allow control over the BLANK signal using Timing
Register 0. When the BLANK input is enabled (TR03 = 0 and
input pin tied low), the BLANK input can be used to input
externally generated blank signals in Slave Mode 1, 2, or 3. When
the BLANK input is disabled (TR03 = 1 and input pin tied low
or tied high), the BLANK input is not used and the ADV7190/
ADV7191 automatically blanks all normally blank lines as per
CCIR-624. (Timing Register 0.)

YUV Levels

This functionality allows the ADV7190/ADV7191 to output
SMPTE levels or Betacam levels on the Y output when config­ured in PAL or NTSC mode.

Sync Video

Betacam 286 mV 714 mV
SMPTE 300 mV 700 mV
MII 300 mV 700 mV

As the data path is branched at the output of the filters the luma
signal relating to the CVBS or S-Video Y/C output is unaltered.
It is only the Y output of the YCrCb outputs that is scaled.
This control allows color component levels to have a peak-peak
amplitude of 700 mV, 1000 mV or the default values of 934 mV
in NTSC and 700 mV in PAL. (Mode Register 5.)

16-Bit Interface

It is possible to input data in 16-bit format. In this case, the
interface only operates if the data is accompanied by separate
HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not avail­able in Slave Mode 0 since EAV/SAV timing codes are used.
(Mode Register 8.)

4 Oversampling and Internal PLL

It is possible to operate all six DACs at 27 MHz (2¥ Oversam-
pling) or 54 MHz (4¥ Oversampling).

The ADV7190/ADV7191 is supplied with a 27 MHz clock synced
with the incoming data. Two options are available: to run the
device throughout at 27 MHz or to enable the PLL. In the latter
case, even if the incoming data runs at 27 MHz, 4¥ Oversam-
pling and the internal PLL will output the data at 54 MHz.

NOTE
In 4¥ Oversampling Mode the requirements for the optional
output filters are different from those in 2¥ Oversampling. (Mode
Register 1, Mode Register 6.) See Appendix 6 for further details.

ENCODER

ADV7190/ADV7191

I

N

MPEG2

PIXEL BUS

27MHz

2 FILTER

REQUIREMENTS

ENCODER

CORE

54MHz

PLL

FREQUENCY – MHz

T
E
R
P

2

O



L
A

T

I
O
N

REQUIREMENTS

27.0 40.5 54.013.56.75

6

D
A
C

4 FILTER

O
U
T

54MHz

P

OUTPUT

U
T
S

Figure 30. PLL and 4 Oversampling Block Diagram

VIDEO TIMING DESCRIPTION

The ADV7190/ADV7191 is intended to interface to off-the­shelf MPEG1 and MPEG2 Decoders. As a consequence, the
ADV7190/ADV7191 accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 Pixel Port and has several Video Timing Modes of
operation that allow it to be configured as either System Master
Video Timing Generator or a Slave to the System Video Timing
Generator. The ADV7190/ADV7191 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.

The ADV7190/ADV7191 calculates the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.

In addition, the ADV7190/ADV7191 supports a PAL or NTSC
square pixel operation. The part requires an input pixel clock of

24.5454 MHz for NTSC square pixel operation and an input
pixel clock of 29.5 MHz for PAL square pixel operation. The
internal horizontal line counters place the various video waveform
sections in the correct location for the new clock frequencies.

The ADV7190/ADV7191 has four distinct Master and four distinct
Slave timing configurations. Timing Control is established with
the bidirectional HSYNC, BLANK, and VSYNC pins. Timing
Register 1 can also be used to vary the timing pulsewidths and
where they occur in relation to each other. (Mode Register 2,
Timing Register 0, 1.)

RESET SEQUENCE

When RESET becomes active the ADV7190/ADV7191 reverts to
the default output configuration (see Appendix 8 for register
settings). The ADV7190/ADV7191 internal timing is under the
control of the logic level on the NTSC_PAL pin.

REV. B

–19–

ADV7190/ADV7191

When RESET is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7190/ADV7191. Output
timing signals are still suppressed at this stage. DACs A, B, C
are switched off and DACs D, E, F are switched on.

When the user requires valid data, Pixel Data Valid Control is
enabled (MR26 = 1) to allow the valid pixel data to pass through
the encoder. Digital output timing signals become active and the
encoder timing is now under the control of the Timing Registers.
If at this stage, the user wishes to select a different video standard

RESET

DAC D,
DAC E

DAC A,
DAC B,
DAC C

PIXEL_DATA_VALID

DIGITAL TIMING

XXXXXXX XXXXXXX

DAC F

XXXXXXX XXXXXXX

XXXXXXX

MR26

XXXXXXX

XXXXXXX

OFF

0

DIGITAL TIMING SIGNALS SUPPRESSED

to that on the NTSC_PAL pin, Standard I2C Control should be
enabled (MR25 = 1) and the video standard required is selected
by programming Mode Register 0 (Output Video Standard
Selection). Figure 31 illustrates the RESET sequence timing.

BLACK VALUE WITH SYNC

BLACK VALUE

VALID VIDEO

VALID VIDEO

VALID VIDEO

1

TIMING ACTIVE

Figure 31.

RESET

Sequence Timing Diagram

–20–

REV. B

ADV7190/ADV7191

RTC

CLOCK

COMPOSITE

VIDEO

e.g., VCR

OR CABLE

H/L TRANSITION

COUNT START

TIME SLOT: 01

NOTES:

1

FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7190/ADV7191. FSC DDS REGISTER IS FSC PLL INCREMENTS
BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER
FREQUENCY REGISTERS OF THE ADV7190/ADV7191.

2

SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE

3

RESET BIT
RESET ADV7190/ADV7191’s DDS

128

LOW

DECODER

ADV7185

14 BITS

RESERVED

NOT USED IN

ADV7190/

ADV7191

VIDEO

LCC1

P19–P12

4 BITS

RESERVED

14

GLL

21013

19

SCRESET/RTC/TR

P7–P0

F

SAMPLE

ADV7190/ADV7191

PLL INCREMENT

SC

VALID

INVALID
SAMPLE

GREEN/ COMPOSITE/ Y

BLUE/ LUMA/U

RED/ CHROMA/ V

GREEN/ COMPOSITE/ Y

BLUE/ LUMA/U

RED/ CHROMA/ V

RESERVED

1

8/LINE

LOCKED CLOCK

SEQUENCE

5 BITS

0

BIT

Figure 32. RTC Timing and Connections

2

67 68

RESET

BIT

3

RESERVED

Mode 0 (CCIR–656): Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7190/ADV7191 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel
Data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 33. The

HSYNC

, VSYNC and

BLANK pins (if not used) should be tied high during this mode.

ANALOG

VIDEO

EAV CODE SAV CODE

C

INPUT PIXELS

NTSC/ PAL M SYSTEM

(525 LlNES/ 60Hz)

PAL SYSTEM

(625 LINES/ 50Hz)

FF0000XY8

Y

Y

r

4 CLOCK

4 CLOCK

END OF ACTIVE

VIDEO LINE

0

10801

0

FF00FFABABAB80108

ANCILLARY DATA

(HANC)

268 CLOCK

280 CLOCK

000

10F

0

F

4 CLOCK

4 CLOCK

START OF ACTIVE

C

X

0

b

Y

VIDEO LINE

CrC

Y

Y

b

1440 CLOCK

1440 CLOCK

C

C

Y

Y

r

b

Figure 33. Timing Mode 0, Slave Mode

REV. B

–21–

ADV7190/ADV7191

Mode 0 (CCIR–656): Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7190/ADV7191 generates H, V, and F signals required for the SAV and EAV Time Codes in the CCIR656 standard. The H bit
is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin. Mode 0 is illustrated
in Figure 34 (NTSC) and Figure 35 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 36.

DISPLAY

522 523 524 525 1 2 3 4

H

V

F

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

H

V

F

ODD FIELD

ODD FIELDEVEN FIELD

EVEN FIELD

VERTICAL BLANK

67

5

VERTICAL BLANK

9

8

Figure 34. Timing Mode 0, NTSC Master Mode

DISPLAY

10 11 20 21 22

DISPLAY

283

284

285

DISPLAY

622 623 624 625 1 2 3 4

H

V

F ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 314 315 316 317

H

V

F

ODD FIELD

313

EVEN FIELD

Figure 35. Timing Mode 0, PAL Master Mode

VERTICAL BLANK

5

VERTICAL BLANK

67

318

319 320

DISPLAY

22 23

21

DISPLAY

335 336

334

–22–

REV. B