ANALOG DEVICES ADV7188 Service Manual

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Multiformat SDTV Video Decoder with Fast

FEATURES

Multiformat video decoder supports NTSC-(J, M, 4.43),

PAL-(B/D/G/H/I/M/N), SECAM Integrates four 54 MHz, Noise Shaped Video®, 12-bit ADCs SCART fast blank support Clocked from a single 28.63636 MHz crystal Line-locked clock-compatible (LLC) Adaptive digital line length tracking (ADLLT™), signal

processing, and enhanced FIFO management give mini

TBC functionality 5-line adaptive comb filters Proprietary architecture for locking to weak, noisy, and

unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision® copy protection detection CTI (chroma transient improvement) DNR (digital noise reduction) Multiple programmable analog input formats

CVBS (composite video)

S-Video (Y/C)

YPrPb component (VESA, MII, SMPTE, and Betacam) 12 analog video input channels Integrated anti-aliasing filters Programmable Interrupt request output pin Automatic NTSC/PAL/SECAM identification

GENERAL DESCRIPTION

The ADV7188 integrated video decoder automatically detects and converts a standard analog baseband television signal that is compatible with worldwide standards NTSC, PAL, and SECAM, into 4:2:2 component video data-compatible with 20-, 16-, 10-, and 8-bit CCIR601/CCIR656.

The advanced and highly flexible digital output interface enables performance video decoding and conversion in line-locked clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security/surveillance cameras, and professional systems.

The 12-bit accurate ADC provides professional quality video performance and is unmatched. This allows true 10-bit resolution in the 10-bit output mode.

The 12 analog input channels accept standard composite, S-Video, and YPrPb video signals in an extensive number of combinations.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Switch Overlay Support

ADV7188

Digital output formats (8-bit, 10-bit, 16-bit, or 20-bit)

ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD

0.5 V to 1.6 V analog signal input range Differential gain: 0.4% typ Differential phase: 0.4° typ Programmable video controls

Peak white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free-run mode (generates stable video output with no I/P) VBI decode support for close captioning (including XDS),

WSS, CGMS, Gemstar® 1×/2×, teletext, VITC, VPS Power-down mode 2-wire serial MPU interface (I

3.3 V analog, 1.8 V digital core; 3.3 V IO supply Industrial temperature grade: –40°C to +85°C 80-lead LQFP Pb-free package

APPLICATIONS

High end DVD recorders Video projectors HDD-based PVRs/DVDRs LCD TVs Set-top boxes Professional video products AVR receiver

AGC and clamp restore circuitry allow an input video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively, these can be bypassed for manual settings.

The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise, accurate sampling and digital filtering. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ±5% line length variation. The output control signals allow glueless interface connections in almost any application. The ADV7188 modes are set up over a 2-wire, serial, bidirectional port (I

SCART and overlay functionality are enabled by the ADV7188’s ability to simultaneously process CVBS and standard definition RGB signals. Signal mixing is controlled by the fast blank pin. The ADV7188 is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. It is packaged in a small 80-lead LQFP Pb-free package.

C®-compatible)

C-compatible).

ADV7188

TABLE OF CONTENTS

Introduction ...................................................................................... 4

VBI Data Recovery..................................................................... 23

Analog Front End......................................................................... 4

Standard Definition Processor (SDP)........................................ 4

Electrical Characteristics ............................................................. 5

Video Specifications..................................................................... 6

Timing Specifications .................................................................. 7

Analog Specifications................................................................... 7

Thermal Specifications ................................................................ 8

Timing Diagrams.......................................................................... 8

Absolute Maximum Ratings............................................................ 9

Package Thermal Performance................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Analog Front End........................................................................... 12

Analog Input Muxing ................................................................ 12

Manual Input Muxing................................................................ 14

General Setup.............................................................................. 23

Color Controls............................................................................ 25

Clamp Operation........................................................................ 27

Luma Filter.................................................................................. 28

Chroma Filter.............................................................................. 31

Gain Operation........................................................................... 32

Chroma Transient Improvement (CTI) .................................. 35

Digital Noise Reduction (DNR), and Luma Peaking Filter.. 36

Comb Filters................................................................................ 37

AV Code Insertion and Controls ............................................. 39

Synchronization Output Signals............................................... 41

Sync Processing .......................................................................... 48

VBI Data Decode ....................................................................... 49

C Readback Registers.............................................................. 58

Pixel Port Configuration ............................................................... 72

XTAL Clock Input Pin Functionality.......................................15

28.63636 MHz Crystal Operation............................................ 15

Antialiasing Filters .....................................................................15

SCART and Fast Blanking......................................................... 15

Fast Blank Control...................................................................... 16

Readback of FB Pin Status......................................................... 18

Global Control Registers ............................................................... 19

Power-Save Modes...................................................................... 19

Reset Control .............................................................................. 19

Global Pin Control..................................................................... 19

Global Status Registers................................................................... 21

Standard Definition Processor (SDP).......................................... 22

SD Luma Path ............................................................................. 22

SD Chroma Path......................................................................... 22

Sync Processing........................................................................... 23

MPU Port Description................................................................... 73

C Sequencer.............................................................................. 74

C Register Maps........................................................................... 75

User Map ..................................................................................... 75

User Sub Map.............................................................................. 91

C Programming Examples........................................................ 100

Mode 1 CVBS Input................................................................. 100

Mode 2 S-Video Input .............................................................101

Mode 3 525i/625i YPrPb Input .............................................. 102

Mode 4 SCART—S-Video or CVBS autodetect................... 103

Mode 5 SCART Fast Blank—CVBS & RGB .........................104

Mode 6 SCART RGB Input (Static Fast Blank)—CVBS and

RGB ............................................................................................

105

PCB Layout Recommendations.................................................. 106

Rev. 0 | Page 2 of 112

ADV7188

Analog Interface Inputs........................................................... 106

XTAL And Load Capacitor Values Selection ........................107

Power Supply Decoupling....................................................... 106

PLL ............................................................................................. 106

Digital Outputs (Both Data and Clocks) .............................. 106

Digital Inputs............................................................................ 107

REVISION HISTORY

7/05—Revision 0: Initial Version

Typical Circuit Connection .........................................................108

Outline Dimensions......................................................................109

Ordering Guide.........................................................................109

Rev. 0 | Page 3 of 112

ADV7188

INTRODUCTION

The ADV7188 is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format.

ANALOG FRONT END

The ADV7188 analog front end includes four 12-bit noise shaped video ADCs that digitize the analog video signal before applying it to the standard definition processor. The analog front end uses differential channels to each ADC to ensure high performance in mixed-signal applications.

The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7188. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7188. The ADCs are configured to run in 4× oversampling mode.

The ADV7188 has optional anti-aliasing filters on each of the four input channels. The filters are designed for SD video with approximately 6 MHz bandwidth.

SCART and overlay functionality are enabled by the ADV7188’s ability to simultaneously process CVBS and Standard Definition RGB signals. Signal mixing is controlled by the Fast Blank pin.

STANDARD DEFINITION PROCESSOR (SDP)

The ADV7188 is capable of decoding a large selection of baseband video signals in composite, S-Video, and component formats. The video standards supported include PAL B/D/I / G /H, PAL 6 0 , PAL M, PA L N, PAL Nc, N T SC M/ J, NTSC

4.43, and SECAM B/D/G/K/L. The ADV7188 can automatically detect the video standard and process it accordingly.

The ADV7188 has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality without user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7188.

The ADV7188 implements a patented adaptive digital line length tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7188 to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The ADV7188 contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions.

The ADV7188 can process a variety of VBI data services, such as closed captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), Gemstar 1×/2×, extended data service (XDS) and teletext. The ADV7188 is fully Macrovision certified; detection circuitry enables Type I, II, and III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs.

AIN1– AIN12

CVBS

S-VIDEO

YPrPb

RGB + CVBS

SCLK

SDA

ALSB

CLAMP

INPUT

CLAMP

MUX

CLAMP

SYNC PROCESSING AND

CLOCK GENERATION

SERIAL INTERFACE

CONTROL AND VBI DATA

ANTI

ALIAS

FILTER

ANTI

ALIAS

FILTER

ANTI

ALIAS

FILTER

ANTI

ALIAS

FILTER

A/D

SYNC AND

CLK CONTROL

ADV7188

DATA

PREPROCESSOR

DECIMATION AND

DOWNSAMPLING

FILTERS

CONTROL

AND DATA

FUNCTIONAL BLOCK DIAGRAM

STANDARD DEFINITION PROCESSOR

CVBS/Y

RECOVERY

CVBS

CHROMA

C Cr Cb R G B

DEMOD

COLORSPACE

CONVERSION

VBI DATA RECOVERY

MACROVISION

DETECTION

Figure 1.

Rev. 0 | Page 4 of 112

LUMA

FILTER

SYNC

EXTRACT

CHROMA

FILTER

GLOBAL CONTROL

STANDARD

AUTODETECTION

LUMA

RESAMPLE

CONTROL

CHROMA

RESAMPLE

Y Cr Cb

LUMA

2D COMB (5H MAX)

CHROMA 2D COMB

(4H MAX)

SYNTHESIZED LLC CONTROL

FREE RUN

OUTPUT CONTROL

FAST BLANK

OVERLAY CONTROL

PIXEL DATA

P19-P10 P9-P0

FIELD

LLC1

OUTPUT FORMATTER

LLC2

SFL

INT

05478-001

ADV7188

ELECTRICAL CHARACTERISTICS

At A

= 3.15 V to 3.45 V, D

VDD

Operating temperature range, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions Min Typ Max Unit

STATIC PERFORMANCE

1, 2, 3

Resolution (Each ADC) N 12 Bits Integral Nonlinearity INL BSL at 54 MHz –1.5/+2.5 ±8 LSB Differential Nonlinearity DNL BSL at 54 MHz –0.7/+0.7 –0.99/+2.5 LSB

DIGITAL INPUTS

Input High Voltage4 V Input Low Voltage5 V Input Current IIN Pins listed in Note 6 –50 +50 μA All other pins7 –10 +10 μA Input Capacitance9 C

DIGITAL OUTPUTS

Output High Voltage8 V Output Low Voltage8 V High Impedance Leakage Current I Output Capacitance9 C

POWER REQUIREMENTS9

Digital Core Power Supply D Digital I/O Power Supply D PLL Power Supply P Analog Power Supply A Digital Core Supply Current I Digital I/O Supply Current I PLL Supply Current I Analog Supply Current I SCART RGB FB input11 269 mA Power-Down Current I Power-Up Time t

All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale +12.5%.

Max INL and DNL specificationss obtained with part configured for component video input.

Temperature range T

To obtain specified V

Pins: 36, 64, 79.

Excluding all “TEST” pins (TEST0 to TEST8)

and VOL levels obtained using default drive strength value (0xD5) in register subaddress 0xF4.

Guaranteed by characterization.

ADC0 powered on only.

All four ADCs powered on.

to T

MIN

MAX

level on Pin 29, register 0x13 (write only) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00, then V

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V, nominal input range 1.6 V.

VDD

2 V

0.8 V

10 pF

10 μA

LEAK

20 pF

OUT

1.65 1.8 2.0 V

VDD

3.0 3.3 3.6 V

VDDIO

1.71 1.8 1.89 V

VDD

3.15 3.3 3.45 V

VDD

105 mA

DVDD

4 mA

DVDDIO

11 mA

PVDD

CVBS input10 99 mA

AVDD

0.65 mA

PWRDN

20 ms

PWRUP

, –40°C to +85°C. The min/max specifications are guaranteed over this range.

= 0.4 mA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

on Pin 29 = 1.2 V.

on Pin 29 = 0.4 V.

Rev. 0 | Page 5 of 112

ADV7188

VIDEO SPECIFICATIONS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise noted).

Table 2.

Parameter

1,2

Symbol Test Conditions Min Typ Max Unit

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS I/P, modulate 5-step 0.4 0.6 degree Differential Gain DG CVBS I/P, modulate 5-step 0.4 0.6 % Luma Nonlinearity LNL CVBS I/P, 5-step 0.4 0.7 %

NOISE SPECIFICATIONS

SNR Unweighted Luma ramp 61 63 dB Luma flat field 63 65 dB Analog Front End Crosstalk 60 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range –5 +5 % Vertical Lock Range 40 70 Hz Fsc Subcarrier Lock Range ±1.3 Hz Color Lock In Time 60 Lines Sync Depth Range3 20 200 % Color Burst Range 5 200 % Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines

CHROMA SPECIFICATIONS

Hue Accuracy HUE 1 degree Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.4 % Chroma Phase Error 0.3 degree Chroma Luma Intermodulation 0.1 %

LUMA SPECIFICATIONS

Luma Brightness Accuracy CVBS, 1 V I/P 1 % Luma Contrast Accuracy CVBS, 1 V I/P 1 %

Temperature range T

Guaranteed by characterization.

Nominal sync depth is 300 mV at 100% sync depth range.

to T

MIN

MAX

= 1.65 V to 2.0 V, D

VDD

, –40°C to +85°C. The min/max specifications are guaranteed over this range.

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

Rev. 0 | Page 6 of 112

ADV7188

TIMING SPECIFICATIONS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise noted).

Table 3.

Parameter

1,2

Symbol Test Conditions Min Typ Max Unit

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency 28.63636 MHz Frequency Stability ±50 ppm

I2C PORT3

SCLK Frequency 400 kHz SCLK Min Pulse Width High t1 0.6 μs SCLK Min Pulse Width Low t2 1.3 μs Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 μs

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC1 Mark Space Ratio t9:t10 45:55 55:45 % Duty Cycle LLC1 Rising to LLC2 Rising t11 1 ns LLC1 Rising to LLC2 Falling t12 1 ns

DATA AND CONTROL OUTPUTS

Data Output Transitional Time4 t13

Data Output Transitional Time4 t14

Propagation Delay to Hi Z t15 6 ns Max Output Enable Access Time t16 7 ns Min Output Enable Access Time t17 4 ns

Temperature range T

Guaranteed by characterization.

TTL input values are 0 to 3 volts, with rise/fall times ≤3 ns, measured between the 10% and 90% points.

SDP timing figures obtained using default drive strength value (0xD5) in register subaddress 0xF4.

to T

MIN

MAX

ANALOG SPECIFICATIONS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise noted). Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.

Table 4.

Parameter

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF Input Impedance3 Clamps switched off 10 MΩ Input impedance of Pin 40 (FB) 20 kΩ Large Clamp Source Current 0.75 mA Large Clamp Sink Current 0.75 mA Fine Clamp Source Current 60 μA Fine Clamp Sink Current 60 μA

Temperature range T

Guaranteed by characterization.

Except Pin 40 (FB).

1,2

Symbol Test Condition Min Typ Max Unit

to T

MIN

MAX

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

Negative clock edge to start of valid data

= t

ACCESS

– t13)

End of valid data to negative clock edge

= t9 + t14)

HOLD

, –40°C to +85°C. The min/max specifications are guaranteed over this range.

= 1.65 V to 2.0 V, D

VDD

, –40°C to +85°C. The min/max specifications are guaranteed over this range.

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

3.6 ns

2.4 ns

Rev. 0 | Page 7 of 112

ADV7188

THERMAL SPECIFICATIONS

Table 5.

Parameter Symbol Test Conditions Min Typ Max Unit

Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane 7.6 °C/W Junction-to-Ambient Thermal Resistance (Still Air) θJA 4-layer PCB with solid ground plane 38.1 °C/W

TIMING DIAGRAMS

Figure 2. I

C Timing

SDA

SCLK

05478-002

OUTPUT LLC 1

OUTPUT LLC 2

OUTPUTS P0–P19, VS,

HS, FIELD,

SFL

05478-003

Figure 3. Pixel Port and Control Output Timing

05478-004

P0–P19, HS,

VS, FIELD,

SFL

Figure 4.

Timing

Rev. 0 | Page 8 of 112

ADV7188

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

to AGND 4 V

VDD

to DGND 2.2 V

VDD

to AGND 2.2 V

VDD

to DGND 4 V

VDDIO

to AVDD –0.3 V to +0.3 V

VDDIO

to D

VDD

VDDIO

VDD

Digital Inputs Voltage to DGND –0.3V to D Digital Output Voltage to DGND –0.3V to D Analog Inputs to AGND AGND – 0.3 V to A Maximum Junction Temperature

–0.3 V to +0.3 V

VDD

to P

–0.3V to +2 V

VDD

to D

–0.3V to +2 V

VDD

to P

–0.3V to +2 V

VDD

to D

–0.3V to +2 V

VDD

max)

125°C

VDDIO

+ 0.3 V + 0.3 V

VDD

+ 0.3 V

Storage Temperature Range –65°C to +150°C Infrared Reflow Soldering (20 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption the user is advised to turn off any unused ADCs when using the part.

The junction temperature must always stay below the maximum junction temperature (T following equation shows how to calculate the junction temperature:

= T

+ (θJA × W

A Max

Max

)

where:

= 85°C.

A Max

= 30°C/W.

Max

= ((A

VDD

× I

VDD

PVDD

× I

)).

AV D D

) + ( D

max) of 125°C. The

× I

DVDD

) + (D

VDD

VDDIO

× I

DVDDIO

) +

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 9 of 112

ADV7188

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FIELD79OE78TEST177TEST676P1675P1774P1873P1972DVDD71DGND70TEST069TEST468SCLK67SDA66ALSB65TEST764RESET63TEST562AIN661AIN12

VS HS

DGND

DVDDIO

P15 P14 P13 P12

DGND

DVDD

INT

SFL

TEST2

DGND

DVDDIO

TEST8

P11 P10

PIN 1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

21P722P623P524P425

TEST3

LLC227LLC1

ADV7188

TOP VIEW

(Not to Scale)

XTAL

XTAL1

32P333P234P135P036

DVDD

DGND

PWRDN

ELPF

PVDD

AGND

AIN5

AIN11

AIN4

AIN10

AGND

CAPC2

CAPC1

AGND

CML

REFOUT

AVDD

CAPY2

CAPY1

AGND

AIN3

AIN9

AIN2

AIN8

AIN1

AIN7

Figure 5. 80-Lead LQFP Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type Function

3, 9, 14, 31, 71 DGND G Digital Ground. 39, 47, 53, 56 AGND G Analog Ground. 4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V). 10, 30, 72 DVDD P Digital Core Supply Voltage (1.8 V). 50 AVDD P Analog Supply Voltage (3.3 V). 38 PVDD P PLL Supply Voltage (1.8 V). 42, 44, 46, 58, 60, 62,

AIN1 to AIN12 I Analog Video Input Channels.

41, 43, 45, 57, 59, 61 11

INT

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video. See the User Sub Map register details in

40 FB I

Fast Blank. FB is a fast switch overlay input that switches between CVBS and RGB analog

signals. 70, 78, 13, 25, 69, 63 TEST0 to TEST5 Leave these pins unconnected. 77, 65 TEST6 to TEST7 Tie to AGND 16 TEST8 Tie to DVDDIO 35, 34, 33, 32, 24, 23,

P0 to P19 O Video Pixel Output Port. 22, 21, 20, 19, 18, 17, 8, 7, 6, 5, 76, 75, 74, 73

2 HS O Horizontal Synchronization Output Signal. 1 VS O Vertical Synchronization Output Signal. 80 FIELD O Field Synchronization Output Signal. 67 SDA I/O I2C Port Serial Data Input/Output Pin. 68 SCLK I I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).

05478-005

Table 103.

Rev. 0 | Page 10 of 112

ADV7188

Pin No. Mnemonic Type Function

66 ALSB I

27 LLC1 O

26 LLC2 O

29 XTAL I

28 XTAL1 O

37 ELPF I

12 SFL O

51 REFOUT O

52 CML O

48, 49 CAPY1, CAPY2 I

54. 55 CAPC1, CAPC2 I

RESET

PWRDN

This pin selects the I write as 0x40; set to Logic 1 sets the address to 0x42.

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7188 circuitry.

Line-Locked Clock 1. This is a line-locked output clock for the pixel data output by the ADV7188. Nominally 27 MHz, but varies up or down according to video line length.

Line-Locked Clock 2. This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7188. Nominally 13.5 MHz, but varies up or down according to video line length.

This is the input pin for the 28.63636 MHz crystal, or can be overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7188. In crystal mode, the crystal must be a fundamental crystal.

Logic 0 on this pin places the ADV7188 in a power-down mode. Refer to the I2C Register Maps section for more options on power-down modes for the ADV7188.

When set to Logic 0, OE enables the pixel output bus, P19 to P0 of the ADV7188. Logic 1 on the OE pin places P19 to P0, HS, VS, and SFL/SYNC_OUT into a high impedance state.

The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 50.

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video encoder.

Internal Voltage Reference Output. Refer to network for this pin.

The CML pin is a common-mode level for the internal ADC’s. Refer to recommended capacitor network for this pin.

ADC’s Capacitor Network. Refer to this pin.

C address for the ADV7188. ALSB set to Logic 0 sets the address for a

Figure 50 for a recommended capacitor

Figure 50 for a

Figure 50 for a recommended capacitor network for

Rev. 0 | Page 11 of 112

ADV7188

ANALOG FRONT END

ANALOG INPUT MUXING

AIN1

AIN7

AIN2

AIN8

AIN3

AIN9

AIN4

RGB_IP_SEL

INSEL[3:0]

AIN10

AIN5

AIN11

AIN6

AIN12

ADC_SW_MAN_EN

AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12

1 0

PRIM_MODE[3:0]

SDM_SEL[1:0]

ADC0_SW[3:0]

ADC0

INTERNAL

MAPPING

FUNCTIONS

Figure 6. Internal Pin Connections

The ADV7188 has an integrated analog muxing section that allows connecting more than one source of video signal to the decoder.

Figure 6 outlines the overall structure of the input

muxing provided in ADV7188.

As can be seen in

Figure 6, the analog input muxes can be

controlled in two ways:

• By functional registers (INSEL). Using INSEL[3:0]

simplifies the setup of the muxes, and minimizes crosstalk between channels by pre-assigning the input channels. This is referred to as ADI recommended input muxing.

• By an I

C manual override (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW, and ADC3_SW). This is provided for applications with special requirements, such as number/combinations of signals, which would not be served by the pre-assigned input connections. This is referred to as manual input muxing.

Refer to

Figure 7 for an overview of the two methods of

controlling input muxing.

AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12

AIN2 AIN8 AIN5 AIN11 AIN6 AIN12 AIN4

AIN4

AIN7

1 0

YES

SET INSEL[3:0] AND

SDM_SEL[1:0]

FOR REQUIRED MUXING

CONFIGURATION

Figure 7. Input Muxing Overview

ADC1_SW[3:0]

ADC1

ADC2_SW[3:0]

ADC2

ADC3_SW[3:0]

ADC3

CONNECTING

ANALOG SIGNALS

TO ADV7188

ADI RECOMMENDED

INPUT MUXING;

SEE TABLES 8 AND 9

TO DECODE VIDEO FORMAT:

SCART (CVBS/RGB): 1111

S-VIDEO/CVBS AUTODETECT

USE MANUAL INPUT MUXING

(ADC_SW_MAN_EN, ADC0_SW,

05478-006

SET INSEL[3:0] TO

CONFIGURE ADV7188

CVBS: 0000

YC: 0110

YPrPb: 1001

SET SDM_SEL[1:0] FOR

ADC1_SW, ADC2_SW,

ADC3_SW)

05478-007

Rev. 0 | Page 12 of 112

ADV7188

ADI Recommended Input Muxing

A maximum of 12 CVBS inputs can be connected and decoded by the ADV7188. As seen in

Figure 5, this means the sources must be connected to adjacent pins on the IC. This calls for a careful design of the PCB layout, for example, ground shielding between all signals routed through tracks that are physically close together.

SDM_SEL[1:0], S-Video and CVBS Autodetect Mode Select, Address 0x69 [1:0]

The SDM_SEL bits decide on input routing and whether INSEL[3:0] is used to govern I/P routing decisions.

The CVBS/YC autodetection feature is enabled using SDM_SEL = 11.

Table 8: SDM_SEL[1:0]

SDM_SEL[1:0] Mode Analogue Video Inputs

00 As per INSEL[3:0] As per INSEL[3:0] 01 CVBS AIN11 10 YC

Y = AIN10 C = AIN12

11 YC/CVBS auto

CVBS = AIN11 Y = AIN11 C = AIN12

Table 9. Input Channel Switching Using INSEL[3:0]

Description

INSEL[3:0]

0000(default) CVBS1 = AIN1

0001 CVBS2 = AIN2

0010 CVBS3 = AIN3

0011 CVBS4 = AIN4

Analog Input Pins Video Format

SCART (CVBS and R, G, B )

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

SCART (CVBS and R, G, B ) B = AIN7 R = AIN8 G = AIN9

0100 CVBS1 = AIN1

SCART (CVBS and R, G, B ) B = AIN4 R = AIN5 G = AIN6

0101 CVBS1 = AIN1

SCART (CVBS and R, G, B ) B = AIN4 R = AIN5 G = AIN6

0110 Y1 = AIN1

YC C1 = AIN4

0111 Y2 = AIN2

YC C2 = AIN5

INSEL[3:0] Input Selection, Address 0x00 [3:0]

The INSEL bits allow the user to select an input channel and the input format. Depending on the PCB connections, only a subset of the INSEL modes are valid. The INSEL[3:0] not only switches the analog input muxing, it also configures ADV7188 to process CVBS (Comp), S-Video (Y/C), or component (YPbPr) format.

ADI-recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity.

Table 10 summarizes how the PCB

layout should connect analog video signals to the ADV7188.

It is strongly recommended to connect any unused analog input pins to AGND to act as a shield.

Connect inputs AIN7 to AIN11 to AGND when only six input channels are used. This improves the quality of the sampling due to better isolation between the channels.

AIN12 is not under the control of INSEL[3:0]. It can be routed to ADC0/ADC1/ADC2 only by manual muxing. See

Tabl e 11

for details.

INSEL[3:0]

Analog Input Pins Video Format

1000 Y3 = AIN3

Description

C3 = AIN6

1001 Y1 = AIN1

YPrPb PB1 = AIN4 PR1 = AIN5

1010 Y2 = AIN2

YPrPb PB2 = AIN3 PR2 = AIN6

1011 CVBS7 = AIN7

SCART (CVBS and R, G, B ) B = AIN7 R = AIN8 G = AIN9

1100 CVBS8 = AIN8

SCART (CVBS and R, G, B ) B = AIN7 R = AIN8 G = Ain9

1101 CVBS9 = AIN9

SCART (CVBS and R, G, B ) B = AIN7 R = AIN8 G = Ain9

1110 CVBS10 = AIN10

B = AIN4 or AIN7 R = Ain5 or Ain8 G = Ain6 or Ain9

1111 CVBS11 = AIN11

B = AIN4 or AIN7 R = AIN5 or AIN81

Selectable via RGB_IP_SEL.

G = AIN6 or AIN9

SCART (CVBS and R, G, B )

Rev. 0 | Page 13 of 112

ADV7188

Table 10. Input Channel Assignments

Input Channel Pin ADI-Recommended Input Muxing Control INSEL[3:0]

AIN7 41 CVBS7 SCART1-B AIN1 42 CVBS1 YC1-Y YPrPb1-Y SCART2-CVBS AIN8 43 CVBS8 SCART1-R AIN2 44 CVBS2 YC2-Y YPrPb2-Y AIN9 45 CVBS9 SCART1-G AIN3 46 CVBS3 YC3-Y YPrPb2-Pb AIN10 57 CVBS10 AIN4 58 CVBS4 YC1-C YPrPb1-Pb SCART2-B AIN11 59 CVBS11 SCART1-CVBS AIN5 60 CVBS5 YC2-C YPrPb1-Pr SCART2-R AIN12 61 Not Available AIN6 62 CVBS6 YC3-C YPrPb2-Pr SCART2-G

Table 11. Manual Mux Settings for All ADCs (SETADC_SW_MAN_EN = 1)

ADC0

ADC0_sw[3:0]

0000 No Connection 0000 No Connection 0000 No Connection 0000 No Connection 0001 AIN1 0001 No Connection 0001 No Connection 0001 No Connection 0010 AIN2 0010 No Connection 0010 AIN2 0010 No Connection 0011 AIN3 0011 AIN3 0011 No Connection 0011 No Connection 0100 AIN4 0100 AIN4 0100 No Connection 0100 AIN4 0101 AIN5 0101 AIN5 0101 AIN5 0101 No Connection 0110 AIN6 0110 AIN6 0110 AIN6 0110 No Connection 0111 No Connection 0111 No Connection 0111 No Connection 0111 No Connection 1000 No Connection 1000 No Connection 1000 No Connection 1000 No Connection 1001 AIN7 1001 No Connection 1001 No Connection 1001 AIN7 1010 AIN8 1010 No Connection 1010 AIN8 1010 No Connection 1011 AIN9 1011 AIN9 1011 No Connection 1011 No Connection 1100 AIN10 1100 AIN10 1100 No Connection 1100 No Connection 1101 AIN11 1101 AIN11 1101 AIN11 1101 No Connection 1110 AIN12 1110 AIN12 1110 AIN12 1110 No Connection 1111 No Connection 1111 No Connection 1111 No Connection 1111 No Connection

Connected To

ADC1_sw[3:0]

RGB_IP_SEL, Address 0xF1 [0]

For SCART input, R, G and B signals can be input on either AIN4, AIN5, and AIN6 or on AIN7, AIN8, and AIN9.

0 (default)—B is input on AIN4, R is input on AIN 5, and G is input on AIN6.

1—B is input on AIN7, R is input on AIN 8, and G is input on AIN9.

MANUAL INPUT MUXING

By accessing a set of manual override muxing registers, the analog input muxes of the ADV7188 can be controlled directly. This is referred to as manual input muxing. Manual input muxing overrides other input muxing control bits, for example, INSEL and SDM_SEL.

Manual muxing is activated by setting the ADC_SW_MAN_EN bit. It affects only the analog switches in front of the ADCs. This

ADC1 Connected To

ADC2_sw[3:0]

ADC2 Connected To

ADC3_sw[3:0]

ADC3 Connected To

means if the settings of INSEL and the manual input muxing registers (ADC0/ADC1/ADC2/ADC3_SW) contradict each other, the ADC0/ADC1/ADC2/ADC3_SW settings apply and INSEL/SDM_SEL is ignored.

Manual input muxing controls only the analog input muxes. INSEL[3:0] still has to be set so the follow-on blocks process the video data in the correct format. This means INSEL must still be used to tell the ADV7188 whether the input signal is of component, YC, or CVBS format.

Restrictions in the channel routing are imposed by the analog signal routing inside the IC; every input pin cannot be routed to each ADC. Refer to

Figure 6 for an overview on the routing capabilities inside the chip. The four mux sections can be controlled by the reserved control signal buses ADC0_SW[3:0], ADC1_SW[3:0}, ADC2_SW[3:0}, and ADC3_SW[3:0]. Table 11 explains the control words used.

Rev. 0 | Page 14 of 112

ADV7188

SETADC_SW_MAN_EN, Manual Input Muxing Enable, Address C4 [7]

ADC0_sw[3:0], ADC0 Mux Configuration, Address 0xC3 [3:0]

ADC1_sw[3:0], ADC1 Mux Configuration, Address 0xC3 [7:4]

ADC2_sw[3:0], ADC2 Mux Configuration, Address 0xC4 [3:0]

ADC3_sw[3:0], ADC3 Mux Configuration, Address 0xF3 [7:4]

See

Table 11.

XTAL CLOCK INPUT PIN FUNCTIONALITY

XTAL_TTL_SEL, Address 0x13 [2]

The XTAL pad is normally part of the crystal oscillator circuit, powered from a 1.8 V supply. For optimal clock generation, the slice level of the input buffer of this circuit is at approximately half the supply voltage. This makes it incompatible with TLL level signals.

0 (default)—A crystal is used to generate the ADV7188’s clock.

1—An external TTL level clock is supplied. A different input buffer can be selected, which slices at TTL-compatible levels. This inhibits operation of the crystal oscillator and, therefore, can only be used when a clock signal is applied.

28.63636 MHZ CRYSTAL OPERATION

EN28XTAL, Address 0x1D [6]

The ADV7188 can operate on two different base crystal frequencies. Selecting one over the other can be desirable in systems in which board crosstalk between different components leads to undesirable interference between video signals. It is recommended by ADI to use an XTAL of frequency 28.63636 MHz to clock the ADV7188. The programming examples at the end of this datasheet presume 28.63636 MHz crystal is used.

0 (default)—XTAL frequency is 27 MHz.

1—XTAL frequency is 28.63636 MHz.

AA_FILT_EN[2], Address 0xF3 [2]

0 (default)—The filter on channel 2 is disabled

1—The filter on channel 2 is enabled

AA_FILT_EN[3], Address 0xF3 [3]

0 (default)—The filter on channel 3 is disabled

1—The filter on channel 3 is enabled

RESPONSE OF AA FILTER WITH CALIBRATED CAPACITORS

0 –2 –4 –6 –8

–10 –12 –14 –16 –18 –20 –22 –24 –26 –28 –30 –32 –34

ATTENUATION (dB)

–36 –38 –40 –42 –44 –46 –48 –50 –52

1M 1G

Figure 8. Frequency Response of Internal ADV7188 Antialiasing Filters

10M 100M

FREQUENCY (Hz)

05478-008

SCART AND FAST BLANKING

The ADV7188 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality.

This function is available when INSEL[3:0] is set appropriately

Table 9). Timing extraction is always performed by the

(see ADV7188 on the CVBS signal. However, a combination of the CVBS and RGB inputs can be mixed and output under control

of I

C registers and the fast blank (FB) pin.

Four basic modes are supported:

ANTIALIASING FILTERS

The ADV7188 has optional antialiasing filters on each of the four input channels. The filters are designed for SD video with approximately 6 MHz bandwidth.

A plot of the filter response is shown in can be individually enabled via I

C under the control of

AA_FILT_EN[3:0].

AA_FILT_EN[0], Address 0xF3 [0]

0 (default)—The filter on channel 0 is disabled

1—The filter on channel 0 is enabled

AA_FILT_EN[1], Address 0xF3 [1]

0 (default)—The filter on channel 1 is disabled

1—The filter on channel 1 is enabled

Figure 8. The filters

Rev. 0 | Page 15 of 112

Static Switch Mode

The FB pin is not used. The timing is extracted from the CVBS signal, and either the CVBS content or RGB content can be output under the control of CVBS_RGB_SEL. This mode allows the selection of a full-screen picture from either source. Overlay is not possible in static switch mode.

Fixed Alpha Blending

The FB pin is not used. The timing is extracted from the CVBS signal, and an alpha blended combination of the video from the CVBS and RGB sources is output. This alpha blending is applied to the full screen. The alpha blend factor is selected with

C signal MAN_ALPHA[6:0]. Overlay is not possible in

the I fixed alpha blending mode.

ADV7188

Dynamic Switching (Fast Mux)

Source selection is under the control of the fast blank (FB) pin. This enables dynamic multiplexing between the CVBS and RGB sources. With default settings, when Logic 1 is applied to the FB pin, the RGB source is selected; when Logic 0 is applied to the FB pin, the CVBS source is selected. This mode is suitable for the overlay of subtitles, teletext, or other material. Typically, the CVBS source carries the main picture and the RGB source has the overlay data.

Dynamic Switching with Edge-Enhancement

This provides the same functionality as the dynamic switching mode, but with ADI proprietary edge-enhancement algorithms that improve the visual appearance of transitions for signals from a wide variety of sources.

System Diagram

A block diagram of the ADV7188 fast blanking configuration is shown in

The CVBS signal is processed by the ADV7188 and converted to YPrPb. The RGB signals are processed by a color space converter (CSC) and samples are converted to YPrPb. Both sets of YPrPb signals are input to the sub-pixel blender, which can be configured to operate in any of the four modes outlined above.

The fast blank position resolver determines the time position of the FB to a very high accuracy (<1 ns); this position information is then used by the sub-pixel blender in dynamic switching modes. This enables the ADV7188 to implement high performance multiplexing between the CVBS and RGB sources, even when the RGB data source is completely asynchronous to the sampling crystal reference.

An anti-aliasing filter is required on all four data channels (R, G, B, and CVBS). The order of this filter is reduced as all of the signals are sampled at 54 MHz.

Figure 9.

FAST BLANK

(FB PIN)

FAST BLANK

POSITION

RESOLVER

The switched or blended data is output from the ADV7188 in the standard output formats (see

Table 98).

FAST BLANK CONTROL

FB_MODE[1:0], Address 0xED [1:0]

FB_MODE controls which of the fast blank modes is selected.

Table 12: FB_MODE[1:0] function

FB_MODE[1:0] Description

00 (default) Static Switch Mode. 01 Fixed Alpha Blending. 10 Dynamic Switching (Fast Mux). 11 Dynamic Switching with Edge Enhancement.

Static Mux Selection Control

CVBS_RGB_SEL, Address 0xED [2]

CVBS_RGB_SEL controls whether the video from the CVBS or the RGB source is selected for output from the ADV7188.

0 (default)—Data from the CVBS source is selected for output. 1—Data from the RGB source is selected for output.

Alpha Blend Coefficient

MAN_ALPHA_VAL[6:0], Address 0xEE [6:0]

When FB_MODE[1:0] = 01 and fixed alpha blending is selected, MAN_ALPHA_VAL[6:0] determines the proportion in which the video from the CVBS source and the RGB source are blended. Equation 1 shows how these bits affect the video output.

VALALPHAMAN

]0:6[__

Video

RGB

⎛

−×=

VideoVideo

CVBSout

×+

⎜ ⎝

VALALPHAMAN

The maximum valid value for MAN_ALPHA_VAL[6:0] is 1000000 such that the alpha blender coefficients remain between 0 and 1. The default value for MAN_ALPHA_VAL[6:0] is 0000000.

CONTROL

]0:6[__

⎞ ⎟

⎠

(1)

CVBS

ADC0

CONDITIONING

CLAMPING AND

ADC1

ADC2

ADC3

SIGNAL

DECIMATION

TIMING

EXTRACTION

SIGNAL

CONDITIONING

CLAMPING AND

DECIMATION

Figure 9. Fast Blank Block Diagram

Rev. 0 | Page 16 of 112

VIDEO

PROCESSING

RGB

≥

YPrPb

CONVERSION

YPrPb

SUBPIXEL BLENDER

OUTPUT

FORMATTER

05478-009

ADV7188

Fast Blank Edge Shaping

FB_EDGE_SHAPE[2:0], Address 0xEF [2:0]

To improve the picture transition for high speed fast blank switching, an edge shape mode is available on the ADV7188. Depending on the format of the RGB inputs, it may be advantageous to apply this scheme to different degrees. The levels are selected via the FB_EDGE_SHAPE[2:0] bits. Users are advised to try each of the settings and select the setting that is most visually pleasing in their system.

Table 13. FB_EDGE_SHAPE[2:0] Function

FB_EDGE_SHAPE[2:0] Description

000 No Edge Shaping. 001 Level 1 Edge Shaping. 010 (default) Level 2 Edge Shaping. 011 Level 3 Edge Shaping. 100 Level 4 Edge Shaping. 101 to 111 Not Valid.

Contrast Reduction

For overlay applications, text can be more readable if the contrast of the video directly behind the text is reduced. To enable the definition of a window of reduced contrast behind inserted text, the signal applied to the FB pin can be interpreted as a tri-level signal, as shown in

RGB SOURCE

100%

Figure 10.

Contrast Mode

CNTR_MODE[1:0], Address 0xF1 [3:2]

The contrast level in the selected contrast reduction box is selected using the CNTR_MODE[1:0] bits.

Table 14. CNTR_MODE[1:0] Function

CNTR_MODE[1:0] Description

00 (default) 25%. 01 50%. 10 75%. 11 100%.

Fast Blank and Contrast Reduction Programmable Thresholds

FB_LEVEL[1:0], Address 0xF1 [5:4]

Controls the reference level for the fast blank comparator.

CNTR_LEVEL[1:0], Address 0xF1 [7:6]

Controls the reference level for the contrast reduction comparator.

The internal fast blank and contrast reduction signals are resolved from the tri-level FB signal using two comparators, as shown in

Figure 11. To facilitate compliance with different input level standards, the reference level to these comparators is programmable under the control of FB_LEVEL[1:0] and CNTR_LEVEL[1:0]. The resulting thresholds are given in Table 15.

CVBS SOURCE

50% CONTRAS

SANDCASTLE

CVBS SOURCE

100%

Figure 10. Fast Blank Signal Representation with

Contrast Reduction Enabled

05478-010

Contrast Reduction Enable

CNTR_ENABLE, Address 0xEF [3]

This register enables the contrast reduction feature and changes the meaning of the signal applied to the FB pin.

0 (default)—The contrast reduction feature is disabled and the fast blank signal is interpreted as a bi-level signal.

1—The contrast reduction feature is enabled and the fast blank signal is interpreted as a tri-level signal.

FB PIN

PROGRAMMABLE

THRESHOLDS

CNTR ENABLE

CNTR_LEVEL<1:0>

FB_LEVEL<1:0>

Figure 11. Fast Blank and Contrast Reduction Programmable Threshold

FAST BLANK COMPARATOR

–

CONTRAST REDUCTION COMPARATOR

FAST BLANK

05478-011

Rev. 0 | Page 17 of 112

ADV7188

Table 15. Fast Blank and Contrast Reduction Programmable Threshold I2C Controls

CNTR_ENABLE FB_LEVEL[1:0] CNTR_LEVEL[1:0] Fast Blanking Threshold Contrast Reduction Threshold

0 00 (default) XX 1.4 V n/a 0 01 XX 1.6 V n/a 0 10 XX 1.8 V n/a 0 11 XX 2.0 V n/a 1 00 (default) 00 1.6 V 0.4 V 1 01 01 1.8 V 0.6 V 1 10 10 2.0 V 0.8 V 1 11 11 2.2 V 2.0 V

Table 16. FB_STATUS Functions

FB_STATUS [3:0] Bit Name Description

0 FB_STATUS.0

1 FB_STATUS.1

2 FB_STATUS.2 3 FB_STATUS.3

FB_rise. A high value indicates there has been a rising edge on FB since the last I read. Value is cleared by current I

FB_fall. A high value indicates there has been a falling edge on FB since the last I2C read. Value is cleared by current I

FB_stat. Value of FB input pin at time of read. FB_high. A high value indicates there has been a rising edge on FB since the last I2C

read. Value is cleared by current I

FB_INV, Address 0xED [3] (write only)

The interpretation of the polarity of the signal applied to the FB pin can be changed using FB_INV.

0 (default)—The fast blank pin is active high.

1—The fast blank pin is active low.

READBACK OF FB PIN STATUS

FB_STATUS[3:0], Address 0xED [7:4]

FB_STATUS[3:0] is a readback value that provides the system information on the status of the FB pins as shown in

FB Timing

FB_SP_ADJUST[3:0], Address 0xEF [7:4]

The critical information extracted from the FB signal is the time at which it switches relative to the input video. Due to small timing inequalities either on the IC or on the PCB, it may be necessary to adjust the result by fractions of one clock cycle. This is controlled by FB_SP_ADJUST[3:0].

Each LSB of FB_SP_ADJUST[3:0] corresponds to 1/8 of an ADC clock cycle. Increasing the value is equivalent to adding delay to the FB signal. The reset value is chosen to give equalized channels when the ADV7188 internal anti-aliasing filters are enabled and there is no unintentional delay on the PCB.

The default value of FB_SP_ADJUST[3:0] is 0100.

Table 16.

C read – self-clearing bit.

Alignment of FB Signal

FB_DELAY[3:0], Address 0xF0 [3:0]

In the event of misalignment between the FB input signal and the other input signals (CVBS, RGB) or unequalized delays in their processing, it is possible to alter the delay of the FB signal in 28.63636 MHz clock cycles. (For a finer granularity delay of the FB signal, refer to

FB_SP_ADJUST[3:0], Address 0xEF [7:4]

above.)

The default value of FB_DELAY[3:0] is 0100.

Color Space Converter Manual Adjust

FB_CSC_MAN, Address 0xEE [7]

As shown in

Figure 9, the data from the CVBS source and the RGB source are both converted to YPbPr before being combined. For the RGB source, the color space converter (CSC) must be used to perform this conversion. When SCART support is enabled, the parameters for the CSC are automatically configured correctly for this operation.

If the user wishes to use a different conversion matrix, this autoconfiguration can be disabled and the CSC can be manually programmed. For details on this manual configuration, please contact ADI.

0 (default)—The CSC is configured automatically for the RGB to YPrPb conversion.

1—The CSC can be configured manually (not recommended).

Rev. 0 | Page 18 of 112

ADV7188

GLOBAL CONTROL REGISTERS

POWER-SAVE MODES

Power-Down

PDBP, Address 0x0F [2]

The digital core of the ADV7188 can be shut down by using a pin (

PWRDN

controls which of the two has the higher priority. The default is to give the pin (

the ADV7188 powered down by default.

) and the PWRDN bit. The PDBP register

PWRDN

) priority. This allows the user to have

PWRDN_ADC_3, Address 0x3A [0]

0 (default)—The ADC is in normal operation.

1—ADC3 is powered down.

FB_PWRDN, Address 0x0F [1]

To achieve very low power-down current, it is necessary to prevent activity on toggling input pins from reaching circuitry that could consume current. FB_PWRDN gates signals from the FB input pin.

0 (default)—The digital core power is controlled by the PWRDN

pin (the bit is disregarded).

1—The bit has priority (the pin is disregarded).

PWRDN, Address 0x0F [5]

Setting the PWRDN bit switches the ADV7188 into a chip-wide power-down mode. The power-down stops the clock from entering the digital section of the chip, thereby freezing its

operation. No I

C bits are lost during power-down. The PWRDN bit also affects the analog blocks and switches them into low current modes. The I

C interface itself is unaffected,

and remains operational in power-down mode.

The ADV7188 leaves the power-down state if the PWRDN bit is set to 0 (via I

C), or if the overall part is reset using the

RESET

pin. Note that PDBP must be set to 1 for the PWRDN bit to power down the ADV7188.

0 (default)—The chip is operational. 1—The ADV7188 is in chip-wide power-down.

ADC Power-Down Control

The ADV7188 contains four 12-bit ADCs (ADC 0, ADC 1, ADC 2 and ADC 3). If required, it is possible to power down each ADC individually.

• In CVBS mode, ADC1 and ADC2 should be powered

down to save on power consumption.

• In S-Video mode, ADC2 should be powered down to save

on power consumption.

PWRDN_ADC_0, Address 0x3A [3]

0 (default)—The ADC is in normal operation.

1—ADC0 is powered down.

PWRDN_ADC_1, Address 0x3A [2]

0 (default)—The ADC is in normal operation.

1—ADC1 is powered down.

PWRDN_ADC_2, Address 0x3A [1]

0 (default)—The ADC is in normal operation.

1—ADC2 is powered down.

0 (default)—The FB input is in normal operation.

1—The FB input is in power-save mode.

RESET CONTROL

RES Chip Reset, Address 0x0F [7]

Setting this bit, equivalent to controlling the

ADV7188, issues a full chip reset. All I

C registers are reset to

RESET

pin on the

their default values, making these bits self-clearing. Some register bits do not have a reset value specified. They keep their last written value. Those bits are marked as having a reset value of x in the register tables. After the reset sequence, the part immediately starts to acquire the incoming video signal.

Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before performing any more I

writes.

C master controller receives a no acknowledge condition

The I on the ninth clock cycle when chip reset is implemented. See

MPU Port Description section for a full description.

the

0 (default)—Operation is normal.

1—The reset sequence starts.

GLOBAL PIN CONTROL

Three-State Output Drivers

TOD, Address 0x03 [6]

This bit allows the user to three-state the output drivers of the ADV7188. Upon setting the TOD bit, the P19 to P0, HS, VS, FIELD, and SFL pins are three-stated. The ADV7188 also supports three-stating via a dedicated pin,

drivers are three-stated if the TOD bit or the

The timing pins (HS/VS/FIELD) can be forced active via the TIM_OE bit. For more information on three-state control, refer to the

Three-State LLC Drivers and the Timing Signals Output Enable sections. Individual drive strength controls are provided by the DR_STR_XX bits.

0 (default)—The output drivers are enabled.

1—The output drivers are three-stated.

. The output

pin is set high.

Rev. 0 | Page 19 of 112

ADV7188

Three-State LLC Drivers

TRI_LLC, Address 0x1D [7]

This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7188 to be three-stated. For more information on three-state control, refer to the the

Timing Signals Output Enable sections. Individual drive

strength controls are provided via the DR_STR_XX bits.

0 (default)—The LLC pin drivers work according to the DR_STR_C[1:0] setting (pin enabled).

1—The LLC pin drivers are three-stated.

Timing Signals Output Enable

TIM_OE, Address 0x04 [3]

The TIM_OE bit should be regarded as an addition to the TOD bit. Setting it high forces the output drivers for HS, VS, and FIELD into the active (that is, driving) state even if the TOD bit is set. If set to low, the HS, VS, and FIELD pins are three-stated dependent on the TOD bit. This functionality is useful if the decoder is to be used as a timing generator only. This may be the case if only the timing signals are to be extracted from an incoming signal, or if the part is in free-run mode where, for example, a separate chip can output a company logo. For more information on three-state control, refer to the Output Drivers and the Individual drive strength controls are provided via the DR_STR_XX bits.

0 (default)—HS, VS, and FIELD are three-stated according to the TOD bit.

1—HS, VS, and FIELD are forced active all the time.

Drive Strength Selection (Data)

DR_STR[1:0], Address 0xF4 [5:4]

For EMC and crosstalk reasons, it may be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR[1:0] bits affect the P[19:0] output drivers.

For more information on three-state control, refer to the Strength Selection (Clock) and the (Sync) sections.

Table 17. DR_STR_C Function

DR_STR_C[1:0] Description

01 (default) Medium low drive strength (2×). 10 Medium high drive strength (3×). 11 High drive strength (4×).

Three-State Output Drivers and

Three-State

Three-State LLC Drivers sections.

Drive

Drive Strength Selection

Drive Strength Selection (Clock)

DR_STR_C[1:0] Address 0xF4 [3:2]

The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the Strength Selection (Data) sections.

Table 18. DR_STR_C Function

DR_STR_C[1:0] Description

01 (default) Medium low drive strength (2×). 10 Medium high drive strength (3×). 11 High drive strength (4×).

Drive Strength Selection (Sync) and the Drive

Drive Strength Selection (Sync)

DR_STR_S[1:0], Address 0xF4 [1:0]

The DR_STR_S[1:0] bits allow the user to select the strength of the synchronization signals with which HS, VS, and F are driven. For more information, refer to the (Clock) and the

Table 19. DR_STR_S Function

DR_STR_S[1:0] Description

01 (default) Medium low drive strength (2×). 10 Medium high drive strength (3×). 11 High drive strength (4×).

Drive Strength Selection (Data) sections.

Drive Strength Selection

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN, Address 0x04 [1]

The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as GenLock) from the ADV7188 core to an encoder in a decoder-encoder back-to-back arrangement.

0 (default)—The subcarrier frequency lock output is disabled.

1—The subcarrier frequency lock information is presented on the SFL pin.

Polarity LLC Pin

PCLK, Address 0x37 [0]

The polarity of the clock that leaves the ADV7188 via the LLC1 and LLC2 pins can be inverted using the PCLK bit. Changing the polarity of the LLC clock output may be necessary to meet the setup-and-hold time expectations of follow-on chips. This bit also inverts the polarity of the LLC2 clock.

0—The LLC output polarity is inverted.

1 (default)—The LLC output polarity is normal (as per the timing diagrams).

Rev. 0 | Page 20 of 112

ADV7188

GLOBAL STATUS REGISTERS

Three registers provide summary information about the video decoder. The STATUS_1, STATUS_2, and STATUS_3 registers contain status bits that report operational information to the user.

STATUS_1[7:0] Address 0x10 [7:0]

This read only register provides information about the internal status of the ADV7188. See 0x51 [2:0] and

COL[2:0] Count Out of Lock, Address 0x51 [5:3]

CIL[2:0] Count Into Lock, Address

for information on the timing.

Depending on the setting of the FSCLE bit, the STATUS_1[0] and STATUS_1[1] bits are based solely on horizontal timing information or on the horizontal timing and lock status of the color subcarrier. See the

FSCLE Fsc Lock Enable, Address 0x51

[7] section.

STATUS_2[7:0], Address 0x12 [7:0]

See

Table 22.

Table 21. STATUS_1 Function

STATUS 1 [7:0] Bit Name Description

0 IN_LOCK In lock (right now). 1 LOST_LOCK Lost lock (since last read of this register). 2 FSC_LOCK Fsc locked (right now). 3 FOLLOW_PW AGC follows peak white algorithm. 4 AD_RESULT.0 Result of autodetection. 5 AD_RESULT.1 Result of autodetection. 6 AD_RESULT.2 Result of autodetection. 7 COL_KILL Color kill active.

STATUS_3[7:0], Address 0x13 [7:0]

Table 23.

See

AD_RESULT[2:0] Autodetection Result Address 0x10 [6:4]

These bits report back on the findings from the autodetection block. For more information on enabling the autodetection block, see the configuring it, see the

General Setup section. For information on

Autodetection of SD Modes section.

Table 20. AD_RESULT Function

AD_RESULT[2:0] Description

000 NTSM-MJ 001 NTSC-443 010 PAL-M 011 PAL-60 100 PAL-BGHID 101 SECAM 110 PAL-Combination N 111 SECAM 525

Table 22. STATUS_2 Function

STATUS 2 [7:0] Bit Name Description

0 MVCS DET Detected Macrovision color striping. 1 MVCS T3 Macrovision color striping protection. Conforms to Type 3 if high, and to Type 2 if low. 2 MV_PS DET Detected Macrovision pseudo Sync pulses. 3 MV_AGC DET Detected Macrovision AGC pulses. 4 LL_NSTD Line length is nonstandard. 5 FSC_NSTD Fsc frequency is nonstandard. 6 Reserved

7 Reserved

Table 23. STATUS_3 Function

STATUS 3 [7:0] Bit Name Description

0 INST_HLOCK Horizontal lock indicator (instantaneous). 1 GEMD Gemstar detect. 2 SD_OP_50HZ Flags whether 50 Hz or 60 Hz is present at output. 3 CVBS Indicates if a CVBS signal is detected in ‘YC/CVBS autodetection’ configuration 4 FREE_RUN_ACT

5 STD_FLD_LEN Field length is correct for currently selected video standard. 6 INTERLACED Interlaced video detected (field sequence found). 7 PAL_SW_LOCK Reliable sequence of swinging bursts detected.

Indicates if the ADV7188 is in free run mode. Outputs a blue screen by default. See the DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C [1] bit for details about disabling this function.

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ADV7188

STANDARD DEFINITION PROCESSOR (SDP)

STANDARD DEFINITION PROCESSOR

DIGITIZED CVBS

DIGITIZED Y (YC)

DIGITIZED CVBS

DIGITIZED C (YC)

MACROVISION

DETECTION

LUMA

DIGITAL

FINE

CLAMP

CHROMA

DIGITAL

FINE

CLAMP

RECOVERY

CHROMA

DEMOD

RECOVERY

VBI DATA

FILTER

EXTRACT

CHROMA

FILTER

AUTODETECTION

LUMA

SYNC

STANDARD

Figure 12. Block Diagram of the Standard Definition Processor

A block diagram of the ADV7188’s standard definition processor (SDP) is shown in

Figure 12.

The SDP block can handle standard definition video in CVBS, YC, and YPrPb formats. It can be divided into a luminance and a chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input.

SD LUMA PATH

The input signal is processed by the following blocks:

Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal.

Luma Filter Block. This block contains a luma decimation filter (YAA) with a fixed response, and some shaping filters (YSH) that have selectable responses.

Luma Gain Control. The automatic gain control (AGC) can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain.

Luma Resample. To correct for line-length errors and dynamic line-length changes, the data is digitally resampled.

Luma 2D Comb. The two-dimensional comb filter provides YC separation.

AV Code Insertion. At this point, the decoded luma (Y) signal is merged with the retrieved chroma values. AV codes (as per ITU-R. BT-656) can be inserted.

GAIN

CONTROL

LINE

LENGTH

PREDICTOR

GAIN

CONTROL

SLLC

CONTROL

LUMA

RESAMPLE

CONTROL

CHROMA

RESAMPLE

LUMA

2D COMB

CHROMA 2D COMB

CODE

INSERTION

VIDEO DATA OUTPUT

MEASUREMENT BLOCK (= >1

VIDEO DATA PROCESSING BLOCK

05478-012

SD CHROMA PATH

The input signal is processed by the following blocks:

Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal.

Chroma Demodulation. This block uses a color subcarrier (Fsc) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC and an FM demodulation for SECAM.

Chroma Filter Block. This block contains a chroma decimation filter (CAA) with a fixed response, and some shaping filters (CSH) that have selectable responses.

Gain Control. Automatic gain control (AGC) can operate on several different modes, including gain based on the color subcarrier’s amplitude, gain based on the depth of the horizontal sync pulse on the luma channel, or fixed manual gain.

Chroma Resample. The chroma data is digitally resampled to keep it perfectly aligned with the luma data. The resampling is done to correct for static and dynamic line-length errors of the incoming video signal.

Chroma 2D Comb. The two-dimensional, 5-line, superadaptive comb filter provides high quality YC separation in case the input signal is CVBS.

AV Code Insertion. At this point, the demodulated chroma (Cr and Cb) signal is merged with the retrieved luma values. AV codes (as per ITU-R. BT-656) can be inserted.

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ADV7188

SYNC PROCESSING

The ADV7188 extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources such as videocassette recorders with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this block is then used to drive the digital resampling section to ensure that the ADV7188 outputs 720 active pixels per line.

The sync processing on the ADV7188 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video.

• VSYNC Processor. This block provides extra filtering of the

detected VSYNCs to give improved vertical lock.

• HSYNC Processor. The HSYNC processor is designed to

filter incoming HSYNCs that have been corrupted by noise, providing much improved performance for video signals with stable time base but poor SNR.

VBI DATA RECOVERY

The ADV7188 can retrieve the following information from the input video:

• Wide-screen signaling (WSS)

• Copy generation management system (CGMS)

• Closed caption (CC)

• Macrovision protection presence

• Gemstar-compatible data slicing

• Te l et e x t

The ADV7188 is also capable of automatically detecting the incoming video standard with respect to

• Color subcarrier frequency

• Field rate

• Line rate

The ADV7188 can configure itself to support PAL(B/G/H/I/D/M/N), PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz, NTSC-4.43, and PAL-60.

GENERAL SETUP

Video Standard Selection

The VID_SEL[3:0] register allows the user to force the digital core into a specific video standard. Under normal circumstances, this should not be necessary. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. The following section describes the autodetection system.

Autodetection of SD Modes

In order to guide the autodetect system, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being automatically detected. Instead, the system picks the closest of the remaining enabled standards. The results of the autodetection can be read back via the status registers. See the section for more information.

VID_SEL[3:0] Address 0x00 [7:4]

Table 24. VID_SEL Function

VID_SEL[3:0] Description

0000 (default)

0001

0010

0011

0100 NTSC-J (1) 0101 NTSC-M (1) 0110 PAL-60 0111 NTSC-4.43 (1) 1000 PAL-BGHID. 1001 PAL-N (= PAL BGHID (with pedestal)) 1010 PAL-M (without pedestal) 1011 PAL-M 1100 PAL-combination N 1101 PAL-combination N (with pedestal) 1110 SECAM 1111 SECAM (with pedestal)

Autodetect (PAL-BGHID) <–> NTSC-J (without pedestal), SECAM

Autodetect (PAL-BGHID) <–> NTSC-M (with pedestal), SECAM

Autodetect (PAL N) (pedestal) <–> NTSC-J (no pedestal), SECAM

Autodetect (PAL N) (with pedestal) <–> NTSC-M (with pedestal), SECAM

AD_SEC525_EN Enable Autodetection of SECAM 525 Line Video, Address 0x07 [7]

0 (default)—Disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component.

1—Enables autodetection.

AD_SECAM_EN Enable Autodetection of SECAM, Address 0x07 [6]

0—Disables the autodetection of SECAM.

1 (default)—Enables autodetection.

Global Status Registers

Rev. 0 | Page 23 of 112

ADV7188

AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07 [5]

0—Disables the autodetection of NTSC style systems with a

4.43 MHz color subcarrier.

1 (default)—Enables autodetection.

AD_P60_EN Enable Autodetection of PAL-60, Address 0x07 [4]

0—Disables the autodetection of PAL systems with a 60 Hz field rate.

1 (default)—Enables autodetection.

Second, there was a design change in Analog Devices encoders from ADV717x to ADV719x. The older versions used the SFL (GenLock Telegram) bit directly, while the later ones invert the bit prior to using it. The reason for this is that the inversion compensated for the 1-line delay of an SFL (GenLock Telegram) transmission.

As a result, ADV717x encoders need the PAL switch bit in the SFL (GenLock Telegram) to be 1 for NTSC to work. Also, the ADV7190/ADV7191/ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC. If the state of the PAL switch bit is wrong, a 180°phase shift occurs.

AD_PALN_EN Enable Autodetection of PAL-N, Address 0x07 [3]

0—Disables the autodetection of the PAL -N standard.

1 (default)—Enables autodetection.

AD_PALM_EN Enable Autodetection of PAL-M, Address 0x07 [2]

0—Disables the autodetection of PAL-M.

1 (default)—Enables autodetection.

AD_NTSC_EN Enable Autodetection of NTSC, Address 0x07 [1]

0—Disables the autodetection of standard NTSC.

1 (default)—Enables autodetection.

AD_PAL_EN Enable Autodetection of PAL, Address 0x07 [0]

0—Disables the autodetection of standard PAL.

1 (default)—Enables autodetection.

Subcarrier Frequency Lock Inversion

The SFL_INV bit controls the behavior of the PAL switch bit in the SFL (GenLock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves two problems.

First, the PAL switch bit is only meaningful in PAL. Some encoders (including Analog Devices encoders) also look at the state of this bit in NTSC.

SELECT THE RAW LOCK SIGNAL SRLS

TIME_WIN

FREE_RUN

LOCK

1 0

COUNTER OUT OF LOCK

In a decoder/encoder back-to-back system in which SFL is used, this bit must be set up properly for the specific encoder used.

SFL_INV Address 0x41 [6]

0 (default)—Makes the part SFL-compatible with ADV7190/ ADV7191/ADV7194 and ADV73xx encoders.

1—Makes the part SFL-compatible with ADV717x encoders.

Lock-Related Controls

Lock information is presented to the user through Bits [1:0] of the Status 1 register. See the section. available to influence the way the lock status information is generated.

SRLS Select Raw Lock Signal, Address 0x51 [6]

Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits [1:0] in the Status 1 register).

The time_win signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quite quickly.

The free_run signal evaluates the properties of the incoming video over several fields, and takes vertical synchronization information into account.

0 (default)—Selects the free_run signal.

1—Selects the time_win signal.

FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0]

COUNTER INTO LOCK

STATUS_1[7:0] Address 0x10 [7:0]

Figure 13 outlines the signal flow and the controls

STATUS 1 [0]

MEMORY

STATUS 1 [1]

TAKE F

LOCK INTO ACCOUNT

FSCLE

Figure 13. Lock-Related Signal Path

Rev. 0 | Page 24 of 112

05478-013

ADV7188

FSCLE Fsc Lock Enable, Address 0x51 [7]

The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits [1:0] in STATUS_1. This bit must be set to 0 when operating in YPrPb component mode to generate a reliable HLOCK status bit.

0 (default)—Makes the overall lock status dependent on the horizontal sync lock.

1—Makes the overall lock status dependent on the horizontal sync lock and Fsc lock.

VS_Coast[1:0], Address 0xF9 [3:2]

These bits are used to set VS free-run (coast) frequency.

Table 25. VS_COAST[1:0] function

VS_COAST [1:0] Description

00 (default)

01 Forces 50 Hz coast Mode 10 Forces 60 Hz coast Mode 11 Reserved

Auto coast Mode – follows VS frequency from last video input

Table 27. COL Function

COL[2:0] Description

000 1 001 2 010 5 011 10 100 (default) 100 101 500 110 1000 111 100000

ST_NOISE_VLD, HS Tip Noise Measurement Valid, Address 0xDE [3] (read only)

0—The ST_NOISE[10:0] measurement is not valid

1 (default)—The ST_NOISE[10:0] measurement is valid.

ST_NOISE[10:0] HS Tip Noise Measurement, Address 0xDE [2:0], 0xDF [7:0]

The ST_NOISE[10:0] measures, over four fields, a readback value of the average of the noise in the HSYNC tip. ST_NOISE_VLD must be 1 for this measurement to be valid.

CIL[2:0] Count Into Lock, Address 0x51 [2:0]

CIL[2:0] determines the number of consecutive lines for which the into-lock condition must be true before the system switches into the locked state, and reports this via STATUS_1[1:0]. It counts the value in lines of video.

Table 26. CIL Function

CIL[2:0] Description

000 1 001 2 010 5 011 10 100 (default) 100 101 500 110 1000 111 100000

COL[2:0] Count Out of Lock, Address 0x51 [5:3]

COL[2:0] determines the number of consecutive lines for which the out-of-lock condition must be true before the system switches into unlocked state, and reports this via STATUS_0[1:0]. It counts the value in lines of video.

1 bit of ST_NOISE[10:0] = 1 ADC code.

1 bit of ST_NOISE[10:0] = 1.6 V/4096 = 390.625 μV.

COLOR CONTROLS

These registers allow the user to control the picture appearance, including control of the active data in the event of video being lost. These controls are independent of any other controls. For instance, brightness control is independent of picture clamping, although both controls affect the signal’s dc level.

CON[7:0] Contrast Adjust, Address 0x08 [7:0]

This register allows the user to adjust the contrast of the picture.

Table 28. CON Function

CON[7:0] Description

0x80 (default) Gain on luma channel = 1 0x00 Gain on luma channel = 0 0xFF Gain on luma channel = 2

SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address 0xE3 [7:0]

This register allows the user to control the gain of the Cb channel only. The user can adjust the saturation of the picture.

Table 29. SD_SAT_Cb Function

SD_SAT_Cb[7:0] Description

0x80 (default) Gain on Cb channel = 1 0x00 Gain on Cb channel = 0 0xFF Gain on Cb channel = 2

Rev. 0 | Page 25 of 112

ADV7188

SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4 [7:0]

This register allows the user to control the gain of the Cr channel only. The user can adjust the saturation of the picture.

Table 30. SD_SAT_Cr Function

SD_SAT_Cr[7:0] Description

0x80 (default) Gain on Cr channel = 1 0x00 Gain on Cr channel = 0 0xFF Gain on Cr channel = 2

SD_OFF_Cb[7:0] SD Offset Cb Channel, Address 0xE1 [7:0]

This register allows the user to select an offset for data on the Cb channel only and adjust the hue of the picture. There is a functional overlap with the HUE[7:0] register.

Table 31. SD_OFF_Cb Function

SD_OFF_Cb[7:0] Description

0x80 (default) 0 offset applied to the Cb channel. 0x00 −568 mV offset applied to the Cb channel. 0xFF +568 mV offset applied to the Cb channel.

SD_OFF_Cr [7:0] SD Offset Cr Channel, Address 0xE2 [7:0]

This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture. There is a functional overlap with the HUE[7:0] register.

Table 32. SD_OFF_Cr Function

SD_OFF_Cr[7:0] Description

0x80 (default) 0 offset applied to the Cr channel. 0x00 −568 mV offset applied to the Cr channel. 0xFF +568 mV offset applied to the Cr channel.

BRI[7:0] Brightness Adjust, Address 0x0A [7:0]

This register controls the brightness of the video signal. It allows the user to adjust the brightness of the picture.

Table 33. BRI Function

BRI[7:0] Description

0x00 (default) Offset of the luma channel = 0mV 0x7F Offset of the luma channel = +204mV 0x80 Offset of the luma channel = −204mV

HUE[7:0] Hue Adjust, Address 0x0B [7:0]

This register contains the value for the color hue adjustment. It allows the user to adjust the hue of the picture.

HUE[7:0] has a range of ±90°, with 0x00 equivalent to an adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.

Table 34. HUE Function

HUE[7:0] Description 0x00 (default) Phase of the chroma signal = 0°. 0x7F Phase of the chroma signal = +90°. 0x80 Phase of the chroma signal = −90°.

DEF_Y[5:0] Default Value Y, Address 0x0C [7:2]

If the ADV7188 loses lock on the incoming video signal or if there is no input signal, the DEF_Y[5:0] bits allow the user to specify a default luma value to be output. The register is used under the following conditions:

• If DEF_VAL_AUTO_EN bit is set to high and the

ADV7188 loses lock to the input video signal. This is the intended mode of operation (automatic mode).

• The DEF_VAL_EN bit is set, regardless of the lock status of

the video decoder. This is a forced mode that may be useful during configuration.

The DEF_Y[5:0] values define the 6 MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 10-bit mode, the output is Y[9:0] = {DEF_Y[5:0], 0, 0, 0, 0}.

The value for Y is set by the DEF_Y[5:0] bits. A value of 0x0D produces a blue color in conjunction with the DEF_C[7:0] default setting.

DEF_C[7:0] Default Value C, Address 0x0D [7:0]

The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the 4 MSBs of Cr and Cb values to be output if

• The DEF_VAL_AUTO_EN bit is set to high and the

ADV7188 can’t lock to the input video (automatic mode).

• DEF_VAL_EN bit is set to high (forced output).

The data that is finally output from the ADV7188 for the chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0}.

In full 10-bit output mode, two extra LSBs of value 00 are appended.

The values for Cr and Cb are set by the DEF_C[7:0] bits. A value of 0x7C produces a blue color in conjunction with the DEF_Y[5:0] default setting.

The hue adjustment value is fed into the AM color demodulation block. Therefore, it only applies to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb).

Rev. 0 | Page 26 of 112

ADV7188

DEF_VAL_EN Default Value Enable, Address 0x0C [0]

This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. In this mode, the decoder also outputs a stable 27 MHz clock, HS, and VS.

0 (default)—Outputs a colored screen determined by userprogrammable Y, Cr, and Cb values when the decoder freeruns. Free-run mode is turned on and off by the DEF_VAL_AUTO_EN bit.

1—Forces a colored screen output determined by userprogrammable Y, Cr, and Cb values. This overrides picture data even if the decoder is locked.

DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C [1]

This bit enables the automatic use of the default values for Y, Cr, and Cb when the ADV7188 cannot lock to the video signal.

0—Disables free-run mode. If the decoder is unlocked, it outputs noise.

1 (default)—Enables free-run mode. A colored screen set by the user-programmable Y, Cr, and Cb values is displayed when the decoder loses lock.

CLAMP OPERATION

The input video is ac-coupled into the ADV7188 through a

0.1 μF capacitor. It is recommended that the range of the input video signal is 0.5 V to 1.6 V (typically 1 V exceeds this range, it cannot be processed correctly in the decoder. Since the input signal is ac-coupled into the decoder, its dc value needs to be restored. This process is referred to as clamping the video. This section explains the general process of clamping on the ADV7188 and shows the different ways in which a user can configure its behavior.

The ADV7188 uses a combination of current sources and a digital processing block for clamping, as shown in The analog processing channel shown is replicated three times inside the IC. While only one single-channel (and only one ADC) is needed for a CVBS signal, two independent channels are needed for YC (S-VHS) type signals, and three independent channels are needed to allow component signals (YPrPb) to be processed.

The clamping can be divided into two sections

• Clamping before the ADC (analog domain): current

sources.

p-p). If the signal

Figure 14.

The ADCs can digitize an input signal only if it resides within their 1.6 V input voltage range. An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range.

The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range.

After digitization, the digital fine clamp block corrects for any remaining variations in dc level. Since the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations may occur. Furthermore, dynamic changes in the dc level almost certainly lead to visually objectionable artifacts, and must therefore be prohibited.

The clamping scheme must be able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation.

To quickly acquire an unknown video signal, the large current clamps may be activated. It is assumed that the amplitude of the video signal at this point is of a nominal value. Control of the coarse and fine current clamp parameters is automatically performed by the decoder.

Standard definition video signals may have excessive noise on them. In particular, CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mV). A voltage clamp would be unsuitable for this type of video signal. Instead, the ADV7188 uses a set of four current sources that can cause coarse (>0.5 mA) and fine (<0.1 mA) currents to flow into and away from the high impedance node that carries the video signal (see Figure 14).

The following sections describe the I

C signals that can be used to

influence the behavior of the clamping block on the ADV7188.

CCLEN Current Clamp Enable, Address 0x14 [4]

The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether. This may be useful if the incoming analog video signal is clamped externally.

0—The current sources are switched off.

1 (default)—The current sources are enabled.

• Clamping after the ADC (digital domain): digital

processing block.

Rev. 0 | Page 27 of 112

ADV7188

FINE CURRENT SOURCES

COARSE CURRENT SOURCES

NALO

VIDEO

INPUT

ADC

Figure 14. Clamping Overview

DCT[1:0] Digital Clamp Timing, Address 0x15 [6:5]

The clamp timing register determines the time constant of the digital fine clamp circuitry. It is important to realize that the digital fine clamp reacts very quickly since it is supposed to immediately correct any residual dc level error for the active line. The time constant of the digital fine clamp must be much quicker than the one from the analog blocks.

By default, the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal.

Table 35. DCT Function

DCT[1:0] Description

00 Slow (TC = 1 sec). 01 Medium (TC = 0.5 sec). 10 (default) Fast (TC = 0.1 sec). 11

Determined by the ADV7188, depending on the I/P video parameters.

DCFE Digital Clamp Freeze Enable, Address 0x15 [4]

This register bit allows the user to freeze the digital clamp loop at any time. It is intended for users who would like to do their own clamping. Users should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the DCFE bit.

0 (default)—The digital clamp is operational.

1—The digital clamp loop is frozen.

LUMA FILTER

Data from the digital fine clamp block is processed by three sets of filters. The data format at this point is CVBS for CVBS input or luma only for Y/C and YPrPb input formats.

• Luma antialias filter (YAA). The ADV7188 receives video

at a rate of 27 MHz. (For 4× oversampled video, the ADCs sample at 54 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the ADV7188 is always 27 MHz.) The ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video using a high quality, linear phase, low-pass filter that preserves the luma signal while at the same time attenuating out-of-band components. The luma antialias filter has a fixed response.

DATA

PRE-

PROCESSOR

(DPP)

CLAMP CONTROL

SDP

WITH DIGITAL

FINE CLAMP

05478-014

• Luma shaping filters (YSH). The shaping filter block is a

programmable low-pass filter with a wide variety of responses. It can be used to selectively reduce the luma video signal bandwidth (needed prior to scaling, for example). For some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. A follow-on video compression stage may work more efficiently if the video is low-pass filtered.

The ADV7188 has two responses for the shaping filter: one that is used for good quality CVBS, component, and S-VHS type sources, and a second for nonstandard CVBS signals. The YSH filter responses also include a set of notches for PAL and NTSC. However, it is recommended to use the comb filters for YC separation.

• Digital resampling filter. This block is used to allow dynamic

resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system with no requirement for user intervention.

Figure 16 through Figure 19 show the overall response of all filters together. Unless otherwise noted, the filters are set into a typical wideband mode.

Y-Shaping Filter

For input signals in CVBS format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. YC separation must aim for best possible crosstalk reduction while still retaining as much bandwidth (especially on the luma component) as possible. High quality YC separation can be achieved by using the internal comb filters of the ADV7188. Comb filtering, however, relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (Fsc). For good quality CVBS signals, this relationship is known; the comb filter algorithms can be used to separate out luma and chroma with high accuracy.

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ADV7188

For nonstandard video signals, the frequency relationship may be disturbed and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of the shaping filter block.

An automatic mode is provided. Here, the ADV7188 evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to manually override the automatic decisions in part or in full.

The luma shaping filter has three control registers

• YSFM[4:0] allows the user to manually select a shaping

filter mode (applied to all video signals) or to enable an automatic selection (dependent on video quality and video standard).

• WYSFMOVR allows the user to manually override the

WYSFM decision.

• WYSFM[4:0] allows the user to select a different shaping

filter mode for good quality CVBS, component (YPrPb), and S-VHS (YC) input signals.

In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources (since they can successfully be combed) and for luma components of YPrPb and YC sources, since they need not be combed. For poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation in order to reduce visual artifacts. The decisions of the control logic are shown in

Figure 15.

YSFM[4:0] Y Shaping Filter Mode, Address 0x17 [4:0]

The Y-shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters. When switched in automatic mode, the filter is selected based on other register selections, such as detected video standard, and properties extracted from the incoming video itself, such as quality and time base stability. The automatic selection always picks the widest possible bandwidth for the video input encountered.

• If the YSFM settings specify a filter (that is, YSFM is set to

values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality.

• In automatic selection mode, the notch filters are used

only for bad quality video signals. For all other video signals, wideband filters are used; see

Table 36.

WYSFMOVR Wideband Y Shaping Filter Override, Address 0x18,[7]

Setting the WYSFMOVR bit enables the use of the WYSFM[4:0] settings for good quality video signals. For more information, refer to the general discussion of the luma shaping filters in the Y-Shaping Filter section and the flowchart shown in Figure 15.

0—The shaping filter for good quality video signals is selected automatically.

1 (default)—Enables manual override via WYSFM[4:0].

Table 36. YSFM Function

YSFM[4:0] Description

00000

00001 (default)

00010 SVHS 1 00011 SVHS 2 00100 SVHS 3 00101 SVHS 4 00110 SVHS 5 00111 SVHS 6 01000 SVHS 7 01001 SVHS 8 01010 SVHS 9 01011 SVHS 10 01100 SVHS 11 01101 SVHS 12 01110 SVHS 13 01111 SVHS 14 10000 SVHS 15 10001 SVHS 16 10010 SVHS 17 10011 SVHS 18 (CCIR 601) 10100 PAL NN 1 10101 PAL NN 2 10110 PAL NN 3 10111 PAL WN 1 11000 PAL WN 2 11001 NTSC NN 1 11010 NTSC NN 2 11011 NTSC NN 3 11100 NTSC WN 1 11101 NTSC WN 2 11110 NTSC WN 3 11111 Reserved

Automatic selection including a wide notch response (PAL/NTSC/SECAM)

Automatic selection including a narrow notch response (PAL/NTSC/SECAM)

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ADV7188

SET YSFM

YES NO

VIDEO

BAD GOOD

AUTO SELECT LUMA

SHAPING FILTER TO

COMPLEMENT COMB

QUALITY

1 0

SELECT WIDEBAND

FILTER AS PER

WYSFM[4:0]

Figure 15. YSFM and WYSFM Control Flowchart

WYSFM[4:0] Wide Band Y Shaping Filter Mode, Address 0x18 [4:0]

The WYSFM[4:0] bits allow the user to manually select a shaping filter for good quality video signals, for example, CVBS with stable time base, luma component of YPrPb, and luma component of YC. The WYSFM bits are only active if the WYSFMOVR bit is set to 1. See the general discussion of the shaping filter settings in the

Y-Shaping Filter section.

Table 37. WYSFM Function

WYSFM[4:0] Description

00000 Do not use 00001 Do not use 00010 SVHS 1 00011 SVHS 2 00100 SVHS 3 00101 SVHS 4 00110 SVHS 5 00111 SVHS 6 01000 SVHS 7 01001 SVHS 8 01010 SVHS 9 01011 SVHS 10 01100 SVHS 11 01101 SVHS 12 01110 SVHS 13 01111 SVHS 14 10000 SVHS 15 10001 SVHS 16 10010 SVHS 17 10011 (default) SVHS 18 (CCIR 601) 10100–11111 Do not use

The filter plots in S-VHS 18 (widest) shaping filter settings.

Figure 16 show the S-VHS 1 (narrowest) to

Figure 18 shows the PAL notch filter responses. The NTSC-compatible notches are shown in

Figure 19.

YSFM IN AUTO MODE?

00000 OR 00001

WYSFMOVR

SELECT AUTOMATIC

USE YSFM SELECTED

FILTER REGARDLESS FOR

GOOD AND BAD VIDEO

WIDEBAND FILTER

–10

–20

–30

–40

AMPLITUDE (dB)

–50

–60

–70

010864212

COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,

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Y RESAMPLE

FREQUENCY (MHz)

Figure 16. Y S-VHS Combined Responses

COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,

–20

–40

–60

AMPLITUDE (dB)

–80

–100

–120

010864212

Y RESAMPLE

FREQUENCY (MHz)

Figure 17. Y S-VHS 18 Extra Wideband Filter (CCIR 601-Compliant)

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Rev. 0 | Page 30 of 112

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ANALOG DEVICES ADV7188 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual