ANALOG DEVICES ADV7184 Service Manual

Multiformat SDTV Video Decoder

FEATURES

Multiformat video decoder supports NTSC (J/M/4.43),

PAL (B/D/G/H/I/M/N), SECAM Integrates four 54 MHz, 10-bit ADCs SCART fast blank support Clocked from a single 28.63636 MHz crystal Line-locked clock-compatible (LLC) Adaptive Digital Line Length Tracking (ADLLT™), signal

processing, and enhanced FIFO management give

mini-TBC functionality 5-line adaptive comb filters Proprietary architecture for locking to weak, noisy, and

unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated automatic gain control (AGC) with adaptive peak

white mode Macrovision® copy protection detection Chroma transient improvement (CTI) Digital noise reduction (DNR) Multiple programmable analog input formats

CVBS (composite video)

Y/C (S-video)

YPrPb (component) (VESA, MII, SMPTE, and BETACAM) 12 analog video input channels Integrated antialiasing filters Programmable interrupt request output pin Automatic NTSC/PAL/SECAM identification

GENERAL DESCRIPTION

with Fast Switch Overlay Support

ADV7184

Digital output formats (8-bit or 16-bit)

ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD

0.5 V to 1.6 V analog signal input range Differential gain: 0.5% typical Differential phase: 0.5° typical Programmable video controls

Peak white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free-run mode (generates stable video output with no input) VBI decode support for close captioning (including Gemstar®

1×/2× (XDS)), WSS, CGMS, teletext, VITC, VPS Power-down mode 2-wire serial MPU interface (I

3.3 V analog, 1.8 V digital core, 3.3 V input/output supply Industrial temperature grade: −40°C to +85°C 80-lead, Pb-free LQFP

APPLICATIONS

High end DVD recorders Video projectors HDD-based PVRs/DVDRs LCD T Vs Set-top boxes Security systems Digital televisions AVR rece ivers

C® compatible)

The ADV7184 integrated video decoder automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC, PAL, and SECAM standards into 4:2:2 component video data compatible with 16- or 8-bit CCIR 601/CCIR 656.

The advanced, highly flexible digital output interface enables performance video decoding and conversion in line-locked, clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security and surveillance cameras, and professional systems.

The accurate 10-bit ADC provides professional quality video performance and is unmatched. This allows true 8-bit resolution in the 8-bit output mode.

The 12 analog input channels accept standard composite, S-video, and component video signals in an extensive number of combinations.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AGC and clamp-restore circuitry allow an input video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively, these can be bypassed for manual settings.

The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise, accurate sampling and digital filtering. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ±5% variation in line length. The output control signals allow glueless interface connections in most applications. The ADV7184 modes are set up over a 2-wire, serial, bidirectional port (I

C compatible).

SCART and overlay functionality are enabled by the ability of the ADV7184 to process CVBS and standard definition RGB signals simultaneously. Signal mixing is controlled by the fast blank pin. The ADV7184 is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. It is packaged in a small, Pb-free, 80-lead LQFP.

ADV7184

TABLE OF CONTENTS

Features.............................................................................................. 1

Global Status Registers .............................................................. 23

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Introduction ...................................................................................... 4

Analog Front End......................................................................... 4

Standard Definition Processor (SDP)........................................ 4

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Electrical Characteristics ............................................................. 5

Video Specifications..................................................................... 6

Analog Specifications................................................................... 6

Thermal Specifications ................................................................ 7

Timing Specifications .................................................................. 7

Timing Diagrams.......................................................................... 8

Absolute Maximum Ratings............................................................ 9

Standard Definition Processor (SDP).......................................... 24

SD Luma Path ............................................................................. 24

SD Chroma Path......................................................................... 24

Sync Processing .......................................................................... 25

VBI Data Recovery..................................................................... 25

General Setup.............................................................................. 25

Color Controls............................................................................ 28

Clamp Operation........................................................................ 30

Luma Filter.................................................................................. 31

Chroma Filter.............................................................................. 34

Gain Operation........................................................................... 35

Chroma Transient Improvement (CTI) .................................. 39

Digital Noise Reduction (DNR) and Luma Peaking Filter... 39

Comb Filters................................................................................ 40

AV Code Insertion and Controls ............................................. 43

Package Thermal Performance................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Analog Front End........................................................................... 12

Analog Input Muxing ................................................................ 13

Manual Input Muxing................................................................ 15

XTAL Clock Input Pin Functionality.......................................16

28.63636 MHz Crystal Operation............................................ 16

Antialiasing Filters .....................................................................16

SCART and Fast Blanking......................................................... 16

Fast Blank Control...................................................................... 17

Global Control Registers ............................................................... 21

Power-Saving Modes.................................................................. 21

Reset Control .............................................................................. 21

Global Pin Control..................................................................... 21

Synchronization Output Signals............................................... 45

Sync Processing .......................................................................... 53

VBI Data Decode ....................................................................... 53

C Interface ................................................................................ 60

Standard Detection and Identification.................................... 62

C Readback Registers.............................................................. 64

Pixel Port Configuration ............................................................... 79

Pixel Port–Related Controls...................................................... 79

MPU Port Description................................................................... 80

C Sequencer.............................................................................. 81

C Programming Examples ..................................................... 81

C Register Maps........................................................................... 82

User Map ..................................................................................... 82

Rev. A | Page 2 of 112

ADV7184

User Sub Map...............................................................................99

Digital Inputs.............................................................................110

PCB Layout Recommendations ................................................. 109

Analog Interface Inputs........................................................... 109

Power Supply Decoupling....................................................... 109

PLL ............................................................................................. 109

Digital Outputs (Both Data and Clocks) .............................. 109

REVISION HISTORY

2/07—Rev. 0 to Rev. A

Corrected Register and Bit Names................................... Universal

Change to Features............................................................................1

Changes to Pin Configuration and

Function Descriptions Section.................................................10

Change to Table 9 ............................................................................14

Change to Table 17 ..........................................................................22

Changes to Table 24 ........................................................................25

Changes to SFL_INV, Address 0x41 [6] Section.........................26

Change to Table 35 ..........................................................................31

Change to Table 40 ..........................................................................36

Change to LAGT [1:0], Luma Automatic Gain Timing,

Address 0x2F [7:6] Section .......................................................36

Change to NVBIOLCM [1:0], NTSC VBI Odd Field Luma

Comb Mode, Address 0xEB [7:6] Section ..............................43

Change to NVBIELCM [1:0], NTSC VBI Even Field Luma

Comb Mode, Address 0xEB [5:4] Section ..............................43

Change to NVBIOCCM [1:0], NTSC VBI Odd Field Chroma

Comb Mode, Address 0xEC [7:6] Section..............................43

Change to NVBIECCM [1:0], NTSC VBI Even Field Chroma

Comb Mode, Address 0xEC [5:4] Section..............................43

Changes to NEWAVMODE, New AV Mode,

Address 0x31 [4] Section...........................................................47

Change to Table 69 ..........................................................................56

Added Standard Detection and Identification Section ..............62

Changes to MPU Port Description Section.................................80

Changes to I

Change to Table 104........................................................................82

Changes to Table 105 ......................................................................84

Change to Table 107......................................................................101

C Programming Examples Section........................81

XTAL and Load Capacitor Values Selection .........................110

Typical Circuit Connection .........................................................111

Outline Dimensions......................................................................112

Ordering Guide.........................................................................112

7/05—Revision 0: Initial Version

Rev. A | Page 3 of 112

ADV7184

INTRODUCTION

The ADV7184 is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-video, and component video into a digital ITU-R BT.656 format.

The advanced, highly flexible digital output interface enables performance video decoding and conversion in line-locked, clockbased systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security and surveillance cameras, and professional systems.

ANALOG FRONT END

The ADV7184 analog front end includes four 10-bit ADCs that digitize the analog video signal before applying it to the standard definition processor (SDP). The analog front end uses differential channels for each ADC to ensure high performance in mixedsignal applications.

The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7184. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7184. The ADCs are configured to run in 4× oversampling mode.

The ADV7184 has optional antialiasing filters on each of the four input channels. The filters are designed for standard definition (SD) video with approximately 6 MHz bandwidth.

SCART and overlay functionality are enabled by the ability of the ADV7184 to process CVBS and standard definition RGB signals simultaneously. Signal mixing is controlled by the fast blank (FB) pin.

FUNCTIONAL BLOCK DIAGRAM

AIN1 TO

AIN12

SCLK

SDA

ALSB

INPUT

MUX

CVBS, S-VIDEO ,

YPrPb, OR

SCART (RGB AND CVBS)

SYNC PROCESSI NG AND

CLOCK GENERAT ION

CONTROL AND V BI DATA

ANTI-

ALIAS

CLAMP

FILTER

ANTI-

ALIAS

CLAMP

FILTER

ANTI-

ALIAS

CLAMP

FILTER

ANTI-

ALIAS

CLAMP

FILTER

SERIAL INT ERFACE

A/D

SYNC AND

CLK CONTROL

ADV7184

DATA

PREPROCESSO R

DECIMATIO N AND

DOWNSAMPL ING

FILTERS

CONTROL

AND DATA

CVBS

C Cr Cb R G

COLOR SPACE

CONVERSION

VBI DATA RECOVERY

CVBS/Y

RECOVERY

MACROVISIO N

DETECTIO N

Figure 1.

STANDARD DEFINITION PROCESSOR (SDP)

The ADV7184 is capable of decoding a large selection of baseband video signals in composite, S-video, and component formats. The video standards that are supported include PAL B/D/I/G/H, PAL 60, PA L M, PAL N , PAL Nc, N T S C M/J, NT S C 4.43 , a nd SECAM B/D/G/K/L. The ADV7184 can automatically detect the video standard and process it accordingly.

The ADV7184 has a 5-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7184.

The ADV7184 implements the patented ADLLT algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7184 to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs, VCD players, and camcorders. The ADV7184 contains a CTI processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions.

The ADV7184 can process a variety of VBI data services, such as closed captioning (CC), wide-screen signaling (WSS), copy generation management system (CGMS), Gemstar® 1×/2×, extended data service (XDS), and teletext. The ADV7184 is fully Macrovision certified; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs.

STANDARD DEFINI TION PRO CESSOR

LUMA

2D COMB (5H MAX)

CHROMA 2D COMB

(4H MAX)

SYNTHESIZED LLC CONT ROL

FREE-RUN

OUTPUT CO NTROL

FAST

BLANK OVERLAY CONTROL

AND

AV CODE

INSERTION

CHROMA

DEMOD

LUMA

FILTER

SYNC

EXTRACT

CHROMA

FILTER

GLOBAL CO NTROL

STANDARD

AUTODETECTION

LUMA

RESAMPLE

CONTROL

CHROMA

RESAMPLE

Y Cr Cb

PIXEL DATA

P15 TO P P7 TO P0

FIELD

LLC1

OUTPUT FO RMATTER

LLC2

SFL

INT

05479-001

Rev. A | Page 4 of 112

ADV7184

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

= 3.15 V to 3.45 V, D

VDD

Operating temperature range, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions Min Typ Max Unit

STATIC PERFORMANCE

Resolution (Each ADC) N 10 Bits Integral Nonlinearity INL BSL at 54 MHz −0.6/+0.7 ±3 LSB Differential Nonlinearity DNL BSL at 54 MHz −0.5/+0.5 −0.99/+2.5 LSB

DIGITAL INPUTS

Input High Voltage Input Low Voltage Input Current

6, 7

−10 +10 μA Input Capacitance

DIGITAL OUTPUTS

Output High Voltage Output Low Voltage High Impedance Leakage Current I Output Capacitance

POWER REQUIREMENTS

Digital Core Power Supply D Digital Input/Output Power Supply D PLL Power Supply P Analog Power Supply A Digital Core Supply Current I Digital Input/Output Supply Current I PLL Supply Current I Analog Supply Current I YPrPb input Power-Down Current I Power-Up Time t

All ADC linearity tests performed with the input range at full scale − 12.5% and at zero scale + 12.5%.

Maximum INL and DNL specifications obtained with the part configured for component video input.

Temperature range T

To obtain specified VIH level on Pin 29, Register 0x13 (write only) must be programmed with Value 0x04. If Register 0x13 is programmed with Value 0x00, then V

To obtain specified VIL level on Pin 29, Register 0x13 (write only) must be programmed with Value 0x04. If Register 0x13 is programmed with Value 0x00, then V

Pins 36 and 79.

Excluding all TEST pins (TEST0 to TEST12)

VOH and VOL levels obtained using default drive strength value (0xD5) in Register 0xF4.

Guaranteed by characterization.

Only ADC0 is powered on.

All four ADCs powered on.

to T

MIN

= 1.65 V to 2.0 V, D

VDD

1, 2, 3

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V, nominal input range 1.6 V.

VDD

VIH 2 V VIL 0.8 V IIN −50 +50 μA

CIN 10 pF

, −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.

MAX

VOH I VOL I

10 μA

LEAK

20 pF

OUT

= 0.4 mA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

1.65 1.8 2 V

VDD

3.0 3.3 3.6 V

VDDIO

1.71 1.8 1.89 V

VDD

3.15 3.3 3.45 V

VDD

105 mA

DVDD

4 mA

DVDDIO

11 mA

PVDD

CVBS input

AVDD

0.65 mA

PWRDN

20 ms

PWRUP

99 mA 269 mA

on Pin 29 is 1.2 V.

on Pin 29 is 0.4 V.

Rev. A | Page 5 of 112

ADV7184

VIDEO SPECIFICATIONS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise noted).

Table 2.

Parameter

1, 2

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulate five steps 0.5 0.7 Degree Differential Gain DG CVBS input, modulate five steps 0.5 0.7 % Luma Nonlinearity LNL CVBS input, five steps 0.5 0.7 %

NOISE SPECIFICATIONS

SNR Unweighted Luma ramp 54 56 dB Luma flat field 56 58 dB Analog Front End Crosstalk 60 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range −5 +5 % Vertical Lock Range 40 70 Hz FSC Subcarrier Lock Range ±1.3 Hz Color Lock-In Time 60 Lines Sync Depth Range

Color Burst Range 5 200 % Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines

CHROMA SPECIFICATIONS

Hue Accuracy HUE 1 Degree Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.5 % Chroma Phase Error 0.4 Degree Chroma Luma Intermodulation 0.2 %

LUMA SPECIFICATIONS

Luma Brightness Accuracy CVBS, 1 V input 1 % Luma Contrast Accuracy CVBS, 1 V input 1 %

Temperature range T

Guaranteed by characterization.

Nominal sync depth is 300 mV at 100% sync depth range.

to T

MIN

MAX

ANALOG SPECIFICATIONS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise noted). Recommended analog input video signal range is 0.5 V to 1.6 V, typically 1 V p-p.

Table 3.

Parameter

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF Input Impedance Input Impedance of Pin 40 (FB) 20 kΩ Large-Clamp Source Current 0.75 mA Large-Clamp Sink Current 0.75 mA Fine-Clamp Source Current 17 μA Fine-Clamp Sink Current 17 μA

Temperature range T

Guaranteed by characterization.

Except Pin 40 (FB).

1, 2

to T

MIN

MAX

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

Symbol Test Conditions Min Typ Max Unit

20 200 %

is −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

Symbol Test Condition Min Typ Max Unit

Clamps switched off 10 MΩ

is −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.

Rev. A | Page 6 of 112

ADV7184

THERMAL SPECIFICATIONS

Table 4.

Parameter Symbol Test Conditions Min Typ Max Unit

Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane 7.6 °C/W Junction-to-Ambient Thermal Resistance (Still Air) θJA 4-layer PCB with solid ground plane 38.1 °C/W

TIMING SPECIFICATIONS

= 3.15 V to 3.45 V, D

VDD

otherwise noted).

Table 5.

Parameter

1, 2

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency 28.63636 MHz Frequency Stability ±50 ppm

I2C PORT

SCLK Frequency 400 kHz SCLK Minimum Pulse Width High t1 0.6 μs SCLK Minimum Pulse Width Low t2 1.3 μs Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 μs

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC1 Mark-Space Ratio t9:t10 45:55 55:45 % duty cycle LLC1 Rising to LLC2 Rising t11 1 ns LLC1 Rising to LLC2 Falling t12 1 ns

DATA AND CONTROL OUTPUTS

Data Output Transitional Time

Propagation Delay to High-Z t15 6 ns Max Output Enable Access Time t16 7 ns Min Output Enable Access Time t17 4 ns

Temperature range T

Guaranteed by characterization.

TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.

SDP timing figures obtained using default drive strength value (0xD5) in Register 0xF4.

to T

MIN

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

Symbol Test Conditions Min Typ Max Unit

t13

t14

is −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.

MAX

Negative clock edge to start of valid data

= t10 − t13)

ACCESS

End of valid data to negative clock edge (t

= t9 + t14)

HOLD

3.6 ns

2.4 ns

Rev. A | Page 7 of 112

ADV7184

TIMING DIAGRAMS

05479-002

SDA

SCLK

Figure 2. I

C Timing

OUTPUT LLC1

OUTPUT LLC2

OUTPUTS P0 TO P15, VS,

HS, FIEL D,

SFL

Figure 3. Pixel Port and Control Output Timing

05479-003

05479-004

P0 TO P15, HS,

VS, FIELD,

SFL

Figure 4.

Timing

Rev. A | Page 8 of 112

ADV7184

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

to AGND 4 V

VDD

to DGND 2.2 V

VDD

to AGND 2.2 V

VDD

to DGND 4 V

VDDIO

to A

VDDIO

to D

VDD

VDDIO

to P

VDD

to D

VDD

Digital Inputs Voltage to DGND −0.3 V to D Digital Output Voltage to DGND −0.3 V to D Analog Inputs to AGND AGND − 0.3 V to A Maximum Junction Temperature

J max

−0.3 V to +0.3 V

VDD

−0.3 V to +0.3 V

VDD

to P

−0.3 V to +2 V

VDD

to D

−0.3 V to +2 V

VDD

−0.3 V to +2 V

VDD

−0.3 V to +2 V

VDD

125°C

)

VDDIO

+ 0.3 V + 0.3 V

VDD

+ 0.3 V

Storage Temperature Range −65°C to +150°C Infrared Reflow Soldering (20 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption the user is advised to turn off any unused ADCs when using the part.

The junction temperature must always stay below the maximum junction temperature (T following equation to calculate the junction temperature:

= T

+ (θJA × W

A max

max

where:

= 85°C.

A max

= 30°C/W.

W (P

max

VDD

= ((A

× I

PVDD

VDD

)).

× I

AV D D

) + (D

VDD

max) of 125°C. Use the

)

× I

) + (D

DVDD

VDDIO

× I

DVDDIO

) +

ESD CAUTION

Rev. A | Page 9 of 112

ADV7184

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FIELD79OE78TEST177TEST676P1275P1374P1473P1572DVDD71DGND70TEST069TEST468SCLK67SDA66ALSB65TEST764RESET63SOY62AIN661AIN12

DGND

DVDDIO

P11

P10

DGND

DVDD

INT

SFL

TEST2

DGND

DVDDIO

TEST8

TEST12

TEST11

PIN 1

21P522P423P324P225

ADV7184

TOP VIEW

(Not to Scale)

32P133P034

LLC227LLC1

XTAL

DVDD

TEST3

XTAL1

DGND

TEST9

TEST10

Figure 5. 80-Lead LQFP Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type Description

3, 9, 14, 31, 71 DGND G Digital Ground. 39, 47, 53, 56 AGND G Analog Ground. 4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V). 10, 30, 72 DVDD P Digital Core Supply Voltage (1.8 V). 50 AVDD P Analog Supply Voltage (3.3 V). 38 PVDD P PLL Supply Voltage (1.8 V). 42, 44, 46, 58,

60, 62, 41, 43,

AIN1 to AIN12

I Analog Video Input Channels.

45, 57, 59, 61 11

INT

Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video. See the User Sub Map register details in

40 FB I

Fast Blank. FB is a fast switch overlay input that switches between CVBS and RGB analog input signals.

70, 78, 13, 25, 69, 35, 34, 18, 17

TEST0 to TEST4,

Leave these pins unconnected.

TEST9 to TEST12

77, 65

TEST6,

Tie to AGND.

TEST7 16 TEST8 Tie to DVDDIO. 33, 32, 24 to 19,

P0 to P15 O Video Pixel Output Ports. 8 to 5, 76 to 73

2 HS O Horizontal Synchronization Output Signal. 1 VS O Vertical Synchronization Output Signal. 80 FIELD O Field Synchronization Output Signal.

PWRDN

ELPF

PVDD

AGND

Table 107.

AIN5

AIN11

AIN4

AIN10

AGND

CAPC2

CAPC1

AGND

CML

REFOUT

AVDD

CAPY2

CAPY1

AGND

AIN3

AIN9

AIN2

AIN8

AIN1

AIN7

05479-005

Rev. A | Page 10 of 112

ADV7184

Mnemonic Type Description Pin No.

67 SDA I/O I2C Port Serial Data Input/Output. 68 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. 66 ALSB I

27 LLC1 O

26 LLC2 O

29 XTAL I

28 XTAL1 O

37 ELPF I The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 52. 12 SFL O

63 SOY I

51 REFOUT O

52 CML O

48, 49

54, 55

RESET

PWRDN

CAPY1, CAPY2

CAPC1, CAPC2

I ADC Capacitor Network. Refer to Figure 52 for a recommended capacitor network for this pin.

I ADC Capacitor Network. Refer to

This pin selects the I a write to 0x40; set to Logic 1 sets the address to 0x42.

System Reset Input (active low). A minimum low reset pulse width of 5 ms is required to reset the ADV7184 circuitry.

Line-Locked Clock 1. This is a line-locked output clock for the pixel data output by the ADV7184. Nominally 27 MHz, but varies according to video line length.

Line-Locked Clock 2. This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7184. Nominally 13.5 MHz, but varies according to video line length.

Crystal Input. This is the input pin for the 28.63636 MHz crystal, or it can be overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external

3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7184. In crystal mode, the crystal must be a fundamental crystal.

Logic 0 on this pin places the ADV7184 in a power-down mode. Refer to the section for more options on power-down modes for the ADV7184.

When set to Logic 0, OE pin places P15 to P0, HS, VS, and SFL into a high impedance state.

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc., digital video encoder.

SYNC on Y. This input pin should only be used with the standard detection and identification function (see the signal of a component input for standard identification function.

Internal Voltage Reference Output. Refer to this pin.

Common-Mode Level. The CML pin is a common-mode level for the internal ADCs. Refer to Figure 52 for a recommended capacitor network for this pin.

Standard Detection and Identification section). This pin should be connected to the Y

C address for the ADV7184. ALSB set to Logic 0 sets the address for

I2C Register Maps

OE enables the pixel output bus, P15 to P0 of the ADV7184. Logic 1 on the

Figure 52 for a recommended capacitor network for

Figure 52 for a recommended capacitor network for this pin.

Rev. A | Page 11 of 112

ADV7184

ANALOG FRONT END

RGB_IP_SEL

INSEL[3:0]

AIN1

AIN7

AIN2

AIN8

AIN3

AIN9

AIN4

AIN10

AIN5

AIN11

AIN6

AIN12

ADC_SW_MAN_EN

AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12

PRIM_MODE[3:0]

SDM_SEL[1:0]

ADC0_SW[3:0]

ADC0

INTERNAL

MAPPING

FUNCTIONS

AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12

AIN2 AIN8 AIN5 AIN11 AIN6 AIN12 AIN4

AIN4

AIN7

Figure 6. Internal Pin Connections

ADC1_SW[3:0]

ADC2_SW[3:0]

ADC3_SW[3:0]

ADC1

ADC2

ADC3

5479-006

Rev. A | Page 12 of 112

ADV7184

ANALOG INPUT MUXING

The ADV7184 has an integrated analog muxing section that allows connecting more than one source of video signal to the decoder. muxing provided in the ADV7184.

As can be seen in controlled in two ways:

• By the functional register (INSEL). Using INSEL [3:0]

• By an I

Figure 7 shows an overview of the two methods of controlling input muxing.

Figure 6 outlines the overall structure of the input

Figure 6, the analog input muxes can be

simplifies the setup of the muxes and minimizes crosstalk between channels by preassigning the input channels. This is referred to as the recommended input muxing.

C manual override (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW, and ADC3_SW). This is provided for applications with special requirements, such as number/combinations of signals that are not served by the preassigned input connections. This is referred to as manual input muxing.

CONNECTING

ANALOG SIG NALS

TO ADV7184

Recommended Input Muxing

A maximum of 12 CVBS inputs can be connected and decoded by the ADV7184, meaning that the sources must be connected to adjacent pins on the IC, as seen in

Figure 5. This calls for a careful design of the PCB layout, for example, placing ground shielding between all signals routed through tracks that are physically close together.

SDM_SEL [1:0], Y/C and CVBS Autodetect Mode Select, Address 0x69 [1:0]

The SDM_SEL bits decide on input routing and whether INSEL [3:0] is used to govern input routing decisions.

The S-video/composite autodetection feature is enabled using SDM_SEL = 11.

Table 8. SDM_SEL [1:0]

SDM_SEL [1:0] Mode Analog Video Inputs

00 As per INSEL [3:0] As per INSEL [3:0] 01 CVBS AIN11 10 Y/C

Y = AIN10 C = AIN12

S-video/composite autodetection

CVBS = AIN11 Y = AIN11 C = AIN12

SEE TABLE 8 AND T ABLE 9?

YES

SET SDM_SEL[1:0] AND

INSEL[3: 0]

FOR REQUIRED MUXING

CONFIGURATION

Figure 7. Input Muxing Overview

RECOMMENDED

INPUT MUXING;

(ADC_SW_MAN_EN, ADC0_S W,

SET SDM_SEL[1:0] AND

INSEL[3:0] TO CONF IGURE

ADV7184 TO DECO DE

VIDEO FO RMAT:

CVBS: 0000

YC: 0110

YPrPb: 1001

SCART (CVBS/RG B): 1111

SET SDM_SEL[1:0] FO R

S-VIDEO/COMPOSITE

AUTODETECT

USE MANUAL INPUT MUXING

ADC1_SW, ADC2_SW,

ADC3_SW)

05479-007

Rev. A | Page 13 of 112

ADV7184

INSEL [3:0], Input Selection, Address 0x00 [3:0]

The INSEL bits allow the user to select the input channel and format. Depending on the PCB connections, only a subset of the INSEL modes is valid. INSEL [3:0] not only switches the analog input muxing, but also configures ADV7184 to process composite (CVBS), S-video (Y/C), or component (YPbPr/RGB) format signals.

The recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity.

Tabl e 10 summarizes how the PCB

layout should connect analog video signals to the ADV7184.

It is strongly recommended that users connect any unused analog input pins to AGND to act as a shield.

Connect the AIN7 to AIN11 inputs to AGND when only six input channels are used. This improves the quality of the sampling due to better isolation between the channels.

AIN12 is not controlled by INSEL [3:0]. It can be routed to ADC0/ADC1/ADC2 only by manual muxing. See

Tabl e 11

for details.

Table 9. Input Channel Switching Using INSEL [3:0]

INSEL [3:0]

0000 (default)

Analog Input Pins Video Format

CVBS1 = AIN1 B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

0001 CVBS2 = AIN2

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

0010 CVBS3 = AIN3

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

0011 CVBS4 = AIN4

Description

SCART (CVBS and R, G, B)

SCART (CVBS and R, G, B) B = AIN7 R = AIN8 G = AIN9

0100 CVBS1 = AIN5

SCART (CVBS and R, G, B) B = AIN7 R = AIN8 G = AIN9

0101 CVBS1 = AIN6

SCART (CVBS and R, G, B) B = AIN7 R = AIN8 G = AIN9

0110 Y1 = AIN1

Y/C C1 = AIN4

0111 Y2 = AIN2

Y/C C2 = AIN5

1000 Y3 = AIN3

Y/C C3 = AIN6

1001 Y1 = AIN1

YPrPb PB1 = AIN4 PR1 = AIN5

1010 Y2 = AIN2

YPrPb PB2 = AIN3 PR2 = AIN6

1011 CVBS7 = AIN7

SCART (CVBS and R, G, B) B = AIN4 R = AIN5 G = AIN6

1100 CVBS8 = AIN8

SCART (CVBS and R, G, B) B = AIN4 R = AIN5 G = AIN6

1101 CVBS9 = AIN9

SCART (CVBS and R, G, B) B = AIN4 R = AIN5 G = AIN6

1110 CVBS10 = AIN10

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

1111 CVBS11 = AIN11

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

Selectable via RGB_IP_SEL.

SCART (CVBS and R, G, B)

Rev. A | Page 14 of 112

ADV7184

Table 10. Input Channel Assignments

Input Channel Pin No. Recommended Input Muxing Control—INSEL [3:0]

AIN7 41 CVBS7 SCART1-B AIN1 42 CVBS1 YC1-Y YPrPb1-Y SCART2-CVBS AIN8 43 CVBS8 SCART1-R AIN2 44 CVBS2 YC2-Y YPrPb2-Y AIN9 45 CVBS9 SCART1-G AIN3 46 CVBS3 YC3-Y YPrPb2-Pb AIN10 57 CVBS10 AIN4 58 CVBS4 YC1-C YPrPb1-Pb SCART2-B AIN11 59 CVBS11 SCART1-CVBS AIN5 60 CVBS5 YC2-C YPrPb1-Pr SCART2-R AIN12 61 Not available AIN6 62 CVBS6 YC3-C YPrPb2-Pr SCART2-G

Table 11. Manual Mux Settings for All ADCs (Set ADC_SW_MAN_EN to 1)

ADC0

ADC0_SW [3:0]

0000 No connection 0000 No connection 0000 No connection 0000 No connection 0001 AIN1 0001 No connection 0001 No connection 0001 No connection 0010 AIN2 0010 No connection 0010 AIN2 0010 No connection 0011 AIN3 0011 AIN3 0011 No connection 0011 No connection 0100 AIN4 0100 AIN4 0100 No connection 0100 AIN4 0101 AIN5 0101 AIN5 0101 AIN5 0101 No connection 0110 AIN6 0110 AIN6 0110 AIN6 0110 No connection 0111 No connection 0111 No connection 0111 No connection 0111 No connection 1000 No connection 1000 No connection 1000 No connection 1000 No connection 1001 AIN7 1001 No connection 1001 No connection 1001 AIN7 1010 AIN8 1010 No connection 1010 AIN8 1010 No connection 1011 AIN9 1011 AIN9 1011 No connection 1011 No connection 1100 AIN10 1100 AIN10 1100 No connection 1100 No connection 1101 AIN11 1101 AIN11 1101 AIN11 1101 No connection 1110 AIN12 1110 AIN12 1110 AIN12 1110 No connection 1111 No connection 1111 No connection 1111 No connection 1111 No connection

Conne cted To

ADC1_SW [3:0]

RGB_IP_SEL, Address 0xF1 [0]

For SCART input, R, G, and B signals can be input either on AIN4, AIN5, and AIN6 or on AIN7, AIN8, and AIN9.

0 (default)—B is input on AIN4, R is input on AIN5, and G is input on AIN6.

1—B is input on AIN7, R is input on AIN8, and G is input on AIN9.

ADC1 Conne cted To

ADC2_SW [3:0]

ADC2 Conne cted To

ADC3_SW [3:0]

ADC3 Connected To

Therefore, if the settings of INSEL and the manual input muxing bits (ADC0_SW/ADC1_SW/ADC2_SW/ADC3_SW) contradict each other, the ADC0_SW/ADC1_SW/ADC2_SW/ ADC3_SW settings apply and INSEL is ignored.

Manual input muxing controls only the analog input muxes. For the follow-on blocks to process video data in the correct format, however, INSEL must still be used to indicate whether the input signal is of YPbPr, Y/C, or CVBS format.

MANUAL INPUT MUXING

By accessing a set of manual override muxing registers, the analog input muxes of the ADV7184 can be controlled directly. This is referred to as manual input muxing. Manual input muxing overrides other input muxing control bits, including INSEL.

Manual muxing is activated by setting the ADC_SW_MAN_EN bit. It only affects the analog switches in front of the ADCs.

Rev. A | Page 15 of 112

Restrictions in the channel routing are imposed by the analog signal routing inside the IC; each input pin cannot be routed to each ADC. Refer to

Figure 6 for an overview on the routing capabilities inside the chip. The four mux sections can be controlled by the reserved control signal buses, ADC0_SW [3:0], ADC1_SW [3:0], ADC2_SW [3:0], and ADC3_SW [3:0].

Tabl e 1 1 explains the

control words used.

ADV7184

ADC_SW_MAN_EN, Manual Input Muxing Enable, Address 0xC4 [7]

ADC0_SW [3:0], ADC0 Mux Configuration, Address 0xC3 [3:0]

ADC1_SW [3:0], ADC1 Mux Configuration, Address 0xC3 [7:4]

ADC2_SW [3:0], ADC2 Mux Configuration, Address 0xC4 [3:0]

ADC3_SW [3:0], ADC3 Mux Configuration, Address 0xF3 [7:4]

See Tab le 1 1.

XTAL CLOCK INPUT PIN FUNCTIONALITY

XTAL_TTL_SEL, Address 0x13 [2]

The crystal pad is normally part of the crystal oscillator circuit, powered from a 1.8 V supply. For optimal clock generation, the slice level of the input buffer of this circuit is at approximately half the supply voltage, making it incompatible with TLL level signals.

0 (default)—A crystal is used to generate the ADV7184 clock.

1—An external TTL level clock is supplied. A different input buffer can be selected that slices at TTL-compatible levels. This inhibits operation of the crystal oscillator and therefore can only be used when a clock signal is applied.

28.63636 MHz CRYSTAL OPERATION

EN28XTAL, Address 0x1D [6]

The ADV7184 can operate on two different base crystal frequencies. Selecting one over the other may be desirable in systems in which board crosstalk between different components leads to undesirable interference between video signals. It is recommended to use a crystal of frequency 28.63636 MHz to clock the ADV7184.

0 (default)—The crystal frequency is 27 MHz.

1—The crystal frequency is 28.63636 MHz.

ANTIALIASING FILTERS

The ADV7184 has optional antialiasing filters on each of the four input channels. The filters are designed for SD video with approximately 6 MHz bandwidth.

A plot of the filter response is shown in

can be individually enabled via I

C under the control of

AA_FILT_EN [3:0].

AA_FILT_EN [0], Address 0xF3 [0]

0 (default)—The filter on Channel 0 is disabled.

1—The filter on Channel 0 is enabled.

Figure 8. The filters

AA_FILT_EN [1], Address 0xF3 [1]

0 (default)—The filter on Channel 1 is disabled.

1—The filter on Channel 1 is enabled.

AA_FILT_EN [2], Address 0xF3 [2]

0 (default)—The filter on Channel 2 is disabled.

1—The filter on Channel 2 is enabled.

AA_FILT_EN [3], Address 0xF3 [3]

0 (default)—The filter on Channel 3 is disabled.

1—The filter on Channel 3 is enabled.

RESPONSE OF AA FILT ER WITH CALIBRATED CAPACI TORS

0 –2 –4 –6 –8

–10 –12 –14 –16 –18 –20 –22 –24 –26 –28 –30 –32 –34

ATTENUATIO N (dB)

–36 –38 –40 –42 –44 –46 –48 –50 –52

1M 1G

Figure 8. Frequency Response of Internal ADV7184 Antialiasing Filters

10M 100M

FREQUENCY (Hz)

05479-008

SCART AND FAST BLANKING

The ADV7184 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality.

This function is available when INSEL [3:0] is set appropriately

Tabl e 9). Timing extraction is always performed by the

(see ADV7184 on the CVBS signal. However, a combination of the CVBS and RGB inputs can be mixed and output under the control of the I

Four basic modes are supported:

• Static Switch Mode. The FB pin is not used. The timing is

extracted from the CVBS signal, and either the CVBS content or RGB content can be output under the control of CVBS_RGB_SEL. This mode allows the selection of a fullscreen picture from either source. Overlay is not possible in static switch mode.

• Fixed Alpha Blending. The FB pin is not used. The timing

is extracted from the CVBS signal, and an alpha blended combination of the video from the CVBS and RGB sources is output. This alpha blending is applied to the full screen.

C registers and the FB pin.

Rev. A | Page 16 of 112

ADV7184

The alpha blend factor is selected with the I2C signal MAN_ALPHA_VAL [6:0]. Overlay is not possible in fixed alpha blending mode.

• Dynamic Switching (Fast Mux). The FB pin can be used to

select the source. This enables dynamic multiplexing between the CVBS and RGB sources. With default settings, when Logic 1 is applied to the FB pin, the RGB source is selected; when Logic 0 is applied to the FB pin, the CVBS source is selected. This mode is suitable for the overlay of subtitles, teletext, or other material. Typically, the CVBS source carries the main picture, and the RGB source has the overlay data.

• Dynamic Switching with Edge Enhancement. This provides

the same functionality as the dynamic switching mode, but with the benefit of Analog Devices proprietary edgeenhancement algorithms, which improve the visual appearance of transitions for signals from a wide variety of sources.

The switched or blended data is output from the ADV7184 in the standard output formats (see

Table 102).

FAST BLANK CONTROL

FB_MODE [1:0], Address 0xED [1:0]

FB_MODE controls which fast blank mode is selected.

Table 12. FB_MODE [1:0] Function

FB_MODE [1:0] Description

00 (default) Static switch mode 01 Fixed alpha blending 10 Dynamic switching (fast mux) 11 Dynamic switching with edge enhancement

Static Mux Selection Control

CVBS_RGB_SEL, Address 0xED [2]

CVBS_RGB_SEL controls whether the video from the CVBS or RGB source is selected for output from the ADV7184.

System Diagram

A block diagram of the ADV7184 fast blanking configuration is shown in

Figure 9.

The CVBS signal is processed by the ADV7184 and converted to YPrPb. The RGB signals are processed by a color space converter (CSC), and samples are converted to YPrPb. Both sets of YPrPb signals are input to the subpixel blender, which can be configured to operate in any of the four modes previously outlined in this section.

The fast blank position resolver determines the time position of the FB pin accurately (<1 ns). This position information is then used by the subpixel blender in dynamic switching modes, enabling the ADV7184 to implement high performance multiplexing between the CVBS and RGB sources even when the RGB data source is completely asynchronous to the sampling crystal reference.

An antialiasing filter is required on all four data channels (R, G, B, and CVBS). The order of this filter is reduced because all signals are sampled at 54 MHz.

0 (default)—Data from the CVBS source is selected for output.

1—Data from the RGB source is selected for output.

Alpha Blend Coefficient

MAN_ALPHA_VAL [6:0], Address 0xEE [6:0]

When fixed alpha blending is selected (FB_MODE [1:0] = 01), MAN_ALPHA_VAL [6:0] determines the proportion in which the video from the CVBS and RGB sources are blended. Equation 1 shows how these bits affect the video output.

]06[__

:VALALPHAMAN

out

Video

RGB

⎛ ⎜

CVBS

−×=

⎜ ⎝

]06[__

:VALALPHAMAN

VideoVideo

×+

⎞ ⎟

⎟ ⎠

(1)

The maximum valid value for MAN_ALPHA_VAL [6:0] is 1000000, such that the alpha blender coefficients remain between 0 and 1. The default value for MAN_ALPHA_VAL [6:0] is 0000000.

Rev. A | Page 17 of 112

ADV7184

FAST BLANK

(FB PIN)

FAST BLANK

POSITION

RESOLVER

CONTROL

CVBS

ADC0

CONDITIONING

CLAMPI NG AND

ADC1

ADC2

ADC3

SIGNAL

DECIMAT ION

TIMING

EXTRACTION

SIGNAL CONDITIO NING CLAMPING AND

DECIMATION

Figure 9. Fast Blanking Configuration

Fast Blank Edge Shaping

FB_EDGE_SHAPE [2:0], Address 0xEF [2:0]

To improve the picture transition for high speed fast blank switching, an edge-shaping mode is available on the ADV7184. Depending on the format of the RGB inputs, it may be advantageous to apply different levels of edge shaping. The levels are selected via the FB_EDGE_SHAPE [2:0] bits. Users are advised to try each of the settings and select the setting that is most visually pleasing on their system.

Table 13. FB_EDGE_SHAPE [2:0] Function

FB_EDGE_SHAPE [2:0] Description

000 No edge shaping 001 Level 1 edge shaping 010 (default) Level 2 edge shaping 011 Level 3 edge shaping 100 Level 4 edge shaping 101 to 111 Not valid

Contrast Reduction

For overlay applications, text can be more readable if the contrast of the video directly behind the text is reduced. To enable the definition of a window of reduced contrast behind inserted text, the signal applied to the FB pin can be interpreted as a trilevel signal, as shown in

Figure 10.

VIDEO

PROCESSING

RGB

≥

YPrPb

CONVERSION

RGB SOURCE

100%

CVBS SOURCE

50% CONTRAST

CVBS SOURCE

100%

YPrPb SUBPIXEL BLENDER

OUTPUT

FORMATTE R

SANDCASTLE

05479-009

Figure 10. Fast Blank Signal Representation with

Contrast Reduction Enabled

Contrast Reduction Enable

CNTR_ENABLE, Address 0xEF [3]

This bit enables the contrast reduction feature and changes the meaning of the signal applied to the FB pin.

0 (default)—The contrast reduction feature is disabled, and the fast blank signal is interpreted as a bilevel signal.

1—The contrast reduction feature is enabled, and the fast blank signal is interpreted as a trilevel signal.

Contrast Mode

CNTR_MODE [1:0], Address 0xF1 [3:2]

The contrast level in the selected contrast reduction box is selected using the CNTR_MODE [1:0] bits.

Table 14. CNTR_MODE [1:0] Function

CNTR_MODE [1:0] Description

00 (default) 25% 01 50% 10 75% 11 100%

05479-010

Rev. A | Page 18 of 112

ADV7184

Fast Blank and Contrast Reduction Programmable Thresholds

The internal fast blank and contrast reduction signals are resolved from the trilevel FB signal using two comparators, as shown in Figure 11. To facilitate compliance with different input level standards, the reference level to these comparators is program-

PROGRAMMABLE

mable via FB_LEVEL [1:0] and CNTR_LEVEL [1:0]. The resulting thresholds are given in

Tabl e 1 5 .

FB_LEVEL [1:0], Address 0xF1 [5:4]

These bits control the reference level for the fast blank comparator.

CNTR_LEVEL [1:0], Address 0xF1 [7:6]

These bits control the reference level for the contrast reduction

Figure 11. Fast Blank and Contrast Reduction Programmable Threshold

comparator.

Table 15. Fast Blank and Contrast Reduction Programmable Threshold I

C Controls

CNTR_ENABLE FB_LEVEL [1:0] CNTR_LEVEL [1:0] Fast Blanking Threshold (V) Contrast Reduction Threshold (V)

0 00 (default) XX 1.4 n/a 0 01 XX 1.6 n/a 0 10 XX 1.8 n/a 0 11 XX 2.0 n/a 1 00 (default) 00 1.6 0.4 1 01 01 1.8 0.6 1 10 10 2.0 0.8 1 11 11 2.2 2.0

FB PIN

THRESHOLDS

CNTR ENABLE

CNTR_LEVEL [1:0]

FAST BLANK COMPARATOR

–

CONTRAST REDUCTION COMPARATOR

FB_LEVEL[1:0]

FAST BLANK

05479-011

Rev. A | Page 19 of 112

ADV7184

FB_INV, Address 0xED [3], Write Only

The interpretation of the polarity of the signal applied to the FB pin can be changed using FB_INV.

0 (default)—The fast blank pin is active high.

1—The fast blank pin is active low.

Readback of FB Pin Status

FB_STATUS [3:0], Address 0xED [7:4]

FB_STATUS [3:0] is a readback value that provides the system information on the status of the FB pins, as shown in

Tabl e 16 .

FB Timing

FB_SP_ADJUST [3:0], Address 0xEF [7:4]

The critical information extracted from the FB signal is the time at which it switches relative to the input video. Due to small timing inequalities either on the IC or on the PCB, it may be necessary to adjust the result by a fraction of one clock cycle. This is controlled by FB_SP_ADJUST [3:0].

Each LSB of FB_SP_ADJUST [3:0] corresponds to ⅛

of an ADC clock cycle. Increasing the value is equivalent to adding delay to the FB signal. The reset value is chosen to produce equalized channels when the ADV7184 internal antialiasing filters are enabled and there are only intentional delays on the PCB.

Alignment of FB Signal

FB_DELAY [3:0], Address 0xF0 [3:0]

In the event of misalignment between the FB input signal and the other input signals (CVBS and RGB) or unequalized delays in their processing, it is possible to alter the delay of the FB signal in 28.63636 MHz clock cycles. (For a finer granularity delay of the FB signal, refer to the Address 0xEF [7:4]

section.)

FB_SP_ADJUST [3:0],

The default value of FB_DELAY [3:0] is 0100.

Color Space Converter Manual Adjust

FB_CSC_MAN, Address 0xEE [7]

As shown in Figure 9, the data from the CVBS and RGB sources are converted to YPbPr before being combined. For the RGB source, CSC must be used to perform this conversion. When SCART support is enabled, the parameters for CSC are automatically configured for this operation.

If the user wishes to use a different conversion matrix, this autoconfiguration can be disabled and the CSC can be manually programmed. For details on this manual configuration, contact an Analog Devices representative.

0 (default)—The CSC is configured automatically for the RGBto-YPrPb conversion.

The default value of FB_SP_ADJUST [3:0] is 0100.

1—The CSC can be configured manually (not recommended).

Table 16. FB_STATUS Functions

FB_STATUS [3:0] Bit Name Description

0 FB_STATUS.0

1 FB_STATUS.1

2 FB_STATUS.2 FB_STAT. The value of the FB input pin at the time of the read. 3 FB_STATUS.3

FB_RISE. A high value indicates that there has been a rising edge on FB since the last

C read. The value is cleared by an I2C read (this is a self-clearing bit).

I FB_FALL. A high value indicates that there has been a falling edge on FB since the last

C read. The value is cleared by an I2C read (this is a self-clearing bit).

FB_HIGH. A high value indicates that there has been a rising edge on FB since the last

C read. The value is cleared by an I2C read (this is a self-clearing bit).

Rev. A | Page 20 of 112

ADV7184

GLOBAL CONTROL REGISTERS

POWER-SAVING MODES

Power-Down

PDBP, Address 0x0F [2]

The digital core of the ADV7184 can be shut down by using the PWRDN of the two controls has the higher priority. The default is to give the pin (

ADV7184 powered down by default.

0 (default)—The digital core power is controlled by the PWRDN

1—The bit has priority (the pin is disregarded).

PWRDN, Address 0x0F [5]

Setting the PWRDN bit switches the ADV7184 into a chip-wide power-down mode. The power-down stops the clock from entering the digital section of the chip, thereby freezing its operation. No I PWRDN bit also affects the analog blocks and switches them into low current modes. The I and remains operational in power-down mode.

The ADV7184 leaves the power-down state if the PWRDN bit is set to 0 (via I

pin. Note that PDBP must be set to 1 for the PWRDN bit to power down the ADV7184.

0 (default)—The chip is operational.

1—The ADV7184 is in chip-wide power-down mode.

ADC Power-Down Control

The ADV7184 contains four 10-bit ADCs (ADC0, ADC1, ADC2, and ADC3). If required, it is possible to power down each ADC individually.

• In CVBS mode, ADC1 and ADC2 should be powered

• In S-video mode, ADC2 should be powered down to

PWRDN_ADC_0, Address 0x3A [3]

0 (default)—The ADC is in normal operation.

1—ADC0 is powered down.

PWRDN_ADC_1, Address 0x3A [2]

0 (default)—The ADC is in normal operation.

1—ADC1 is powered down.

pin or the PWRDN bit. The PDBP bit determines which

PWRDN

) priority. This allows the user to have the

pin (the bit is disregarded).

C bits are lost during power-down. The

C interface itself is unaffected

C) or if the overall part is reset using the

down to reduce power consumption.

reduce power consumption.

RESET

PWRDN_ADC_2, Address 0x3A [1]

0 (default)—The ADC is in normal operation.

1—ADC2 is powered down.

PWRDN_ADC_3, Address 0x3A [0]

0 (default)—The ADC is in normal operation.

1—ADC3 is powered down.

FB_PWRDN, Address 0x0F [1]

To achieve a very low power-down current, it is necessary to prevent activity on toggling input pins from reaching circuitry, where it could consume current. FB_PWRDN gates signals from the FB input pin.

0 (default)—The FB input is in normal operation.

1—The FB input is in the power-saving mode.

RESET CONTROL

RES, Chip Reset, Address 0x0F [7]

Setting this bit, which is equivalent to controlling the

on the ADV7184, issues a chip reset. All I

C registers are reset to

RESET

their default values, making these bits self-clearing. Some register bits do not have a reset value specified and instead keep the last value written to them. These bits are marked as having a reset value of x in the register tables. After the reset sequence, the part immediately starts to acquire the incoming video signal.

Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before performing subsequent I

C master controller receives a no acknowledge condition

The I

C writes.

on the ninth clock cycle when a chip reset is implemented. See the

MPU Port Description section for a full description.

0 (default)—Operation is normal.

1—The reset sequence starts.

GLOBAL PIN CONTROL

Three-State Output Drivers

TOD, Address 0x03 [6]

This bit allows the user to three-state the output drivers of the ADV7184. Upon setting the TOD bit, the P15 to P0, HS, VS, FIELD, and SFL pins are three-stated. The ADV7184 also supports three-stating via a dedicated pin,

drivers are three-stated if the TOD bit or the

The timing pins (HS, VS, and FIELD) can be forced active via the TIM_OE bit of Register 0x04. For more information on three-state control, refer to the

Three-State LLC Drivers and the

Timing Signals Output Enable sections. Individual drive

. The output

pin is set high.

Rev. A | Page 21 of 112

ADV7184

strength controls are provided by the DR_STR_S, DR_STR_C, and DR_STR bits of Register 0xF4.

0 (default)—The output drivers are enabled.

1—The output drivers are three-stated.

Three-State LLC Drivers

TRI_LLC, Address 0x1D [7]

This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7184 to be three-stated. For more information on three-state control, refer to the the

Timing Signals Output Enable sections. Individual drive strength controls are provided via the DR_STR_S, DR_STR_C, and DR_STR bits.

0 (default)—The LLC pin drivers work according to the DR_STR_C [1:0] setting (pin enabled).

1—The LLC pin drivers are three-stated.

Three-State Output Drivers and

Timing Signals Output Enable

TIM_OE, Address 0x04 [3]

The TIM_OE bit should be regarded as an addition to the TOD bit. Setting it high forces the output drivers for HS, VS, and FIELD into the active (that is, driving) state even if the TOD bit is set. If the TIM_OE bit is set to low, the HS, VS, and FIELD pins are three-stated depending on the TOD bit. This functionality is useful if the decoder is to be used only as a timing generator. This may be the case if only the timing signals are to be extracted from an incoming signal or if the part is in free-run mode, where, for example, a separate chip can output a company logo. For more information on three-state control, refer to the Drivers

and the Three-State LLC Drivers sections. Individual drive strength controls are provided via the DR_STR_S, DR_STR_C, and DR_STR bits.

0 (default)—HS, VS, and FIELD are three-stated according to the TOD bit.

1—HS, VS, and FIELD are forced active.

Three-State Output

Drive Strength Selection (Data)

DR_STR [1:0], Address 0xF4 [5:4]

Because of EMC and crosstalk factors, it may be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR [1:0] bits affect the P [15:0] output drivers.

For more information on three-state control, refer to the Strength Selection (Clock) (Sync)

sections.

Table 17. DR_STR Function

DR_STR [1:0] Description

01 (default) Medium-low drive strength (2×) 10 Medium-high drive strength (3×) 11 High drive strength (4×)

and the Drive Strength Selection

Drive

Drive Strength Selection (Clock)

DR_STR_C [1:0], Address 0xF4 [3:2]

The DR_STR_C [1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the Strength Selection (Data)

Table 18. DR_STR_C Function

DR_STR_C [1:0] Description

01 (default) Medium-low drive strength (2×) 10 Medium-high drive strength (3×) 11 High drive strength (4×)

Drive Strength Selection (Sync) and the Drive

sections.

Drive Strength Selection (Sync)

DR_STR_S [1:0], Address 0xF4 [1:0]

The DR_STR_S [1:0] bits allow the user to select the strength of the synchronization signals with which HS, VS, and FIELD are driven. For more information, refer to the Selection (Clock) sections.

Table 19. DR_STR_S Function

DR_STR_S [1:0] Description

01 (default) Medium-low drive strength (2×) 10 Medium-high drive strength (3×) 11 High drive strength (4×)

and the Drive Strength Selection (Data)

Drive Strength

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN, Address 0x04 [1]

The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as genlock) from the ADV7184 core to an encoder in a decoder/encoder back-to-back arrangement.

0 (default)—The subcarrier frequency lock output is disabled.

1—The subcarrier frequency lock information is presented on the SFL pin.

Polarity LLC Pin

PCLK, Address 0x37 [0]

The polarity of the clock that leaves the ADV7184 via the LLC1 and LLC2 pins can be inverted using the PCLK bit. Changing the polarity of the LLC clock output may be necessary to meet the setup time and hold time expectations of follow-on chips. This bit also inverts the polarity of the LLC2 clock.

0—The LLC output polarity is inverted.

1 (default)—The LLC output polarity is normal, as per the timing diagrams (see

Figure 2 to Figure 4).

Rev. A | Page 22 of 112

ADV7184

GLOBAL STATUS REGISTERS

Three registers provide summary information about the video decoder: Status Register 1, Status Register 2, and Status Register 3. These registers contain status bits that report operational information to the user.

Status Register 1 [7:0], Address 0x10 [7:0]

This read-only register provides information about the internal status of the ADV7184. See the Address 0x51 [2:0] Address 0x51 [5:3]

and the COL [2:0], Count-Out-of-Lock, sections for information on the timing.

Depending on the setting of the FSCLE bit, the IN_LOCK [0] and LOST_LOCK [1] bits of Status Register 1 are based solely on the horizontal timing information or on the horizontal timing and lock status of the color subcarrier. See the Enable, Address 0x51 [7]

AD_RESULT [2:0], Autodetection Result, Address 0x10 [6:4]

These bits report the findings from the autodetection block. For more information on enabling the autodetection block, see the

Table 21. Status Register 1 Function

Status Register 1 [7:0] Bit Name Description

0 IN_LOCK In lock (now). 1 LOST_LOCK Lost lock (since last read of this register). 2 FSC_LOCK FSC locked (now). 3 FOLLOW_PW AGC follows peak white algorithm. 4 AD_RESULT.0 Result of autodetection. 5 AD_RESULT.1 Result of autodetection. 6 AD_RESULT.2 Result of autodetection. 7 COL_KILL Color kill is active.

Table 22. Status Register 2 Function

Status Register 2 [7:0] Bit Name Description

0 MVCS DET Detected Macrovision color striping. 1 MVCS T3 Macrovision color striping protection. Conforms to Type 3 if high, Type 2 if low. 2 MV_PS DET Detected Macrovision pseudosync pulses. 3 MV_AGC DET Detected Macrovision AGC pulses. 4 LL_NSTD Line length is nonstandard. 5 FSC_NSTD FSC frequency is nonstandard. 6 Reserved

7 Reserved

Table 23. Status Register 3 Function

Status Register 3 [7:0] Bit Name Description

0 INST_HLOCK Horizontal lock indicator (instantaneous). 1 GEMD Gemstar detect. 2 SD_OP_50HZ Flags whether 50 Hz or 60 Hz is present at output. 3 CVBS Indicates if a CVBS signal is detected in composite/S-video autodetection configuration. 4 FREE_RUN_ACT

5 STD_FLD_LEN Field length is correct for currently selected video standard. 6 INTERLACED Interlaced video detected (field sequence found). 7 PAL_SW_LOCK Reliable sequence of swinging bursts detected.

CIL [2:0], Count-Into-Lock,

FSCLE, FSC Lock

section.

Indicates if the ADV7184 is in free-run mode. Outputs a blue screen by default. See the DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1] section for details about disabling this function.

Rev. A | Page 23 of 112

General Setup section. For information on configuring this block, see the

Autodetection of SD Modes section.

Table 20. AD_RESULT Function

AD_RESULT [2:0] Description

000 NTSC M/J 001 NTSC 443 010 PAL M 011 PAL 60 100 PAL B/G/H/I/D 101 SECAM 110 PAL Combination N 111 SECAM 525

Status Register 2 [7:0], Address 0x12 [7:0]

See Tab le 2 2.

Status Register 3 [7:0], Address 0x13 [7:0]

See Tab le 2 3.

ADV7184

STANDARD DEFINITION PROCESSOR (SDP)

STANDARD DEFINITION PROCESSOR

DIGITI ZED CVBS

DIGITI ZED Y (YC)

DIGITI ZED CVBS

DIGITI ZED C (YC)

MACROVISIO N

DETECT ION

LUMA

DIGITAL

FINE

CLAMP

CHROMA

DIGITAL

FINE

CLAMP

RECOVERY

CHROMA

DEMOD

Fsc

RECOVERY

VBI DATA

LUMA

FILTER

EXTRACT

CHROMA

FILTER

AUTODETECTION

SYNC

STANDARD

Figure 12. Block Diagram of the Standard Definition Processor

A block diagram of the ADV7184 standard definition processor (SDP) is shown in

Figure 12.

The SDP can handle standard definition video in CVBS, Y/C, and YPrPb formats. It can be divided into a luminance path and a chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input.

SD LUMA PATH

The input signal is processed by the following blocks:

• Luma Digital Fine Clamp. This block uses a high precision

algorithm to clamp the video signal.

• Luma Filter. This block contains a luma decimation filter

(YAA) with a fixed response and some luma-shaping filters (YSH) that have selectable responses.

• Luma Gain Control. The automatic gain control (AGC) can

operate on a variety of modes, including a mode based on the depth of the horizontal sync pulse, a mode based on the peak white mode, and a mode that uses a fixed manual gain.

• Luma Resample. To correct for errors and dynamic changes

in line lengths, the data is digitally resampled.

• Luma 2D Comb. The two-dimensional comb filter provides

Y/C separation.

• AV Code Insertion. At this point, the decoded luma (Y)

signal is merged with the retrieved chroma values. AV codes (as per ITU-R. BT-656) can be inserted.

LUMA

GAIN

CONTROL

LINE

LENGTH

PREDICTOR

CHROMA

GAIN

CONTROL

SLLC

CONTROL

LUMA

RESAMPLE

CONTRO L

CHROMA

RESAMPLE

LUMA

2D COMB

CHROMA 2D COMB

CODE

INSERTION

VIDEO DATA OUTPUT

MEASUREMENT BLOCK (= >I

VIDEO DATA PROCESSING BLOCK

05479-012

SD CHROMA PATH

The input signal is processed by the following blocks:

• Chroma Digital Fine Clamp. This block uses a high

precision algorithm to clamp the video signal.

• Chroma Demodulation. This block uses a color subcarrier

) recovery unit to regenerate the color subcarrier for

any modulated chroma scheme and then performs an AM demodulation for PAL and NTSC and an FM demodulation for SECAM.

• Chroma Filter. This block contains a chroma decimation

filter (CAA) with a fixed response and some chromashaping filters (CSH) that have selectable responses.

• Chroma Gain Control. Automatic gain control (AGC) can

operate on several modes, including a mode based on the color subcarrier’s amplitude, a mode based on the depth of the horizontal sync pulse on the luma channel, and a mode that uses a fixed manual gain.

• Chroma Resample. The chroma data is digitally resampled

to keep it aligned with the luma data. The resampling is done to correct for static and dynamic errors in the line lengths of the incoming video signal.

• Chroma 2D Comb. The two-dimensional, 5-line, super-

adaptive comb filter provides high quality Y/C separation in case the input signal is CVBS.

• AV Code Insertion. At this point, the demodulated chroma

(Cr and Cb) signal is merged with the retrieved luma values. AV codes (as per ITU-R. BT-656) can be inserted.

Rev. A | Page 24 of 112

ADV7184

SYNC PROCESSING

The ADV7184 extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction is optimized to support imperfect video sources, such as videocassette recorders with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this block is then used to drive the digital resampling section to ensure that the ADV7184 outputs 720 active pixels per line.

The sync processing on the ADV7184 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video.

• Vsync Processor. This block provides extra filtering of the

detected vsyncs to improve the vertical lock.

• Hsync Processor. The hsync processor is designed to filter

incoming hsyncs that have been corrupted by noise, providing much improved performance for video signals with a stable time base but poor SNR.

VBI DATA RECOVERY

The ADV7184 can retrieve the following information from the input video:

• Wide-screen signaling (WSS)

• Copy generation management system (CGMS)

• Closed captioning (CC)

• Macrovision protection presence

• Gemstar-compatible data slicing

• Te le t e xt

• VITC/VPS

The ADV7184 is also capable of automatically detecting the incoming video standard with respect to

• Color subcarrier frequency

• Field rate

• Line rate

The ADV7184 can configure itself to support PAL (B/G/H/I/D/M/N), PAL Combination N, NTSC M, NTSC J, SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60.

GENERAL SETUP

Video Standard Selection

The VID_SEL [3:0] bits allow the user to force the digital core into a specific video standard. Under normal circumstances, this should not be necessary. The VID_SEL [3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. The following section describes the autodetection system.

Autodetection of SD Modes

To guide the autodetection system, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being automatically detected. Instead, the system selects the closest of the remaining enabled standards. The results of the autodetection can be read back via the status registers. See the section for more information.

VID_SEL [3:0], Address 0x00 [7:4]

Table 24. VID_SEL Function

VID_SEL [3:0] Description

0000 (default)

0001

0010

0011

0100 NTSC J (1) 0101 NTSC M (1) 0110 PAL 60 0111 NTSC 4.43 (1) 1000 PAL B/G/H/I/D 1001 PAL N (PAL B/G/H/I/D without pedestal) 1010 PAL M (without pedestal) 1011 PAL M 1100 PAL Combination N 1101 PAL Combination N (with pedestal) 1110 SECAM 1111 SECAM (with pedestal)

Autodetect PAL (B/G/H/I/D), NTSC (without pedestal), SECAM

Autodetect PAL (B/G/H/I/D), NTSC M (with pedestal), SECAM

Autodetect PAL N (without pedestal), NTSC M (without pedestal), SECAM

Autodetect PAL N (with pedestal), NTSC M (with pedestal), SECAM

Global Status Registers

Rev. A | Page 25 of 112

ADV7184

AD_SEC525_EN, SECAM 525 Autodetect Enable, Address 0x07 [7]

0 (default)—Disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component.

1—Enables autodetection.

AD_SECAM_EN, SECAM Autodetect Enable, Address 0x07 [6]

0—Disables the autodetection of SECAM.

1 (default)—Enables autodetection.

AD_N443_EN, NTSC 443 Autodetect Enable, Address 0x07 [5]

0—Disables the autodetection of NTSC style systems with a

4.43 MHz color subcarrier.

AD_NTSC_EN, NTSC Autodetect Enable, Address 0x07 [1]

0—Disables the autodetection of standard NTSC.

1 (default)—Enables autodetection.

AD_PAL_EN, PAL (B/G/I/H) Autodetect Enable, Address 0x07 [0]

0—Disables the autodetection of standard PAL.

1 (default)—Enables autodetection.

Subcarrier Frequency Lock Inversion

The SFL_INV bit of Register 0x41 controls the behavior of the PAL switch bit in the SFL (genlock telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves two problems.

1 (default)—Enables autodetection.

AD_P60_EN, PAL 60 Autodetect Enable, Address 0x07 [4]

0—Disables the autodetection of PAL systems with a 60 Hz field rate.

1 (default)—Enables autodetection.

AD_PALN_EN, PAL N Autodetect Enable, Address 0x07 [3]

0—Disables the autodetection of the PAL N standard.

1 (default)—Enables autodetection.

AD_PALM_EN, PAL M Autodetect Enable, Address 0x07 [2]

0—Disables the autodetection of PAL M.

1 (default)—Enables autodetection.

First, the PAL switch bit is only meaningful in PAL. Some encoders (including Analog Devices encoders) also look at the state of this bit in NTSC.

Second, there was a design change in Analog Devices encoders from ADV717x to ADV719x. The older versions used the SFL (genlock telegram) bit directly, whereas the more recent versions invert the bit prior to using it to compensate for the 1-line delay of an SFL (genlock telegram) transmission.

As a result, to be compatible with NTSC format, the PAL switch bit in the SFL (genlock telegram) must be 1 for ADV717x encoders and 0 for ADV7190/ADV7191/ADV7194 encoders. If the state of the PAL switch bit is set incorrectly, a 180° phase shift occurs.

In a decoder/encoder back-to-back system in which SFL is used, this bit must be set up properly for the specific encoder used.

SFL_INV, Address 0x41 [6]

0 (default)—Makes the part SFL compatible with ADV717x and ADV73xx encoders.

1—Makes the part SFL compatible with ADV7190/ADV7191/ ADV7194 encoders.

Rev. A | Page 26 of 112

ADV7184

Lock-Related Controls

Lock information is presented to the user through Bits [1:0] of Status Register 1. See the

section. Figure 13 outlines the signal flow and the controls

[7:0]

Status Register 1 [7:0], Address 0x10

that are available to influence how the lock status information is generated.

The TIME_WIN signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quickly.

The FREE_RUN signal evaluates the properties of the incoming video over several fields, taking vertical synchronization information into account.

SRLS, Select Raw Lock Signal, Address 0x51 [6]

Using the SRLS bit, the user can choose between two sources for determining the lock status, which is indicated via Status Register 1, Bits [1:0].

SELECT THE RAW LOCK SI GNAL SRLS

TIME_WIN

FREE_RUN

Fsc LOCK

TAKE Fsc LO CK INTO ACCO UNT

COUNTER OUT OF LOCK

FSCLE

Figure 13. Lock-Related Signal Path

0 (default)—Selects the FREE_RUN signal.

1—Selects the TIME_WIN signal.

FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0]

COUNTER INTO LOCK

MEMORY

IN_LOCK

LOST_LOCK

5479-013

Rev. A | Page 27 of 112

ADV7184

FSCLE, FSC Lock Enable, Address 0x51 [7]

The FSCLE bit allows the user to choose if the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits [1:0] in Status Register 1. The FSCLE bit must be set to 0 when operating in YPrPb (component) mode to generate a reliable horizontal lock status bit (INST_HLOCK).

0 (default)—Makes the overall lock status dependent on the horizontal sync lock.

1—Makes the overall lock status dependent on the horizontal sync lock and the F

lock.

CIL [2:0], Count-Into-Lock, Address 0x51 [2:0]

CIL [2:0] determines the number of consecutive lines the system must remain in the into-lock condition before reporting a locked state in Status Register 1 [1:0]. It counts the value in lines of video.

Table 25. CIL [2:0] Function

CIL [2:0] Description

000 1 line of video 001 2 lines of video 010 5 lines of video 011 10 lines of video 100 (default) 100 lines of video 101 500 lines of video 110 1000 lines of video 111 100,000 lines of video

COL [2:0], Count-Out-of-Lock, Address 0x51 [5:3]

COL [2:0] determines the number of consecutive lines the system must be in the out-of-lock condition before reporting an unlocked state in Status Register 0 [1:0]. It counts the value in lines of video.

Table 26. COL [2:0] Function

COL [2:0] Description

000 1 line of video 001 2 lines of video 010 5 lines of video 011 10 lines of video 100 (default) 100 lines of video 101 500 lines of video 110 1000 lines of video 111 100,000 lines of video

VS_COAST_MODE [1:0], Address 0xF9 [3:2]

These bits are used to set the VS free-run (coast) frequency.

Table 27. VS_COAST_MODE [1:0] Function

VS_COAST_MODE [1:0] Description

00 (default)

01 Forces 50 Hz coast mode 10 Forces 60 Hz coast mode 11 Reserved

Autocoast mode—follows VS frequency from last video input

ST_NOISE_VLD, Sync Tip Noise Measurement Valid, Address 0xDE [3], Read Only

This read-only bit measures whether ST_NOISE is valid or invalid.

0—The ST_NOISE [10:0] measurement is invalid.

1 (default)—The ST_NOISE [10:0] measurement is valid.

ST_NOISE [10:0], Sync Tip Noise Measurement, Addresses 0xDE [2:0], 0xDF [7:0]

The ST_NOISE [10:0] measures the noise in the horizontal sync tip over four fields and shows a readback value of the average noise. ST_NOISE_VLD must be 1 for this measurement to be valid.

One bit of ST_NOISE [10:0] = one ADC code.

One bit of ST_NOISE [10:0] = 1.6 V/4096 = 390.625 μV.

COLOR CONTROLS

These registers allow the user to control the appearance of the picture, including control of the active data in the event of video being lost. These controls are independent of any other control. For instance, brightness control is independent of picture clamping, although both controls affect the dc level of the signal.

CON [7:0], Contrast Adjust, Address 0x08 [7:0]

These bits allow the user to adjust the contrast of the picture.

Table 28. CON [7:0] Function

CON [7:0] Description

0x80 (default) Gain on luma channel = 1 0x00 Gain on luma channel = 0 0xFF Gain on luma channel = 2

SD_SAT_CB [7:0], SD Saturation Cb Channel, Address 0xE3 [7:0]

These bits allow the user to control only the gain of the Cb channel. The user can adjust the saturation of the picture.

Table 29. SD_SAT_CB [7:0] Function

SD_SAT_CB [7:0] Description

0x80 (default) Gain on Cb channel = 1 0x00 Gain on Cb channel = 0 0xFF Gain on Cb channel = 2

SD_SAT_CR [7:0], SD Saturation Cr Channel, Address 0xE4 [7:0]

These bits allow the user to control only the gain of the Cr channel. The user can adjust the saturation of the picture.

Table 30. SD_SAT_CR [7:0] Function

SD_SAT_CR [7:0] Description

0x80 (default) Gain on Cr channel = 1 0x00 Gain on Cr channel = 0 0xFF Gain on Cr channel = 2

Rev. A | Page 28 of 112

ADV7184

SD_OFF_CB [7:0], SD Offset Cb Channel, Address 0xE1 [7:0]

These bits allow the user to adjust the hue of the picture by selecting the offset for the Cb channel. There is a functional overlap with the HUE [7:0] bits.

Table 31. SD_OFF_CB [7:0] Function

SD_OFF_CB [7:0] Description

0x80 (default) 0 mV offset applied to the Cb channel 0x00 −568 mV offset applied to the Cb channel 0xFF +568 mV offset applied to the Cb channel

SD_OFF_CR [7:0], SD Offset Cr Channel, Address 0xE2 [7:0]

These bits allow the user to select an offset for data on only the Cr channel and to adjust the hue of the picture. There is a functional overlap with the HUE [7:0] bits.

Table 32. SD_OFF_CR [7:0] Function

SD_OFF_CR [7:0] Description

0x80 (default) 0 mV offset applied to the Cr channel 0x00 −568 mV offset applied to the Cr channel 0xFF +568 mV offset applied to the Cr channel

BRI [7:0], Brightness Adjust, Address 0x0A [7:0]

These bits control the brightness of the video signal and allow the user to adjust the brightness of the picture.

Table 33. BRI [7:0] Function

BRI [7:0] Description

0x00 (default) Offset of the luma channel = 0 mV 0x7F Offset of the luma channel = +204 mV 0x80 Offset of the luma channel = −204 mV

HUE [7:0], Hue Adjust, Address 0x0B [7:0]

These bits contain the value for the color hue adjustment and allow the user to adjust the hue of the picture.

DEF_Y [5:0], Default Value Y, Address 0x0C [7:2]

If the ADV7184 loses lock to the incoming video signal or if there is no input signal, the DEF_Y [5:0] bits allow the user to specify a default luma value to be output. The register is used if

• The DEF_VAL_AUTO_EN bit is set high and the ADV7184

loses lock to the input video signal. This is the intended mode of operation (automatic mode).

• The DEF_VAL_EN bit is set regardless of the lock status of

the video decoder. This is a forced mode that may be useful during configuration.

The DEF_Y [5:0] values define the six MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 8-bit mode, the output is Y [7:0] = {DEF_Y [5:0], 0, 0}.

The value for Y is set by the DEF_Y [5:0] bits. A value of 0x0D in conjunction with the DEF_C [7:0] default setting produces a blue color.

DEF_C [7:0], Default Value C, Address 0x0D [7:0]

The DEF_C [7:0] bits complement the DEF_Y [5:0] bits. These bits define the four MSBs of the Cr and Cb values to be output if

• The DEF_VAL_AUTO_EN bit is set high and the ADV7184

cannot lock to the input video (automatic mode).

• The DEF_VAL_EN bit is set high (forced output).

The data that is finally output from the ADV7184 for the chroma side is the output pixel buses Cr [7:0] = {DEF_C [7:4], 0, 0, 0, 0} and Cb [7:0] = {DEF_C [3:0], 0, 0, 0, 0}.

The values for Cr and Cb are set by the DEF_C [7:0] bits. A value of 0x7C in conjunction with the DEF_Y [5:0] default setting produces a blue color.

HUE [7:0] has a range of ±90°, with a value of 0x00 equivalent to an adjustment of 0°. The resolution of HUE [7:0] for one bit is 0.7°.

The hue adjustment value is fed into the AM color demodulation block. Therefore, it only applies to video signals that contain chroma information in the form of an AM-modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb).

Table 34. HUE [7:0] Function

HUE [7:0] Description 0x00 (default) Phase of the chroma signal = 0° 0x7F Phase of the chroma signal = +90° 0x80 Phase of the chroma signal = −90°

Rev. A | Page 29 of 112

DEF_VAL_EN, Default Value Enable, Address 0x0C [0]

This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions in the Address 0x0C [7:2] 0x0D [7:0]

sections for additional information. In this mode,

and DEF_C [7:0], Default Value C, Address

DEF_Y [5:0], Default Value Y,

the decoder also outputs a stable 27 MHz clock, HS, and VS.

0 (default)—Outputs a colored screen determined by userprogrammable Y, Cr, and Cb values when the decoder free runs. Free-run mode is turned on and off via DEF_VAL_AUTO_EN.

1—Forces a colored screen output determined by userprogrammable Y, Cr, and Cb values. This overrides picture data even if the decoder is locked.

ADV7184

DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1]

This bit enables the automatic use of the default values for Y, Cr, and Cb when the ADV7184 cannot lock to the video signal.

0—Disables free-run mode. If the decoder is unlocked, it outputs noise.

1 (default)—Enables free-run mode. A colored screen set by the user-programmable Y, Cr, and Cb values is displayed when the decoder loses lock.

CLAMP OPERATION

The input video is ac-coupled into the ADV7184 through a

0.1 μF capacitor. It is recommended that the range of the input video signal is 0.5 V to 1.6 V (typically 1 V p-p). If the signal exceeds this range, it cannot be processed correctly in the decoder. Because the input signal is ac-coupled into the decoder, its dc value needs to be restored. This process is referred to as clamping the video. This section explains the general process of clamping for the ADV7184 and shows the different ways that a user can configure the device’s behavior.

The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog-to-digital conversion can occur. Therefore, precise clamping of the input signal within the analog domain is unnecessary if the video signal fits within the ADC range.

After digitization, the digital fine-clamp block corrects for any remaining variations in dc level. Because the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations may occur. Furthermore, dynamic changes in the dc level usually lead to significant artifacts and must therefore be prohibited.

The clamping scheme must be able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation.

To quickly acquire an unknown video signal, activate the largecurrent clamps. It is assumed that the amplitude of the video signal at this point is of a nominal value. Control of the coarseand fine-current clamp parameters is automatically performed by the decoder.

The ADV7184 uses a combination of current sources and a digital processing block for clamping, as shown in Figure 14. There are three analog processing channels (like the one shown in Figure 14) inside the IC. Although only one channel (and only one ADC) is needed for a CVBS signal, two independent channels are needed for S-video (Y/C) type signals, and three independent channels are needed to allow component (YPrPb) signals to be processed.

The clamping can be divided into two sections:

• Clamping before the ADC (analog domain): current

sources

• Clamping after the ADC (digital domain): digital

processing block

The ADCs can digitize an input signal only if it is within the 1.6 V input voltage range. An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range.

FINE-CURRENT

SOURCES

COARSE-CURRENT SOURCES

Standard definition video signals may contain excessive noise. In particular, CVBS signals transmitted by terrestrial broadcast and then demodulated using a tuner usually show very large levels of noise (>100 mV). A voltage clamp would be unsuitable for this type of video signal. Instead, the ADV7184 uses a set of four current sources that can cause coarse (>0.5 mA) and fine (<0.1 mA) currents to flow into and away from the high impedance node that carries the video signal (see

CCLEN, DCT [1:0], and DCFE are the I

C signals that can be used

Figure 14).

to influence the behavior of the clamping block of the ADV7184.

CCLEN, Current Clamp Enable, Address 0x14 [4]

The current clamp enable bit allows the user to switch off the current sources entirely in the analog front end. This may be useful if the incoming analog video signal is clamped externally.

0—The current sources are switched off.

1 (default)—The current sources are enabled.

NALOG

VIDEO INPUT

ADC

Figure 14. Clamping Overview

Rev. A | Page 30 of 112

DATA

PREPROCESSOR

(DPP)

CLAMP CONTRO L

SDP

WITH DIGITAL

FINE CLAMP

05479-014

ADV7184

DCT [1:0], Digital Clamp Timing, Address 0x15 [6:5]

The clamp timing register determines the time constant of the digital fine-current clamp circuitry. It is important to realize that the digital fine-current clamp reacts quickly, correcting any residual dc level error for the active line immediately. Therefore, the time constant of the digital fine clamp must be much quicker than the one for the analog blocks.

By default, the time constant of the digital fine-current clamp is adjusted dynamically to suit the currently connected input signal.

Table 35. DCT [1:0] Function

DCT [1:0] Description

00 (default) Slow (TC = 1 sec) 01 Medium (TC = 0.5 sec) 10 Fast (TC = 0.1 sec) 11 TC determined by the input video parameters

DCFE, Digital Clamp Freeze Enable, Address 0x15 [4]

This register bit allows the user to freeze the digital clamp loop at any time. It is intended for users who do their own clamping. Users should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the DCFE bit.

0 (default)—The digital clamp is operational.

1—The digital clamp loop is frozen.

LUMA FILTER

Data from the digital fine-clamp block is processed by three sets of filters. The data format at this point is CVBS for CVBS input format or luma only for Y/C and YPrPb input formats.

• Luma Antialias (YAA) Filter. The ADV7184 receives video

at a rate of 27 MHz. (For 4× oversampled video, the ADCs are sampled at 54 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the ADV7184 is always 27 MHz.) The ITU-R BT.601 standard recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video using a high quality linear phase, low-pass filter that preserves the luma signal and simultaneously attenuates out-of-band components. The luma antialias filter has a fixed response.

• Luma-Shaping (YSH) Filters. The shaping filter block is a

programmable low-pass filter with a wide variety of responses. It can be used to selectively reduce the luma video signal bandwidth (needed prior to scaling, for example). For some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. A follow-on video compression stage may work more efficiently if the video is low-pass filtered.

The ADV7184 has two responses for the shaping filter: one that is used for good quality composite, component, and

S-video type sources, and a second for nonstandard composite signals. The YSH filter responses also include a set of notches for PAL and NTSC. However, it is recommended to use the comb filters for Y/C separation.

• Digital Resampling Filter. This block allows dynamic

resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system without requiring user intervention.

Figure 16 through Figure 19 show the responses of all luma filters. Unless otherwise noted, the filters are set in a typical wideband mode.

Y-Shaping Filter

For input signals in CVBS format, the luma-shaping filters play an essential role in removing the chroma component from a composite signal. Y/C separation must aim for best possible crosstalk reduction while retaining as much bandwidth (especially on the luma component) as possible. High quality Y/C separation can be achieved by using the internal comb filters of the ADV7184. Comb filtering, however, relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (F CVBS signals, this relationship is known and therefore the comb filter algorithms can be used to separate luma and chroma with high accuracy.

For nonstandard video signals, the frequency relationship may have an offset, and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of a shaping filter.

An automatic mode is provided. In this mode, the ADV7184 evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to override the automatic decisions manually in part or in full (see

Figure 15).

The luma-shaping filter has three sets of control bits:

• YSFM [4:0] (Address 0x17) allow the user to manually

select a shaping filter mode (applied to all video signals) or to enable an automatic selection (dependent on video quality and video standard).

• WYSFMOVR (Address 0x18) allows the user to override

the automatic WYSFM filter selection and enable manual selection of the WYSFM filter via WYSFM [4:0].

• WYSFM [4:0] (Address 0x18) allow the user to select a

different shaping filter mode for good quality composite (CVBS), component (YPrPb), and S-video (Y/C) input signals.

). For good quality

Rev. A | Page 31 of 112

ADV7184

In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources (because they can successfully be combed) and for luma components of YPrPb and Y/C sources (because they need not be combed). For poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation to reduce visual artifacts. The control logic is shown in

Figure 15.

YSFM [4:0], Y-Shaping Filter Mode, Address 0x17 [4:0]

The Y-shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters. When these bits are set to either of the automatic selection modes, the filter is selected based on other bit selections, such as detected video standard, and properties extracted from the incoming video itself, such as quality and time-base stability. The automatic selection always picks the widest possible bandwidth for the video input encountered.

If the YSFM settings specify a filter (that is, YSFM is set to values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality.

In either of the automatic selection modes, the notch filters are only used for poor quality video signals. For all other video signals, wideband filters are used (see

Table 3 6).

Table 36. YSFM Function

YSFM [4:0] Description

00000

Automatic selection, including a wide-notch response (PAL/NTSC/SECAM)

00001 (default)

Automatic selection, including a

narrow-notch response (PAL/NTSC/SECAM) 00010 SVHS 1 00011 SVHS 2 00100 SVHS 3 00101 SVHS 4 00110 SVHS 5 00111 SVHS 6 01000 SVHS 7 01001 SVHS 8 01010 SVHS 9 01011 SVHS 10 01100 SVHS 11 01101 SVHS 12 01110 SVHS 13 01111 SVHS 14 10000 SVHS 15 10001 SVHS 16 10010 SVHS 17 10011 SVHS 18 (CCIR 601) 10100 PAL NN 1 10101 PAL NN 2 10110 PAL NN 3 10111 PAL WN 1 11000 PAL WN 2 11001 NTSC NN 1 11010 NTSC NN 2 11011 NTSC NN 3 11100 NTSC WN 1 11101 NTSC WN 2 11110 NTSC WN 3 11111 Reserved

SET YSFM

VIDEO

QUALITY

BAD GOOD

AUTO SELECT LUMA-

SHAPING FILTER TO

COMPLEME NT COMB

1 0

SELECT WIDEBAND

FILTER AS PER

WYSFM[4:0]

Figure 15. YSFM and WYSFM Control Flowchart

YES NO

YSFM IN AUTO MODE?

00000 OR 00001

WYSFMOVR

AUTOMATICAL LY

SELECT BEST

WIDEBAND FI LTER

Rev. A | Page 32 of 112

USE YSFM-SELECTED

FILTER REGARDLESS O F

VIDEO QUALITY

05479-015

ADV7184

WYSFMOVR, Wideband Y-Shaping Filter Override, Address 0x18 [7]

Setting the WYSFMOVR bit enables the use of the WYSFM [4:0] settings for good quality video signals. For more information, refer to the general discussion of the luma-shaping filters in the Y-Sh ap i ng Fi l ter section and the flowchart shown in Figure 15.

0—The best wideband Y-shaping filter for good quality video signals is selected automatically.

1 (default)—Enables manual selection of a wideband filter via WYSFM [4:0].

WYSFM [4:0], Wideband Y-Shaping Filter Mode, Address 0x18 [4:0]

The WYSFM [4:0] bits allow the user to select a wideband Y-shaping filter manually for good quality video signals, for example, CVBS with a stable time base, a luma component of YPrPb, or a luma component of Y/C. The WYSFM bits are active only if the WYSFMOVR bit is set to 1. See the general discussion of the shaping filter settings in the

Y-Sh ap i ng Fi l ter section.

Table 37. WYSFM [4:0] Function

WYSFM [4:0] Description

00000 Reserved; do not use 00001 Reserved; do not use 00010 SVHS 1 00011 SVHS 2 00100 SVHS 3 00101 SVHS 4 00110 SVHS 5 00111 SVHS 6 01000 SVHS 7 01001 SVHS 8 01010 SVHS 9 01011 SVHS 10 01100 SVHS 11 01101 SVHS 12 01110 SVHS 13 01111 SVHS 14 10000 SVHS 15 10001 SVHS 16 10010 SVHS 17 10011 (default) SVHS 18 (CCIR 601) 10100 to 11111 Reserved; do not use

Figure 16 shows the filter responses of the SVHS 1 (narrowest) to SVHS 18 (widest) shaping filter settings, PAL notch filter responses, and

Figure 19 shows the NTSC notch

Figure 18 shows the

filter responses.

COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,

–10

–20

–30

–40

AMPLITUDE (dB)

–50

–60

–70

0186421

Y RESAMPLE

FREQUENCY (MHz )

05479-016

Figure 16. Y SVHS 1 to SVHS 18 Filter Responses

COMBINED Y ANTI ALIAS, CCI R MODE SHAPING FILT ER,

–20

–40

–60

AMPLITUDE (dB)

–80

–100

–120

0186421

Y RESAMPLE

FREQUENCY (MHz )

05479-017

Figure 17. Y SVHS 18 Extra Wideband Filter (CCIR 601 Compliant)

COMBINED Y ANTI ALIAS, PAL NOTCH FI LTERS,

–10

–20

–30

–40

AMPLITUDE (dB)

–50

–60

–70

0186421

Y RESAMPLE

FREQUENCY (MHz )

05479-018

Figure 18. Y PAL Notch Filter Responses

Rev. A | Page 33 of 112

ADV7184

–10

–20

–30

–40

AMPLITUDE (dB)

–50

–60

–70

COMBINED Y ANTI ALIAS, NT SC NOTCH FI LTERS,

0186421

Figure 19. Y NTSC Notch Filter Responses

Y RESAMPLE

FREQUENCY (MHz )

05479-019

CHROMA FILTER

Data from the digital fine-clamp block is processed by three sets of filters. The data format at this point is CVBS for CVBS inputs, chroma only for Y/C, or Cr/Cb interleaved for YPrPb input formats.

• Chroma Antialias (CAA) Filter. The ADV7184 oversamples

the CVBS by a factor of 2 and the chroma or Cr/Cb by a factor of 4. CAA, a decimating filter, is used to preserve the active video band and to remove any out-of-band components. The CAA filter has a fixed response.

• Chroma-Shaping (CSH) Filters. These filters can be

programmed to perform a variety of low-pass responses. They can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression.

• Digital Resampling Filter. This filter is used to allow

dynamic resampling of the video signal to alter parameters, such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system without user intervention.

COMBINED C ANTIALIAS, C SHAPI NG FIL TER,

–10

–20

–30

–40

ATTENUATIO N (dB)

–50

–60

0543216

Figure 20. Chroma-Shaping Filter Responses

C RESAMPLER

FREQUENCY (MHz )

CSFM [2:0], C-Shaping Filter Mode, Address 0x17 [7:5]

The C-shaping filter mode bits allow the user to select from a range of low-pass filters for the chrominance signal.

Table 38. CSFM [2:0] Function

CSFM [2:0] Description

000 (default) 1.5 MHz bandwidth filter 001 2.17 MHz bandwidth filter 010 SH1 011 SH2 100 SH3 101 SH4 110 SH5 111 Wideband mode

05479-020

Figure 20 shows the overall response of all filters, from SH1 (narrowest) to SH5 (widest), in addition to the wideband mode (in red).

Rev. A | Page 34 of 112

ADV7184

GAIN OPERATION

The gain control within the ADV7184 is done on a purely digital basis. The input ADCs support a 10-bit range, mapped into a 1.6 V analog voltage range. Gain correction takes place after the digitization in the form of a digital multiplier.

This architecture is advantageous because, unlike the commonly used programmable gain amplifier (PGA) placed in front of the ADCs, the gain is completely independent of supply, temperature, and process variations.

As shown in as long as it fits into the ADC window.

Figure 21, the ADV7184 can decode a video signal

The minimum supported amplitude of the input video is determined by the ability of the ADV7184 to retrieve horizontal and vertical timing and to lock to the color burst, if present.

There are separate gain control units for luma and chroma data. Both can operate independently of each other. The chroma unit, however, can also take its gain value from the luma path.

The possible AGC modes are summarized in

Table 3 9.

It is possible to freeze the automatic gain control loops. This causes the loops to stop updating and maintains the AGCdetermined gain that is active at the time of the freeze until the loop is either unfrozen or the gain mode of operation is changed.

The two components of decoding a video signal are the amplitude of the input signal and the dc level on which it resides. The dc level is set by the clamping circuitry (see the

Clamp Operation section).

If the amplitude of the analog video signal is too high, clipping can occur, resulting in visual artifacts. The analog input range

The currently active gain from any of the modes can be read back. Refer to the description of the dual-function manual gain bits, LMG [11:0] luma manual gain and CMG [11:0] chroma manual gain, in the

Luma Gain and the Chroma Gain sections.

of the ADC, together with the clamp level, determines the maximum supported amplitude of the video signal.

NALOG VO LTAGE

MAXIMUM VOLTAGE

MINIMUM VOLTAGE

CLAMP

LEVEL

RANGE SUPPORT ED BY ADC (1.6V RANG E FOR ADV7184)

DATA

ADC

Figure 21. Gain Control Overview

PRE-

PROCESSOR

(DPP)

SDP (GAIN SEL ECTION O NLY)

GAIN

CONTROL

Table 39. AGC Modes

Input Video Type Luma Gain Chroma Gain

Any Manual luma gain Manual chroma gain CVBS

Dependent on color burst amplitude Dependent on horizontal sync depth Taken from luma path

Peak white

Dependent on color burst amplitude Taken from luma path

Y/C

Dependent on color burst amplitude Dependent on horizontal sync depth Taken from luma path

Peak white

Dependent on color burst amplitude Taken from luma path

YPrPb Dependent on horizontal sync depth Taken from luma path

05479-021

Rev. A | Page 35 of 112

ADV7184

≤

Luma Gain

LAGC [2:0], Luma Automatic Gain Control, Address 0x2C [6:4]

The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path.

Analog Devices internal parameters can be used to customize the peak white gain control. Contact an Analog Devices representative for more information.

Table 40. LAGC [2:0] Function

LAGC [2:0] Description

000 Manual fixed gain (use LMG [11:0]) 001 Reserved 010 (default)

011 Reserved 100

101 Reserved 110 Reserved 111 Freeze gain

AGC peak white algorithm enabled (blank level to sync tip)

AGC peak white algorithm disabled (blank level to sync tip)

LAGT [1:0], Luma Automatic Gain Timing, Address 0x2F [7:6]

The luma automatic gain timing bits allow the user to influence the tracking speed of the luminance automatic gain control. Note that these bits only have an effect if the LAGC [2:0] bits are set to 010 or 100 (automatic gain control modes).

If peak white AGC is enabled and active (see the [7:0], Address 0x10 [7:0]

section), the actual gain update speed

Status Register 1

is dictated by the peak white AGC loop and, as a result, the LAGT settings have no effect. As soon as the part leaves peak white AGC, LAGT becomes relevant.

The update speed for the peak white algorithm can be customized by using internal parameters. Contact an Analog Devices representative for more information.

Table 41. LAGT [1:0] Function

LAGT [1:0] Description

00 Slow (TC = 2 sec) 01 Medium (TC = 1 sec) 10 Fast (TC = 0.2 sec) 11 (default) Adaptive

LG [11:0]/LMG [11:0], Luma Gain/Luma Manual Gain, Address 0x2F [3:0], Address 0x30 [7:0]

Luma manual gain [11:0] are dual-function bits. If these bits are written to, a desired manual luma gain can be programmed. This gain becomes active if the LAGC [2:0] mode is switched to manual fixed gain. Equation 2 and Equation 3 show how to calculate a desired gain for NTSC and PAL standards, respectively.

NTSC Luma_Gain =

:LMG

1128

4095]011[1024

63.39078.0

(2)

PAL Luma_Gain =

4095]011[1024

1222

≤< :LMG

351.3838.0

(3)

If read back, this register returns the current gain value. Depending on the settings of the LAGC [2:0] bits, this value is one of the following:

• Luma manual gain value (LAGC [2:0] set to luma manual

gain mode)

• Luma automatic gain value (LAGC [2:0] set to any of the

automatic modes)

Table 42. LG [11:0]/LMG [11:0] Function

LG [11:0]/LMG [11:0] Read/Write Description

LMG [11:0] = X Write Manual gain for luma path LG [11:0] Read Actual gain used

For example, to program the ADV7184 into manual fixed gain mode with a desired gain of 0.95 for the NTSC standard

1. Use Equation 2 to convert the gain:

0.95 × 1128 = 1071.6

2. Truncate to integer value:

1071.6 = 1071

3. Convert to hexadecimal:

1071d = 0x42F

4. Split into two registers and program:

Luma Gain Control 1 [3:0] = 0x4 Luma Gain Control 2 [7:0] = 0x2F

5. Enable manual fixed gain mode:

Set LAGC [2:0] to 000

Rev. A | Page 36 of 112

ADV7184

BETACAM, Enable BETACAM Levels, Address 0x01 [5]

If YPrPb data is routed through the ADV7184, the automatic gain control modes can target different video input levels, as outlined in

Tabl e 44 . Note that the BETACAM bit is valid only if the input mode is YPrPb (component). The BETACAM bit sets the target value for AGC operation.

PW_UPD, Peak White Update, Address 0x2B [0]

The peak white and average video algorithms determine the gain based on measurements taken from the active video. The PW_UPD bit determines the rate of gain change. LAGC [2:0] must be set to the appropriate mode to enable the peak white or average video mode.

A review of the following sections is useful:

• The

INSEL [3:0], Input Selection, Address 0x00 [3:0] section describes how component video (YPrPb) can be routed through the ADV7184.

• The

Video Standard Selection section describes the various standards, for example, with and without pedestal.

For more information, refer to the Gain Control, Address 0x2C [6:4]

0—Updates the gain once per video line.

1 (default)—Updates the gain once per field.

LAGC [2:0], Luma Automatic

section.

The automatic gain control (AGC) algorithms adjust the levels based on the setting of the BETACAM bit.

Table 43. BETACAM Function

BETACAM Description

0 (default)

Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE 1

Selecting PAL with pedestal selects BETACAM

Selecting NTSC with pedestal selects BETACAM

Standard video input (assuming YPrPb is selected as input format)

BETACAM input enable (assuming YPrPb is selected as input format)

Selecting PAL without pedestal selects BETACAM variant

Selecting NTSC without pedestal selects BETACAM variant

Table 44. BETACAM Levels

Name BETACAM (mV) BETACAM Variant (mV) SMPTE (mV) MII (mV)

Y Range 0 to 714 (including 7.5% pedestal) 0 to 714 0 to 700 0 to 700 (including 7.5% pedestal) Pr and Pb Ranges −467 to +467 −505 to +505 −350 to +350 −324 to +324 Sync Depth 286 286 300 300

Rev. A | Page 37 of 112

ADV7184

Chroma Gain

CAGC [1:0], Chroma Automatic Gain Control, Address 0x2C [1:0]

These two bits select the basic mode of operation for automatic gain control in the chroma path.

Table 45. CAGC [1:0] Function

CAGC [1:0] Description

00 Manual fixed gain (use CMG [11:0]) 01 Use luma gain for chroma 10 (default) Automatic gain (based on color burst) 11 Freeze chroma gain

CAGT [1:0], Chroma Automatic Gain Timing, Address 0x2D [7:6]

These bits allow the user to influence the tracking speed of the chroma automatic gain control, but have an effect only if the CAGC [1:0] bits are set to 10 (automatic gain).

Table 46. CAGT [1:0] Function

CAGT [1:0] Description

00 Slow (TC = 2 sec) 01 Medium (TC = 1 sec) 10 Fast (TC = 0.2 sec) 11 (default) Adaptive

CMG [11:0]/CG [11:0], Chroma Manual Gain/Chroma Gain, Address 0x2D [3:0], Address 0x2E [7:0]

CMG [11:0] are dual-function bits. If these bits are written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC [1:0] mode is switched to manual fixed gain. Refer to Equation 4 to calculate a desired gain. If read back, these bits return the current gain value. Depending on the setting in the CAGC [1:0] bits, this is either

• Chroma manual gain value (CAGC [1:0] set to chroma

manual gain mode)

• Chroma automatic gain value (CAGC [1:0] set to any of

the automatic modes)

Table 47. CG [11:0]/CMG [11:0] Function

CG [11:0]/CMG [11:0] Read/Write Description

CMG [11:0] Write

CG [11:0] Read Currently active gain

_ =

()

GainChroma

1024

40950

≤<=CG

Manual gain for chroma path

4...0

(4)

For example, freezing the automatic gain loop results in a readback value of 0x47A for the CMG [11:0] bits.

Convert the readback value to decimal:

1. 0x47A = 1146d

Apply Equation 4 to convert the readback value:

1146/1024 = 1.12

CKE, Color-Kill Enable, Address 0x2B [6]

This bit allows the optional color-kill function to be switched on or off. For QAM-based video standards (PAL and NTSC) and FM-based systems (SECAM), the threshold for the colorkill decision is selectable via the CKILLTHR [2:0] bits (Address 0x3D).

If color kill is enabled and the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines, color processing is switched off (black and white output). To switch the color processing back on, another 128 consecutive lines with a color burst greater than the threshold are required.

The color-kill option only works for input signals with a modulated chroma part. For component (YPrPb) input, there is no color kill.

0—Disables color kill.

1 (default)—Enables color kill.

CKILLTHR [2:0], Color-Kill Threshold, Address 0x3D [6:4]

The CKILLTHR [2:0] bits allow the user to select a threshold for the color-kill function. The threshold applies only to QAMbased (NTSC and PAL) or FM-modulated (SECAM) video standards.

To enable the color-kill function, the CKE bit must be set. For CKILLTHR settings 000, 001, 010, and 011, chroma demodulation inside the ADV7184 may not work satisfactorily for poor input video signals.

Table 48. CKILLTHR [2:0] Function

CKILLTHR [2:0] SECAM NTSC, PAL 000 No color kill Kill at <0.5% 001 Kill at <5% Kill at <1.5% 010 Kill at <7% Kill at <2.5% 011 Kill at <8% Kill at <4.0% 100 (default) Kill at <9.5% Kill at <8.5% 101 Kill at <15% Kill at <16.0% 110 Kill at <32% Kill at <32.0%. 111

Reserved for Analog Devices internal use only;

Description

do not select

Rev. A | Page 38 of 112

ADV7184

CHROMA TRANSIENT IMPROVEMENT (CTI)

The signal bandwidth allocated for chroma is typically much smaller than that of luminance. With older devices, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance.

The uneven bandwidth, however, may lead to visual artifacts during sharp color transitions. At the border of two bars of color, both components (luma and chroma) change at the same time (see

Due to the higher bandwidth, the signal transition of the luma component is usually much sharper than that of the chroma component. The color edge is not sharp and can be blurred, in the worst case, over several pixels.

DEMODUL ATED

To correct for such uneven bandwidths, the CTI block examines the input video data. It detects transitions of chroma and can be programmed to create steeper chroma edges in an attempt to artificially restore lost color bandwidth. By operating only on edges that are greater than a certain threshold, the CTI block ensures that noise is not emphasized. Care has also been taken to avoid edge ringing and undesirable saturation and hue distortion.

Chroma transient improvements are needed primarily for signals that have severe chroma bandwidth limitations. For these types of signals, it is strongly recommended to enable the CTI block via CTI_EN.

CTI_EN, Chroma Transient Improvement Enable, Address 0x4D [0]

0—Disables the CTI block.

1 (default)—Enables the CTI block.

CTI_AB_EN, Chroma Transient Improvement Alpha Blend Enable, Address 0x4D [1]

This bit enables an alpha-blend function, which mixes the transient improved chroma with the original signal. The sharpness of the alpha blending can be configured via the CTI_AB [1:0] bits. For the alpha blender to be active, the CTI

Figure 22).

LUMA

SIGNAL

CHROMA

SIGNAL

LUMA SIGNAL WITH A TRANSITIO N, ACCOMPANI ED BY A CHROMA TRANSIT ION

ORIGINAL SLOW CHROMA TRANSITION PRIOR TO CTI

SHARPENED CHROMA TRANSITION AT THE OUTPUT OF CTI

Figure 22. CTI Luma/Chroma Transition

05479-022

block must be enabled via the CTI_EN bit. The settings of the CTI_AB_EN bit are as follows:

0—Disables the CTI alpha blender.

1 (default)—Enables the CTI alpha blender.

CTI_AB [1:0], Chroma Transient Improvement Alpha Blend, Address 0x4D [3:2]

The CTI_AB [1:0] controls the behavior of alpha-blend circuitry, which mixes the sharpened chroma signal with the original one. It thereby controls the visual impact of CTI on the output data.

For CTI_AB [1:0] to become active, the CTI block must be enabled via the CTI_EN bit and the alpha blender must be switched on via CTI_AB_EN.

Sharp blending maximizes the effect of CTI on the picture, but may also increase the visual impact of small amplitude, high frequency chroma noise.

Table 49. CTI_AB [1:0] Function

CTI_AB [1:0] Description

00 Sharpest mixing 01 Sharp mixing 10 Smooth mixing 11 (default) Smoothest mixing

CTI_C_TH [7:0], CTI Chroma Threshold, Address 0x4E [7:0]

The CTI_C_TH [7:0] value is an unsigned, 8-bit number specifying how big the amplitude step in a chroma transition must be to be steepened by the CTI block. Programming a small value into this register causes even, small edges to be steepened by the CTI block. Making CTI_C_TH [7:0] a large value causes the block to only improve large transitions.

The default value for CTI_C_TH [7:0] is 0x08, indicating the threshold for the chroma edges prior to CTI.

DIGITAL NOISE REDUCTION (DNR) AND LUMA PEAKING FILTER

DNR is based on the assumption that high frequency signals with low amplitude are probably noise and that their removal, therefore, improves picture quality. There are two DNR blocks in the ADV7184: the DNR1 block before the luma peaking filter and the

DNR2

Figure 23.

LUMA OUTPUT

05479-023

DNR2 block after the luma peaking filter, as shown in

LUMA

IGNAL

DNR1

Figure 23. DNR and Peaking Block Diagram

LUMA PEAKING

FILTER

Rev. A | Page 39 of 112

ADV7184

DNR_EN, Digital Noise Reduction Enable, Address 0x4D [5] DNR_TH2 [7:0], DNR Noise Threshold 2,

0—Bypasses DNR (disables it).

1 (default)—Enables DNR on the luma data.

DNR_TH [7:0], DNR NoiseThreshold, Address 0x50 [7:0]

The DNR1 block is positioned before the luma peaking block. The DNR_TH [7:0] value is an unsigned, 8-bit number that determines the maximum edge that is interpreted as noise and therefore blanked from the luma data. Programming a large value into DNR_TH [7:0] causes the DNR block to interpret even, large transients as noise and remove them. As a result, the effect on the video data is more visible.

Programming a small value causes only small transients to be seen as noise and to be removed.

The recommended DNR_TH [7:0] setting for A/V inputs is 0x04, and the recommended DNR_TH [7:0] setting for tuner inputs is 0x0A.

The default value for DNR_TH [7:0] is 0x08, indicating the threshold for maximum luma edges to be interpreted as noise.

PEAKING_GAIN [7:0], Luma Peaking Gain, Address 0xFB [7:0]

This filter can be manually enabled. The user can boost or attenuate the mid region of the Y spectrum around 3 MHz. The peaking filter can visually improve the picture by showing more definition on the picture details that contain frequency components around 3 MHz. The default value (0x40) in this register passes through the luma data unaltered (0 dB response). A lower value attenuates the signal, and a higher value amplifies it. A plot of the filter responses is shown in

–5

–10

FILTER RESPONSE (dB)

–15

–20

PEAKING GAI N USING BP F ILTER

123456

Figure 24. Peaking Filter Responses

Figure 24.

FREQUENCY (M Hz)

05479-024

Address 0xFC [7:0]

The DNR2 block is positioned after the luma peaking block and therefore affects the amplified luma signal. It operates in the same way as the DNR1 block, but has an independent threshold control, DNR_TH2 [7:0]. This value is an unsigned, 8-bit number that determines the maximum edge that is interpreted as noise and therefore blanked from the luma data. Programming a large value into DNR_TH2 [7:0] causes the DNR block to interpret even, large transients as noise and remove them. As a result, the effect on the video data is more visible. Programming a small value causes only small transients to be seen as noise and to be removed.

COMB FILTERS

The comb filters of the ADV7184 have been greatly improved to automatically handle video of all types, standards, and levels of quality. The NTSC and PAL configuration registers allow the user to customize comb filter operation, depending on which video standard is detected (by autodetection) or selected (by manual programming). In addition to the bits listed in this section, there are other Analog Devices internal controls. Contact an Analog Devices representative for more information.

NTSC Comb Filter Settings

Used for NTSC M and NTSC J CVBS inputs.

NSFSEL [1:0], Split Filter Selection NTSC, Address 0x19 [3:2]

NSFSEL [1:0] selects how much of the overall signal bandwidth is fed to the combs. A narrow bandwidth split filter results in better performance on diagonal lines, but more dot crawl in the final output image. The opposite is true for a wide bandwidth split filter.

Table 50. NSFSEL [1:0] Function

NSFSEL [1:0] Description

00 (default) Narrow 01 Medium 10 Medium 11 Wide

CTAPSN [1:0], Chroma Comb Taps NTSC, Address 0x38 [7:6]

Table 51. CTAPSN [1:0] Function

CTAPSN [1:0] Description

00 Do not use 01

10 (default)

NTSC chroma comb adapts three lines (three taps) to two lines (two taps)

NTSC chroma comb adapts five lines (five taps) to three lines (three taps)

NTSC chroma comb adapts five lines (five taps) to four lines (four taps)

Rev. A | Page 40 of 112

ADV7184

CCMN [2:0], Chroma Comb Mode NTSC, Address 0x38 [5:3]

Table 52. CCMN [1:0] Function

CCMN [2:0] Description Configuration 000 (default) Adaptive comb mode

100 Disable chroma comb 101 Fixed chroma comb (top lines of line memory)

110 Fixed chroma comb (all lines of line memory)

111 Fixed chroma comb (bottom lines of line memory)

YCMN [2:0], Luma Comb Mode NTSC, Address 0x38 [2:0]

Table 53. YCMN [2:0] Function

YCMN [2:0] Description Configuration

000 (default) Adaptive comb mode Adaptive 3-line (three taps) luma comb 100 Disable luma comb Use low-pass/notch filter; see the Y-Shaping Filter section 101 Fixed luma comb (top lines of line memory) Fixed 2-line (two taps) luma comb 110 Fixed luma comb (all lines of line memory) Fixed 3-line (three taps) luma comb 111 Fixed luma comb (bottom lines of line memory) Fixed 2-line (two taps) luma comb

Adaptive 3-line chroma comb for CTAPSN = 01 Adaptive 4-line chroma comb for CTAPSN = 10 Adaptive 5-line chroma comb for CTAPSN = 11

Fixed 2-line chroma comb for CTAPSN = 01 Fixed 3-line chroma comb for CTAPSN = 10 Fixed 4-line chroma comb for CTAPSN = 11 Fixed 3-line chroma comb for CTAPSN = 01 Fixed 4-line chroma comb for CTAPSN = 10 Fixed 5-line chroma comb for CTAPSN = 11 Fixed 2-line chroma comb for CTAPSN = 01 Fixed 3-line chroma comb for CTAPSN = 10 Fixed 4-line chroma comb for CTAPSN = 11

Rev. A | Page 41 of 112

ADV7184

PAL Comb Filter Settings

Used for PAL B/G/H/I/D, PAL M, PAL Combinational N, PAL 60, and NTSC 4.43 CVBS inputs.

PSFSEL [1:0], Split Filter Selection PAL, Address 0x19 [1:0]

PFSEL [1:0] selects how much of the overall signal bandwidth is fed to the combs. A wide bandwidth split filter eliminates dot crawl, but shows imperfections on diagonal lines. The opposite is true for a narrow bandwidth split filter.

Table 54. PSFSEL [1:0] Function

PSFSEL [1:0] Description

00 Narrow 01 (default) Medium 10 Wide 11 Widest

CTAPSP [1:0], Chroma Comb Taps PAL, Address 0x39 [7:6]

Table 55. CTAPSP [1:0] Function

CTAPSP [1:0] Description

00 Do not use 01

11 (default)

PAL chroma comb adapts five lines (three taps) to three lines (two taps); cancels cross luma only

PAL chroma comb adapts five lines (five taps) to three lines (three taps); cancels cross luma and hue error less well

PAL chroma comb adapts five lines (five taps) to four lines (four taps); cancels cross luma and hue error well

CCMP [2:0], Chroma Comb Mode PAL, Address 0x39 [5:3]

Table 56. CCMP [2:0] Function

CCMP [2:0]

000 (default)

100 Disable chroma comb 101

110

111

Description Configuration

Adaptive comb mode

Fixed chroma comb (top lines of line memory)

Fixed chroma comb (all lines of line memory)

Fixed chroma comb (bottom lines of line memory)

Adaptive 3-line chroma comb for CTAPSP = 01

Adaptive 4-line chroma comb for CTAPSP = 10

Adaptive 5-line chroma comb for CTAPSP = 11

Fixed 2-line chroma comb for CTAPSP = 01

Fixed 3-line chroma comb for CTAPSP = 10

Fixed 4-line chroma comb for CTAPSP = 11

Fixed 3-line chroma comb for CTAPSP = 01

Fixed 4-line chroma comb for CTAPSP = 10

Fixed 5-line chroma comb for CTAPSP = 11

Fixed 2-line chroma comb for CTAPSP = 01

Fixed 3-line chroma comb for CTAPSP = 10

Fixed 4-line chroma comb for CTAPSP = 11

YCMP [2:0], Luma Comb Mode PAL, Address 0x39 [2:0]

Table 57. YCMP [2:0] Function

YCM P [2:0]

0xx (default)

100 Disable luma comb

101

110

111

Description Configuration

Adaptive comb mode

Fixed luma comb (top lines of line memory)

Fixed luma comb (all lines of line memory)

Fixed luma comb (bottom lines of line memory)

Adaptive 5-line, 3-tap luma comb

Use low-pass/notch filter (see the section)

Fixed 3-line, 2-tap luma comb

Fixed 5-line, 3-tap luma comb

Fixed 3-line, 2-tap luma comb

Y-Shaping Filter

Rev. A | Page 42 of 112

ADV7184

Vertical Blank Control

Each vertical blank control register (Addresses 0xEB and 0xEC) has the same meaning for the following bit settings:

00—Early by one line. 10—Delayed by one line. 11—Delayed by two lines. 01 (default)—Described in each register section.

NVBIOLCM [1:0], NTSC VBI Odd Field Luma Comb Mode, Address 0xEB [7:6]

These bits control the first combed line after VBI on NTSC odd field (luma comb).

01 (default)—SMPTE170-/ITU-R BT.470-compliant; blank Lines 1 to 20, 264 to 282; comb half lines.

NVBIELCM [1:0], NTSC VBI Even Field Luma Comb Mode, Address 0xEB [5:4]

These bits control the first combed line after VBI on NTSC even field (luma comb).

01 (default)—SMPTE170-/ITU-R BT.470-compliant; blank Lines 1 to 20, 264 to 282; comb half lines.

PVBIOLCM [1:0], PAL VBI Odd Field Luma Comb Mode, Address 0xEB [3:2]

These bits control the first combed line after VBI on PAL odd field (luma comb).

01 (default)—ITU-R BT.470-compliant; blank Lines 624 to 22, 311 to 335; comb half lines.

PVBIELCM [1:0], PAL VBI Even Field Luma Comb Mode, Address 0xEB [1:0]

These bits control the first combed line after VBI on PAL even field (luma comb).

PVBIOCCM [1:0], PAL VBI Odd Field Chroma Comb Mode, Address 0xEC [3:2]

These bits control the first combed line after VBI on PAL odd field (chroma comb).

01 (default)—ITU-R BT.470-compliant; no color on Lines 624 to 22, 311 to 335; chroma present on half lines.

PVBIECCM [1:0], PAL VBI Even Field Chroma Comb Mode, Address 0xEC [1:0]

These bits control the position of the first combed line after VBI on PAL even field (chroma comb).

01 (default)—ITU-R BT.470-compliant; no color on Lines 624 to 22, 311 to 335; chroma present on half lines.

AV CODE INSERTION AND CONTROLS

This section describes the I2C-based controls that affect

Insertion of AV codes into the data stream

•

Data blanking during the vertical blanking interval (VBI)

•

The range of data values permitted in the output data stream

•

The relative delay of luma vs. chroma signals

•

Note that some of the decoded VBI data is inserted during the horizontal blanking interval. See the section for more information.

BT656-4, ITU-R BT.656-4 Enable, Address 0x04 [7]

Revisions 3 and 4 of the ITU-R BT.656 standard have different positions for toggling the V bit within the SAV EAV codes for NTSC. The BT656-4 bit allows the user to select an output mode that is compliant with either the previous or new standard. For more information, visit the International Telecommunication Union’s website.

Gemstar Data Recovery

01 (default)—ITU-R BT.470-compliant; blank Lines 624 to 22, 311 to 335; comb half lines.

NVBIOCCM [1:0], NTSC VBI Odd Field Chroma Comb Mode, Address 0xEC [7:6]

These bits control the first combed line after VBI on NTSC odd field (chroma comb).

01 (default)—SMPTE170-/ITU-R BT.470-compliant; no color on Lines 1 to 20, 264 to 282; chroma present on half lines.

NVBIECCM [1:0], NTSC VBI Even Field Chroma Comb Mode, Address 0xEC [5:4]

These bits control the first combed line after VBI on NTSC even field (chroma comb).

01 (default)—SMPTE170-/ITU-R BT.470-compliant; no color on Lines 1 to 20, 264 to 282; chroma present on half lines.

Rev. A | Page 43 of 112

Note that the standard change affects only NTSC and has no bearing on PAL.

0 (default)—The ITU-R BT.656-3 specification is used. The V bit goes low at EAV of Lines 10 and 273.

1—The ITU-R BT.656-4 specification is used. The V bit goes low at EAV of Lines 20 and 283.

SD_DUP_AV, Duplicate AV Codes, Address 0x03 [0]

Depending on the output interface width, it may be necessary to duplicate the AV codes from the luma path into the chroma path.

In an 8-bit-wide output interface (Cb/Y/Cr/Y interleaved data), the AV codes are defined as FF/00/00/AV, with AV being the transmitted word that contains information about H/V/F.

In this output interface mode, the following assignment takes place: Cb = FF, Y = 00, Cr = 00, and Y = AV.

ADV7184

In a 16-bit output interface where Y and Cr/Cb are delivered via separate data buses, the AV code is over the whole 16 bits. The SD_DUP_AV bit allows the user to replicate the AV codes on both buses; therefore, the full AV sequence can be found on the Y data bus and on the Cr/Cb data bus (see

Figure 25).

0 (default)—The AV codes are in single fashion (to suit 8-bit interleaved data output).

1—The AV codes are duplicated (for 16-bit interfaces).

Refer to the Address 0x04 [2]

0 (default)—All video lines are filtered and scaled.

1—Only the active video region is filtered and scaled.

BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2]

Setting BL_C_VBI high blanks the Cr and Cb values of all VBI lines. This is done to prevent data that arrives during VBI from being decoded as color and output through Cr and Cb. As

VBI_EN, Vertical Blanking Interval Data Enable, Address 0x03 [7]

The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the

a result, it is possible to send VBI lines into the decoder, and then output them undistorted through an encoder. Without this blanking, any incorrectly decoded color would be encoded by

the video encoder and therefore the VBI lines would be distorted. decoder with a minimal amount of filtering. All data for Line 1 to Line 21 is passed through and available at the output port.

The ADV7184 does not blank the luma data, but automatically

0—Decodes and outputs color during VBI.

1 (default)—Blanks Cr and Cb values during VBI.

switches all filters along the luma data path into their widest bandwidth. For active video, the filter settings for YSH and YPK are restored.

SD_DUP_

Y DATA BUS 00 AV YFF 00 00 AV Y

r/Cb DATA BUS 00 00 AV Cb FF 00 Cb

AV CODE SECTION AV CODE SECTION

= 1 SD_DUP_

Figure 25. AV Code Duplication Control

BL_C_VBI, Blank Chroma During VBI,

section for information on the chroma path.

= 0

8-BIT INT ERFACE16-BIT INTERFACE16-BIT INT ERFACE

Cb/Y/Cr/Y

INTERLEAVED

FF 00 00 AV Cb

AV CODE SECTION

05479-025

Rev. A | Page 44 of 112

ADV7184

RANGE, Range Selection, Address 0x04 [0]

AV codes (as per ITU-R BT.656, formerly known as CCIR 656) consist of a fixed header made up of 0xFF and 0x00 values. These two values are reserved and therefore are not to be used for active video. Additionally, the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and between 16 and 240 for chroma.

CTA [2:0], Chroma Timing Adjust, Address 0x27 [5:3]

These bits allow the user to specify a timing difference between chroma and luma samples. This may be used to compensate for external filter group delay differences in the luma vs. chroma path and to allow a different number of pipeline delays while processing the video downstream. Review this functionality together with that of the LTA [1:0] bits.

The RANGE bit allows the user to limit the range of values output by the ADV7184 to the recommended value range. This ensures that the reserved values of 255d (0xFF) and 00d (0x00) are not presented on the output pins unless they are part of an AV c o de h e a de r.

Table 58. RANGE Function

RANGE Description

0 16 ≤ Y ≤ 235 16 ≤ C ≤ 240 1 (default) 1 ≤ Y ≤ 254 1 ≤ C ≤ 254

AUTO_PDC_EN, Automatic Programmed Delay Control, Address 0x27 [6]

Enabling AUTO_PDC_EN activates a function within the ADV7184 that automatically programs LTA [1:0] and CTA [2:0] to have the chroma and luma data match delays for all modes of operation.

0—The ADV7184 uses the LTA [1:0] and CTA [2:0] values for delaying luma and chroma samples. Refer to the Luma Timing Adjust, Address 0x27 [1:0] Chroma Timing Adjust, Address 0x27 [5:3]

LTA [1:0],

and the CTA [2:0],

sections.

1 (default)—The ADV7184 automatically programs the LTA and CTA values to have luma and chroma aligned at the output. Manual registers LTA [1:0] and CTA [2:0] are not used.

LTA [1:0], Luma Timing Adjust, Address 0x27 [1:0]

These bits allow the user to specify a timing difference between chroma and luma samples.

Note that there is a certain functionality overlap with the CTA [2:0] bits. For manual programming, use the following defaults:

•

CVBS input LTA [1:0] = 00

Y/C input LTA [1:0] = 01

•

YPrPb input LTA [1:0] = 01

•

Table 59. LTA [1:0] Function

LTA [1:0] Description

00 (default) No delay 01 Luma 1 clock (37 ns) delayed 10 Luma 2 clock (74 ns) early 11 Luma 1 clock (37 ns) early

The chroma can be delayed or advanced only in chroma pixel steps. One chroma pixel step is equal to two luma pixels. The programmable delay occurs after demodulation, when no delay by luma pixel steps are allowed.

For manual programming, use the following defaults:

•

CVBS input CTA [2:0] = 011

Y/C input CTA [2:0] = 101

•

• YPrPb input CTA [2:0] = 110

Table 60. CTA Function

CTA [2:0] Description

000 Not used 001 Chroma plus two chroma pixels (early) 010 Chroma plus one chroma pixel (early) 011 (default) No delay 100 Chroma minus one chroma pixel (delayed) 101 Chroma minus two chroma pixels (delayed) 110 Chroma minus three chroma pixels (delayed) 111 Not used

SYNCHRONIZATION OUTPUT SIGNALS

HS Configuration

The following controls allow the user to configure the behavior of the HS output pin only:

HSB [10:0]: sets beginning of HS signal

•

• HSE [10:0]: sets end of HS signal

PHS: sets polarity of HS

•

The HS begin (HSB) and HS end (HSE) bits allow the user to position the HS output pin anywhere within the video line. The values in HSB [10:0] and HSE [10:0] are measured in pixel units from the falling edge of HS. Using both values, the user can program both the position and length of the HS output signal.

HSB [10:0], HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]

The position of this edge is controlled by placing a binary number into HSB [10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF, 00, 00, XY (see to 00000000010, which is two LLC1 clock cycles from Count [0].

The default value of HSB [10:0] is 0x002, indicating that the HS pulse starts two pixels after the falling edge of HS.

Figure 26). HSB [10:0] is set

Rev. A | Page 45 of 112

ADV7184

Table 61. HS Timing Parameters (see Figure 26)

Characteristics

Active Video Samples/Line

Figure 26)

(D in

Standard

HS Begin Adjust (HSB [10:0]) (Default)

HS End Adjust (HSE [10:0]) (Default)

HS to Active Video (LLC1 Clock Cycles)

Figure 26) (Default)

(C in

NTSC 00000000010 00000000000 272 720Y + 720C = 1440 1716 NTSC Square

00000000010 00000000000 276 640Y + 640C = 1280 1560

Pixel

PAL 00000000010 00000000000 284 720Y + 720C = 1440 1728

LLC1

Total LLC1 Clock Cycles

Figure 26)

(E in

PIXEL

BUS

Cr Y FF 00 00 XY 80 10 80 10 80 10 FF 00 00 XY Cb Y Cr Y Cb Y Cr

ACTIVE

VIDEO

HSB[10:0]HSE[10:0]

4 LLC1

Figure 26. HS Timing

HSE [10:0] HS End, Address 0x34 [2:0], Address 0x36 [7:0]

The position of this edge is controlled by placing a binary number into HSE [10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF, 00, 00, XY (see

Figure 26). HSE is set to

00000000000, which is 0 LLC1 clock cycles from Count [0].

The default value of HSE [10:0] is 000, indicating that the HS pulse ends 0 pixels after the falling edge of HS.

For example,

• To shift the HS toward active video by 20 LLC1s, add

20 LLC1s to both HSB and HSE, that is, HSB [10:0] = [00000010110] and HSE [10:0] = [00000010100].

• To shift the HS away from active video by 20 LLC1s, add

1696 LLC1s to both HSB and HSE (for NTSC), that is, HSB [10:0] = [11010100010] and HSE [10:0] = [11010100000]. The number 1696 is derived from the NTSC total number of pixels = 1716.

To move 20 LLC1s away from active video is equal to subtracting 20 from 1716 and adding the result in binary to both HSB [10:0] and HSE [10:0].

PHS Polarity HS, Address 0x37 [7]

The polarity of the HS pin can be inverted using the PHS bit.

SAV ACTIVE VIDEOH BLANKEAV

05479-026

VS and FIELD Configuration

The following controls allow the user to configure the behavior

of the VS and FIELD output pins and to generate the following

embedded AV codes:

•

ADV encoder-compatible signals via NEWAVMODE

PVS, PF

•

HVSTIM

•

VSBHO, VSBHE

•

VSEHO, VSEHE

•

For NTSC control

•

• NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG [4:0]

• NVENDDELO, NVENDDELE, NVENDSIGN, NVEND [4:0]

• NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG [4:0]

For PAL control

•

• PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG [4:0]

• PVENDDELO, PVENDDELE, PVENDSIGN, PVEND [4:0]

• PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG [4:0]

0 (default)—HS is active high.

1—HS is active low.

Rev. A | Page 46 of 112

ADV7184

NEWAVMODE, New AV Mode, Address 0x31 [4]

0—EAV/SAV codes are generated to suit Analog Devices encoders. No adjustments are possible.

1 (default)—Enables the manual position of VS/FIELD and AV codes using Register 0x32, Register 0x33, and Register 0xE5 to Register 0xEA. Default register settings are CCIR 656 compliant;

Figure 27 for NTSC and Figure 32 for PAL. For

see recommended manual user settings, see for NTSC and

Table 6 3 and Figure 33 for PAL.

Tabl e 62 and Figure 28

HVSTIM, Horizontal VS Timing, Address 0x31 [3]

The HVSTIM bit allows the user to select where the VS signal is asserted within a line of video. Some interface circuitry may require VS to go low while HS is low.

0 (default)—The start of the line is relative to HSE.

1—The start of the line is relative to HSB.

VSBHO, VS Begin Horizontal Position Odd, Address 0x32 [7]

This bit selects the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state only when HS is high or low.

0 (default)—The VS pin goes high at the middle of a line of video (odd field).

1—The VS pin changes state at the start of a line (odd field).

VSBHE, VS Begin Horizontal Position Even, Address 0x32 [6]

This bit selects the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state only when HS is high or low.

0—The VS pin goes high at the middle of a line of video (even field).

1 (default)—The VS pin changes state at the start of a line (even field).

VSEHO VS, End Horizontal Position Odd, Address 0x33 [7]

This bit selects the position within a line at which the VS pin (not the bit in the AV code) becomes inactive. Some follow-on chips require the VS pin to change state only when HS is high or low.

0—The VS pin goes low (inactive) at the middle of a line of video (odd field).

1 (default)—The VS pin changes state at the start of a line (odd field).

VSEHE, VS End Horizontal Position Even, Address 0x33 [6]

This bit selects the position within a line at which the VS pin (not the bit in the AV code) becomes inactive. Some follow-on chips require the VS pin to change state only when HS is high or low.

0 (default)—The VS pin goes low (inactive) at the middle of a line of video (even field).

1—The VS pin changes state at the start of a line (even field).

PVS, Polarity VS, Address 0x37 [5]

The polarity of the VS pin can be inverted using the PVS bit.

0 (default)—VS is active high.

1—VS is active low.

PF, Polarity FIELD, Address 0x37 [3]

The polarity of the FIELD pin can be inverted using the PF bit.

0 (default)—FIELD is active high.

1—FIELD is active low.

Table 62. Recommended User Settings for NTSC (See Figure 28)

0x31 Vsync Field Control 1 0x1A 0x32 Vsync Field Control 2 0x81 0x33 Vsync Field Control 3 0x84 0x34 Hsync Position 1 0x00 0x35 Hsync Position 2 0x00 0x36 Hsync Position 3 0x7D 0x37 Polarity 0xA1 0xE5 NTSV V bit begin 0x41 0xE6 NTSC V bit end 0x84 0xE7 NTSC F bit toggle 0x06

Rev. A | Page 47 of 112

ADV7184

OUTPUT

VIDEO

OUTPUT

VIDEO

*APPLIES I F NEMAVMODE = 0:

525 1 2 3 4 5 6 7 8 9 10111213 19 2021 22

NVBEG[4: 0] = 0x5

262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 28 3 284 285

NVBEG[4:0] = 0x5 NVEND[4:0] = 0x4

MUST BE MANUALL Y SHIFTED IF NEWAVMODE = 1.

FIELD 1

NVEND[4:0] = 0x4

NFTOG [4:0] = 0x3

FIELD 2

*BT .656-4

REG 0x04, BIT 7 = 1

NFTOG [4:0] = 0x 3

Figure 27. NTSC Default (ITU-R BT.656), the Polarities of HS, VS, and FIELD are Embedded in the Data

*BT.656-4

REG 0x04, BIT 7 = 1

05479-027

OUTPUT

VIDEO

OUTPUT

FIELD

OUTPUT

VIDEO

OUTPUT

FIELD

OUTPUT

FIELD 1

5251 23456 7 8 9 1011121314152122

NVBEG[4:0] = 0x0 NVEND[4:0] = 0x3

NFTOG [4:0] = 0x5

FIELD 2

262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 284 285

NVBEG[4:0] = 0x0 NVEND[4:0] = 0x3

Figure 28. NTSC Typical VS/FIELD Positions Using Register Writes in

NFTOG [4:0] = 0x5

Table 62

05479-028

Rev. A | Page 48 of 112

ADV7184

ADVANCE BEGIN OF

VSYNC BY NVBEG[ 4:0]

NOT VALID FOR USER

PROGRAMMING

NVBEGDELO

ADDITIONAL

DELAY BY

1 LINE

VSBHO

ADVANCE BY

0.5 LINE

1 0

NVBEGSIG N

ODD FIELD?

DELAY BEGIN O F

VSYNC BY NVBEG[4: 0]

NOYES

NVBEGDELE

ADDITIONAL

DELAY BY

1 LINE

VSBHE

ADVANCE BY

0.5 LINE

ADVANCE END OF

VSYNC BY NVEND[4:0]

NOT VALID FOR USER

PROGRAMMING

NVENDDELO

ADDITIONAL

DELAY BY

1 LINE

VSEHO

ADVANCE BY

0.5 LINE

1 0

NVENDSIGN

ODD FIELD?

DELAY END OF VSYNC

BY NVEND[4:0]

NOYES

NVENDDELE

ADDITIONAL

DELAY BY

1 LINE

VSEHE

ADVANCE BY

0.5 LINE

VSYNC BEGIN

05479-029

Figure 29. NTSC Vsync Begin

NVBEGDELO, NTSC Vsync Begin Delay on Odd Field, Address 0xE5 [7]

0 (default)—No delay.

1—Delays vsync going high on an odd field by a line relative to NVBEG.

NVBEGDELE, NTSC Vsync Begin Delay on Even Field, Address 0xE5 [6]

0 (default)—No delay.

1—Delays vsync going high on an even field by a line relative to NVBEG.

NVBEGSIGN, NTSC Vsync Begin Sign, Address 0xE5 [5]

0—Delays the start of vsync. Set for user manual programming.

1 (default)—Advances the start of vsync. Not recommended for user programming.

NVBEG [4:0], NTSC Vsync Begin, Address 0xE5 [4:0]

The default value of NVBEG is 00101, indicating the NTSC vsync begin position. For all NTSC/PAL vsync timing controls, both the V bit in the AV code and the vsync on the VS pin are modified.

VSYNC END

05479-030

Figure 30. NTSC Vsync End

NVENDDELO, NTSC Vsync End Delay on Odd Field, Address 0xE6 [7]

0 (default)—No delay.

1—Delays vsync from going low on an odd field by a line relative to NVEND.

NVENDDELE, NTSC Vsync End Delay on Even Field, Address 0xE6 [6]

0 (default)—No delay.

1—Delays vsync from going low on an even field by a line relative to NVEND.

NVENDSIGN, NTSC Vsync End Sign, Address 0xE6 [5]

0 (default)—Delays the end of vsync. Set for user manual programming.

1—Advances the end of vsync. Not recommended for user programming.

NVEND [4:0], NTSC Vsync End, Address 0xE6 [4:0]

The default value of NVEND is 00100, indicating the NTSC vsync end position.

Rev. A | Page 49 of 112

ADV7184

For all NTSC/PAL vsync timing controls, both the V bit in the AV code and the vsync on the VS pin are modified.

NFTOGDELO, NTSC Field Toggle Delay on Odd Field, Address 0xE7 [7]

0 (default)—No delay.

1—Delays the field toggle/transition on an odd field by a line relative to NFTOG.

NFTOGDELE, NTSC Field Toggle Delay on Even Field, Address 0xE7 [6]

0—No delay.

NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]

0—Delays the field transition. Set for manual programming.

1 (default)—Advances the field transition. Not recommended

for user programming.

NFTOG [4:0], NTSC Field Toggle, Address 0xE7 [4:0]

The default value of NFTOG is 00011, indicating the NTSC

field toggle position.

For all NTSC/PAL field timing controls, both the F bit in the

AV code and the field signal on the FIELD/DE pin are

modified.

1 (default)—Delays the field toggle/transition on an even field by a line relative to NFTOG.

PVBEGDELO, PAL Vsync Begin Delay on Odd Field,

Address 0xE8 [7]

0 (default)—No delay.

NFTOGSIGN

1—Delays vsync going high on an odd field by a line relative to

ADVANCE TOGG LE OF

FIELD BY NFTOG[ 4:0]

DELAY TOGGLE OF

FIELD BY NFTOG[ 4:0]

PVBEG.

PVBEGDELE, PAL Vsync Begin Delay on Even Field,

NOT VALID FOR USER

PROGRAMMING

ODD FIELD?

NOYES

Address 0xE8 [6]

0 (default)—No delay.

1 (default)—Delays vsync going high on an even field by a line

relative to PVBEG.

NFTOGDELO

1 0

ADDITIONAL

DELAY BY

1 LINE

NFTOGDELE

ADDITIONAL

DELAY BY

1 LINE

PVBEGSIGN, PAL Vsync Begin Sign, Address 0xE8 [5]

0—Delays the beginning of vsync. Set for user manual

programming.

1 (default)—Advances the beginning of vsync. Not

recommended for user programming.

PVBEG [4:0], PAL Vsync Begin, Address 0xE8 [4:0]

FIELD

TOGGLE

Figure 31. NTSC Field Toggle

05479-031

The default value of PVBEG is 00101, indicating the PAL vsync

begin position.

For all NTSC/PAL vsync timing controls, both the V bit in the

AV code and the vsync on the VS pin are modified.

Table 63. Recommended User Settings for PAL (see Figure 33)

0x31 Vsync Field Control 1 0x1A 0x32 Vsync Field Control 2 0x81 0x33 Vsync Field Control 3 0x84 0x34 Hsync Position 1 0x00 0x35 Hsync Position 2 0x00 0x36 Hsync Position 3 0x7D 0x37 Polarity 0xA1 0xE8 PAL V bit begin 0x41 0xE9 PAL V bit end 0x84 0xEA PAL F bit toggle 0x06

Rev. A | Page 50 of 112

ADV7184

OUTPUT

VIDEO

OUTPUT

VIDEO

OUTPUT

VIDEO

FIELD 1

622 623 624 625 1 2 3 4 5 6 7 8 9 10 22 23 24

PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4

PFTOG[4:0] = 0x3

FIELD 2

310 311 312 31 3 314 315 316 317 318 319 320 321 322 335 336 33 7

PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4

PFTOG[4:0] = 0x3

Figure 32. PAL Default (ITU-R BT.656), the Polarities of HS, VS, and FIELD are Embedded in the Data

FIELD 1

622 623 624

123 45 67 8 91011 2324

625

05479-032

OUTPUT

FIELD

OUTPUT

VIDEO

OUTPUT

FIELD

OUTPUT

PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4

PFTOG [4:0] = 0x6

FIELD 2

310 311 312

314 315 316 317 318 319 320 321 322 323 336 337

313

PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4

PFTOG [4:0] = 0x6

Figure 33. PAL Typical VS/FIELD Positions Using Register Writes in

Table 63

05479-033

Rev. A | Page 51 of 112

ADV7184

ADVANCE BEGIN OF

VSYNC BY PVBEG[4:0]

NOT VALID FOR USER

PROGRAMMING

PVBEGDELO

ADDITIONAL

DELAY BY

1 LINE

VSBHO

ADVANCE BY

0.5 LINE

1 0

PVBEGSIGN

ODD FIELD?

DELAY BEGIN OF

VSYNC BY PVBEG [4:0]

NOYES

PVBEGDELE

ADDITIONAL

DELAY BY

1 LINE

VSBHE

ADVANCE BY

0.5 LINE

ADVANCE END OF

VSYNC BY PVEND[4: 0]

NOT VALID FOR USER

PROGRAMMING

PVENDDELO

ADDITIONAL

DELAY BY

1 LINE

VSEHO

ADVANCE BY

0.5 LINE

1 0

PVENDSIGN

ODD FIELD?

DELAY END OF VSYNC

BY PVEND[4:0]

NOYES

PVENDDELE

ADDITIONAL

DELAY BY

1 LINE

VSEHE

ADVANCE BY

0.5 LINE

VSYNC BEGIN

Figure 34. PAL Vsync Begin

PVENDDELO, PAL Vsync End Delay on Odd Field, Address 0xE9 [7]

0 (default)—No delay.

1—Delays vsync going low on an odd field by a line relative to PVEND.

PVENDDELE, PAL Vsync End Delay on Even Field, Address 0xE9 [6]

0 (default)—No delay.

1—Delays vsync going low on an even field by a line relative to PVEND.

PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]

0 (default)—Delays the end of vsync. Set for user manual programming.

1—Advances the end of vsync. Not recommended for user programming.

05479-034

VSYNC END

05479-035

Figure 35. PAL Vsync End

PVEND [4:0], PAL Vsync End, Address 0xE9 [4:0]

The default value of PVEND is 10100, indicating the PAL vsync

end position.

For all NTSC/PAL vsync timing controls, both the V bit in the

AV code and the vsync on the VS pin are modified.

PFTOGDELO, PAL Field Toggle Delay on Odd Field,

Address 0xEA [7]

0 (default)—No delay.

1—Delays the F toggle/transition on an odd field by a line

relative to PFTOG.

PFTOGDELE, PAL Field Toggle Delay on Even Field,

Address 0xEA [6]

0 (default)—No delay.

1 (default)—Delays the F toggle/transition on an even field by a

line relative to PFTOG.

Rev. A | Page 52 of 112

ADV7184

PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]

0—Delays the field transition. Set for manual programming.

1 (default)—Advances the field transition. Not recommended for user programming.

ENVSPROC, Enable Vsync Processor, Address 0x01 [3]

This block provides extra filtering of the detected vsyncs to improve vertical lock.

0—Disables the vsync processor.

PFTOG, PAL Field Toggle, Address 0xEA [4:0]

The default value of PFTOG is 00011, indicating the PAL field toggle position.

For all NTSC/PAL field timing controls, the F bit in the AV code and the field signal on the FIELD/DE pin are modified.

ADVANCE TOGG LE OF

FIELD BY P TOG[4:0]

NOT VALID FOR USER

PROGRAMMING

PFTOGDELO

ADDITIONAL

DELAY BY

1 LINE

PFTOGSIGN

ODD FIELD?

1 0

FIELD

TOGGLE

Figure 36. PAL F Toggle

DELAY TOGGLE OF

FIELD BY PFTOG [4:0]

NOYES

PFTOGDELE

ADDITIONAL

DELAY BY

1 LINE

05479-036

SYNC PROCESSING

The ADV7184 has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via the following two I

ENHSPLL, Enable Hsync Processor, Address 0x01 [6]

The hsync processor is designed to filter incoming hsyncs that have been corrupted by noise; therefore, it improves the performance of the ADV7184 for video signals with stable time bases but poor SNR.

0—Disables the hsync processor.

1 (default)—Enables the hsync processor.

C bits.

1 (default)—Enables the vsync processor.

VBI DATA DECODE

There are two VBI data slicers on the ADV7184. The first is called the VBI data processor (VDP), and the second is called the VBI System 2.

The VDP can slice both low bandwidth standards and high bandwidth standards, such as teletext. VBI System 2 can slice low data rate VBI standards only.

The VDP is capable of slicing multiple VBI data standards on SD video. It decodes the VBI data on the incoming CVBS and Y/C or YUV data. The decoded results are available as ancillary data in the output 656 data stream. For low data rate VBI standards such as CC/WSS/CGMS, the user can read the decoded data bytes from I decoded by the VDP are shown in

Table 64. PAL

Feature Standard

Teletext System A or C or D ITU-R BT.653 Teletext System B/WST ITU-R BT.653 VPS (Video Programming System) ETSI EN 300 231 V1.3.1 VITC (Vertical Interval Time Codes) – WSS (Wide-Screen Signaling) BT.1119-1/ETSI EN 300 294 CC (Closed Captioning) –

Table 65. NTSC

Feature Standard

Teletext System B and D ITU-R BT.653 Teletext System C/NABTS ITU-R BT.653/EIA-516 VITC (Vertical Interval Time Codes) – CGMS (Copy Generation

Management System) Gemstar – CC (Closed Captioning) EIA-608

The VBI data standard that the VDP decodes on a particular line of incoming video has been set by default, as described in Tabl e 6 6 . This can be overridden manually, and any VBI data can be decoded on any line. The details of manual programming are described in

VDP Default Configuration

The VDP can decode different VBI data standards on a line-toline basis. The various standards supported by default on different lines of VBI are explained in

C registers. The VBI data standards that can be

Tabl e 6 4 and Tab l e 6 5 .

EIA-J CPR-1204/IEC 61880

Table 6 7 and Ta b le 6 8.

Tabl e 66.

Rev. A | Page 53 of 112

ADV7184

VDP Manual Configuration

MAN_LINE_PGM, Enable Manual Line Programming of VBI Standards, Address 0x64 [7], User Sub Map

The user can configure the VDP to decode different standards on a line-to-line basis through manual line programming. For this, the user must set the MAN_LINE_PGM bit and write to the VBI_DATA_Px_Ny line programming bits (see Register 0x64 to Register 0x77 of the user sub map).

(default)—The VDP decodes default standards on lines as

shown in

Tabl e 6 6 .

1—The VBI standards to be decoded are manually programmed.

VBI_DATA_Px_Ny [3:0], VBI Standard to be Decoded on Line x for PAL, Line y for NTSC, Addresses 0x64 to 0x77, User Sub Map

These bits are related 4-bit clusters in Register 0x64 to Register 0x77 of the user sub map. The 4-bit line-programming registers, named VBI_DATA_Px_Ny, identify the VBI data standard that would be decoded on Line x in PAL mode or on Line y in NTSC mode. The

Table 66. Default Line Standards for PAL and NTSC

PAL—625/50 NTSC—525/60

Default VBI

Line No.

6 WST 318 VPS 23 Gemstar 1× – – 7 WST 319 WST 24 Gemstar 1× 286 Gemstar 1× 8 WST 320 WST 25 Gemstar 1× 287 Gemstar 1× 9 WST 321 WST – – 288 Gemstar 1× 10 WST 322 WST – – – – 11 WST 323 WST – – – – 12 WST 324 WST 10 NABTS 272 NABTS 13 WST 325 WST 11 NABTS 273 NABTS 14 WST 326 WST 12 NABTS 274 NABTS 15 WST 327 WST 13 NABTS 275 NABTS 16 VPS 328 WST 14 VITC 276 NABTS 17 – 329 VPS 15 NABTS 277 VITC 18 – 330 – 16 VITC 278 NABTS 19 VITC 331 – 17 NABTS 279 VITC 20 WST 332 VITC 18 NABTS 280 NABTS 21 WST 333 WST 19 NABTS 281 NABTS 22 CC 334 WST 20 CGMS 282 NABTS 23 WSS 335 CC 21 CC 283 CGMS 24 + full

odd field

Data Decoded

WST 336 WST

Line No.

337 + full even field

Default VBI Data Decoded

WST

different types of VBI standards decoded by VBI_DATA_Px_Ny are shown in

Tabl e 6 7 . Note that the interpretation of its value

depends on whether the ADV7184 is in PAL or NTSC mode.

Notes

• Full field detection (lines other than VBI lines) of

any standard can also be enabled by writing into the VBI_DATA_P24_N22 [3:0] and VBI_DATA_P337_N285 [3:0] bits. Therefore, if VBI_DATA_P24_N22 [3:0] is programmed with any teletext standard, then teletext is decoded from the entire odd field. The corresponding bits for the even field are VBI_DATA_P337_N285 [3:0].

• In teletext system identification, VDP assumes that if teletext

is present in a video channel, all the teletext lines comply with a single standard system. Therefore, the line programming using VBI_DATA_Px_Ny registers identifies whether the data in line is teletext; the actual standard is identified by the VDP_TTXT_TYPE_MAN bit. To program the VDP_TTXT_TYPE_MAN bit, the VDP_TTXT_TYPE_ MAN_ENABLE bit must be set to 1.

Line No.

22 + full odd field

Default VBI Data Decoded

NABTS 284 CC

Line No.

285 + full even field

Default VBI Data Decoded

NABTS

Rev. A | Page 54 of 112

ADV7184

Table 67. VBI Data Standards for Manual Configuration

VBI_DATA_Px_Ny PAL—625/50 NTSC—525/60

0000 Disable VDP Disable VDP 0001 Teletext system identified by VDP_TTXT_TYPE Teletext system identified by VDP_TTXT_TYPE 0010 VPS—ETSI EN 300 231 V 1.3.1 Reserved 0011 VITC VITC 0100 WSS ITU-R BT.1119-1/ETSI.EN.300294 CGMS EIA-J CPR-1204/IEC 61880 0101 Reserved Gemstar 1× 0110 Reserved Gemstar 2× 0111 CC CC EIA-608 1000 to 1111 Reserved Reserved

Table 68. VBI Data Standards to be Decoded on Line Px (PAL) or Line Ny (NTSC)

Address Signal Name Register Location Dec Hex

VBI_DATA_P6_N23 VDP_LINE_00F [7:4] 101 0x65 VBI_DATA_P7_N24 VDP_LINE_010 [7:4] 102 0x66 VBI_DATA_P8_N25 VDP_LINE_011 [7:4] 103 0x67 VBI_DATA_P9 VDP_LINE_012 [7:4] 104 0x68 VBI_DATA_P10 VDP_LINE_013 [7:4] 105 0x69 VBI_DATA_P11 VDP_LINE_014 [7:4] 106 0x6A VBI_DATA_P12_N10 VDP_LINE_015 [7:4] 107 0x6B VBI_DATA_P13_N11 VDP_LINE_016 [7:4] 108 0x6C VBI_DATA_P14_N12 VDP_LINE_017 [7:4] 109 0x6D VBI_DATA_P15_N13 VDP_LINE_018 [7:4] 110 0x6E VBI_DATA_P16_N14 VDP_LINE_019 [7:4] 111 0x6F VBI_DATA_P17_N15 VDP_LINE_01A [7:4] 112 0x70 VBI_DATA_P18_N16 VDP_LINE_01B [7:4] 113 0x71 VBI_DATA_P19_N17 VDP_LINE_01C [7:4] 114 0x72 VBI_DATA_P20_N18 VDP_LINE_01D [7:4] 115 0x73 VBI_DATA_P21_N19 VDP_LINE_01E [7:4] 116 0x74 VBI_DATA_P22_N20 VDP_LINE_01F [7:4] 117 0x75 VBI_DATA_P23_N21 VDP_LINE_020 [7:4] 118 0x76 VBI_DATA_P24_N22 VDP_LINE_021 [7:4] 119 0x77 VBI_DATA_P318 VDP_LINE_00E [3:0] 100 0x64 VBI_DATA_P319_N286 VDP_LINE_00F [3:0] 101 0x65 VBI_DATA_P320_N287 VDP_LINE_010 [3:0] 102 0x66 VBI_DATA_P321_N288 VDP_LINE_011 [3:0] 103 0x67 VBI_DATA_P322 VDP_LINE_012 [3:0] 104 0x68 VBI_DATA_P323 VDP_LINE_013 [3:0] 105 0x69 VBI_DATA_P324_N272 VDP_LINE_014 [3:0] 106 0x6A VBI_DATA_P325_N273 VDP_LINE_015 [3:0] 107 0x6B VBI_DATA_P326_N274 VDP_LINE_016 [3:0] 108 0x6C VBI_DATA_P327_N275 VDP_LINE_017 [3:0] 109 0x6D VBI_DATA_P328_N276 VDP_LINE_018 [3:0] 110 0x6E VBI_DATA_P329_N277 VDP_LINE_019 [3:0] 111 0x6F VBI_DATA_P330_N278 VDP_LINE_01A [3:0] 112 0x70 VBI_DATA_P331_N279 VDP_LINE_01B [3:0] 113 0x71 VBI_DATA_P332_N280 VDP_LINE_01C [3:0] 114 0x72 VBI_DATA_P333_N281 VDP_LINE_01D [3:0] 115 0x73 VBI_DATA_P334_N282 VDP_LINE_01E [3:0] 116 0x74 VBI_DATA_P335_N283 VDP_LINE_01F [3:0] 117 0x75 VBI_DATA_P336_N284 VDP_LINE_020 [3:0] 118 0x76 VBI_DATA_P337_N285 VDP_LINE_021 [3:0] 119 0x77

Rev. A | Page 55 of 112

ADV7184

VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual Selection of Teletext Type, Address 0x60 [2], User Sub Map

0 (default)—Manual programming of the teletext type is disabled.

ADF_DID [4:0], User-Specified Data ID Word in Ancillary Data, Address 0x62 [4:0], User Sub Map

These bits select the DID to be inserted into the ancillary data stream with the data decoded by the VDP.

1—Manual programming of the teletext type is enabled.

VDP_TTXT_TYPE_MAN [1:0], Specify the Teletext Type, Address 0x60 [1:0], User Sub Map

These bits specify the teletext type to be decoded. These bits are functional only if VDP_TTXT_TYPE_MAN_ENABLE is set to 1.

Table 69. VDP_TTXT_TYPE_MAN Function

VDP_TTXT_ TYPE_MAN [1:0]

00 (default)

625/50 (PAL ) 525/60 (NTSC)

Teletext-ITU-R BT.653-625/50-A

Teletext-ITU-R BT.653-625/50-B (WST)

Teletext-ITU-R BT.653-625/50-C

Teletext-ITU-R BT.653-625/50-D

Description

Reserved

Teletext-ITU-R BT.653525/60-B

Teletext-ITU-R BT.653525/60-C or EIA516 (NABTS)

Teletext-ITU-R BT.653525/60-D

VDP Ancillary Data Output

Reading the data back via I2C may not be feasible for VBI data standards with high data rates (for example, teletext). An alternative is to place the sliced data in a packet within the line blanking of the digital output CCIR 656 stream. This is available for all standards sliced by the VDP module.

When data is sliced on a given line, the corresponding ancillary data packet is placed immediately after the next EAV code that occurs at the output (that is, data sliced from multiple lines is not buffered up and then emitted in a burst). Note that the line on which the packet is placed differs from the line on which the data was sliced due to the vertical delay through the comb filters.

The user can enable or disable the insertion of VDP-decoded results into the 656 ancillary streams by using the ADF_ENABLE bit.

ADF_ENABLE, Enable Ancillary Data Output Through 656 Stream, Address 0x62 [7], User Sub Map

0 (default)—Disables insertion of VBI decoded data into an ancillary 656 stream.

The default value of ADF_DID [4:0] is 10101.

ADF_SDID [5:0], User-Specified Secondary Data ID Word in Ancillary Data, Address 0x63 [5:0], User Sub Map

These bits select the SDID to be inserted in the ancillary data stream with the data decoded by the VDP.

The default value of ADF_SDID [5:0] is 101010.

DUPLICATE_ADF, Enable Duplication/Spreading of Ancillary Data over Y and C Buses, Address 0x63 [7], User Sub Map

This bit determines whether the ancillary data is duplicated over both the Y and C buses or if the data packets are spread between the two channels.

(default)—The ancillary data packet is spread across the Y and

C data streams.

1—The ancillary data packet is duplicated on the Y and C data streams.

ADF_MODE [1:0], Determine the Ancillary Data Output Mode, Address 0x62 [6:5], User Sub Map

These bits determine if the ancillary data output mode is in byte mode or nibble mode.

Table 70. ADF_MODE [1:0]

ADF_MODE [1:0] Description

00 (default) Nibble mode 01 Byte mode, no code restrictions 10

11 Reserved

Byte mode, but 0x00 and 0xFF are prevented (0x00 replaced by 0x01, 0xFF replaced by 0xFE)

The ancillary data packet sequence is explained in Tab l e 7 1 and Tabl e 7 2 . The nibble output mode is the default mode of output from the ancillary stream when ancillary stream output is enabled. This format complies with ITU-R BT.1364.

Some definitions of the abbreviations used in

Table 7 1 and

Tabl e 7 2 are as follows:

1—Enables insertion of VBI decoded data into an ancillary 656 stream.

The user can select the data identification word (DID) and the secondary data identification word (SDID) by programming the ADF_DID [4:0] and ADF_SDID [5:0] bits, respectively, as explained in the following sections.

Rev. A | Page 56 of 112

EP. Even parity for Bits B8 to B2. This means that Parity

•

Bit EP is set so that an even number of 1s are in Bits B8 to B2, including the D8 parity bit.

•

CS. Checksum word. The CS word is used to increase the

integrity of the ancillary data packet from the DID, SDID, and dc through user data-words (UDWs). It consists of 10 bits: a 9-bit calculated value and B9 as the inverse of B8.

ADV7184

The checksum value of B8 to B0 is equal to the nine LSBs of the sum of the nine LSBs of the DID, SDID, and dc, as well as all UDWs in the packet. Prior to the start of the checksum count cycle, all checksum and carry bits are preset to 0. Any carry resulting from the checksum count cycle is ignored.

•

. The MSB, B9, is the inverse of EP. This ensures that

restricted Codes 0x00 and 0xFF do not occur.

Line_number [9:0]. The number of the line that immediately

•

precedes the ancillary data packet. This number is as per the

Table 71. Ancillary Data in Nibble Output Format

Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Description

0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3

. . . . . . . . . . .

n − 3 1 0 0 0 0 0 0 0 0 0 n − 2 1 0 0 0 0 0 0 0 0 0 n − 1

EP 0 I2C_DID6_2 [4:0] 0 0

EP I2C_SDID7_2 [5:0] 0 0

EP 0 DC [4:0] 0 0 Data count.

EP padding [1:0] VBI_DATA_STD [3:0] 0 0 ID0 (User Data-Word 1).

EP 0 Line_number [9:5] 0 0 ID1 (User Data-Word 2).

EP Even_Field Line_number [4:0] 0 0 ID2 (User Data-Word 3).

EP 0 0 0 0

EP 0 0 VBI_WORD_1 [7:4] 0 0 User Data-Word 5.

EP 0 0 VBI_WORD_1 [3:0] 0 0 User Data-Word 6.

EP 0 0 VBI_WORD_2 [7:4] 0 0 User Data-Word 7.

EP 0 0 VBI_WORD_2 [3:0] 0 0 User Data-Word 8.

EP 0 0 VBI_WORD_3 [7:4] 0 0 User Data-Word 9.

Checksum 0 0 CS (checksum word).

numbering system of ITU-R BT.470, ranging from 1 to 625 in a 625-line system and from 1 to 263 in a 525-line system. Note that the line on which the packet is output differs from the line on which the VBI data was sliced due to the vertical delay through the comb filters.

•

Data Count. The data count specifies the number of UDWs

in the ancillary stream for the standard. The total number of user data-words is four times the data count. Padding words can be introduced so that the total number of UDWs is divisible by 4.

Ancillary data preamble.

DID (data identification word).

SDID (secondary data identification word).

VDP_TTXT_TYPE [1:0]

0 0 ID3 (User Data-Word 4).

Pad 0x200. These padding words may not be present depending on ancillary data type. User Data-Word XX.

Rev. A | Page 57 of 112

ADV7184

Table 72. Ancillary Data in Byte Output Format

Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Description

0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 EP

4 EP

5 EP

6 EP

7 EP

8 EP

9 EP

10 VBI_WORD_1 [7:0] 0 0 User Data-Word 5. 11 VBI_WORD_2 [7:0] 0 0 User Data-Word 6. 12 VBI_WORD_3 [7:0] 0 0 User Data-Word 7. 13 VBI_WORD_4 [7:0] 0 0 User Data-Word 8. 14 VBI_WORD_5 [7:0] 0 0 User Data-Word 9.

. . . . . . . . . . .

n − 3 1 0 0 0 0 0 0 0 0 0 n − 2 1 0 0 0 0 0 0 0 0 0 n − 1 B8

This mode does not fully comply with ITU-R BT.1364.

EP 0 I2C_DID6_2 [4:0] 0 0 DID.

EP I2C_SDID7_2 [5:0] 0 0 SDID.

EP 0 DC [4:0] 0 0 Data count.

EP padding [1:0] VBI_DATA_STD [3:0] 0 0 ID0 (User Data-Word 1).

EP 0 Line_number [9:5] 0 0 ID1 (User Data-Word 2).

EP Even_Field Line_number [4:0] 0 0 ID2 (User Data-Word 3).

EP 0 0 0 0 VDP_TTXT_TYPE [1:0] 0 0 ID3 (User Data-Word 4).

Structure of VBI Words in Ancillary Data Stream

Each VBI data standard has been split into a clock run-in (CRI), a framing code (FC), and a number of data bytes (n). The data packet in the ancillary stream includes only the FC and data bytes. The VBI_WORD_X in the ancillary data stream has the format described in

Tabl e 73 .

Table 73. Structure of VBI Data-Words in Ancillary Stream

Byte

Ancillary Data Byte Number

Type

Byte Description

VBI_WORD_1 FC0 Framing Code [23:16] VBI_WORD_2 FC1 Framing Code [15:8] VBI_WORD_3 FC2 Framing Code [7:0]

Ancillary data preamble.

Pad 0x200. These padding words may not be present depending on ancillary data type. User Data-Word XX.

Checksum 0 0 CS (checksum word).

Example

For teletext (B-WST), the framing code byte is 11100100 (0xE4), with bits shown in the order of transmission. Thus, VBI_WORD_1 = 0x27, VBI_WORD_2 = 0x00, and VBI_WORD_3 = 0x00. Translating these into UDWs in the ancillary data stream, for the nibble mode,

UDW5 [5:2] = 0010 UDW6 [5:2] = 0111 UDW7 [5:2] = 0000 (undefined bits, automatically set to 0) UDW8 [5:2] = 0000 (undefined bits, automatically set to 0) UDW9 [5:2] = 0000 (undefined bits, automatically set to 0) UDW10 [5:2] = 0000 (undefined bits, automatically set to 0)

VBI_WORD_4 DB1 First data byte … … … VBI_WORD_N+3 DBn Last (nth) data byte

VDP Framing Code

The length of the actual framing code depends on the VBI data standard. For uniformity, the length of the framing code reported in the ancillary data stream is always 24 bits. For standards with a shorter framing code length, the extra LSB bits are set to 0. The valid length of the framing code can be decoded from the VBI_DATA_STD bit available in ID0 (UDW1).

The framing code is always reported in the reverse order of transmission.

Tabl e 74 shows the framing code and its valid

length for VBI data standards supported by VDP.

and for the byte mode,

UDW5 [9:2] = 0010_0111 UDW6 [9:2] = 0000_0000 (undefined bits, automatically set to 0) UDW7 [9:2] = 0000_0000 (undefined bits, automatically set to 0)

Data Bytes

VBI_WORD_4 to VBI_WORD_N+3 contain the data-words that were decoded by the VDP in the order of transmission. The position of bits in bytes is in the reverse order of transmission. For example, closed captioning has two user data bytes, as shown in

Tabl e 8 0 .

The data bytes in the ancillary data stream in this case are as follows:

VBI_WORD_4 = BYTE1 [7:0] VBI_WORD_5 = BYTE2 [7:0]

The number of VBI_WORDS for each VBI data standard and the total number of UDWs in the ancillary data stream are shown in

Tabl e 7 5 .

Rev. A | Page 58 of 112

ADV7184

Table 74. Framing Code Sequence for Different VBI Standards

Error-Free Framing Code Bits

VBI Standard Length in Bits

(In Order of Transmission )

TTXT_SYSTEM_A (PAL) 8 11100111 11100111 TTXT_SYSTEM_B (PAL) 8 11100100 00100111 TTXT_SYSTEM_B (NTSC) 8 11100100 00100111 TTXT_SYSTEM_C (PAL and NTSC) 8 11100111 11100111 TTXT_SYSTEM_D (PAL and NTSC) 8 11100101 10100111 VPS (PAL) 16 10001010100011001 1001100101010001 VITC (NTSC and PAL) 1 0 0 WSS (PAL) 24 000111100011110000011111 111110000011110001111000 Gemstar 1× (NTSC) 3 001 100 Gemstar 2× (NTSC) 11 1001 1011 101 101 1101 1001 CC (NTSC and PAL) 3 001 100 CGMS (NTSC) 1 0 0

Table 75. Total User Data-Words for Different VBI Standards

VBI Standard ADF Mode

Framing Code UDWs

VBI DataWords

00 (nibble mode) 6 74 0 84 TTXT_SYSTEM_A (PAL) 01, 10 (byte mode) 3 37 0 44 00 (nibble mode) 6 84 2 96 TTXT_SYSTEM_B (PAL) 01, 10 (byte mode) 3 42 3 52 00 (nibble mode) 6 68 2 80 TTXT_SYSTEM_B (NTSC) 01, 10 (byte mode) 3 34 3 44 00 (nibble mode) 6 66 0 76 TTXT_SYSTEM_C (PAL and NTSC) 01, 10 (byte mode) 3 33 2 42 00 (nibble mode) 6 68 2 80 TTXT_SYSTEM_D (PAL and NTSC) 01, 10 (byte mode) 3 34 3 44 00 (nibble mode) 6 26 0 36 VPS (PAL) 01, 10 (byte mode) 3 13 0 20 00 (nibble mode) 6 18 0 28 VITC (NTSC and PAL) 01, 10 (byte mode) 3 9 0 16 00 (nibble mode) 6 4 2 16 WSS (PAL) 01, 10 (byte mode) 3 2 3 12 00 (nibble mode) 6 4 2 16 Gemstar 1× (NTSC) 01, 10 (byte mode) 3 2 3 12 00 (nibble mode) 6 8 2 20 Gemstar 2× (NTSC) 01, 10 (byte mode) 3 4 1 12 00 (nibble mode) 6 4 2 16 CC (NTSC and PAL) 01, 10 (byte mode) 3 2 3 12 00 (nibble mode) 6 6 0 16 CGMS (NTSC) 01, 10 (byte mode) 3 3 + 3 2 12

The first four UDWs are always the identification word.

Error-Free Framing Code Reported by VDP (In Reverse Order of Transmission )

Number of Padding Word s

Total UDWs

Rev. A | Page 59 of 112

ADV7184

I2C INTERFACE

Dedicated I2C readback registers are available for CC, CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. Because teletext is a high data rate standard, data extraction is supported only through the ancillary data packet. The details of these registers and their access procedures are described in this section.

User Interface for I2C Readback Registers

The VDP decodes all enabled VBI data standards in real time. Because the I rate, the registers may be updated with data from the next line when they are being accessed. To avoid this, VDP has a selfclearing CLEAR bit and an AVAILABLE status bit accompanying all the I

The user has to clear the I the CLEAR bit. This resets the state of the AVAILABLE bit to low and indicates that the data in the associated readback registers is not valid. After the VDP decodes the next line of the corresponding VBI data, the decoded data is placed in the I and the AVAILABLE bit is set high to indicate that valid data is now available.

Although the VDP, if present, decodes this VBI data in subsequent lines, the decoded data is not updated to the readback registers until the CLEAR bit is set high again. However, this data is available through the 656 ancillary data packets.

C access speed is much slower than the decoded

C readback registers.

C readback register by writing a high to

C readback register

VDP—Content-Based Data Update

For certain standards, such as WSS, CGMS, Gemstar, PDC, UTC, and VPS, the information content in the signal transmitted remains the same over numerous lines, and the user may want to be notified only when there is a change in the information content or loss of the information content. The user needs to enable content-based updating for the required standard through the GS_VPS_PDC_UTC_CB_CHANGE and WSS_CGMS_CB_CHANGE bits. Therefore, the AVAILABLE bit shows the availability of that standard only when its content has changed.

Content-based updating also applies to loss of data at the lines where some data was previously present. Thus, for standards like VPS, Gemstar, CGMS, and WSS, if no data arrives in the next four lines programmed, the corresponding AVAILABLE bit in the VDP_STATUS register is set high and the content in the

C registers for that standard is set to 0. The user must write

I high to the corresponding CLEAR bit so that when a subsequent valid line is decoded, the decoded results are available in the

C registers, with the AVAILABLE status bit set high.

If content-based updating is enabled, the AVAILABLE bit is set high (assuming the CLEAR bit was written to) in the following cases:

•

The data contents changed.

The CLEAR and AVAILABLE bits are in the VDP_STATUS_CLEAR (Address 0x78, user sub map, write only) and VDP_STATUS (Address 0x78, user sub map, read only) registers.

Example I2C Readback Procedure

To read one packet (line) of PDC data from the decoder

Write 10 to I2C_GS_VPS_PDC_UTC [1:0] (Address 0x9C,

user sub map) to specify that PDC data has to be updated

to I

C registers.

Write high to the GS_PDC_VPS_UTC_CLEAR bit

(Address 0x78, user sub map) to enable I

C register

updating.

Poll the GS_PDC_VPS_UTC_AVL bit (Address 0x78,

user sub map) going high to check the availability of the PDC packets.

Read the data bytes from the PDC I

C registers. To read

another line or packet of data, repeat the previous steps.

To read a packet of CC, CGMS, or WSS data, only Steps 1 through 3 are required because these types of data have dedicated registers.

Data was being decoded and four lines with no data have

•

been detected.

• No data was being decoded and new data is now being

decoded.

GS_VPS_PDC_UTC_CB_CHANGE, Enable ContentBased Updating for Gemstar/VPS/PDC/UTC, Address 0x9C [5], User Sub Map

0—Disables content-based updating.

1 (default)—Enables content-based updating.

WSS_CGMS_CB_CHANGE, Enable Content-Based Updating for WSS/CGMS, Address 0x9C [4], User Sub Map

0—Disables content-based updating.

1 (default)—Enables content-based updating.

Rev. A | Page 60 of 112

ADV7184

VDP—Interrupt-Based Reading of VDP I2C Registers

Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the AVAILABLE status bit. The user can configure the video decoder to trigger an interrupt request on the available in I

C registers. This function is available for the

INT

pin in response to the valid data

following data types:

• CGMS or WSS. The user can select triggering an interrupt

request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. Selection is made via the WSS_CGMS_CB_CHANGE bit.

• Gemstar, PDC, VPS, or UTC. The user can select

triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. Selection is made via the GS_VPS_PDC_UTC_ CB_CHANGE bit.

The sequence for the interrupt-based reading of the VDP I

data registers is as follows for the CC standard:

The user unmasks the CC interrupt mask bit (Bit 0 of

Address 0x50, user sub map, set to 1). CC data occurs upon the incoming video. VDP slices CC data and places it in the VDP readback registers.

The VDP CC available bit goes high, and the VDP module

signals to the interrupt controller to stimulate an interrupt request (for CC in this case).

The user reads the interrupt status bits (user sub map) and

sees that new CC data is available (Bit 0 of Address 0x4E, user sub map, set to 1).

The user writes 1 to the CC interrupt clear bit (Bit 0 of

Address 0x4F, user sub map, set to 1) in the interrupt I

space (this is a self-clearing bit). This clears the interrupt on

INT

the

pin but does not have an effect in the VDP I2C area.

VDP_CGMS_WSS_CHNGD_MSKB, Address 0x50 [2], User Sub Map

0 (default)—Disables interrupt on VDP_CGMS_WSS_ CHNGD_Q signal.

1—Enables interrupt on VDP_CGMS_WSS_CHNGD_Q signal.

VDP_GS_VPS_PDC_UTC_CHNG_MSKB, Address 0x50 [4], User Sub Map

0 (default)—Disables interrupt on VDP_GS_VPS_PDC_UTC_ CHNG_Q signal.

1—Enables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q signal.

VDP_VITC_MSKB, Address 0x50 [6], User Sub Map

0 (default)—Disables interrupt on VDP_VITC_Q signal.

1—Enables interrupt on VDP_VITC_Q signal.

Interrupt Status Register Details

The following read-only bits contain data detection information from the VDP module since the status bit was last cleared or unmasked.

VDP_CCAPD_Q, Address 0x4E [0], User Sub Map

0 (default)—Closed caption data was not detected.

1—Closed caption data was detected.

VDP_CGMS_WSS_CHNGD_Q, Address 0x4E [2], User Sub Map

0 (default)—CGMS or WSS data was not detected.

1—CGM or WSS data was detected.

VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E [4], User Sub Map

0 (default)—Gemstar, PDC, UTC, or VPS data was not detected.

5. The user reads the CC data from the VDP I2C area.

The user writes to a bit, CC_CLEAR (Bit 0 of Address 0x78,

user sub map, set to 1) in the VDP_STATUS_CLEAR [0] register, to signify that the CC data has been read and the VDP CC can be updated at the next occurrence of CC).

Back to Step 2.

Interrupt Mask Register Details

The following bits set the interrupt mask on the signal from the VDP VBI data slicer.

VDP_CCAPD_MSKB, Address 0x50 [0], User Sub Map

0 (default)—Disables interrupt on VDP_CCAPD_Q signal.

1—Enables interrupt on VDP_CCAPD_Q signal.

Rev. A | Page 61 of 112

1—Gemstar, PDC, UTC, or VPS data was detected.

VDP_VITC_Q, Address 0x4E [6], User Sub Map, Read Only

0 (default)—VITC data was not detected.

1—VITC data was detected.

Interrupt Status Clear Register Details

It is not necessary to write 0 to these write-only bits because they automatically reset when they are set (self-clearing).

VDP_CCAPD_CLR, Address 0x4F [0], User Sub Map

1—Clears the VDP_CCAP_Q bit.

ADV7184

VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F [2], User Sub Map

1—Clears the VDP_CGMS_WSS_CHNGD_Q bit.

VDP_GS_VPS_PDC_UTC_CHNG_CLR, Address 0x4F [4], User Sub Map

1—Clears the VDP_GS_VPS_PDC_UTC_CHNG_Q bit.

VDP_VITC_CLR, Address 0x4F [6], User Sub Map

1—Clears the VDP_VITC_Q bit.

STANDARD DETECTION AND IDENTIFICATION

The standard detection and identification (STDI) block of the ADV7184 monitors the synchronization signals received on the SOY pin. STDI_LINE_COUNT_MODE must be set to 1 to enable the STDI block and achieve valid synchronization signal analysis. Four key measurements are performed:

•

Block Length BL [13:0]. This is the number of clock cycles in

a block of eight lines. From this, the time duration of one line can be concluded. Note that the crystal frequency determines the clock cycle and that a crystal frequency of 28.63636 MHz should be used for the ADV7184.

•

Line Count in Field LCF [10:0]. The LCF [10:0] readback

value is the number of lines between two vsyncs, that is, over one field.

•

Line Count in Vsync LCVS [4:0]. The LCVS [4:0] readback

value is the number of lines within one vsync period.

STDI_DVALID, Standard Identification Data Valid Read Back, Address 0xB1 [7]

X—This bit is set by the ADV7184 as soon as the measurements of the STDI block are finished. A high level signals the validity of the BL, LCVS, LCF, and STDI_INTLCD parameters. To prevent false readouts, especially during the signal acquisition, the DVALID bit only goes high after recording four fields with the same length. As a result, the measurements can require up to five fields to finish.

STDI_LINE_COUNT_MODE, Address 0x86 [3]

0 (default)—Disables the STDI functionality.

1—Enables STDI functionality. This enables valid readback of the STDI block registers.

BL [13:0], Block Length Readback, Address 0xB1 [5:0], Address 0xB2 [7:0]

XX XXXX XXXX XXXX—Number of clock cycles in a block of eight lines of incoming video. Data is only valid if STDI_DVALID is high.

LCVS [4:0], Line Count in Vsync Readback, Address 0xB3 [7:3]

X XXXX—Number of lines within a vertical synchronization period. Data is only valid if STDI_DVALID is high.

LCF [10:0], Line Count in Field Readback, Address 0xB3 [2:0], Address 0xB4 [7:0]

XX XXXX XXXX—Number of lines between two vsyncs per one field/frame. Data is only valid if STDI_DVALID is high.

• Field Length FCL [12:0]. This is the number of clock cycles

in 1/256 the field length in clock cycles.

By interpreting these four parameters, it is possible to distinguish among the types of input signals.

A data valid flag, STDI_VALID, is provided that is held low during the measurements. The four parameters should only be read after the STDI_VALID flag has gone high. Refer to for information on the readback values.

of a field. Multiplying this value by 256 calculates

Tabl e 76

Notes

• Types of synchronization pulses include horizontal

synchronization pulses, equalization and serration pulses, and Macrovision pulses.

•

Macrovision pseudosynchronization and AGC pulses are

counted by the STDI block in normal readback mode. This does not prohibit the identification of the video signal.

• The ADV7184 only measures the parameters; it does not take

any action based on these measurements. Therefore, the part helps to identify the input to avoid problems in the scheduling of a system controller, but it does not reconfigure itself.

FCL [12:0], 1/256th of Field Length in Number of Crystal Clocks Read back, Address 0xCA [4:0], Address 0xCB [7:0]

XXX—Number of crystal clocks (with the recommended

28.63636 MHz frequency) in 1/256 if STDI_DVALID is high.

of a field. Data is only valid

Rev. A | Page 62 of 112

ADV7184

STDI Readback Values for SD, PR, and HD

The readback values provided are only valid when using a crystal with the recommended 28.63636 MHz frequency.

Table 76. STDI Results for Video Standards (SD, PR, and HD)

Video Standard BL [13:0] LCF [10:0] LCVS [4:0]

525i 60 14552 ± 80 261 ± 50 3 ± 3 240p 60 14552 ± 80 261 ± 50 2 ± 2 625i 50 14653 ± 80 311 ± 50 2 ± 2 288p 50 14654 ± 80 313 ± 50 2 ± 2 480p 60 7271 ± 40 524 ± 50 5 ± 2 720p 50 6101 ± 40 749 ± 50 4 ± 2 720p 60 5083 ± 40 749 ± 50 4 ± 2 1035i 30 6780 ± 40 562 ± 50 5 ± 2 1080i 25 7322 ± 40 1249 ± 50 0 ± 2 1080i 30 6780 ± 40 561 ± 50 4 ± 2 1080p 25 8137 ± 40 1124 ± 50 4 ± 2 1080p 50 4064 ± 40 1124 ± 50 4 ± 2 1080p 60 3385 ± 40 1124 ± 50 4 ± 2 1152i 50 Wide 7321 ± 40 623 ± 50 0 ± 2 1152i 50 Full 7321 ± 40 623 ± 50 4 ± 2

100nF

Figure 37. Example Connection of SOY pin

ADV7184

AIN4

AIN5

AIN6

SOY

05479-055

YES NO

RECONFIGURE

SYSTEM

APPROPR IATEL Y

ENABLE STDI F UNCTION

STDI_LINE_COUNT_MODE = 1

MONITORS

IN-LOCK ST AUS

SYSTEM HAS LOST LOCK?

READ

STDI VALID

STDI VALID?

YES

READ AND INTERPRET

BL[3:0], LCF[10:0],

LCVS[4:0], AND FCL[12:0]

TO DETERMINE

INPUT STANDARD

SYSTEM

SUPPORTS INPUT

STANDARD?

SYSTEM FLAGS UNSUPPORTED

Figure 38. Example Use of STDI Block

INPUT

05479-056

Rev. A | Page 63 of 112

ADV7184

I2C READBACK REGISTERS

Teletext

Because teletext is a high data rate standard, the decoded bytes are available only as ancillary data. However, a TTXT_AVL bit is provided in I has detected teletext. Note that the TTXT_AVL bit is a plain status bit and does not use the protocol identified in the Interface

TTXT_AVL, Teletext Detected Status Bit, Address 0x78 [7], User Sub Map, Read Only

0—Teletext was not detected.

1—Teletext was detected.

WST Packet Decoding

For WST only, the VDP decodes the magazine and row address of WST teletext packets and further decodes the packet’s 8 × 4 hamming coded words. This feature can be disabled by using the WST_PKT_ DECOD_ DISABLE user sub map). This feature is only valid for WST.

Table 78. WST Packet Description

Packet Byte Description

Header Packet

(X/00)

Tex t Packets

(X/01 to X/25)

8/30 (Format 1) packet

Design Code = 0000 or 0001 UTC

8/30 (Format 2) packet

Design Code = 0010 or 0011 PDC

X/26, X/27, X/28, X/29, X/30, X/31

For X/26, X/28, and X/29, further decoding needs 24 × 18 hamming decoding. Not supported at present.

C so that the user can check whether the VDP

section.

bit (Bit 3, Register 0x60,

I2C

1st byte Magazine number—dehammed Byte 4 2nd byte Row number—dehammed Byte 5 3rd byte Page number—dehammed Byte 6 4th byte Page number—dehammed Byte 7 5th to 10th byte Control Bytes—dehammed Byte 8 to Byte 13 11th to 42nd byte Raw data bytes 1st byte Magazine number—dehammed Byte 4 2nd byte Row number—dehammed Byte 5

to 42nd byte Raw data bytes

3 1st byte Magazine number—dehammed Byte 4 2nd byte Row number—dehammed Byte 5 3rd byte Design code—dehammed Byte 6 4th to 10th byte Dehammed Initial teletext page, Byte 7 to Byte 12 11th to 23rd byte UTC bytes—dehammed Byte 13 to Byte 25

to 42nd byte Raw status bytes

24 1st byte Magazine number—dehammed Byte 4 2nd byte Row number—dehammed Byte 5 3rd byte Design code—dehammed Byte 6 4th to 10th byte Dehammed Initial teletext page, Byte 7 to Byte 12 11th to 23rd byte PDC bytes—dehammed Byte 13 to Byte 25 24th to 42nd byte Raw status bytes 1st byte Magazine number—dehammed Byte 4 2nd byte Row number—dehammed Byte 5 3rd byte Design code—dehammed Byte 6 4th to 42nd byte Raw data bytes

WST_PKT_DECOD_DISABLE, Disable Hamming Decoding of Bytes in WST, Address 0x60 [3], User Sub Map

0—Enables hamming decoding of WST packets.

1 (default)—Disables hamming decoding of WST packets.

For hamming coded bytes, the dehammed nibbles, along with error information from the hamming decoder, are output as follows:

• Input hamming coded byte: {D3, P3, D2, P2, D1, P1, D0, P0}

(bits in decoded order)

• Output dehammed byte: {E1, E0, 0, 0, D3', D2', D1', D0'}

(where Di' is the corrected bit, and Ei represents the error information).

Table 77. Explanation of Error Bits in the Dehammed Output Byte

Output Data Bits

E [1:0] Error Information

00 No errors detected Okay 01 Error in P4 Okay 10 Double error Not okay 11 Single error found and corrected Okay

in Nibble

The types of WST packets that are decoded are described in Tabl e 7 8 .

Rev. A | Page 64 of 112

ADV7184

CGMS and WSS

The CGMS and WSS data packets convey the same type of information for different video standards. WSS is for PAL and CGMS is for NTSC; therefore, the CGMS and WSS readback registers are shared. WSS is biphase coded, and the VDP performs a biphase decoding to produce the 14 raw WSS bits in the CGMS/ WSS readback I

C registers and to set the CGMS_WSS_AVL bit.

CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78 [2], User Sub Map, Write Only, Self-Clearing

1—Reinitializes the CGMS/WSS readback registers.

CGMS_WSS_AVL CGMS/WSS, Available Bit, Address 0x78 [2], User Sub Map, Read Only

0—CGMS/WSS was not detected.

1—CGMS/WSS was detected.

VDP_CGMS_WSS_DATA_0 [3:0], Address 0x7D [3:0]

VDP_CGMS_WSS_DATA_1 [7:0], Address 0x7E [7:0]

VDP_CGMS_WSS_DATA_2 [7:0], Address 0x7F [7:0]

These read-only bits, located in the user sub map, hold the decoded CGMS or WSS data.

Refer to bit mapping.

Figure 39 and Figure 40 for the I2C to WSS and CGMS

Two bytes of decoded closed caption data are available in the

C registers. The field information of the decoded CC data can

I be obtained from the CC_EVEN_FIELD bit (Register 0x78).

CC_CLEAR, Closed Captioning Clear, Address 0x78 [0], User Sub Map, Write Only, Self-Clearing

1—Reinitializes the CC readback registers.

CC_AVL, Closed Captioning Available, Address 0x78 [0], User Sub Map, Read Only

0—Closed captioning was not detected.

1—Closed captioning was detected.

CC_EVEN_FIELD, Address 0x78 [1], User Sub Map, Read Only

Identifies the field from which the CC data was decoded.

0—Closed captioning was detected on an odd field.

1—Closed captioning was detected on an even field.

VDP_CCAP_DATA_0, Address 0x79 [7:0], User Sub Map, Read Only

Decoded Byte 1 of CC data.

VDP_CCAP_DATA_1, Address 0x7A [7:0], User Sub Map, Read Only

Decoded Byte 2 of CC data.

Rev. A | Page 65 of 112

ADV7184

DP_CGMS _WSS_

DATA_1[5:0]

ACTIVE

VIDEO

05479-037

11.0µs

RUN-IN

SEQUENCE

START

CODE

VDP_CGMS_W SS_DATA_2

0 1 2 3 4 5 6 7 0 1 2 3 4 5

38.4µs

42.5µs

Figure 39. WSS Waveform

+100 IRE

+70 IRE

0 IRE

–40 IRE

11.2µs

2.235µs ± 20ns

VDP_CGMS_WSS_DATA_2REF

012 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3

VDP_CGMS_WSS_DATA_1

49.1µs ± 0.5µ s

VDP_CGMS_WSS_ DATA_0[3:0]

CRC SEQUENCE

05479-038

Figure 40. CGMS Waveform

10.5 ± 0.25µ s 12.91µs

SEVEN CYCLES

OF 0.5035MHz

(CLOCK RUN I N)

2 3 4 5 6 7 0 1 2 3 4 5 67

50 IRE

S T A R T

P A R

I T Y

P A R

I T Y

40 IRE

REFERENCE COLO R BURST

(NINE CYCLES)

10.003µs

= 3.579545MHz

27.382µs

FREQUENCY = F

AMPLITUDE = 40 IRE

VDP_CCAP_DATA_0

33.764µs

VDP_CCAP_DATA_1

05479-039

Figure 41. CC Waveform and Decoded Data Correlation

Table 79. CGMS Readback Registers

Address (User Sub Map) Signal Name Register Location Dec Hex

CGMS_WSS_DATA_0 [3:0] VDP_CGMS_WSS_DATA_0 [3:0] 125d 0x7D CGMS_WSS_DATA_1 [7:0] VDP_CGMS_WSS_DATA_1 [7:0] 126d 0x7E CGMS_WSS_DATA_2 [7:0] VDP_CGMS_WSS_DATA_2 [7:0] 127d 0x7F

The register is a readback register; the default value does not apply.

Table 80. Closed Captioning Readback Registers

Address (User Sub Map) Signal Name Register Location Dec Hex

CCAP_BYTE_1 [7:0] VDP_CCAP_DATA_0 [7:0] 121d 0x79 CCAP_BYTE_2 [7:0] VDP_CCAP_DATA_1 [7:0] 122d 0x7A

The register is a readback register; the default value does not apply.

Rev. A | Page 66 of 112

ADV7184

VITC

VITC has a sequence of 10 syncs in between each data byte. The VDP strips these syncs from the data stream to output only the data bytes. The VITC results are available in the VDP_VITC_DATA_0 to VDP_VITC_DATA_8 registers (Register 0x92 to Register 0x9A, user sub map).

The VITC has a CRC byte at the end; the syncs in between each data byte are also used in this CRC calculation. Because these syncs are not output, the CRC is calculated internally. The calculated CRC is also available for the user in the VDP_VITC_CALC_CRC register (Register 0x9B, User Sub Map). After the VDP completes decoding the VITC line, the VDP_VITC_DATA_x and VDP_VITC_CALC_CRC registers are updated and the VITC_AVL bit is set.

VITC_CLEAR, VITC Clear, Address 0x78 [6], User Sub Map, Write Only, Self-Clearing

1—Reinitializes the VITC readback registers.

VITC_AVL, VITC Available, Address 0x78 [6], User Sub Map, Read Only

0—VITC data was not detected.

1—VITC data was detected.

VITC Readback Registers

See Figure 42 for the I2C to VITC bit mapping.

BIT 0, BI T 1 BIT 88, BIT 89

Figure 42. VITC Waveform and Decoded Data Correlation

VITC WAVEFORM

05479-040

Table 81. VITC Readback Registers

Address (User Sub Map) Signal Name Register Location Dec Hex

VITC_DATA_0 [7:0] VDP_VITC_DATA_0 [7:0] (VITC Bits [9:2]) 146d 0x92 VITC_DATA_1 [7:0] VDP_VITC_DATA_1 [7:0] (VITC Bits [19:12]) 147d 0x93 VITC_DATA_2 [7:0] VDP_VITC_DATA_2 [7:0] (VITC Bits [29:22]) 148d 0x94 VITC_DATA_3 [7:0] VDP_VITC_DATA_3 [7:0] (VITC Bits [39:32]) 149d 0x95 VITC_DATA_4 [7:0] VDP_VITC_DATA_4 [7:0] (VITC Bits [49:42]) 150d 0x96 VITC_DATA_5 [7:0] VDP_VITC_DATA_5 [7:0] (VITC Bits [59:52]) 151d 0x97 VITC_DATA_6 [7:0] VDP_VITC_DATA_6 [7:0] (VITC Bits [69:62]) 152d 0x98 VITC_DATA_7 [7:0] VDP_VITC_DATA_7 [7:0] (VITC Bits [79:72]) 153d 0x99 VITC_DATA_8 [7:0] VDP_VITC_DATA_8 [7:0] (VITC Bits [89:82]) 154d 0x9A VITC_CALC_CRC [7:0] VDP_VITC_CALC_CRC [7:0] 155d 0x9B

The register is a readback register; the default value does not apply.

Rev. A | Page 67 of 112

ADV7184

VPS/PDC/UTC/Gemstar

The readback registers for VPS, PDC, and UTC are shared. Gemstar is a high data rate standard and therefore is available only through the ancillary stream. For evaluation purposes, any

one line of Gemstar is available through the I

C registers sharing

the same register space as PDC, UTC, and VPS. Therefore, only

one of the following standards can be read through the I

C at a

time: VPS, PDC, UTC, or Gemstar.

To identify the data that should be made available in the I

C registers, the user must program I2C_GS_VPS_PDC_UTC [1:0] (Address 0x9C, user sub map).

I2C_GS_VPS_PDC_UTC (VDP) [1:0], Address 0x9C [6:5], User Sub Map

These bits specify which standard result is available for I2C readback.

Table 82. I2C_GS_VPS_PDC_UTC [1:0] Function

I2C_GS_VPS_PDC_UTC [1:0] Description

00 (default) Gemstar 1×/2× 01 VPS 10 PDC 11 UTC

GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear, Address 0x78 [4], User Sub Map, Write Only, Self-Clearing

1—Reinitializes the GS/PDC/VPS/UTC data readback registers.

VPS

The VPS data bits are biphase decoded by the VDP. The decoded data is available in both the ancillary stream and in

C readback registers. VPS decoded data is available in the

the I VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12 registers (Addresses 0x84 to 0x90, user sub map). VPS readback is set if the user programs the I2C_GS_VPS_PDC_UTC bit to 01, as explained in

Tabl e 8 2 .

Gemstar

The Gemstar decoded data is available in the ancillary stream, and any one line of Gemstar is available in I evaluation purposes. To obtain the Gemstar results in the I

C registers for

C registers, the user must program I2C_GS_VPS_PDC_UTC to 00, as explained in

Tabl e 8 2 .

VDP supports autodetection of Gemstar, distinguishing between Gemstar 1× and Gemstar 2×, and decodes data accordingly. For this autodetection mode to operate correctly, the user must set

the AUTO_DETECT_GS_TYPE I

C bit (Register 0x61, user sub map) and program the decoder to decode Gemstar 2× on the required lines through line programming. The type of Gemstar decoding can be determined by observing the GS_DATA_TYPE bit (Register 0x78, user sub map).

AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map

0 (default)—Disables autodetection of Gemstar type.

GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available, Address 0x78 [4], User Sub Map, Read Only

0—GS, PDC, VPS, or UTC data was not detected.

1—GS, PDC, VPS, or UTC data was detected.

VDP_GS_VPS_PDC_UTC Readback Registers, Addresses 0x84 to 0x90, User Sub Map

See Tab le 8 3.

1—Enables autodetection of Gemstar type.

GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only

This bit identifies the decoded Gemstar data type.

0—Gemstar 1× mode is detected. Read two data bytes from 0x84.

1—Gemstar 2× mode is detected. Read four data bytes from 0x84.

The Gemstar data that is available in the I

C register may be from any line of the input video on which Gemstar was decoded. To read the Gemstar data on a particular video line, the user should use the manual configuration as described in Tabl e 6 7 and Tabl e 68 and enable Gemstar decoding only on the required line.

Rev. A | Page 68 of 112

ADV7184

Table 83. GS/VPS/PDC/UTC Readback Registers

Address (User Sub Map) Signal Name Register Location Dec Hex

GS_VPS_PDC_UTC_BYTE_0 [7:0] VDP_GS_VPS_PDC_UTC_0 [7:0] 132d 0x84 GS_VPS_PDC_UTC_BYTE_1 [7:0] VDP_GS_VPS_PDC_UTC_1 [7:0] 133d 0x85 GS_VPS_PDC_UTC_BYTE_2 [7:0] VDP_GS_VPS_PDC_UTC_2 [7:0] 134d 0x86 GS_VPS_PDC_UTC_BYTE_3 [7:0] VDP_GS_VPS_PDC_UTC_3 [7:0] 135d 0x87 VPS_PDC_UTC_BYTE_4 [7:0] VDP_VPS_PDC_UTC_4 [7:0] 136d 0x88 VPS_PDC_UTC_BYTE_5 [7:0] VDP_VPS_PDC_UTC_5 [7:0] 137d 0x89 VPS_PDC_UTC_BYTE_6 [7:0] VDP_VPS_PDC_UTC_6 [7:0] 138d 0x8A VPS_PDC_UTC_BYTE_7 [7:0] VDP_VPS_PDC_UTC_7 [7:0] 139d 0x8B VPS_PDC_UTC_BYTE_8 [7:0] VDP_VPS_PDC_UTC_8 [7:0] 140d 0x8C VPS_PDC_UTC_BYTE_9 [7:0] VDP_VPS_PDC_UTC_9 [7:0] 141d 0x8D VPS_PDC_UTC_BYTE_10 [7:0] VDP_VPS_PDC_UTC_10 [7:0] 142d 0x8E VPS_PDC_UTC_BYTE_11 [7:0] VDP_VPS_PDC_UTC_11 [7:0] 143d 0x8F VPS_PDC_UTC_BYTE_12 [7:0] VDP_VPS_PDC_UTC_12 [7:0] 144d 0x90

The register is a readback register; the default value does not apply.

PDC/UTC

PDC and UTC are data transmitted through Teletext Packet 8/30 Format 2 (Magazine 8, Row 30, Design Code 2 or 3), and Packet 8/30 Format 1 (Magazine 8, Row 30, Design Code 0 or 1). Therefore, if

PDC or UTC data is to be read through I

C, the corresponding

teletext standard (WST or PAL System B) should be decoded by

The block is configured via the I

GDECEL [15:0] allows data recovery for selected video

•

C in the following ways:

lines on even fields to be enabled and disabled.

GDECOL [15:0] enables data recovery for selected lines for

•

odd fields.

VDP. The whole teletext decoded packet is output on the ancillary data stream. The user can look for the magazine number, row number, and design code and qualify the data as PDC, UTC, or neither of these.

If PDC/UTC packets are identified, Byte 0 to Byte 12 are updated to the GS_VPS_PDC_UTC_0 to VPS_PDC_UTC_12 registers and the GS_PDC_VPS_UTC_AVL bit is set. The full packet data is also available in the ancillary data format.

Note that the data available in the I

C register depends on the status of the WST_PKT_DECODE_DISABLE bit (Bit 3, Subaddress 0x60, user sub map).

VBI System 2

The user can choose to use an alternative VBI data slicer, called VBI System 2. This data slicer is used to decode Gemstar and closed caption VBI signals only.

Using this system, the Gemstar data is only available in the ancillary data stream. A special mode enables one line of data to be read

back via I

C. For more information, contact an Analog Devices

representative for an engineering note on ADV7184 VBI

• GDECAD configures the way in which data is embedded

in the video data stream.

The recovered data is not available through I

C, but is inserted into the horizontal blanking period of an ITU-R BT.656-compatible data stream. The data format is intended to comply with the ITU-R BT.1364 recommendation by the International Telecommunications Union. For more information, visit the International Telecommunications Union’s website. See

Figure 43.

GDE_SEL_OLD_ADF, Address 0x4C [3], User Map

The ADV7184 has an ancillary data output block that can be used by the VDP data slicer and the VBI System 2 data slicer. The new ancillary data formatter is used by setting GDE_SEL_OLD_ADF to 0 (this is the default setting). If this bit is set low, refer to

Tabl e 72 for information about how the data is packaged in

and

Table 7 1

the ancillary data stream.

To use the old ancillary data formatter (to be backward compatible with the ADV7189B), set GDE_SEL_OLD_ADF to 1. The ancillary data format in this section refers to the ADV7189Bcompatible ancillary data formatter.

processing.

Gemstar Data Recovery

0 (default)—Enables the new ancillary data system (for use with VDP and VBI System 2).

The Gemstar-compatible data recovery block (GSCD) supports Gemstar 1× and Gemstar 2× data transmissions. In addition, it can serve as a decoder for closed captioning. Gemstar-compatible

1—Enables the old ancillary data system (for use with VBI System 2 only; ADV7189B compatible).

data transmissions can occur only in NTSC mode. Closed caption data can be decoded in both PAL and NTSC modes.

Rev. A | Page 69 of 112

ADV7184

The format of the data packet depends on the following criteria:

Entries within the packet are as follows:

Transmission is Gemstar 1× or Gemstar 2×.

•

Data is output in 8-bit or 4-bit format (see the GDECAD,

•

Gemstar Decode Ancillary Data Format, Address 0x4C [0] section).

• Data is closed captioning (CC) or Gemstar compatible.

Data packets are output if the corresponding enable bit is set (see the Address 0x48 [7:0], Address 0x49 [7:0]

GDECEL [15:0], Gemstar Decoding Even Lines,

and the GDECOL [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0]

sections) and the decoder detects the presence of data. This means that for video lines where no data has been decoded, no data packet is output, even if the corresponding line enable bit is set.

Each data packet starts immediately after the EAV code of the preceding line.

Figure 43 and Tab l e 8 4 show the overall

structure of the data packet.

DATA IDENTIF ICATION

SECONDARY DATA IDENT IFICATI ON

A fixed preamble sequence of 0x00, 0xFF, and 0xFF.

•

The data identification word (DID) (10-bit value), the

•

value of which is 0x140 for a Gemstar or CC data packet.

•

The secondary data identification word (SDID), which

contains information about the video line from which data was retrieved, whether the Gemstar transmission was of 1× or 2× format, and whether it was retrieved from an even or odd field.

•

The data count byte, which provides the number of user

data-words that follow.

• User data section. This contains the user data, which can

be four or eight words of data.

• Optional padding to ensure that the length of the user

data-word section of a packet is a multiple of four bytes (requirement, as set in ITU-R BT.1364).

•

Checksum byte. This contains the checksum of the packet.

Tabl e 8 4 lists the values within a generic data packet that are output by the ADV7184 in 8-bit format.

00 FF FF DI D SDID

PREAMBLE FOR ANCILLARY DATA

DATA

COUNT

USER DATA (FOUR OR EIGHT WORDS)

Figure 43. Gemstar and CC Embedded Data Packet (Generic)

USER DATA

OPTIONAL PADDING

BYTES

CHECKSUM

05479-045

Table 84. Generic Data Output Packet

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

CS[8]

EP EF 2X line [3:0] 0 0 SDID

EP 0 0 0 0 DC [1] DC [0] 0 0 Data count (DC)

EP 0 0 word1 [7:4] 0 0 User data-words

EP 0 0 word1 [3:0] 0 0 User data-words

EP 0 0 word2 [7:4] 0 0 User data-words

EP 0 0 word2 [3:0] 0 0 User data-words

EP 0 0 word3 [7:4] 0 0 User data-words

EP 0 0 word3 [3:0] 0 0 User data-words

EP 0 0 word4 [7:4] 0 0 User data-words

EP 0 0 word4 [3:0] 0 0 User data-words

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] 0 0 Checksum

Rev. A | Page 70 of 112

ADV7184

Table 85. Data Byte Allocation

Raw Information Bytes

Gemstar 2×

1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01

Retrieved from the Video Line

GDECAD

User Data-Words (Including Padding)

Padding Bytes DC [1:0]

Gemstar Bit Names

• DID. The data identification value is 0x140 (10-bit value).

Care has been taken that in 8-bit systems, the two LSBs do not carry vital information.

•

EP and

. The EP bit is set to ensure even parity on the data-word D [8:0]. Even parity means there is always an even number of 1s within the D [8:0] bit arrangement. This includes the EP bit. and is output on D [9]. The

describes the logic inverse of EP

is output to ensure that the

reserved codes of 00 and FF cannot occur.

EF. Even field identifier. EF = 1 indicates that the data was

•

recovered from a video line on an even field.

• 2×. This bit indicates whether the data sliced was in

Gemstar 1× or 2× format. A high indicates Gemstar 2× format. The 2× bit determines whether the raw information retrieved from the video line was two or four bytes. The state of the GDECAD bit affects whether the bytes are transmitted straight (that is, two bytes transmitted as two bytes) or whether they are split into nibbles (that is, two bytes transmitted as four half bytes). Padding bytes are then added where necessary.

•

line [3:0]. This entry provides a code that is unique for

each of the 16 possible source lines of video from which Gemstar data may have been retrieved. Refer to and

Tabl e 95 .

Tabl e 9 4

•

DC [1:0]. Data count value. The number of UDWs in the

packet divided by 4. The number of UDWs in any packet must be an integral number of 4. Padding is required at the end, if necessary, as set in ITU-R BT.1364. See

CS [8:2]. The checksum is provided to determine the

•

Tabl e 8 5 .

integrity of the ancillary data packet. It is calculated by summing up D [8:2] of DID, SDID, data count byte, and all UDWs, and ignoring any overflow during the summation. Because all data bytes that are used to calculate the checksum have their two LSBs set to 0, the CS [1:0] bits are also always 0.

CS[8]

describes the logic inversion of CS [8]. The value

CS[8]

is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and 0xFF do not occur.

Tabl e 8 6 to Tab l e 9 1 outline the possible data packages.

Gemstar 2× Format, Half-Byte Output Mode

Half-byte output mode is selected by setting GDECAD to 0; full-byte output mode is selected by setting GDECAD to 1.

GDECAD, Gemstar Decode Ancillary Data Format,

See the Address 0x4C [0]

section.

Gemstar 1× Format, Half-Byte Output Mode

Half-byte output mode is selected by setting GDECAD to 0; full-byte output mode is selected by setting GDECAD to 1.

GDECAD, Gemstar Decode Ancillary Data Format,

See the Address 0x4C [0]

section.

Rev. A | Page 71 of 112

ADV7184

Table 86. Gemstar 2× Data, Half-Byte Mode1

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

The bold values represent Gemstar- or CC-specific values.

CS [8]

Table 87. Gemstar 2× Data, Full-Byte Mode

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

6 Gemstar Word1 [7:0] 0 0 User data-words 7 Gemstar Word2 [7:0] 0 0 User data-words 8 Gemstar Word3 [7:0] 0 0 User data-words 9 Gemstar Word4 [7:0] 0 0 User data-words 10

The bold values represent Gemstar- or CC-specific values.

CS [8]

Table 88. Gemstar 1× Data, Half-Byte Mode

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

The bold values represent Gemstar- or CC-specific values.

CS [8]

EP EF

EP 0 0 0 0

line [3:0] 0 0 SDID

1 0

0 0 Data count

EP 0 0 Gemstar Word1 [7:4] 0 0 User data-words

EP 0 0 Gemstar Word1 [3:0] 0 0 User data-words

EP 0 0 Gemstar Word2 [7:4] 0 0 User data-words

EP 0 0 Gemstar Word2 [3:0] 0 0 User data-words

EP 0 0 Gemstar Word3 [7:4] 0 0 User data-words

EP 0 0 Gemstar Word3 [3:0] 0 0 User data-words

EP 0 0 Gemstar Word4 [7:4] 0 0 User data-words

EP 0 0 Gemstar Word4 [3:0] 0 0 User data-words

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] CS [1] CS [0] Checksum

EP EF

EP 0 0 0 0

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] CS [1] CS [0] Checksum

EP EF

EP 0 0 0 0

line [3:0] 0 0 SDID

0 1

0 0 Data count

line [3:0] 0 0 SDID

0 1

0 0 Data count

EP 0 0 Gemstar Word1 [7:4] 0 0 User data-words

EP 0 0 Gemstar Word1 [3:0] 0 0 User data-words

EP 0 0 Gemstar Word2 [7:4] 0 0 User data-words

EP 0 0 Gemstar Word2 [3:0] 0 0 User data-words

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] CS [1] CS [0] Checksum

Rev. A | Page 72 of 112

ADV7184

Table 89. Gemstar 1× Data, Full-Byte Mode

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

EP EF

line [3:0] 0 0 SDID

EP 0 0 0 0

0 1

0 0 Data count

6 Gemstar Word1 [7:0] 0 0 User data-words 7 Gemstar Word2 [7:0] 0 0 User data-words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10

The bold values represent Gemstar- or CC-specific values.

CS [8]

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] CS [1] CS [0] Checksum

Table 90. NTSC CC Data, Half-Byte Mode

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

The bold values represent Gemstar- or CC-specific values.

CS [8]

EP EF

0 1 0 1 1

EP 0 0 0 0

0 1

0 0 SDID

0 0 Data count

EP 0 0 CCAP Word1 [7:4] 0 0 User data-words

EP 0 0 CCAP Word1 [3:0] 0 0 User data-words

EP 0 0 CCAP Word2 [7:4] 0 0 User data-words

EP 0 0 CCAP Word2 [3:0] 0 0 User data-words

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] CS [1] CS [0] Checksum

Table 91. NTSC CC Data, Full-Byte Mode

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

EP EF

0 1 0 1 1

EP 0 0 0 0

0 1

0 0 SDID

0 0 Data count

6 CCAP Word1 [7:0] 0 0 User data-words 7 CCAP Word2 [7:0] 0 0 User data-words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10

The bold values represent Gemstar- or CC-specific values.

CS [8]

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] CS [1] CS [0] Checksum

Rev. A | Page 73 of 112

ADV7184

Table 92. PAL CC Data, Half-Byte Mode

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

The bold values represent Gemstar- or CC-specific values.

CS [8]

EP EF

EP 0 0 0 0

EP 0 0 CCAP Word1 [7:4] 0 0 User data-words

EP 0 0 CCAP Word1 [3:0] 0 0 User data-words

EP 0 0 CCAP Word2 [7:4] 0 0 User data-words

EP 0 0 CCAP Word2 [3:0] 0 0 User data-words

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] CS [1] CS [0] Checksum

Table 93. PAL CC Data, Full-Byte Mode

Byte D [9] D [8] D [7] D [6] D [5] D [4] D [3] D [2] D [1] D [0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4

6 CCAP Word1 [7:0] 0 0 User data-words 7 CCAP Word2 [7:0] 0 0 User data-words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10

The bold values represent Gemstar- or CC-specific values.

CS [8]

EP EF

EP 0 0 0 0

CS [8] CS [7] CS [6] CS [5] CS [4] CS [3] CS [2] CS [1] CS [0] Checksum

NTSC CC Data

Half-byte output mode is selected by setting GDECAD to 0; fullbyte mode is enabled by setting GDECAD to 1. See the Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. The data packet formats are shown in Tabl e 9 1 . Only closed caption data can be embedded in the output data stream.

NTSC closed caption data is sliced on Line 21 on even and odd fields. The corresponding enable bit must be set high. See the GDECEL [15:0], Gemstar Decoding Even Lines, Address 0x48 [7:0], Address 0x49 [7:0]

and the GDECOL [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0] sections.

0 1 0 1 0

0 1

0 1 0 1 0

0 1

0 0 SDID

0 0 Data count

PAL closed caption data is sliced from Line 22 and Line 335. The corresponding enable bits must be set.

GDECAD,

Tabl e 9 0 and

Only closed caption data can be embedded in the output data stream. See the

GDECEL [15:0], Gemstar Decoding Even Lines, Address 0x48 [7:0], Address 0x49 [7:0] [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0]

GDECEL [15:0], Gemstar Decoding Even Lines, Address 0x48 [7:0], Address 0x49 [7:0]

The 16 bits of GDECEL [15:0] are interpreted as a collection of 16 individual lines of decode-enable signals. Each bit refers to a line of video in an even field. Setting the bit enables the decoder

0 0 SDID

0 0 Data count

and the GDECOL

sections.

block trying to find Gemstar or closed caption-compatible data

PAL CC Da t a

Half-byte output mode is selected by setting GDECAD to 0; full-byte output mode is selected by setting GDECAD to 1.

GDECAD, Gemstar Decode Ancillary Data Format,

See the Address 0x4C [0]

section. Tabl e 9 2 and Tab l e 9 3 list the bytes of

on that particular line. Setting the bit to 0 prevents the decoder from trying to retrieve data. See

Tabl e 9 4 and Tabl e 95 .

To retrieve closed caption data services on NTSC (Line 284), GDECEL [11] must be set.

the data packet.

Rev. A | Page 74 of 112

ADV7184

To retrieve closed caption data services on PAL (Line 335), GDECEL [14] must be set.

The default value of GDECEL [15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CC data from any line in the even field. The user should only enable Gemstar slicing on lines where VBI data is expected.

Table 94. NTSC Line Enable Bits and Corresponding Line Numbering

Line Number

line [3:0]

0 10 GDECOL [0] Gemstar 1 11 GDECOL [1] Gemstar 2 12 GDECOL [2] Gemstar 3 13 GDECOL [3] Gemstar 4 14 GDECOL [4] Gemstar 5 15 GDECOL [5] Gemstar 6 16 GDECOL [6] Gemstar 7 17 GDECOL [7] Gemstar 8 18 GDECOL [8] Gemstar 9 19 GDECOL [9] Gemstar 10 20 GDECOL [10] Gemstar 11 21 GDECOL [11] Gemstar or CC 12 22 GDECOL [12] Gemstar 13 23 GDECOL [13] Gemstar 14 24 GDECOL [14] Gemstar 15 25 GDECOL [15] Gemstar 0 273 (10) GDECEL [0] Gemstar 1 274 (11) GDECEL [1] Gemstar 2 275 (12) GDECEL [2] Gemstar 3 276 (13) GDECEL [3] Gemstar 4 277 (14) GDECEL [4] Gemstar 5 278 (15) GDECEL [5] Gemstar 6 279 (16) GDECEL [6] Gemstar 7 280 (17) GDECEL [7] Gemstar 8 281 (18) GDECEL [8] Gemstar 9 282 (19) GDECEL [9] Gemstar 10 283 (20) GDECEL [10] Gemstar 11 284 (21) GDECEL [11] Gemstar or CC 12 285 (22) GDECEL [12] Gemstar 13 286 (23) GDECEL [13] Gemstar 14 287 (24) GDECEL [14] Gemstar 15 288 (25) GDECEL [15] Gemstar

(ITU-R BT.470)

Enable Bit Comment

Table 95. PAL Line Enable Bits and Corresponding Line Numbering

Line Number

Line [3:0]

12 8 GDECOL [0] Not valid 13 9 GDECOL [1] Not valid 14 10 GDECOL [2] Not valid 15 11 GDECOL [3] Not valid 0 12 GDECOL [4] Not valid 1 13 GDECOL [5] Not valid 2 14 GDECOL [6] Not valid 3 15 GDECOL [7] Not valid 4 16 GDECOL [8] Not valid 5 17 GDECOL [9] Not valid 6 18 GDECOL [10] Not valid 7 19 GDECOL [11] Not valid 8 20 GDECOL [12] Not valid 9 21 GDECOL [13] Not valid

10 22 GDECOL [14] CC

11 23 GDECOL [15] Not valid 12 321 (8) GDECEL [0] Not valid 13 322 (9) GDECEL [1] Not valid 14 323 (10) GDECEL [2] Not valid 15 324 (11) GDECEL [3] Not valid 0 325 (12) GDECEL [4] Not valid 1 326 (13) GDECEL [5] Not valid 2 327 (14) GDECEL [6] Not valid 3 328 (15) GDECEL [7] Not valid 4 329 (16) GDECEL [8] Not valid 5 330 (17) GDECEL [9] Not valid 6 331 (18) GDECEL [10] Not valid 7 332 (19) GDECEL [11] Not valid 8 333 (20) GDECEL [12] Not valid 9 334 (21) GDECEL [13] Not valid

10 335 (22) GDECEL [14] CC

11 336 (23) GDECEL [15] Not valid

As indicated by the bold rows, two standards can use the same line for VBI data.

(ITU-R BT.470)

Enable Bit Comment

Rev. A | Page 75 of 112

ADV7184

GDECOL [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0]

The 16 bits of the GDECOL [15:0] form a collection of 16 individual line decode enable signals. See

Tabl e 9 4 and Tab l e 9 5 .

To retrieve closed caption data services on NTSC (Line 21), GDECOL [11] must be set.

To retrieve closed caption data services on PAL (Line 22), GDECOL [14] must be set.

The default value of GDECOL [15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CC data from any line in the odd field. The user should only enable Gemstar slicing on lines where VBI data is expected.

GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0]

The decoded data from Gemstar-compatible transmissions or closed caption transmission is inserted into the horizontal blanking period of the respective line of video. A potential problem can arise if the retrieved data bytes have the value 0x00 or 0xFF. In an ITU-R BT.656-compatible data stream, these values are reserved and used only to form a fixed preamble.

The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways:

•

Insert all data straight into the data stream, even the reserved

values of 0x00 and 0xFF, if they occur. This may violate the output data format specification ITU-R BT.1364.

•

Split all data into nibbles and insert the half-bytes over

twice the number of cycles in a 4-bit format.

0 (default)—The data is split into half-bytes and inserted.

1—The data is output straight in 8-bit format.

Letterbox Detection

Incoming video signals may conform to different aspect ratios (16:9 wide-screen or 4:3 standard). For certain transmissions in the wide-screen format, a digital sequence (WSS) is transmitted with the video signal. If a WSS sequence is provided, the aspect ratio of the video can be derived from the digitally decoded bits that WSS contains.

In the absence of a WSS sequence, letterbox detection can be used to find wide-screen signals. The detection algorithm examines the active video content of lines at the start and end of a field. If black lines are detected, this may indicate that the currently shown picture is in wide-screen format.

The active video content (luminance magnitude) over a line of video is summed together. At the end of a line, this accumulated value is compared with a threshold and a decision is made as to whether a particular line is black. The threshold value needed may depend on the type of input signal; some control is provided via LB_TH [4:0].

Detection at the Start of a Field

The ADV7184 expects a section of at least six consecutive black lines of video at the top of a field. Once those lines are detected, Register LB_LCT [7:0] is updated. Register LB_LCT [7:0] reports the number of black lines that were actually found. By default, the ADV7184 starts looking for those black lines in sync with the beginning of active video, for example, immediately after the last VBI video line. LB_SL [3:0] allows the user to set the start of letterbox detection from the beginning of a frame on a line-by-line basis. The letterbox detection ends in the middle of the field.

Detection at the End of a Field

The ADV7184 expects at least six continuous lines of black video at the bottom of a field before reporting the number of lines actually found via the LB_LCB [7:0] value. The activity window for letterbox detection (end of field) starts in the middle of an active field. Its end is programmable via LB_EL [3:0].

Detection at the Midrange

Some transmissions of wide-screen video include subtitles within the lower black box. If the ADV7184 finds at least two black lines followed by more nonblack video, for example, the subtitle followed by the remainder of the bottom black block, it reports a midcount via LB_LCM [7:0]. If no subtitles are found, LB_LCM [7:0] reports the same number as LB_LCB [7:0].

There is a two-field delay in the reporting of line count parameters.

There is no letterbox detected bit. Read the LB_LCT [7:0] and LB_LCB [7:0] bit values to conclude whether or not the letterbox type of video is present in the software.

LB_LCT [7:0], Letterbox Line Count Top, Address 0x9B [7:0]; LB_LCM [7:0], Letterbox Line Count Mid, Address 0x9C [7:0]; LB_LCB [7:0], Letterbox Line Count Bottom, Address 0x9D [7:0]

Table 96. LB_LCx [7:0] Access Information

Signal Name Address

LB_LCT [7:0] 0x9B LB_LCM [7:0] 0x9C LB_LCB [7:0] 0x9D

This register is a readback register; the default value does not apply.

Rev. A | Page 76 of 112

ADV7184

LB_TH [4:0], Letterbox Threshold Control, Address 0xDC [4:0]

Table 97. LB_TH [4:0] Function

LB_TH [4:0] Description

01100

Default threshold for detection of black lines

(default)

01101 to

10000

00000 to

01011

Increase threshold (need larger active video content before identifying nonblack lines)

Decrease threshold (even small noise levels can cause the detection of nonblack lines)

LB_SL [3:0], Letterbox Start Line, Address 0xDD [7:4]

The LB_SL [3:0] bits are set at 0100 by default. For an NTSC signal, the letterbox detection is from Line 23 to Line 286.

By changing the bits to 0101, the detection starts on Line 24 and ends on Line 287.

–2

–4

AMPLITUDE (dB)

–6

–8

–10

–12

2.0 4.03.53.02.5 5.04.5

FREQUENCY (MHz)

Figure 44. NTSC IF Compensation Filter Responses

05479-046

LB_EL [3:0], Letterbox End Line, Address 0xDD [3:0]

The LB_EL [3:0] bits are set at 1101 by default. This means that letterbox detection ends with the last active video line. For an NTSC signal, the detection is from Line 262 to Line 525.

By changing the settings of the bits to 1100, the detection starts on Line 261 and ends on Line 254.

IF Compensation Filter

IFFILTSEL [2:0], IF Filter Select, Address 0xF8 [2:0]

The IFFILTSEL [2:0] register allows the user to compensate for SAW filter characteristics on a composite input, such as those associated with tuner outputs.

Figure 44 and Figure 45 show IF

filter compensation for NTSC and PAL.

The options for this feature are as follows:

•

Bypass mode (default)

NTSC—consists of three filter characteristics

•

PAL—consists of three filter characteristics

•

Table 105 for programming details.

See

–2

AMPLITUDE (dB)

–4

–6

–8

3.0 5.04.54.03.5 6.05.5

FREQUENCY (MHz)

Figure 45. PAL IF Compensation Filter Responses

05479-047

I2C Interrupt System

The ADV7184 has a comprehensive interrupt register set. This map is located in the user sub map. See the interrupt register map.

Figure 48 describes how to access

Table 107 for details of

this map.

Rev. A | Page 77 of 112

ADV7184

Interrupt Request Output Operation

When an interrupt event occurs, the interrupt pin INTRQ

goes low, with a programmable duration given

by INTRQ_DUR_SEL [1:0]

INTRQ_DUR_SEL [1:0], Interrupt Duration Select, Address 0x40 [7:6], User Sub Map

Table 98. INTRQ_DUR_SEL [1:0] Function

INTRQ_DUR_SEL [1:0] Description

00 (default) 3 XTAL periods 01 15 XTAL periods 10 63 XTAL periods 11 Active until cleared

When the active-until-cleared interrupt duration is selected and the event that caused the interrupt is no longer in force, the interrupt persists until it is masked or cleared.

For example, if the ADV7184 loses lock, an interrupt is generated

INTRQ

and the locked state,

pin goes low. If the ADV7184 returns to the

INTRQ

continues to be driven low until the

SD_LOCK bit is either masked or cleared.

Interrupt Drive Level

The ADV7184 resets with open drain enabled and interrupt

INTRQ

masking disabled. Therefore,

is in a high impedance state after a reset. Either 01 or 10 must be written to INTRQ_OP_SEL [1:0] for a logic level to be driven out from

INTRQ

the

pin.

It is also possible to write to a bit in the ADV7184 that manually

INTRQ

asserts the

pin. This bit is MPU_STIM_INTRQ.

INTRQ_OP_SEL [1:0], Interrupt Duration Select, Address 0x40 [1:0], User Sub Map

Table 99. INTRQ_OP_SEL [1:0] Function

INTRQ_OP_SEL [1:0] Description

00 (default) Open drain 01 Driven low when active 10 Driven high when active 11 Reserved

Multiple Interrupt Events

If an interrupt event occurs and then another interrupt event occurs before the system controller has cleared or masked the first interrupt event, the ADV7184 does not generate a second interrupt signal. Therefore, the system controller should check all unmasked interrupt status bits because more than one may be active.

Macrovision Interrupt Selection Bits

The user can select between pseudosync pulse and color stripe detection as outlined in

Tabl e 1 0 0.

MV_INTRQ_SEL [1:0], Macrovision Interrupt Selection Bits, Address 0x40 [5:4], User Sub Map

Table 100. MV_INTRQ_SEL [1:0] Function

MV_INTRQ_SEL [1:0] Description

00 Reserved 01 (default) Pseudosync only 10 Color stripe only 11 Either pseudosync or color stripe

Additional information about the interrupt system is detailed in Table 107.

Rev. A | Page 78 of 112

ADV7184

PIXEL PORT CONFIGURATION

The ADV7184 has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs. Table 101 and Table 102 summarize the various functions that the ADV7184 pins can have in different modes of operation.

SWPC, Swap Pixel Cr/Cb, Address 0x27 [7]

0 (default)—No swapping is allowed.

1—The Cr and Cb values can be swapped.

The order of components, for example, the order of Cr and Cb, on the output pixel bus can be changed. Refer to the Swap Pixel Cr/Cb, Address 0x27 [7] the default positions for the Cr/Cb components.

section. Table 101 indicates

SWPC,

PIXEL PORT–RELATED CONTROLS

OF_SEL [3:0], Output Format Selection, Address 0x03 [5:2]

The modes in which the ADV7184 pixel port can be configured are controlled by OF_SEL [3:0]. See

The default LLC frequency output on the LLC1 pin is approximately 27 MHz. For modes that operate with a nominal data rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin stays at the higher rate of 27 MHz. For information on outputting the nominal 13.5 MHz clock on the LLC1 pin, see the Address 0x8F [6:4]

Table 101. P15 to P0 Output/Input Pin Mapping

Processor, Format, and Mode

Video Output, 8-Bit, 4:2:2 YCrCb [7:0] Video Output, 16-Bit, 4:2:2 Y [7:0] CrCb [7:0]

Table 102. Standard Definition Pixel Port Modes

Pixel Port Pins P [15:0] OF_SEL [3:0] Format P [15:8] P [7:0]

0010 16-Bit at LLC2 4:2:2 Y [7:0] CrCb [7:0] 0011 (default) 8-Bit at LLC1 4:2:2 YCrCb [7:0] (default) Three-state 0110 to 1111 Reserved Reserved—do not use

LLC_PAD_SEL [2:0], LLC1 Output Selection,

section.

Table 102 for details.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LLC_PAD_SEL [2:0], LLC1 Output Selection, Address 0x8F [6:4]

The following I2C write allows the user to select between LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).

The LLC2 signal is useful for LLC2-compatible wide bus (16-bit) output modes. See the Selection, Address 0x03 [5:2] The LLC2 signal and data on the data bus are synchronized. By default, the rising edge of LLC1/LLC2 is aligned with the Y data; the falling edge occurs when the data bus holds C data. The polarity of the clock, and therefore the Y/C assignments for the clock edges, can be altered by using the polarity LLC pin.

000 (default)—The output is nominally 27 MHz LLC on the LLC1 pin.

101—The output is nominally 13.5 MHz LLC on the LLC1 pin.

Output of Data Port Pins P [15:0]

OF_SEL [3:0], Output Format

section for additional information.

Rev. A | Page 79 of 112

ADV7184

MPU PORT DESCRIPTION

The ADV7184 supports a 2-wire (I2C-compatible) serial interface. Two inputs, serial data (SDA) and serial clock (SCLK),

carry information between the ADV7184 and the system I

master controller. Each slave device is recognized by a unique

address. The ADV7184 I

C port allows the user to set up and configure the decoder and then to read back captured VBI data. The ADV7184 has two possible slave addresses for both read and write operations, depending on the logic level on the ALSB pin. These four unique addresses are shown in

Table 103. The ADV7184 ALSB pin controls Bit 1 of the slave address. By altering the ALSB, it is possible to control two ADV7184s in an application without having a conflict with the same slave address. The LSB (Bit 0) sets either a read or write operation. Logic 1 corresponds to a read operation; Logic 0 corresponds to a write operation.

Table 103. I2C Address

ALSB R/

Slave Address

0 0 0x40 0 1 0x41 1 0 0x42 1 1 0x43

To control the device on the bus, a specific protocol must be followed. First, the master initiates a data transfer by establishing a start condition, which is defined by a high-to-low transition on SDA while SCLK remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition

and shift the next eight bits (7-bit address + R/

bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCLK lines, waiting for the start condition and the correct transmitted address.

The R/

bit determines the direction of the data. If the first byte of the LSB is Logic 0, the master writes information to the peripheral. If the first byte of the LSB is Logic 1, the master reads information from the peripheral.

The ADV7184 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit

addresses plus the R/

bit. The ADV7184 has 249 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses autoincrement, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any subaddress register on a one-by-one basis without updating all the registers.

Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7184 does not issue an acknowledge and returns to the idle condition.

If the highest subaddress is exceeded in autoincrement mode, the following action is taken:

During a read, the highest subaddress register contents

continue to be output until the master device issues a no acknowledge. This indicates the end of a read. In a no acknowledge condition, the SDA line is not pulled low on the ninth pulse.

During a write, the data for the invalid byte is not loaded into

a subaddress register. Instead, a no acknowledge is issued by the ADV7184, and the part returns to the idle condition.

SDATA

SCLOCK

WRITE

EQUENCE

READ

EQUENCE

SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S)

SLAVE ADDR SLAVE ADDRA(S) SUB ADDR A(S) S A(S) DATA A(M)

S = START BIT P = STOP BIT

S P

1–7 1–78 9 8 9 1–7 8 9

START ADDR ACK ACK DATA ACK STOPSUBADDRESS

A(S) = ACKNOWL EDGE BY SLAVE A(M) = ACKNOWL EDGE BY MAST ER

R/W

Figure 46. Bus Data Transfer

LSB = 1LSB = 0

A(S) = NO ACKNOWLEDGE BY SL AVE A(M) = NO ACKNOWLEDGE BY MASTER

Figure 47. Read and Write Sequence

Rev. A | Page 80 of 112

DATA A(S) P

05479-049

DATA A(M) P

05479-050

ADV7184

REGISTER ACCESSES

The MPU can write to and read from all of the ADV7184 registers except those that are read only or write only. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. A read/write operation is then performed from/to the target address, which then increments to the next address until a stop command on the bus is performed.

REGISTER PROGRAMMING

The I2C Register Maps section describes each register in terms of its configuration. After the part has been accessed via the bus and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place. operations controlled by the subaddress register.

Table 106 and Table 107 list the various

I2C SEQUENCER

An I2C sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more I example, HSB [11:0].

When such a parameter is changed using two or more I operations, the parameter may hold an invalid value for the time

between the first and last I

Cs. In other words, the top bits of the parameter may hold the new value while the remaining bits of the parameter still hold the previous value.

To avoid this problem, the I

C sequencer holds the already updated bits of the parameter in local memory. All bits of the parameter are updated together after the last register write operation has completed.

The correct operation of the I

C sequencer relies on the

following:

C registers, for

C write

As can be seen in

Figure 48, the registers in the ADV7184 are arranged into two maps: the user map (enabled by default) and the user sub map. The user sub map has controls for the interrupt and VDP functionality of the ADV7184, and the user map controls everything else.

The user map and the user sub map consist of a common space from Address 0x00 to Address 0x3F. Depending on how Bit 5 in Register 0x0E (SUB_USR_EN) is set, the register map is then split into two sections.

SUB_USR_EN, Address 0x0E [5]

This bit splits the register map at Register 0x40.

0 (default)—The register map does not split and the user map is enabled.

1—The register map splits and the user sub map is enabled.

USER MAP

COMMON I2C SPACE

ADDRESSES 0x00 TO 0x3F

ADDRESS 0x0E BIT 5 = 0b

USER SUB MAP

ADDRESS 0x0E BIT 5 = 1b

• All I2C registers for the parameter in question must be

written to in order of ascending addresses. For example, for HSB [10:0], write to Address 0x34 first, followed by Address 0x35.

•

No other I

(or more) I

C read or write can take place between the two

C writes for the sequence. For example, for HSB [10:0], write to Address 0x34 first, immediately followed by Address 0x35.

I2C PROGRAMMING EXAMPLES

A register programming script consisting of I2C programming examples for all standard modes supported by the ADV7184 is available from the ADV7184 product page on the Analog Devices website. The examples provided are applicable to a system with the analog inputs arranged as shown in registers change in accordance with the layout of the PCB.

Figure 52. The input selection

C SPACE

ADDRESSES 0x40 TO 0xFF

NORMAL REGISTER SPACE

Figure 48. Register Access —User Map and User Sub Map

C SPACE

ADDRESSES 0x40 TO 0x9C

INTERRUPT AND VDP REGISTER SPACE

05479-048

Rev. A | Page 81 of 112

ADV7184

I2C REGISTER MAPS

USER MAP

The collective name for the registers in Tabl e 10 4 is the user map.

Table 104. User Map Register Details

Address

Dec Hex Register Name RW 7 6 5 4 3 2 1 0

0 00 Input Control RW VID_SEL.3 VID_SEL.2 VID_SEL.1 VID_SEL.0 INSEL.3 INSEL.2 INSEL.1 INSEL.0 00000000 00 1 01 Video Selection RW ENHSPLL BETACAM ENVSPROC 11001000 C8 3 03 Output Control RW VBI_EN TOD OF_SEL.3 OF_SEL.2 OF_SEL.1 OF_SEL.0 SD_DUP_AV 00001100 0C 4 04 Extended Output

Control 7 07 Autodetect Enable RW AD_SEC525_EN AD_SECAM_EN AD_N443_EN AD_P60_EN AD_PALN_EN AD_PALM_EN AD_NTSC_EN AD_PAL_EN 01111111 7F 8 08 Contrast RW CON.7 CON.6 CON.5 CON.4 CON.3 CON.2 CON.1 CON.0 10000000 80 10 0A Brightness RW BRI.7 BRI.6 BRI.5 BRI.4 BRI.3 BRI.2 BRI.1 BRI.0 00000000 00 11 0B Hue RW HUE.7 HUE.6 HUE.5 HUE.4 HUE.3 HUE.2 HUE.1 HUE.0 00000000 00 12 0C Default Value Y RW DEF_Y.5 DEF_Y.4 DEF_Y.3 DEF_Y.2 DEF_Y.1 DEF_Y.0 DEF_VAL_

13 0D Default Value C RW DEF_C.7 DEF_C.6 DEF_C.5 DEF_C.4 DEF_C.3 DEF_C.2 DEF_C.1 DEF_C.0 01111100 7C 14 0E Analog Devices

Control 15 0F Power Management RW RES PWRDN PDBP FB_PWRDN 00000000 00 16 10 Status 1 R COL_KILL AD_RESULT.2 AD_RESULT.1 AD_RESULT.0 FOLLOW_PW FSC_LOCK LOST_LOCK IN_LOCK – – 18 12 Status 2 R FSC NSTD LL NSTD MV AGC DET MV PS DET MVCS T3 MVCS DET – – 19 13 Status 3 R PAL_SW_LOCK INTERLACE STD FLD LEN FREE_RUN_ACT CVBS SD_OP_50Hz GEMD INST_HLOCK – – 19 13 Analog Control

Internal 20 14 Analog Clamp

Control 21 15 Digital Clamp

Control 1 23 17 Shaping Filter

Control 24 18 Shaping Filter

Control 2 25 19 Comb Filter Control RW NSFSEL.1 NSFSEL.0 PSFSEL.1 PSFSEL.0 11110001 F1 29 1D Analog Devices

Control 2 39 27 Pixel Delay Control RW SWPC AUTO_PDC_EN CTA.2 CTA.1 CTA.0 LTA.1 LTA.0 01011000 58 43 2B Misc Gain Control RW CKE PW_UPD 11100001 E1 44 2C AGC Mode Control RW LAGC.2 LAGC.1 LAGC.0 CAGC.1 CAGC.0 10101110 AE 45 2D Chroma Gain

Control 1 46 2E Chroma Gain

Control 2 47 2F Luma Gain Control 1 W LAGT.1 LAGT.0 LMG.11 LMG.10 LMG.9 LMG.8 1111xxxx F0 48 30 Luma Gain Control 2 W LMG.7 LMG.6 LMG.5 LMG.4 LMG.3 LMG.2 LMG.1 LMG.0 xxxxxxxx 00 49 31 Vsyn c Field

Control 1 50 32 Vsyn c Field Control 2 RW VSBHO VSBHE 01000001 41 51 33 Vsyn c Field Control 3 RW VSEHO VSEHE 10000100 84 52 34 Hsyn c Position

Control 1 53 35 Hsyn c Position

Control 2 54 36 Hsyn c Position

Control 3 55 37 Polarity RW PHS PVS PF PCLK 00000001 01 56 38 NTSC Comb Control RW CTAPSN.1 CTAPSN.0 CCMN.2 CCMN.1 CCMN.0 YCMN.2 YCMN.1 YCMN.0 10000000 80 57 39 PAL Comb Control RW CTAPSP.1 CTAPSP.0 CCMP.2 CCMP.1 CCMP.0 YCMP.2 YCMP.1 YCMP.0 11000000 C0 58 3A ADC Control RW PDN_ADC0 PDN_ADC1 PDN_ADC2 PDN_ADC3 00010001 11 61 3D Manual Window

Control 65 41 Resample Control RW SFL_INV 00000001 01

RW BT656-4 TIM_OE BL_C_VBI EN_SFL_PIN RANGE 01xx0101 45

AUTO_EN

SUB_USR_EN 00000000 00

W XTAL_TTL_SEL 00000000 00

RW CCLEN 00010010 12

RW DCT.1 DCT.0 DCFS 0000xxxx 00

RW CSFM.2 CSFM.1 CSFM.0 YSFM.4 YSFM.3 YSFM.2 YSFM.1 YSFM.0 00000001 01

RW WYSFMOVR WYSFM.4 WYSFM.3 WYSFM.2 WYSFM.1 WYSFM.0 10010011 93

RW TRI_LLC EN28XTAL 00000xxx 00

W CAGT.1 CAGT.0 CMG.11 CMG.10 CMG.9 CMG.8 11110100 F4

W CMG.7 CMG.6 CMG.5 CMG.4 CMG.3 CMG.2 CMG.1 CMG.0 00000000 00

RW NEWAVMODE HVSTIM 00010010 12

RW HSB.10 HSB.9 HSB.8 HSE.10 HSE.9 HSE.8 00000000 00

RW HSB.7 HSB.6 HSB.5 HSB.4 HSB.3 HSB.2 HSB.1 HSB.0 00000010 02

RW HSE.7 HSE.6 HSE.5 HSE.4 HSE.3 HSE.2 HSE.1 HSE.0 00000000 00

RW CKILLTHR.2 CKILLTHR.1 CKILLTHR.0 01000011 43

DEF_VAL_EN 00110110 36

Reset Value

(Hex)

Rev. A | Page 82 of 112

ADV7184

Address

Dec Hex Register Name RW 7 6 5 4 3 2 1 0

72 48 Gemstar Control 1 RW GDECEL.15 GDECEL.14 GDECEL.13 GDECEL.12 GDECEL.11 GDECEL.10 GDECEL.9 GDECEL.8 00000000 00 73 49 Gemstar Control 2 RW GDECEL.7 GDECEL.6 GDECEL.5 GDECEL.4 GDECEL.3 GDECEL.2 GDECEL.1 GDECEL.0 00000000 00 74 4A Gemstar Control 3 RW GDECOL.15 GDECOL.14 GDECOL.13 GDECOL.12 GDECOL.11 GDECOL.10 GDECOL.9 GDECOL.8 00000000 00 75 4B Gemstar Control 4 RW GDECOL.7 GDECOL.6 GDECOL.5 GDECOL.4 GDECOL.3 GDECOL.2 GDECOL.1 GDECOL.0 00000000 00 76 4C Gemstar Control 5 RW GDECAD xxxx0000 00 77 4D CTI DNR Control 1 RW DNR_EN CTI_AB.1 CTI_AB.0 CTI_AB_EN CTI_EN 11101111 EF 78 4E CTI DNR Control 2 RW CTI_C_TH.7 CTI_C_TH.6 CTI_C_TH.5 CTI_C_TH.4 CTI_C_TH.3 CTI_C_TH.2 CTI_C_TH.1 CTI_C_TH.0 00001000 08 80 50 CTI DNR Control 4 RW DNR_TH.7 DNR_TH.6 DNR_TH.5 DNR_TH.4 DNR_TH.3 DNR_TH.2 DNR_TH.1 DNR_TH.0 00001000 08 81 51 Lock Count RW FSCLE SRLS COL.2 COL.1 COL.0 CIL.2 CIL.1 CIL.0 00100100 24 105 69 Config 1 RW Reserved Reserved Reserved Reserved Reserved Reserved SDM_SEL.1 SDM_SEL.0 00000x00 00 134 86 STDI Control RW Reserved Reserved Reserved Reserved STDI_LINE_

143 8F Free-Run Line

Length 1 153 99 CCAP 1 R CCAP1.7 CCAP1.6 CCAP1.5 CCAP1.4 CCAP1.3 CCAP1.2 CCAP1.1 CCAP1.0 – – 154 9A CCAP 2 R CCAP2.7 CCAP2.6 CCAP2.5 CCAP2.4 CCAP2.3 CCAP2.2 CCAP2.1 CCAP2.0 – – 155 9B Letterbox 1 R LB_LCT.7 LB_LCT.6 LB_LCT.5 LB_LCT.4 LB_LCT.3 LB_LCT.2 LB_LCT.1 LB_LCT.0 – – 156 9C Letterbox 2 R LB_LCM.7 LB_LCM.6 LB_LCM.5 LB_LCM.4 LB_LCM.3 LB_LCM.2 LB_LCM.1 LB_LCM.0 – – 157 9D Letterbox 3 R LB_LCB.7 LB_LCB.6 LB_LCB.5 LB_LCB.4 LB_LCB.3 LB_LCB.2 LB_LCB.1 LB_LCB.0 – – 177 B1 Standard Ident 1 R STDI_DVALID Reserved BL.13 BL.12 BL.11 BL.10 BL.9 BL.8 – – 178 B2 Standard Ident 2 R BL.7 BL.6 BL.5 BL.4 BL.3 BL.2 BL.1 BL.0 – – 179 B3 Standard Ident 3 R LCVS.4 LCVS.3 LCVS.2 LCVS.1 LCVS.0 LCF.10 LCF.9 LCF.8 – – 180 B4 Standard Ident 4 R LCF.7 LCF.6 LCF.5 LCF.4 LCF.3 LCF.2 LCF.1 LCF.0 – – 195 C3 ADC Switch 1 RW ADC1_SW.3 ADC1_SW.2 ADC1_SW.1 ADC1_SW.0 ADC0_SW.3 ADC0_SW.2 ADC0_SW.1 ADC0_SW.0 xxxxxxxx 00 196 C4 ADC Switch 2 RW ADC_SW_MAN ADC2_SW.3 ADC2_SW.2 ADC2_SW.1 ADC2_SW.0 0xxxxxxx 00 202 CA Field Length Count 1 R Reserved Reserved Reserved FCL.12 FCL.11 FCL.10 FCL.9 FCL.8 – – 203 CB Field Length Count 2 R FCL.7 FCL.6 FCL.5 FCL.4 FCL.3 FCL.2 FCL.1 FCL.0 – – 220 DC Letterbox Control 1 RW LB_TH.4 LB_TH.3 LB_TH.2 LB_TH.1 LB_TH.0 10101100 AC 221 DD Letterbox Control 2 RW LB_SL.3 LB_SL.2 LB_SL.1 LB_SL.0 LB_EL.3 LB_EL.2 LB_EL.1 LB_EL.0 01001100 4C 222 DE ST Noise Readback 1 R ST_NOISE_VLD ST_NOISE.10 ST_NOISE.9 ST_NOISE.8 – – 223 DF ST Noise Readback 2 R ST_NOISE.7 ST_NOISE.6 ST_NOISE.5 ST_NOISE.4 ST_NOISE.3 ST_NOISE.2 ST_NOISE.1 ST_NOISE.0 – – 225 E1 SD Offset Cb RW SD_OFF_CB.7 SD_OFF_CB.6 SD_OFF_CB.5 SD_OFF_CB.4 SD_OFF_CB.3 SD_OFF_CB.2 SD_OFF_CB.1 SD_OFF_CB.0 10000000 80 226 E2 SD Offset Cr RW SD_OFF_CR.7 SD_OFF_CR.6 SD_OFF_CR.5 SD_OFF_CR.4 SD_OFF_CR.3 SD_OFF_CR.2 SD_OFF_CR.1 SD_OFF_CR.0 10000000 80 227 E3 SD Saturation Cb RW SD_SAT_CB.7 SD_SAT_CB.6 SD_SAT_CB.5 SD_SAT_CB.4 SD_SAT_CB.3 SD_SAT_CB.2 SD_SAT_CB.1 SD_SAT_CB.0 10000000 80 228 E4 SD Saturation Cr RW SD_SAT_CR.7 SD_SAT_CR.6 SD_SAT_CR.5 SD_SAT_CR.4 SD_SAT_CR.3 SD_SAT_CR.2 SD_SAT_CR.1 SD_SAT_CR.0 10000000 80 229 E5 NTSC V Bit Begin RW NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG.4 NVBEG.3 NVBEG.2 NVBEG.1 NVBEG.0 00100101 25 230 E6 NTSC V Bit End RW NVENDDELO NVENDDELE NVENDSIGN NVEND.4 NVEND.3 NVEND.2 NVEND.1 NVEND.0 00000100 04 231 E7 NTSC F Bit Toggle RW NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG.4 NFTOG.3 NFTOG.2 NFTOG.1 NFTOG.0 01100011 63 232 E8 PAL V Bit Begin RW PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG.4 PVBEG.3 PVBEG.2 PVBEG.1 PVBEG.0 01100101 65 233 E9 PAL V Bit End RW PVENDDELO PVENDDELE PVENDSIGN PVEND.4 PVEND.3 PVEND.2 PVEND.1 PVEND.0 00010100 14 234 EA PAL F Bit Toggle RW PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG.4 PFTOG.3 PFTOG.2 PFTOG.1 PFTOG.0 01100011 63 235 EB Vblank Control 1 RW NVBIOLCM.1 NVBIOLCM.0 NVBIELCM.1 NVBIELCM.0 PVBIOLCM.1 PVBIOLCM.0 PVBIELCM.1 PVBIELCM.0 01010101 55 236 EC Vblank Control 2 RW NVBIOCCM.1 NVBIOCCM.0 NVBIECCM.1 NVBIECCM.0 PVBIOCCM.1 PVBIOCCM.0 PVBIECCM.1 PVBIECCM.0 01010101 55 237 ED FB_STATUS R FB_STATUS.3 FB_STATUS.2 FB_STATUS.1 FB_STATUS.0 – – 237 ED FB_CONTROL1 W FB_INV CVBS_RGB_SEL FB_MODE.1 FB_MODE.0 00010000 10 238 EE FB_CONTROL 2 RW FB_CSC_MAN MAN_ALPHA_

239 EF FB_CONTROL 3 RW FB_SP_

240 F0 FB_CONTROL 4 RW FB_DELAY.3 FB_DELAY.2 FB_DELAY.1 FB_DELAY.0 01000100 44 241 F1 FB_CONTROL 5 RW CNTR_LEVEL.1 CNTR_LEVEL.0 FB_LEVEL.1 FB_LEVEL.0 CNTR_MODE.1 CNTR_MODE.0 RGB_IP_SEL 00001100 0C 243 F3 AFE_CONTROL 1 RW ADC3_SW.3 ADC3_SW.2 ADC3_SW.1 ADC3_SW.0 AA_FILT_EN.3 AA_FILT_EN.2 AA_FILT_EN.1 AA_FILT_EN.0 00000000 00 244 F4 Drive Strength RW DR_STR DR_STR.0 DR_STR_C DR_STR_C.0 DR_STR_S DR_STR_S.0 xx010101 15 248 F8 IF Comp Control RW IFFILTSEL.2 IFFILTSEL.1 IFFILTSEL.0 00000000 00 249 F9 VS Mode Control RW VS_COAST_

251 FB Peaking Control RW PEAKING_

252 FC Coring Threshold 2 RW DNR_TH2.7 DNR_TH2.6 DNR_TH2.5 DNR_TH2.4 DNR_TH2.3 DNR_TH2.2 DNR_TH2.1 DNR_TH2.0 00000100 04

W LLC_PAD_

ADJUST.3

GAIN.7

SEL_MAN

VAL.6 FB_SP_

ADJUST.2

PEAKING_ GAIN.6

LLC_PAD_ SEL.1

MAN_ALPHA_ VAL.5

FB_SP_ ADJUST.1

PEAKING_ GAIN.5

LLC_PAD_ SEL.0

MAN_ALPHA_ VAL.4

FB_SP_ ADJUST.0

PEAKING_ GAIN.4

COUNT_MODE 00000000 00

MAN_ALPHA_ VAL.3

CNTR_ ENABLE

MODE.1 PEAKING_

GAIN.3

Reserved Reserved Reserved 00x00011 03

MAN_ALPHA_ VAL.2

FB_EDGE_ SHAPE.2

VS_COAST_ MODE.0

PEAKING_ GAIN.2

MAN_ALPHA_ VAL.1

FB_EDGE_ SHAPE.1

EXTEND_VS_ MIN_FREQ

PEAKING_ GAIN.1

MAN_ALPHA_ VAL.0

FB_EDGE_ SHAPE.0

EXTEND_VS_ MAX_FREQ

PEAKING_ GAIN.0

Reset Value

00000000 00

01001010 4A

00000000 00

01000000 40

(Hex)

Rev. A | Page 83 of 112

ADV7184

Table 105 provides a detailed description of the registers located in the user map.

Table 105. User Map Detailed Description

Bit

Address Register Bit Description 7 6 5 43210Comments Notes

0x00 Input Control

1011CVBS in on AIN7; SCART: G on

1100CVBS in on AIN8; SCART: G on

1101CVBS in on AIN9; SCART: G on

1110CVBS in on AIN10; SCART: G on

0 0 0 0 Autodetect PAL (B/G/H/I/D), NTSC

0 0 0 1 Autodetect PAL (B/G/H/I/D), NTSC M

0010 Autodetect PAL N, NTSC M

0011 Autodetect PAL N, NTSC M (with

0100 NTSC J

0x01 Video Selection

INSEL [3:0]. These bits allow the user to select an input channel and format.

VID_SEL [3:0]. These bits allow the user to select the input video standard.

Reserved. 0 0 0 Set to default

Reserved. 0 Set to default

sets the target value for AGC operation.

Reserved. 1 Set to default

0 0 0 0 CVBS in on AIN1; SCART: G on

0001CVBS in on AIN2; SCART: G on

0010CVBS in on AIN3; SCART: G on

0011CVBS in on AIN4; SCART: G on

0100CVBS in on AIN5; SCART: G on

0101CVBS in on AIN6; SCART: G on

0110Y on AIN1, C on AIN4 0111Y on AIN2, C on AIN5 1000Y on AIN3, C on AIN6 1001Y on AIN1, Pb on AIN4, Pr on AIN5 1 0 1 0 Y on AIN2, Pb on AIN3, Pr on AIN6

1111CVBS in on AIN11; SCART: G on

0101 NTSC M 0110 PAL 60 0 1 1 1 NTSC 4.43 1000 PAL B/G/H/I/D 1 0 0 1 PAL N (B/G/H/I/D without pedestal) 1 0 1 0 PAL M (without pedestal) 1011 PAL M 1100 PAL Combination N 1101 PAL Combination N 1110 SECAM (with pedestal) 1111 SECAM (with pedestal)

0 Disable vsync processor ENVSPROC.

0 Standard video input BETACAM. Enable BETACAM levels. This bit 1 BETACAM input enable 0 Disable hsync processor ENHSPLL.

1 Enable hsync processor

1 Enable vsync processor

AIN6/AIN9, B on AIN4/AIN7, R on AIN5/AIN8

AIN9, B on AIN7, R on AIN8

AIN6, B on AIN4, R on AIN5

AIN6/AIN9, B on AIN4/AIN7, R on AIN5/AIN8

(without pedestal), SECAM

(with pedestal), SECAM

(without pedestal), SECAM

pedestal), SECAM

Composite and SCART RGB (RGB analog input options selectable via RGB_IP_SEL).

S-video.

YPbPr.

Composite and SCART RGB (RGB analog input options selectable via RGB_IP_SEL).

Rev. A | Page 84 of 112

ADV7184

Bit

Address Register Bit Description 7 6 5 43210Comments Notes

0x03 Output Control

0x04 Extended Output

0x07 Autodetect Enable

0x08 Contrast Register CON [7:0]. Contrast adjust. This is the user

0x09 Reserved Reserved. 1 0 0 0 0 0 0 0

Control

SD_DUP_AV. This bit duplicates the AV codes from the luma into the chroma path.

Reserved. 0 Set as default OF_SEL [3:0]. These bits allow the user to

choose from a set of output formats.

allows the user to three-state the output drivers: P [15:0] HS, VS, FIELD, and SFL.

VBI_EN. This bit allows VBI data (Lines 1 to 21) to be passed through with minimum filtering.

range of output values. It can be ITU-R BT.656 compliant or fill the whole accessible number range.

set, this bit enables data in the VBI region to be passed through the decoder undistorted.

Reserved. xx Reserved. 1 BT.656. ITU-R BT.656-4 enable. This bit allows

the user to select an output mode compatible with ITU-R BT.656-3 or ITU-R BT.656-4.

AD_SEC525_EN. SECAM 525 autodetect enable.

control for contrast adjustment.

0 AV codes to suit 8-bit interleaved

1AV codes duplicated for 16-bit

0000 Reserved 0001 Reserved 0010 16-bit format at LLC2 4:2:2 0 0 1 1 8-bit fo rmat at LLC1 4:2:2

0100 Not used 0101 Not used 0110 Not used 0111 Not used 1000 Not used 1001 Not used 1010 Not used 1011 Not used 1100 Not used 1101 Not used 1110 Not used 1111 Not used 0 Output pins enabled TOD. Three-state output drivers. This bit 1 Drivers three-stated

0 All lines filtered and scaled 1 Only active video region filtered 0 16 < Y < 235, 16 < C < 240 ITU-R BT.656. RANGE. This bit allows the user to select the

0 SFL output is disabled EN_SFL_PIN. 1 SFL information output

0 Decode and output color BL_C_VBI. Blank chroma during VBI. When

0 HS, VS, FIELD three-stated TIM_OE. Timing signals output enable. 1 HS, VS, FIELD forced active

0 ITU-R BT.656-3 compatible 1 ITU-R BT.656-4 compatible

0Disable AD_PAL_EN. PAL B/G/I/H autodetect enable.

0 Disable AD_NTSC_EN. NTSC autodetect enable.

0 Disable AD_PALM_EN. PAL M autodetect enable.

0 Disable AD_PALN_EN. PAL N autodetect enable. 1 Enable 0 Disable AD_P60_EN. PAL 60 autodetect enable.

0 Disable AD_N443_EN. NTSC 443 autodetect enable. 1 Enable 0 Disable AD_SECAM_EN. SECAM autodetect enable.

0 Disable 1 Enable 1 0 0 0 0 0 0 0 Luma gain = 1 0x00 gain = 0.

1 Enable

data output

interfaces

ITU-R BT.656

1 1 < Y < 254, 1 < C < 254 Extended range.

on the SFL pin

1 Blank Cr and Cb

1 Enable

USER SUB MAP

The collective name for the subaddress registers in Table 106 is user sub map. To access the user sub map, SUB_USR_EN in Register Address 0x0E (user map) must be programmed to 1.

Table 106. User Sub Map Register Details

Address

Dec Hex Register Name RW 7 6 5 4 3 2 1 0

64 40 Interrupt

Configuration 0

66 42 Interrupt Status 1 R MV_PS_CS_Q SD_FR_

67 43 Interrupt Clear 1 W MV_PS_CS_CLR SD_FR_

68 44 Interrupt Mask 1 RW MV_PS_CS_MSKB SD_FR_CHNG_

69 45 Raw Status 2 R MPU_STIM_INTRQ EVEN_FIE LD CCAPD – –

70 46 Interrupt Status 2 R MPU_STIM_INTRQ _Q SD_FI ELD_

71 47 Interrupt Clear 2 W MPU_STIM_

72 48 Interrupt Mask 2 RW MPU_STIM_

73 49 Raw Status 3 R SCM_LOCK SD_H_LOCK SD_V_LOCK SD_O P_50Hz – –

74 4A In terrupt Status 3 R PAL_SW_LK_

75 4B Interrupt Clear 3 W PAL_SW_LK_

76 4C Interrupt Mask 3 RW PAL_SW_LK_

78 4E Interrupt Status 4 R VDP_VITC_Q VDP_GS_VPS_

79 4F Interrupt Clear 4 W VDP_VITC_CLR VDP_GS_VPS_

80 50 Interrupt Mask 4 RW VDP_VITC_MSKB VDP_GS_VPS_

96 60 VDP_Config_1 RW WST_PKT_

97 61 VDP_Config_2 RW AUTO_DETECT_

98 62 VDP_ADF_

Config_1

99 63 VDP_ADF_

Config_2

100 64 VDP_LINE_00E RW MAN_LINE_PGM VBI_D ATA_

101 65 VDP_LINE_00F RW VBI_DATA_

102 66 VDP_LINE_010 RW VBI_DATA_

103 67 VDP_LINE_011 RW VBI_DATA_

104 68 VDP_LINE_012 RW VBI_DATA_

105 69 VDP_LINE_013 RW VBI_DATA_

106 6A VDP_LINE_014 RW VBI_DATA_

107 6B VDP_LINE_015 RW VBI_DATA_

108 6C VDP_LINE_016 RW VBI_DATA_

109 6D VDP_LINE_017 RW VBI_DATA_

110 6E VDP_LINE_018 RW VBI_DATA_

111 6F VDP_LINE_019 RW VBI_DATA_

112 70 VDP_LINE_01A RW VBI_DATA_

113 71 VDP_LINE_01B RW VBI_DATA_

114 72 VDP_LINE_01C RW VBI_DATA_

115 73 VDP_LINE_01D RW VBI_DATA_

RW INTRQ_DUR_

SEL.1

INTRQ_CLR

INTRQ_MSKB

RW ADF_ENABLE ADF_MODE.1 ADF_MODE.0 ADF_DID.4 ADF_DID.3 ADF_DID.2 ADF_DID.1 ADF_DID.0 00010101 15

RW DUPLICATE ADF ADF_SDID.5 ADF_SDID.4 ADF_SDID.3 ADF_SDID.2 ADF_SDID.1 ADF_SDID.0 0x101010 2A

P6_N23.3

P7_N24.3

P8_N25.3

P9.3

P10.3

P11.3

P12_N10.3

P13_N11.3

P14_N12.3

P15_N13.3

P16_N14.3

P17_N15.3

P18_N16.3

P19_N17.3

P20_N18.3

INTRQ_DUR_ SEL.0

SD_FIELD_

VBI_DATA_P6_ N23.2

VBI_DATA_P7_ N24.2

VBI_DATA_P8_ N25.2

VBI_DATA_P9.2 VBI_DATA_P9.1 VBI_DATA_P9.0 VBI_DATA_

VBI_DATA_P10.2 VBI_DATA_P10.1 VBI_DATA_P10.0 VBI_DATA_P323.3 VBI_DATA_P323.2 VBI_DATA_

VBI_DATA_P11.2 VBI_DATA_P11.1 VBI_DATA_P11.0 VBI_DATA_P324_

VBI_DATA_P12_ N10.2

VBI_DATA_P13_ N11.2

VBI_DATA_P14_ N12.2

VBI_DATA_P15_ N13.2

VBI_DATA_P16_ N14.2

VBI_DATA_P17_ N15.2

VBI_DATA_P18_ N16.2

VBI_DATA_P19_ N17.2

VBI_DATA_P20_ N18.2

MV_INTRQ_ SEL.1

CHNG_Q

CHNG_CLR

MSKB

CHNG_Q

CHNG_CLR

CHNG_MSKB

VBI_DATA_P6_ N23.1

VBI_DATA_P7_ N24.1

VBI_DATA_P8_ N25.1

VBI_DATA_P12_ N10.1

VBI_DATA_P13_ N11.1

VBI_DATA_P14_ N12.1

VBI_DATA_P15_ N13.1

VBI_DATA_P16_ N14.1

VBI_DATA_P17_ N15.1

VBI_DATA_P18_ N16.1

VBI_DATA_P19_ N17.1

VBI_DATA_P20_ N18.1

MV_INTRQ_ SEL.0

SD_UNLOCK_Q SD_LOCK_Q – –

SD_UNLOCK_CLR SD_LOCK_CLR x0000000 00

SD_UNLOCK_

CHNGD_Q

CHNGD_CLR

CHNGD_MSKB

SCM_LOCK_ CHNG_Q

SCM_LOCK_ CHNG_CLR

SCM_LOCK_ CHNG_MSKB

PDC_UTC_ CHNG_Q

PDC_UTC_ CHNG_CLR

PDC_UTC_ CHNG_MSKB

GS_TYPE

VBI_DATA_P6_ N23.0

VBI_DATA_P7_ N24.0

VBI_DATA_P8_ N25.0

VBI_DATA_P12_ N10.0

VBI_DATA_P13_ N11.0

VBI_DATA_P14_ N12.0

VBI_DATA_P15_ N13.0

VBI_DATA_P16_ N14.0

VBI_DATA_P17_ N15.0

VBI_DATA_P18_ N16.0

VBI_DATA_P19_ N17.0

VBI_DATA_P20_ N18.0

MPU_STIM_INTRQ INTRQ_OP_SEL.1 INTRQ_OP_SEL.0 000 1x000 10

MSKB

GEMD_Q CCAPD_Q – –

GEMD_CLR CCAPD_CLR 0xx00000 00

GEMD_MSKB CCAPD_MSKB 0xx00000 00

SD_AD_CHNG_Q SD_H_LOCK_

SD_AD_CHNG_ CLR

SD_AD_CHNG_ MSKB

VDP_

VDP_CGMS_WSS_

DECOD_ DISABLE

0001xx00 10

P318.3

VBI_DATA_P319_ N286.3

VBI_DATA_P320_ N287.3

VBI_DATA_P321_ N288.3

P322.3

N272.3

VBI_DATA_P325_ N273.3

VBI_DATA_P326_ N274.3

VBI_DATA_P327_ N275.3

VBI_DATA_P328_ N276.3

VBI_DATA_P329_ N277.3

VBI_DATA_P330_ N278.3

VBI_DATA_P331_ N279.3

VBI_DATA_P332_ N280.3

VBI_DATA_P333_ N281.3

CHNG_Q

SD_H_LOCK_ CHNG_CLR

SD_H_LOCK_ CHNG_MSKB

CGMS_WSS_ CHNGD_Q

CHNGD_CLR

CHNGD_MSKB

VDP_TTXT_TYPE_ MAN_ENABLE

VBI_DATA_ P318.2

VBI_DATA_P319_ N286.2

VBI_DATA_P320_ N287.2

VBI_DATA_P321_ N288.2

VBI_DATA_P322.2 VBI_DATA_

VBI_DATA_P324_ N272.2

VBI_DATA_P325_ N273.2

VBI_DATA_P326_ N274.2

VBI_DATA_P327_ N275.2

VBI_DATA_P328_ N276.2

VBI_DATA_P329_ N277.2

VBI_DATA_P330_ N278.2

VBI_DATA_P331_ N279.2

VBI_DATA_P332_ N280.2

VBI_DATA_P333_ N281.2

SD_V_LOCK_ CHNG_Q

SD_V_LOCK_ CHNG_CLR

SD_V_LOCK_ CHNG_MSKB

VDP_CCAPD_Q – –

VDP_CCAPD_CLR 00x0x0x0 00

VDP_CCAPD_

VDP_TTXT_TYPE_ MAN.1

VBI_DATA_ P318.1

VBI_DATA_P319_ N286.1

VBI_DATA_P320_ N287.1

VBI_DATA_P321_ N288.1

P322.1

P323.1

VBI_DATA_P324_ N272.1

VBI_DATA_P325_ N273.1

VBI_DATA_P326_ N274.1

VBI_DATA_P327_ N275.1

VBI_DATA_P328_ N276.1

VBI_DATA_P329_ N277.1

VBI_DATA_P330_ N278.1

VBI_DATA_P331_ N279.1

VBI_DATA_P332_ N280.1

VBI_DATA_P333_ N281.1

SD_LOCK_MSKB x0000000 00

SD_OP_CHNG_Q – –

SD_OP_ CHNG_CLR

SD_OP_ CHNG_MSKB

MSKB

VDP_TTXT_ TYPE_MAN.0

VBI_DATA_ P318.0

VBI_DATA_P319_ N286.0

VBI_DATA_P320_ N287.0

VBI_DATA_P321_ N288.0

VBI_DATA_P322.0 00000000 00

VBI_DATA_P323.0 00000000 00

VBI_DATA_P324_ N272.0

VBI_DATA_P325_ N273.0

VBI_DATA_P326_ N274.0

VBI_DATA_P327_ N275.0

VBI_DATA_P328_ N276.0

VBI_DATA_P329_ N277.0

VBI_DATA_P330_ N278.0

VBI_DATA_P331_ N279.0

VBI_DATA_ P332_N280.0

VBI_DATA_ P333_N281.0

Reset Value

(Hex)

xx000000 00

00x0x0x0 00

10001000 88

0xxx0000 00

00000000 00

Rev. A | Page 99 of 112

ADV7184

Address

Dec Hex Register Name RW 7 6 5 4 3 2 1 0

116 74 VDP_LINE_01E RW VBI_DATA_

117 75 VDP_LINE_01F RW VBI_DATA_

118 76 VDP_LINE_020 RW VBI_DATA_

119 77 VDP_LINE_021 RW VBI_DATA_

120 78 VDP_STATUS R TTXT_AVL VITC_AVL GS_DATA_TYPE GS_PDC_VPS_

120 78 VDP_STATUS_

CLEAR

121 79 VDP_CCAP_

DATA_0

122 7A VDP_CCAP_

DATA_1

125 7D CGMS_WSS_

DATA_0

126 7E CGMS_WSS_

DATA_1

127 7F CGMS_WSS_

DATA_2

132 84 VDP_GS_VPS_

PDC_UTC_0

133 85 VDP_GS_VPS_

PDC_UTC_1

134 86 VDP_GS_VPS_

PDC_UTC_2

135 87 VDP_GS_VPS_

PDC_UTC_3

136 88 VDP_VPS_PDC_

UTC_4

137 89 VDP_VPS_PDC_

UTC_5

138 8A VDP_VPS_PDC_

UTC_6

139 8B VDP_VPS_PDC_

UTC_7

140 8C VDP_VPS_PDC_

UTC_8

141 8D VDP_VPS_PDC_

UTC_9

142 8E VDP_VPS_PDC_

UTC_10

143 8F VDP_VPS_PDC_

UTC_11

144 90 VDP_VPS_PDC_

UTC_12

146 92 VDP_VITC_

DATA_0

147 93 VDP_VITC_

DATA_1

148 94 VDP_VITC_

DATA_2

149 95 VDP_VITC_

DATA_3

150 96 VDP_VITC_

DATA_4

151 97 VDP_VITC_

DATA_5

152 98 VDP_VITC_

DATA_6

153 99 VDP_VITC_

DATA_7

154 9A VDP_VITC_

DATA_8

155 9B VDP_VITC_

CALC_CRC

156 9C VDP_

OUTPUT_SEL

P21_N19.3

P22_N20.3

P23_N21.3

P24_N22.3

W VITC_CLEAR GS_PDC_VPS_

R CCAP_BYTE_1.7 CCAP_BYTE_1.6 CCAP_BYTE_1.5 CCAP_BYTE_1.4 CCAP_BYTE_1.3 CCAP_BYTE_1.2 CCAP_BYTE_1.1 CCAP_

R CCAP_BYTE_2.7 CCAP_BYTE_2.6 CCAP_BYTE_2.5 CCAP_BYTE_2.4 CCAP_BYTE_2.3 CCAP_BYTE_2.2 CCAP_BYTE_2.1 CCAP_

R zero zero zero zero CGMS_CRC.5 CGMS_CRC.4 CGMS_CRC.3 CGMS_

R CGMS_CRC.1 CGMS_CRC.0 CGMS_WSS.13 CGMS_WSS.12 CGMS_WSS.11 CGMS_WSS.10 CGMS_WSS.9 CGMS_

R CGMS_WSS.7 CGMS_WSS.6 CGMS_WSS.5 CGMS_WSS.4 CGMS_WSS.3 CGMS_WSS.2 CGMS_WSS.1 CGMS_

R GS_VPS_PDC_

UTC_BYTE_0.7

R GS_VPS_PDC_

UTC_BYTE_1.7

R GS_VPS_PDC_

UTC_BYTE_2.7

R GS_VPS_PDC_

UTC_BYTE_3.7

R VPS_PDC_UTC_

BYTE_4.7

R VPS_PDC_UTC_

BYTE_5.7

R VPS_PDC_UTC_

BYTE_6.7

R VPS_PDC_UTC_

BYTE_7.7

R VPS_PDC_UTC_

BYTE_8.7

R VPS_PDC_UTC_

BYTE_9.7

R VPS_PDC_UTC_

BYTE_10.7

R VPS_PDC_UTC_

BYTE_11.7

R VPS_PDC_UTC_

BYTE_12.7

R VITC_DATA_1.7 VITC_DATA_1.6 VITC_DATA_1.5 VITC_DATA_1.4 VITC_DATA_1.3 VITC_DATA_1.2 VITC_DATA_1.1 VITC_DATA_1.0 – –

R VITC_DATA_2.7 VITC_DATA_2.6 VITC_DATA_2.5 VITC_DATA_2.4 VITC_DATA_2.3 VITC_DATA_2.2 VITC_DATA_2.1 VITC_DATA_2.0 – –

R VITC_DATA_3.7 VITC_DATA_3.6 VITC_DATA_3.5 VITC_DATA_3.4 VITC_DATA_3.3 VITC_DATA_3.2 VITC_DATA_3.1 VITC_DATA_3.0 – –

R VITC_DATA_4.7 VITC_DATA_4.6 VITC_DATA_4.5 VITC_DATA_4.4 VITC_DATA_4.3 VITC_DATA_4.2 VITC_DATA_4.1 VITC_DATA_4.0 – –

R VITC_DATA_5.7 VITC_DATA_5.6 VITC_DATA_5.5 VITC_DATA_5.4 VITC_DATA_5.3 VITC_DATA_5.2 VITC_DATA_5.1 VITC_DATA_5.0 – –

R VITC_DATA_6.7 VITC_DATA_6.6 VITC_DATA_6.5 VITC_DATA_6.4 VITC_DATA_6.3 VITC_DATA_6.2 VITC_DATA_6.1 VITC_DATA_6.0 – –

R VITC_DATA_7.7 VITC_DATA_7.6 VITC_DATA_7.5 VITC_DATA_7.4 VITC_DATA_7.3 VITC_DATA_7.2 VITC_DATA_7.1 VITC_DATA_7.0 – –

R VITC_DATA_8.7 VITC_DATA_8.6 VITC_DATA_8.5 VITC_DATA_8.4 VITC_DATA_8.3 VITC_DATA_8.2 VITC_DATA_8.1 VITC_DATA_8.0 – –

R VITC_DATA_9.7 VITC_DATA_9.6 VITC_DATA_9.5 VITC_DATA_9.4 VITC_DATA_9.3 VITC_DATA_9.2 VITC_DATA_9.1 VITC_DATA_9.0 – –

R VITC_CRC.7 VITC_CRC.6 VITC_CRC.5 VITC_CRC.4 VITC_CRC.3 VITC_CRC.2 VITC_CRC.1 VITC_CRC.0 – –

RW I2C_GS_VPS_

PDC_UTC.1

VBI_DATA_P21_ N19.2

VBI_DATA_P22_ N20.2

VBI_DATA_P23_ N21.2

VBI_DATA_P24_ N22.2

GS_VPS_PDC_ UTC_BYTE_0.6

GS_VPS_PDC_ UTC_BYTE_1.6

GS_VPS_PDC_ UTC_BYTE_2.6

GS_VPS_PDC_ UTC_BYTE_3.6

VPS_PDC_UTC_ BYTE_4.6

VPS_PDC_UTC_ BYTE_5.6

VPS_PDC_UTC_ BYTE_6.6

VPS_PDC_UTC_ BYTE_7.6

VPS_PDC_UTC_ BYTE_8.6

VPS_PDC_UTC_ BYTE_9.6

VPS_PDC_UTC_ BYTE_10.6

VPS_PDC_UTC_ BYTE_11.6

VPS_PDC_UTC_ BYTE_12.6

I2C_GS_VPS_ PDC_UTC.0

VBI_DATA_P21_ N19.1

VBI_DATA_P22_ N20.1

VBI_DATA_P23_ N21.1

VBI_DATA_P24_ N22.1

GS_VPS_PDC_ UTC_BYTE_0.5

GS_VPS_PDC_ UTC_BYTE_1.5

GS_VPS_PDC_ UTC_BYTE_2.5

GS_VPS_PDC_ UTC_BYTE_3.5

VPS_PDC_UTC_ BYTE_4.5

VPS_PDC_UTC_ BYTE_5.5

VPS_PDC_UTC_ BYTE_6.5

VPS_PDC_UTC_ BYTE_7.5

VPS_PDC_UTC_ BYTE_8.5

VPS_PDC_UTC_ BYTE_9.5

VPS_PDC_UTC_ BYTE_10.5

VPS_PDC_UTC_ BYTE_11.5

VPS_PDC_UTC_ BYTE_12.5

GS_VPS_PDC_ UTC_CB_ CHANGE

VBI_DATA_P21_ N19.0

VBI_DATA_P22_ N20.0

VBI_DATA_P23_ N21.0

VBI_DATA_P24_ N22.0

UTC_AVL

UTC_CLEAR

GS_VPS_PDC_ UTC_BYTE_0.4

GS_VPS_PDC_ UTC_BYTE_1.4

GS_VPS_PDC_ UTC_BYTE_2.4

GS_VPS_PDC_ UTC_BYTE_3.4

VPS_PDC_UTC_ BYTE_4.4

VPS_PDC_UTC_ BYTE_5.4

VPS_PDC_UTC_ BYTE_6.4

VPS_PDC_UTC_ BYTE_7.4

VPS_PDC_UTC_ BYTE_8.4

VPS_PDC_UTC_ BYTE_9.4

VPS_PDC_UTC_ BYTE_10.4

VPS_PDC_UTC_ BYTE_11.4

VPS_PDC_UTC_ BYTE_12.4

WSS_CGMS_ CB_CHANGE

VBI_DATA_P334_ N282.3

VBI_DATA_P335_ N283.3

VBI_DATA_P336_ N284.3

VBI_DATA_P337_ N285.3

CGMS_WSS_AVL CC_EVEN _FIELD CC_AVL – –

CGMS_WSS_

GS_VPS_PDC_ UTC_BYTE_0.3

GS_VPS_PDC_ UTC_BYTE_1.3

GS_VPS_PDC_ UTC_BYTE_2.3

GS_VPS_PDC_ UTC_BYTE_3.3

VPS_PDC_UTC_ BYTE_4.3

VPS_PDC_UTC_ BYTE_5.3

VPS_PDC_UTC_ BYTE_6.3

VPS_PDC_UTC_ BYTE_7.3

VPS_PDC_UTC_ BYTE_8.3

VPS_PDC_UTC_ BYTE_9.3

VPS_PDC_UTC_ BYTE_10.3

VPS_PDC_UTC_ BYTE_11.3

VPS_PDC_UTC_ BYTE_12.3

00110000 30

VBI_DATA_P334_ N282.2

VBI_DATA_P335_ N283.2

VBI_DATA_P336_ N284.2

VBI_DATA_P337_ N285.2

CLEAR

GS_VPS_PDC_ UTC_BYTE_0.2

GS_VPS_PDC_ UTC_BYTE_1.2

GS_VPS_PDC_ UTC_BYTE_2.2

GS_VPS_PDC_ UTC_BYTE_3.2

VPS_PDC_UTC_ BYTE_4.2

VPS_PDC_UTC_ BYTE_5.2

VPS_PDC_UTC_ BYTE_6.2

VPS_PDC_UTC_ BYTE_7.2

VPS_PDC_UTC_ BYTE_8.2

VPS_PDC_UTC_ BYTE_9.2

VPS_PDC_UTC_ BYTE_10.2

VPS_PDC_UTC_ BYTE_11.2

VPS_PDC_UTC_ BYTE_12.2

VBI_DATA_P334_ N282.1

VBI_DATA_P335_ N283.1

VBI_DATA_P336_ N284.1

VBI_DATA_P337_ N285.1

CC_CLEAR 00000000 00

GS_VPS_PDC_ UTC_BYTE_0.1

GS_VPS_PDC_ UTC_BYTE_1.1

GS_VPS_PDC_ UTC_BYTE_2.1

GS_VPS_PDC_ UTC_BYTE_3.1

VPS_PDC_UTC_ BYTE_4.1

VPS_PDC_UTC_ BYTE_5.1

VPS_PDC_UTC_ BYTE_6.1

VPS_PDC_UTC_ BYTE_7.1

VPS_PDC_UTC_ BYTE_8.1

VPS_PDC_UTC_ BYTE_9.1

VPS_PDC_UTC_ BYTE_10.1

VPS_PDC_UTC_ BYTE_11.1

VPS_PDC_UTC_ BYTE_12.1

VBI_DATA_ P334_N282.0

VBI_DATA_ P335_N283.0

VBI_DATA_ P336_N284.0

VBI_DATA_ P337_N285.0

BYTE_1.0

BYTE_2.0

CRC.2

WSS.8

WSS.0

GS_VPS_PDC_ UTC_BYTE_0.0

GS_VPS_PDC_ UTC_BYTE_1.0

GS_VPS_PDC_ UTC_BYTE_2.0

GS_VPS_PDC_ UTC_BYTE_3.0

VPS_PDC_ UTC_BYTE_4.0

VPS_PDC_ UTC_BYTE_5.0

VPS_PDC_ UTC_BYTE_6.0

VPS_PDC_ UTC_BYTE_7.0

VPS_PDC_ UTC_BYTE_8.0

VPS_PDC_ UTC_BYTE_9.0

VPS_PDC_ UTC_BYTE_10.0

VPS_PDC_ UTC_BYTE_11.0

VPS_PDC_ UTC_BYTE_12.0

Reset Value

(Hex)

00000000 00

– –

Rev. A | Page 100 of 112

ANALOG DEVICES ADV7184 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

APPLICATIONS

REVISION HISTORY

INTRODUCTION

ANALOG FRONT END

FUNCTIONAL BLOCK DIAGRAM

STANDARD DEFINITION PROCESSOR (SDP)

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VIDEO SPECIFICATIONS

ANALOG SPECIFICATIONS

THERMAL SPECIFICATIONS

TIMING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL PERFORMANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ANALOG FRONT END

ANALOG INPUT MUXING

Recommended Input Muxing

SDM_SEL [1:0], Y/C and CVBS Autodetect Mode Select, Address 0x69 [1:0]

INSEL [3:0], Input Selection, Address 0x00 [3:0]

RGB_IP_SEL, Address 0xF1 [0]

MANUAL INPUT MUXING

ADC_SW_MAN_EN, Manual Input Muxing Enable, Address 0xC4 [7]

ADC0_SW [3:0], ADC0 Mux Configuration, Address 0xC3 [3:0]

ADC1_SW [3:0], ADC1 Mux Configuration, Address 0xC3 [7:4]

ADC2_SW [3:0], ADC2 Mux Configuration, Address 0xC4 [3:0]

ADC3_SW [3:0], ADC3 Mux Configuration, Address 0xF3 [7:4]

XTAL CLOCK INPUT PIN FUNCTIONALITY

XTAL_TTL_SEL, Address 0x13 [2]

28.63636 MHz CRYSTAL OPERATION

EN28XTAL, Address 0x1D [6]

ANTIALIASING FILTERS

AA_FILT_EN [0], Address 0xF3 [0]

AA_FILT_EN [1], Address 0xF3 [1]

AA_FILT_EN [2], Address 0xF3 [2]

AA_FILT_EN [3], Address 0xF3 [3]

SCART AND FAST BLANKING

FAST BLANK CONTROL

FB_MODE [1:0], Address 0xED [1:0]

Static Mux Selection Control

CVBS_RGB_SEL, Address 0xED [2]

System Diagram

Alpha Blend Coefficient

MAN_ALPHA_VAL [6:0], Address 0xEE [6:0]

Fast Blank Edge Shaping

FB_EDGE_SHAPE [2:0], Address 0xEF [2:0]

Contrast Reduction

Contrast Reduction Enable

CNTR_ENABLE, Address 0xEF [3]

Contrast Mode

CNTR_MODE [1:0], Address 0xF1 [3:2]

Fast Blank and Contrast Reduction Programmable Thresholds

FB_LEVEL [1:0], Address 0xF1 [5:4]

CNTR_LEVEL [1:0], Address 0xF1 [7:6]

FB_INV, Address 0xED [3], Write Only

Readback of FB Pin Status

FB_STATUS [3:0], Address 0xED [7:4]

FB Timing

FB_SP_ADJUST [3:0], Address 0xEF [7:4]

Alignment of FB Signal

FB_DELAY [3:0], Address 0xF0 [3:0]

Color Space Converter Manual Adjust

FB_CSC_MAN, Address 0xEE [7]

GLOBAL CONTROL REGISTERS

POWER-SAVING MODES

Power-Down

PDBP, Address 0x0F [2]

PWRDN, Address 0x0F [5]

ADC Power-Down Control

PWRDN_ADC_0, Address 0x3A [3]

PWRDN_ADC_1, Address 0x3A [2]

PWRDN_ADC_2, Address 0x3A [1]