ANALOG DEVICES ADV7184 Service Manual

Multiformat SDTV Video Decoder

FEATURES

Multiformat video decoder supports NTSC (J/M/4.43),

PAL (B/D/G/H/I/M/N), SECAM Integrates four 54 MHz, 10-bit ADCs SCART fast blank support Clocked from a single 28.63636 MHz crystal Line-locked clock-compatible (LLC) Adaptive Digital Line Length Tracking (ADLLT™), signal

processing, and enhanced FIFO management give

mini-TBC functionality 5-line adaptive comb filters Proprietary architecture for locking to weak, noisy, and

unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated automatic gain control (AGC) with adaptive peak

white mode Macrovision® copy protection detection Chroma transient improvement (CTI) Digital noise reduction (DNR) Multiple programmable analog input formats

CVBS (composite video)

Y/C (S-video)

YPrPb (component) (VESA, MII, SMPTE, and BETACAM) 12 analog video input channels Integrated antialiasing filters Programmable interrupt request output pin Automatic NTSC/PAL/SECAM identification

GENERAL DESCRIPTION

with Fast Switch Overlay Support

ADV7184

Digital output formats (8-bit or 16-bit)

ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD

0.5 V to 1.6 V analog signal input range Differential gain: 0.5% typical Differential phase: 0.5° typical Programmable video controls

Peak white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free-run mode (generates stable video output with no input) VBI decode support for close captioning (including Gemstar®

1×/2× (XDS)), WSS, CGMS, teletext, VITC, VPS Power-down mode 2-wire serial MPU interface (I

3.3 V analog, 1.8 V digital core, 3.3 V input/output supply Industrial temperature grade: −40°C to +85°C 80-lead, Pb-free LQFP

APPLICATIONS

High end DVD recorders Video projectors HDD-based PVRs/DVDRs LCD T Vs Set-top boxes Security systems Digital televisions AVR rece ivers

C® compatible)

The ADV7184 integrated video decoder automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC, PAL, and SECAM standards into 4:2:2 component video data compatible with 16- or 8-bit CCIR 601/CCIR 656.

The advanced, highly flexible digital output interface enables performance video decoding and conversion in line-locked, clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security and surveillance cameras, and professional systems.

The accurate 10-bit ADC provides professional quality video performance and is unmatched. This allows true 8-bit resolution in the 8-bit output mode.

The 12 analog input channels accept standard composite, S-video, and component video signals in an extensive number of combinations.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AGC and clamp-restore circuitry allow an input video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively, these can be bypassed for manual settings.

The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise, accurate sampling and digital filtering. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ±5% variation in line length. The output control signals allow glueless interface connections in most applications. The ADV7184 modes are set up over a 2-wire, serial, bidirectional port (I

C compatible).

SCART and overlay functionality are enabled by the ability of the ADV7184 to process CVBS and standard definition RGB signals simultaneously. Signal mixing is controlled by the fast blank pin. The ADV7184 is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. It is packaged in a small, Pb-free, 80-lead LQFP.

ADV7184

TABLE OF CONTENTS

Features.............................................................................................. 1

Global Status Registers .............................................................. 23

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Introduction ...................................................................................... 4

Analog Front End......................................................................... 4

Standard Definition Processor (SDP)........................................ 4

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Electrical Characteristics ............................................................. 5

Video Specifications..................................................................... 6

Analog Specifications................................................................... 6

Thermal Specifications ................................................................ 7

Timing Specifications .................................................................. 7

Timing Diagrams.......................................................................... 8

Absolute Maximum Ratings............................................................ 9

Standard Definition Processor (SDP).......................................... 24

SD Luma Path ............................................................................. 24

SD Chroma Path......................................................................... 24

Sync Processing .......................................................................... 25

VBI Data Recovery..................................................................... 25

General Setup.............................................................................. 25

Color Controls............................................................................ 28

Clamp Operation........................................................................ 30

Luma Filter.................................................................................. 31

Chroma Filter.............................................................................. 34

Gain Operation........................................................................... 35

Chroma Transient Improvement (CTI) .................................. 39

Digital Noise Reduction (DNR) and Luma Peaking Filter... 39

Comb Filters................................................................................ 40

AV Code Insertion and Controls ............................................. 43

Package Thermal Performance................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Analog Front End........................................................................... 12

Analog Input Muxing ................................................................ 13

Manual Input Muxing................................................................ 15

XTAL Clock Input Pin Functionality.......................................16

28.63636 MHz Crystal Operation............................................ 16

Antialiasing Filters .....................................................................16

SCART and Fast Blanking......................................................... 16

Fast Blank Control...................................................................... 17

Global Control Registers ............................................................... 21

Power-Saving Modes.................................................................. 21

Reset Control .............................................................................. 21

Global Pin Control..................................................................... 21

Synchronization Output Signals............................................... 45

Sync Processing .......................................................................... 53

VBI Data Decode ....................................................................... 53

C Interface ................................................................................ 60

Standard Detection and Identification.................................... 62

C Readback Registers.............................................................. 64

Pixel Port Configuration ............................................................... 79

Pixel Port–Related Controls...................................................... 79

MPU Port Description................................................................... 80

C Sequencer.............................................................................. 81

C Programming Examples ..................................................... 81

C Register Maps........................................................................... 82

User Map ..................................................................................... 82

Rev. A | Page 2 of 112

ADV7184

User Sub Map...............................................................................99

Digital Inputs.............................................................................110

PCB Layout Recommendations ................................................. 109

Analog Interface Inputs........................................................... 109

Power Supply Decoupling....................................................... 109

PLL ............................................................................................. 109

Digital Outputs (Both Data and Clocks) .............................. 109

REVISION HISTORY

2/07—Rev. 0 to Rev. A

Corrected Register and Bit Names................................... Universal

Change to Features............................................................................1

Changes to Pin Configuration and

Function Descriptions Section.................................................10

Change to Table 9 ............................................................................14

Change to Table 17 ..........................................................................22

Changes to Table 24 ........................................................................25

Changes to SFL_INV, Address 0x41 [6] Section.........................26

Change to Table 35 ..........................................................................31

Change to Table 40 ..........................................................................36

Change to LAGT [1:0], Luma Automatic Gain Timing,

Address 0x2F [7:6] Section .......................................................36

Change to NVBIOLCM [1:0], NTSC VBI Odd Field Luma

Comb Mode, Address 0xEB [7:6] Section ..............................43

Change to NVBIELCM [1:0], NTSC VBI Even Field Luma

Comb Mode, Address 0xEB [5:4] Section ..............................43

Change to NVBIOCCM [1:0], NTSC VBI Odd Field Chroma

Comb Mode, Address 0xEC [7:6] Section..............................43

Change to NVBIECCM [1:0], NTSC VBI Even Field Chroma

Comb Mode, Address 0xEC [5:4] Section..............................43

Changes to NEWAVMODE, New AV Mode,

Address 0x31 [4] Section...........................................................47

Change to Table 69 ..........................................................................56

Added Standard Detection and Identification Section ..............62

Changes to MPU Port Description Section.................................80

Changes to I

Change to Table 104........................................................................82

Changes to Table 105 ......................................................................84

Change to Table 107......................................................................101

C Programming Examples Section........................81

XTAL and Load Capacitor Values Selection .........................110

Typical Circuit Connection .........................................................111

Outline Dimensions......................................................................112

Ordering Guide.........................................................................112

7/05—Revision 0: Initial Version

Rev. A | Page 3 of 112

ADV7184

INTRODUCTION

The ADV7184 is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-video, and component video into a digital ITU-R BT.656 format.

The advanced, highly flexible digital output interface enables performance video decoding and conversion in line-locked, clockbased systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security and surveillance cameras, and professional systems.

ANALOG FRONT END

The ADV7184 analog front end includes four 10-bit ADCs that digitize the analog video signal before applying it to the standard definition processor (SDP). The analog front end uses differential channels for each ADC to ensure high performance in mixedsignal applications.

The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7184. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7184. The ADCs are configured to run in 4× oversampling mode.

The ADV7184 has optional antialiasing filters on each of the four input channels. The filters are designed for standard definition (SD) video with approximately 6 MHz bandwidth.

SCART and overlay functionality are enabled by the ability of the ADV7184 to process CVBS and standard definition RGB signals simultaneously. Signal mixing is controlled by the fast blank (FB) pin.

FUNCTIONAL BLOCK DIAGRAM

AIN1 TO

AIN12

SCLK

SDA

ALSB

INPUT

MUX

CVBS, S-VIDEO ,

YPrPb, OR

SCART (RGB AND CVBS)

SYNC PROCESSI NG AND

CLOCK GENERAT ION

CONTROL AND V BI DATA

ANTI-

ALIAS

CLAMP

FILTER

ANTI-

ALIAS

CLAMP

FILTER

ANTI-

ALIAS

CLAMP

FILTER

ANTI-

ALIAS

CLAMP

FILTER

SERIAL INT ERFACE

A/D

SYNC AND

CLK CONTROL

ADV7184

DATA

PREPROCESSO R

DECIMATIO N AND

DOWNSAMPL ING

FILTERS

CONTROL

AND DATA

CVBS

C Cr Cb R G

COLOR SPACE

CONVERSION

VBI DATA RECOVERY

CVBS/Y

RECOVERY

MACROVISIO N

DETECTIO N

Figure 1.

STANDARD DEFINITION PROCESSOR (SDP)

The ADV7184 is capable of decoding a large selection of baseband video signals in composite, S-video, and component formats. The video standards that are supported include PAL B/D/I/G/H, PAL 60, PA L M, PAL N , PAL Nc, N T S C M/J, NT S C 4.43 , a nd SECAM B/D/G/K/L. The ADV7184 can automatically detect the video standard and process it accordingly.

The ADV7184 has a 5-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7184.

The ADV7184 implements the patented ADLLT algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7184 to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs, VCD players, and camcorders. The ADV7184 contains a CTI processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions.

The ADV7184 can process a variety of VBI data services, such as closed captioning (CC), wide-screen signaling (WSS), copy generation management system (CGMS), Gemstar® 1×/2×, extended data service (XDS), and teletext. The ADV7184 is fully Macrovision certified; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs.

STANDARD DEFINI TION PRO CESSOR

LUMA

2D COMB (5H MAX)

CHROMA 2D COMB

(4H MAX)

SYNTHESIZED LLC CONT ROL

FREE-RUN

OUTPUT CO NTROL

FAST

BLANK OVERLAY CONTROL

AND

AV CODE

INSERTION

CHROMA

DEMOD

LUMA

FILTER

SYNC

EXTRACT

CHROMA

FILTER

GLOBAL CO NTROL

STANDARD

AUTODETECTION

LUMA

RESAMPLE

CONTROL

CHROMA

RESAMPLE

Y Cr Cb

PIXEL DATA

P15 TO P P7 TO P0

FIELD

LLC1

OUTPUT FO RMATTER

LLC2

SFL

INT

05479-001

Rev. A | Page 4 of 112

ADV7184

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

= 3.15 V to 3.45 V, D

VDD

Operating temperature range, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions Min Typ Max Unit

STATIC PERFORMANCE

Resolution (Each ADC) N 10 Bits Integral Nonlinearity INL BSL at 54 MHz −0.6/+0.7 ±3 LSB Differential Nonlinearity DNL BSL at 54 MHz −0.5/+0.5 −0.99/+2.5 LSB

DIGITAL INPUTS

Input High Voltage Input Low Voltage Input Current

6, 7

−10 +10 μA Input Capacitance

DIGITAL OUTPUTS

Output High Voltage Output Low Voltage High Impedance Leakage Current I Output Capacitance

POWER REQUIREMENTS

Digital Core Power Supply D Digital Input/Output Power Supply D PLL Power Supply P Analog Power Supply A Digital Core Supply Current I Digital Input/Output Supply Current I PLL Supply Current I Analog Supply Current I YPrPb input Power-Down Current I Power-Up Time t

All ADC linearity tests performed with the input range at full scale − 12.5% and at zero scale + 12.5%.

Maximum INL and DNL specifications obtained with the part configured for component video input.

Temperature range T

To obtain specified VIH level on Pin 29, Register 0x13 (write only) must be programmed with Value 0x04. If Register 0x13 is programmed with Value 0x00, then V

To obtain specified VIL level on Pin 29, Register 0x13 (write only) must be programmed with Value 0x04. If Register 0x13 is programmed with Value 0x00, then V

Pins 36 and 79.

Excluding all TEST pins (TEST0 to TEST12)

VOH and VOL levels obtained using default drive strength value (0xD5) in Register 0xF4.

Guaranteed by characterization.

Only ADC0 is powered on.

All four ADCs powered on.

to T

MIN

= 1.65 V to 2.0 V, D

VDD

1, 2, 3

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V, nominal input range 1.6 V.

VDD

VIH 2 V VIL 0.8 V IIN −50 +50 μA

CIN 10 pF

, −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.

MAX

VOH I VOL I

10 μA

LEAK

20 pF

OUT

= 0.4 mA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

1.65 1.8 2 V

VDD

3.0 3.3 3.6 V

VDDIO

1.71 1.8 1.89 V

VDD

3.15 3.3 3.45 V

VDD

105 mA

DVDD

4 mA

DVDDIO

11 mA

PVDD

CVBS input

AVDD

0.65 mA

PWRDN

20 ms

PWRUP

99 mA 269 mA

on Pin 29 is 1.2 V.

on Pin 29 is 0.4 V.

Rev. A | Page 5 of 112

ADV7184

VIDEO SPECIFICATIONS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise noted).

Table 2.

Parameter

1, 2

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulate five steps 0.5 0.7 Degree Differential Gain DG CVBS input, modulate five steps 0.5 0.7 % Luma Nonlinearity LNL CVBS input, five steps 0.5 0.7 %

NOISE SPECIFICATIONS

SNR Unweighted Luma ramp 54 56 dB Luma flat field 56 58 dB Analog Front End Crosstalk 60 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range −5 +5 % Vertical Lock Range 40 70 Hz FSC Subcarrier Lock Range ±1.3 Hz Color Lock-In Time 60 Lines Sync Depth Range

Color Burst Range 5 200 % Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines

CHROMA SPECIFICATIONS

Hue Accuracy HUE 1 Degree Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.5 % Chroma Phase Error 0.4 Degree Chroma Luma Intermodulation 0.2 %

LUMA SPECIFICATIONS

Luma Brightness Accuracy CVBS, 1 V input 1 % Luma Contrast Accuracy CVBS, 1 V input 1 %

Temperature range T

Guaranteed by characterization.

Nominal sync depth is 300 mV at 100% sync depth range.

to T

MIN

MAX

ANALOG SPECIFICATIONS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise noted). Recommended analog input video signal range is 0.5 V to 1.6 V, typically 1 V p-p.

Table 3.

Parameter

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF Input Impedance Input Impedance of Pin 40 (FB) 20 kΩ Large-Clamp Source Current 0.75 mA Large-Clamp Sink Current 0.75 mA Fine-Clamp Source Current 17 μA Fine-Clamp Sink Current 17 μA

Temperature range T

Guaranteed by characterization.

Except Pin 40 (FB).

1, 2

to T

MIN

MAX

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

Symbol Test Conditions Min Typ Max Unit

20 200 %

is −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

Symbol Test Condition Min Typ Max Unit

Clamps switched off 10 MΩ

is −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.

Rev. A | Page 6 of 112

ADV7184

THERMAL SPECIFICATIONS

Table 4.

Parameter Symbol Test Conditions Min Typ Max Unit

Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane 7.6 °C/W Junction-to-Ambient Thermal Resistance (Still Air) θJA 4-layer PCB with solid ground plane 38.1 °C/W

TIMING SPECIFICATIONS

= 3.15 V to 3.45 V, D

VDD

otherwise noted).

Table 5.

Parameter

1, 2

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency 28.63636 MHz Frequency Stability ±50 ppm

I2C PORT

SCLK Frequency 400 kHz SCLK Minimum Pulse Width High t1 0.6 μs SCLK Minimum Pulse Width Low t2 1.3 μs Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 μs

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC1 Mark-Space Ratio t9:t10 45:55 55:45 % duty cycle LLC1 Rising to LLC2 Rising t11 1 ns LLC1 Rising to LLC2 Falling t12 1 ns

DATA AND CONTROL OUTPUTS

Data Output Transitional Time

Propagation Delay to High-Z t15 6 ns Max Output Enable Access Time t16 7 ns Min Output Enable Access Time t17 4 ns

Temperature range T

Guaranteed by characterization.

TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.

SDP timing figures obtained using default drive strength value (0xD5) in Register 0xF4.

to T

MIN

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.71 V to 1.89 V (operating temperature range, unless

VDD

Symbol Test Conditions Min Typ Max Unit

t13

t14

is −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.

MAX

Negative clock edge to start of valid data

= t10 − t13)

ACCESS

End of valid data to negative clock edge (t

= t9 + t14)

HOLD

3.6 ns

2.4 ns

Rev. A | Page 7 of 112

ADV7184

TIMING DIAGRAMS

05479-002

SDA

SCLK

Figure 2. I

C Timing

OUTPUT LLC1

OUTPUT LLC2

OUTPUTS P0 TO P15, VS,

HS, FIEL D,

SFL

Figure 3. Pixel Port and Control Output Timing

05479-003

05479-004

P0 TO P15, HS,

VS, FIELD,

SFL

Figure 4.

Timing

Rev. A | Page 8 of 112

ADV7184

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

to AGND 4 V

VDD

to DGND 2.2 V

VDD

to AGND 2.2 V

VDD

to DGND 4 V

VDDIO

to A

VDDIO

to D

VDD

VDDIO

to P

VDD

to D

VDD

Digital Inputs Voltage to DGND −0.3 V to D Digital Output Voltage to DGND −0.3 V to D Analog Inputs to AGND AGND − 0.3 V to A Maximum Junction Temperature

J max

−0.3 V to +0.3 V

VDD

−0.3 V to +0.3 V

VDD

to P

−0.3 V to +2 V

VDD

to D

−0.3 V to +2 V

VDD

−0.3 V to +2 V

VDD

−0.3 V to +2 V

VDD

125°C

)

VDDIO

+ 0.3 V + 0.3 V

VDD

+ 0.3 V

Storage Temperature Range −65°C to +150°C Infrared Reflow Soldering (20 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption the user is advised to turn off any unused ADCs when using the part.

The junction temperature must always stay below the maximum junction temperature (T following equation to calculate the junction temperature:

= T

+ (θJA × W

A max

max

where:

= 85°C.

A max

= 30°C/W.

W (P

max

VDD

= ((A

× I

PVDD

VDD

)).

× I

AV D D

) + (D

VDD

max) of 125°C. Use the

)

× I

) + (D

DVDD

VDDIO

× I

DVDDIO

) +

ESD CAUTION

Rev. A | Page 9 of 112

ADV7184

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FIELD79OE78TEST177TEST676P1275P1374P1473P1572DVDD71DGND70TEST069TEST468SCLK67SDA66ALSB65TEST764RESET63SOY62AIN661AIN12

DGND

DVDDIO

P11

P10

DGND

DVDD

INT

SFL

TEST2

DGND

DVDDIO

TEST8

TEST12

TEST11

PIN 1

21P522P423P324P225

ADV7184

TOP VIEW

(Not to Scale)

32P133P034

LLC227LLC1

XTAL

DVDD

TEST3

XTAL1

DGND

TEST9

TEST10

Figure 5. 80-Lead LQFP Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type Description

3, 9, 14, 31, 71 DGND G Digital Ground. 39, 47, 53, 56 AGND G Analog Ground. 4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V). 10, 30, 72 DVDD P Digital Core Supply Voltage (1.8 V). 50 AVDD P Analog Supply Voltage (3.3 V). 38 PVDD P PLL Supply Voltage (1.8 V). 42, 44, 46, 58,

60, 62, 41, 43,

AIN1 to AIN12

I Analog Video Input Channels.

45, 57, 59, 61 11

INT

Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video. See the User Sub Map register details in

40 FB I

Fast Blank. FB is a fast switch overlay input that switches between CVBS and RGB analog input signals.

70, 78, 13, 25, 69, 35, 34, 18, 17

TEST0 to TEST4,

Leave these pins unconnected.

TEST9 to TEST12

77, 65

TEST6,

Tie to AGND.

TEST7 16 TEST8 Tie to DVDDIO. 33, 32, 24 to 19,

P0 to P15 O Video Pixel Output Ports. 8 to 5, 76 to 73

2 HS O Horizontal Synchronization Output Signal. 1 VS O Vertical Synchronization Output Signal. 80 FIELD O Field Synchronization Output Signal.

PWRDN

ELPF

PVDD

AGND

Table 107.

AIN5

AIN11

AIN4

AIN10

AGND

CAPC2

CAPC1

AGND

CML

REFOUT

AVDD

CAPY2

CAPY1

AGND

AIN3

AIN9

AIN2

AIN8

AIN1

AIN7

05479-005

Rev. A | Page 10 of 112

ADV7184

Mnemonic Type Description Pin No.

67 SDA I/O I2C Port Serial Data Input/Output. 68 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. 66 ALSB I

27 LLC1 O

26 LLC2 O

29 XTAL I

28 XTAL1 O

37 ELPF I The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 52. 12 SFL O

63 SOY I

51 REFOUT O

52 CML O

48, 49

54, 55

RESET

PWRDN

CAPY1, CAPY2

CAPC1, CAPC2

I ADC Capacitor Network. Refer to Figure 52 for a recommended capacitor network for this pin.

I ADC Capacitor Network. Refer to

This pin selects the I a write to 0x40; set to Logic 1 sets the address to 0x42.

System Reset Input (active low). A minimum low reset pulse width of 5 ms is required to reset the ADV7184 circuitry.

Line-Locked Clock 1. This is a line-locked output clock for the pixel data output by the ADV7184. Nominally 27 MHz, but varies according to video line length.

Line-Locked Clock 2. This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7184. Nominally 13.5 MHz, but varies according to video line length.

Crystal Input. This is the input pin for the 28.63636 MHz crystal, or it can be overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external

3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7184. In crystal mode, the crystal must be a fundamental crystal.

Logic 0 on this pin places the ADV7184 in a power-down mode. Refer to the section for more options on power-down modes for the ADV7184.

When set to Logic 0, OE pin places P15 to P0, HS, VS, and SFL into a high impedance state.

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc., digital video encoder.

SYNC on Y. This input pin should only be used with the standard detection and identification function (see the signal of a component input for standard identification function.

Internal Voltage Reference Output. Refer to this pin.

Common-Mode Level. The CML pin is a common-mode level for the internal ADCs. Refer to Figure 52 for a recommended capacitor network for this pin.

Standard Detection and Identification section). This pin should be connected to the Y

C address for the ADV7184. ALSB set to Logic 0 sets the address for

I2C Register Maps

OE enables the pixel output bus, P15 to P0 of the ADV7184. Logic 1 on the

Figure 52 for a recommended capacitor network for

Figure 52 for a recommended capacitor network for this pin.

Rev. A | Page 11 of 112

ADV7184

ANALOG FRONT END

RGB_IP_SEL

INSEL[3:0]

AIN1

AIN7

AIN2

AIN8

AIN3

AIN9

AIN4

AIN10

AIN5

AIN11

AIN6

AIN12

ADC_SW_MAN_EN

AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12

PRIM_MODE[3:0]

SDM_SEL[1:0]

ADC0_SW[3:0]

ADC0

INTERNAL

MAPPING

FUNCTIONS

AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12

AIN2 AIN8 AIN5 AIN11 AIN6 AIN12 AIN4

AIN4

AIN7

Figure 6. Internal Pin Connections

ADC1_SW[3:0]

ADC2_SW[3:0]

ADC3_SW[3:0]

ADC1

ADC2

ADC3

5479-006

Rev. A | Page 12 of 112

ADV7184

ANALOG INPUT MUXING

The ADV7184 has an integrated analog muxing section that allows connecting more than one source of video signal to the decoder. muxing provided in the ADV7184.

As can be seen in controlled in two ways:

• By the functional register (INSEL). Using INSEL [3:0]

• By an I

Figure 7 shows an overview of the two methods of controlling input muxing.

Figure 6 outlines the overall structure of the input

Figure 6, the analog input muxes can be

simplifies the setup of the muxes and minimizes crosstalk between channels by preassigning the input channels. This is referred to as the recommended input muxing.

C manual override (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW, and ADC3_SW). This is provided for applications with special requirements, such as number/combinations of signals that are not served by the preassigned input connections. This is referred to as manual input muxing.

CONNECTING

ANALOG SIG NALS

TO ADV7184

Recommended Input Muxing

A maximum of 12 CVBS inputs can be connected and decoded by the ADV7184, meaning that the sources must be connected to adjacent pins on the IC, as seen in

Figure 5. This calls for a careful design of the PCB layout, for example, placing ground shielding between all signals routed through tracks that are physically close together.

SDM_SEL [1:0], Y/C and CVBS Autodetect Mode Select, Address 0x69 [1:0]

The SDM_SEL bits decide on input routing and whether INSEL [3:0] is used to govern input routing decisions.

The S-video/composite autodetection feature is enabled using SDM_SEL = 11.

Table 8. SDM_SEL [1:0]

SDM_SEL [1:0] Mode Analog Video Inputs

00 As per INSEL [3:0] As per INSEL [3:0] 01 CVBS AIN11 10 Y/C

Y = AIN10 C = AIN12

S-video/composite autodetection

CVBS = AIN11 Y = AIN11 C = AIN12

SEE TABLE 8 AND T ABLE 9?

YES

SET SDM_SEL[1:0] AND

INSEL[3: 0]

FOR REQUIRED MUXING

CONFIGURATION

Figure 7. Input Muxing Overview

RECOMMENDED

INPUT MUXING;

(ADC_SW_MAN_EN, ADC0_S W,

SET SDM_SEL[1:0] AND

INSEL[3:0] TO CONF IGURE

ADV7184 TO DECO DE

VIDEO FO RMAT:

CVBS: 0000

YC: 0110

YPrPb: 1001

SCART (CVBS/RG B): 1111

SET SDM_SEL[1:0] FO R

S-VIDEO/COMPOSITE

AUTODETECT

USE MANUAL INPUT MUXING

ADC1_SW, ADC2_SW,

ADC3_SW)

05479-007

Rev. A | Page 13 of 112

ADV7184

INSEL [3:0], Input Selection, Address 0x00 [3:0]

The INSEL bits allow the user to select the input channel and format. Depending on the PCB connections, only a subset of the INSEL modes is valid. INSEL [3:0] not only switches the analog input muxing, but also configures ADV7184 to process composite (CVBS), S-video (Y/C), or component (YPbPr/RGB) format signals.

The recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity.

Tabl e 10 summarizes how the PCB

layout should connect analog video signals to the ADV7184.

It is strongly recommended that users connect any unused analog input pins to AGND to act as a shield.

Connect the AIN7 to AIN11 inputs to AGND when only six input channels are used. This improves the quality of the sampling due to better isolation between the channels.

AIN12 is not controlled by INSEL [3:0]. It can be routed to ADC0/ADC1/ADC2 only by manual muxing. See

Tabl e 11

for details.

Table 9. Input Channel Switching Using INSEL [3:0]

INSEL [3:0]

0000 (default)

Analog Input Pins Video Format

CVBS1 = AIN1 B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

0001 CVBS2 = AIN2

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

0010 CVBS3 = AIN3

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

0011 CVBS4 = AIN4

Description

SCART (CVBS and R, G, B)

SCART (CVBS and R, G, B) B = AIN7 R = AIN8 G = AIN9

0100 CVBS1 = AIN5

SCART (CVBS and R, G, B) B = AIN7 R = AIN8 G = AIN9

0101 CVBS1 = AIN6

SCART (CVBS and R, G, B) B = AIN7 R = AIN8 G = AIN9

0110 Y1 = AIN1

Y/C C1 = AIN4

0111 Y2 = AIN2

Y/C C2 = AIN5

1000 Y3 = AIN3

Y/C C3 = AIN6

1001 Y1 = AIN1

YPrPb PB1 = AIN4 PR1 = AIN5

1010 Y2 = AIN2

YPrPb PB2 = AIN3 PR2 = AIN6

1011 CVBS7 = AIN7

SCART (CVBS and R, G, B) B = AIN4 R = AIN5 G = AIN6

1100 CVBS8 = AIN8

SCART (CVBS and R, G, B) B = AIN4 R = AIN5 G = AIN6

1101 CVBS9 = AIN9

SCART (CVBS and R, G, B) B = AIN4 R = AIN5 G = AIN6

1110 CVBS10 = AIN10

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

1111 CVBS11 = AIN11

B = AIN4 or AIN7 R = AIN5 or AIN8 G = AIN6 or AIN9

Selectable via RGB_IP_SEL.

SCART (CVBS and R, G, B)

Rev. A | Page 14 of 112

ADV7184

Table 10. Input Channel Assignments

Input Channel Pin No. Recommended Input Muxing Control—INSEL [3:0]

AIN7 41 CVBS7 SCART1-B AIN1 42 CVBS1 YC1-Y YPrPb1-Y SCART2-CVBS AIN8 43 CVBS8 SCART1-R AIN2 44 CVBS2 YC2-Y YPrPb2-Y AIN9 45 CVBS9 SCART1-G AIN3 46 CVBS3 YC3-Y YPrPb2-Pb AIN10 57 CVBS10 AIN4 58 CVBS4 YC1-C YPrPb1-Pb SCART2-B AIN11 59 CVBS11 SCART1-CVBS AIN5 60 CVBS5 YC2-C YPrPb1-Pr SCART2-R AIN12 61 Not available AIN6 62 CVBS6 YC3-C YPrPb2-Pr SCART2-G

Table 11. Manual Mux Settings for All ADCs (Set ADC_SW_MAN_EN to 1)

ADC0

ADC0_SW [3:0]

0000 No connection 0000 No connection 0000 No connection 0000 No connection 0001 AIN1 0001 No connection 0001 No connection 0001 No connection 0010 AIN2 0010 No connection 0010 AIN2 0010 No connection 0011 AIN3 0011 AIN3 0011 No connection 0011 No connection 0100 AIN4 0100 AIN4 0100 No connection 0100 AIN4 0101 AIN5 0101 AIN5 0101 AIN5 0101 No connection 0110 AIN6 0110 AIN6 0110 AIN6 0110 No connection 0111 No connection 0111 No connection 0111 No connection 0111 No connection 1000 No connection 1000 No connection 1000 No connection 1000 No connection 1001 AIN7 1001 No connection 1001 No connection 1001 AIN7 1010 AIN8 1010 No connection 1010 AIN8 1010 No connection 1011 AIN9 1011 AIN9 1011 No connection 1011 No connection 1100 AIN10 1100 AIN10 1100 No connection 1100 No connection 1101 AIN11 1101 AIN11 1101 AIN11 1101 No connection 1110 AIN12 1110 AIN12 1110 AIN12 1110 No connection 1111 No connection 1111 No connection 1111 No connection 1111 No connection

Conne cted To

ADC1_SW [3:0]

RGB_IP_SEL, Address 0xF1 [0]

For SCART input, R, G, and B signals can be input either on AIN4, AIN5, and AIN6 or on AIN7, AIN8, and AIN9.

0 (default)—B is input on AIN4, R is input on AIN5, and G is input on AIN6.

1—B is input on AIN7, R is input on AIN8, and G is input on AIN9.

ADC1 Conne cted To

ADC2_SW [3:0]

ADC2 Conne cted To

ADC3_SW [3:0]

ADC3 Connected To

Therefore, if the settings of INSEL and the manual input muxing bits (ADC0_SW/ADC1_SW/ADC2_SW/ADC3_SW) contradict each other, the ADC0_SW/ADC1_SW/ADC2_SW/ ADC3_SW settings apply and INSEL is ignored.

Manual input muxing controls only the analog input muxes. For the follow-on blocks to process video data in the correct format, however, INSEL must still be used to indicate whether the input signal is of YPbPr, Y/C, or CVBS format.

MANUAL INPUT MUXING

By accessing a set of manual override muxing registers, the analog input muxes of the ADV7184 can be controlled directly. This is referred to as manual input muxing. Manual input muxing overrides other input muxing control bits, including INSEL.

Manual muxing is activated by setting the ADC_SW_MAN_EN bit. It only affects the analog switches in front of the ADCs.

Rev. A | Page 15 of 112

Restrictions in the channel routing are imposed by the analog signal routing inside the IC; each input pin cannot be routed to each ADC. Refer to

Figure 6 for an overview on the routing capabilities inside the chip. The four mux sections can be controlled by the reserved control signal buses, ADC0_SW [3:0], ADC1_SW [3:0], ADC2_SW [3:0], and ADC3_SW [3:0].

Tabl e 1 1 explains the

control words used.

ADV7184

ADC_SW_MAN_EN, Manual Input Muxing Enable, Address 0xC4 [7]

ADC0_SW [3:0], ADC0 Mux Configuration, Address 0xC3 [3:0]

ADC1_SW [3:0], ADC1 Mux Configuration, Address 0xC3 [7:4]

ADC2_SW [3:0], ADC2 Mux Configuration, Address 0xC4 [3:0]

ADC3_SW [3:0], ADC3 Mux Configuration, Address 0xF3 [7:4]

See Tab le 1 1.

XTAL CLOCK INPUT PIN FUNCTIONALITY

XTAL_TTL_SEL, Address 0x13 [2]

The crystal pad is normally part of the crystal oscillator circuit, powered from a 1.8 V supply. For optimal clock generation, the slice level of the input buffer of this circuit is at approximately half the supply voltage, making it incompatible with TLL level signals.

0 (default)—A crystal is used to generate the ADV7184 clock.

1—An external TTL level clock is supplied. A different input buffer can be selected that slices at TTL-compatible levels. This inhibits operation of the crystal oscillator and therefore can only be used when a clock signal is applied.

28.63636 MHz CRYSTAL OPERATION

EN28XTAL, Address 0x1D [6]

The ADV7184 can operate on two different base crystal frequencies. Selecting one over the other may be desirable in systems in which board crosstalk between different components leads to undesirable interference between video signals. It is recommended to use a crystal of frequency 28.63636 MHz to clock the ADV7184.

0 (default)—The crystal frequency is 27 MHz.

1—The crystal frequency is 28.63636 MHz.

ANTIALIASING FILTERS

The ADV7184 has optional antialiasing filters on each of the four input channels. The filters are designed for SD video with approximately 6 MHz bandwidth.

A plot of the filter response is shown in

can be individually enabled via I

C under the control of

AA_FILT_EN [3:0].

AA_FILT_EN [0], Address 0xF3 [0]

0 (default)—The filter on Channel 0 is disabled.

1—The filter on Channel 0 is enabled.

Figure 8. The filters

AA_FILT_EN [1], Address 0xF3 [1]

0 (default)—The filter on Channel 1 is disabled.

1—The filter on Channel 1 is enabled.

AA_FILT_EN [2], Address 0xF3 [2]

0 (default)—The filter on Channel 2 is disabled.

1—The filter on Channel 2 is enabled.

AA_FILT_EN [3], Address 0xF3 [3]

0 (default)—The filter on Channel 3 is disabled.

1—The filter on Channel 3 is enabled.

RESPONSE OF AA FILT ER WITH CALIBRATED CAPACI TORS

0 –2 –4 –6 –8

–10 –12 –14 –16 –18 –20 –22 –24 –26 –28 –30 –32 –34

ATTENUATIO N (dB)

–36 –38 –40 –42 –44 –46 –48 –50 –52

1M 1G

Figure 8. Frequency Response of Internal ADV7184 Antialiasing Filters

10M 100M

FREQUENCY (Hz)

05479-008

SCART AND FAST BLANKING

The ADV7184 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality.

This function is available when INSEL [3:0] is set appropriately

Tabl e 9). Timing extraction is always performed by the

(see ADV7184 on the CVBS signal. However, a combination of the CVBS and RGB inputs can be mixed and output under the control of the I

Four basic modes are supported:

• Static Switch Mode. The FB pin is not used. The timing is

extracted from the CVBS signal, and either the CVBS content or RGB content can be output under the control of CVBS_RGB_SEL. This mode allows the selection of a fullscreen picture from either source. Overlay is not possible in static switch mode.

• Fixed Alpha Blending. The FB pin is not used. The timing

is extracted from the CVBS signal, and an alpha blended combination of the video from the CVBS and RGB sources is output. This alpha blending is applied to the full screen.

C registers and the FB pin.

Rev. A | Page 16 of 112

ADV7184

The alpha blend factor is selected with the I2C signal MAN_ALPHA_VAL [6:0]. Overlay is not possible in fixed alpha blending mode.

• Dynamic Switching (Fast Mux). The FB pin can be used to

select the source. This enables dynamic multiplexing between the CVBS and RGB sources. With default settings, when Logic 1 is applied to the FB pin, the RGB source is selected; when Logic 0 is applied to the FB pin, the CVBS source is selected. This mode is suitable for the overlay of subtitles, teletext, or other material. Typically, the CVBS source carries the main picture, and the RGB source has the overlay data.

• Dynamic Switching with Edge Enhancement. This provides

the same functionality as the dynamic switching mode, but with the benefit of Analog Devices proprietary edgeenhancement algorithms, which improve the visual appearance of transitions for signals from a wide variety of sources.

The switched or blended data is output from the ADV7184 in the standard output formats (see

Table 102).

FAST BLANK CONTROL

FB_MODE [1:0], Address 0xED [1:0]

FB_MODE controls which fast blank mode is selected.

Table 12. FB_MODE [1:0] Function

FB_MODE [1:0] Description

00 (default) Static switch mode 01 Fixed alpha blending 10 Dynamic switching (fast mux) 11 Dynamic switching with edge enhancement

Static Mux Selection Control

CVBS_RGB_SEL, Address 0xED [2]

CVBS_RGB_SEL controls whether the video from the CVBS or RGB source is selected for output from the ADV7184.

System Diagram

A block diagram of the ADV7184 fast blanking configuration is shown in

Figure 9.

The CVBS signal is processed by the ADV7184 and converted to YPrPb. The RGB signals are processed by a color space converter (CSC), and samples are converted to YPrPb. Both sets of YPrPb signals are input to the subpixel blender, which can be configured to operate in any of the four modes previously outlined in this section.

The fast blank position resolver determines the time position of the FB pin accurately (<1 ns). This position information is then used by the subpixel blender in dynamic switching modes, enabling the ADV7184 to implement high performance multiplexing between the CVBS and RGB sources even when the RGB data source is completely asynchronous to the sampling crystal reference.

An antialiasing filter is required on all four data channels (R, G, B, and CVBS). The order of this filter is reduced because all signals are sampled at 54 MHz.

0 (default)—Data from the CVBS source is selected for output.

1—Data from the RGB source is selected for output.

Alpha Blend Coefficient

MAN_ALPHA_VAL [6:0], Address 0xEE [6:0]

When fixed alpha blending is selected (FB_MODE [1:0] = 01), MAN_ALPHA_VAL [6:0] determines the proportion in which the video from the CVBS and RGB sources are blended. Equation 1 shows how these bits affect the video output.

]06[__

:VALALPHAMAN

out

Video

RGB

⎛ ⎜

CVBS

−×=

⎜ ⎝

]06[__

:VALALPHAMAN

VideoVideo

×+

⎞ ⎟

⎟ ⎠

(1)

The maximum valid value for MAN_ALPHA_VAL [6:0] is 1000000, such that the alpha blender coefficients remain between 0 and 1. The default value for MAN_ALPHA_VAL [6:0] is 0000000.

Rev. A | Page 17 of 112

ADV7184

FAST BLANK

(FB PIN)

FAST BLANK

POSITION

RESOLVER

CONTROL

CVBS

ADC0

CONDITIONING

CLAMPI NG AND

ADC1

ADC2

ADC3

SIGNAL

DECIMAT ION

TIMING

EXTRACTION

SIGNAL CONDITIO NING CLAMPING AND

DECIMATION

Figure 9. Fast Blanking Configuration

Fast Blank Edge Shaping

FB_EDGE_SHAPE [2:0], Address 0xEF [2:0]

To improve the picture transition for high speed fast blank switching, an edge-shaping mode is available on the ADV7184. Depending on the format of the RGB inputs, it may be advantageous to apply different levels of edge shaping. The levels are selected via the FB_EDGE_SHAPE [2:0] bits. Users are advised to try each of the settings and select the setting that is most visually pleasing on their system.

Table 13. FB_EDGE_SHAPE [2:0] Function

FB_EDGE_SHAPE [2:0] Description

000 No edge shaping 001 Level 1 edge shaping 010 (default) Level 2 edge shaping 011 Level 3 edge shaping 100 Level 4 edge shaping 101 to 111 Not valid

Contrast Reduction

For overlay applications, text can be more readable if the contrast of the video directly behind the text is reduced. To enable the definition of a window of reduced contrast behind inserted text, the signal applied to the FB pin can be interpreted as a trilevel signal, as shown in

Figure 10.

VIDEO

PROCESSING

RGB

≥

YPrPb

CONVERSION

RGB SOURCE

100%

CVBS SOURCE

50% CONTRAST

CVBS SOURCE

100%

YPrPb SUBPIXEL BLENDER

OUTPUT

FORMATTE R

SANDCASTLE

05479-009

Figure 10. Fast Blank Signal Representation with

Contrast Reduction Enabled

Contrast Reduction Enable

CNTR_ENABLE, Address 0xEF [3]

This bit enables the contrast reduction feature and changes the meaning of the signal applied to the FB pin.

0 (default)—The contrast reduction feature is disabled, and the fast blank signal is interpreted as a bilevel signal.

1—The contrast reduction feature is enabled, and the fast blank signal is interpreted as a trilevel signal.

Contrast Mode

CNTR_MODE [1:0], Address 0xF1 [3:2]

The contrast level in the selected contrast reduction box is selected using the CNTR_MODE [1:0] bits.

Table 14. CNTR_MODE [1:0] Function

CNTR_MODE [1:0] Description

00 (default) 25% 01 50% 10 75% 11 100%

05479-010

Rev. A | Page 18 of 112

ADV7184

Fast Blank and Contrast Reduction Programmable Thresholds

The internal fast blank and contrast reduction signals are resolved from the trilevel FB signal using two comparators, as shown in Figure 11. To facilitate compliance with different input level standards, the reference level to these comparators is program-

PROGRAMMABLE

mable via FB_LEVEL [1:0] and CNTR_LEVEL [1:0]. The resulting thresholds are given in

Tabl e 1 5 .

FB_LEVEL [1:0], Address 0xF1 [5:4]

These bits control the reference level for the fast blank comparator.

CNTR_LEVEL [1:0], Address 0xF1 [7:6]

These bits control the reference level for the contrast reduction

Figure 11. Fast Blank and Contrast Reduction Programmable Threshold

comparator.

Table 15. Fast Blank and Contrast Reduction Programmable Threshold I

C Controls

CNTR_ENABLE FB_LEVEL [1:0] CNTR_LEVEL [1:0] Fast Blanking Threshold (V) Contrast Reduction Threshold (V)

0 00 (default) XX 1.4 n/a 0 01 XX 1.6 n/a 0 10 XX 1.8 n/a 0 11 XX 2.0 n/a 1 00 (default) 00 1.6 0.4 1 01 01 1.8 0.6 1 10 10 2.0 0.8 1 11 11 2.2 2.0

FB PIN

THRESHOLDS

CNTR ENABLE

CNTR_LEVEL [1:0]

FAST BLANK COMPARATOR

–

CONTRAST REDUCTION COMPARATOR

FB_LEVEL[1:0]

FAST BLANK

05479-011

Rev. A | Page 19 of 112

ADV7184

FB_INV, Address 0xED [3], Write Only

The interpretation of the polarity of the signal applied to the FB pin can be changed using FB_INV.

0 (default)—The fast blank pin is active high.

1—The fast blank pin is active low.

Readback of FB Pin Status

FB_STATUS [3:0], Address 0xED [7:4]

FB_STATUS [3:0] is a readback value that provides the system information on the status of the FB pins, as shown in

Tabl e 16 .

FB Timing

FB_SP_ADJUST [3:0], Address 0xEF [7:4]

The critical information extracted from the FB signal is the time at which it switches relative to the input video. Due to small timing inequalities either on the IC or on the PCB, it may be necessary to adjust the result by a fraction of one clock cycle. This is controlled by FB_SP_ADJUST [3:0].

Each LSB of FB_SP_ADJUST [3:0] corresponds to ⅛

of an ADC clock cycle. Increasing the value is equivalent to adding delay to the FB signal. The reset value is chosen to produce equalized channels when the ADV7184 internal antialiasing filters are enabled and there are only intentional delays on the PCB.

Alignment of FB Signal

FB_DELAY [3:0], Address 0xF0 [3:0]

In the event of misalignment between the FB input signal and the other input signals (CVBS and RGB) or unequalized delays in their processing, it is possible to alter the delay of the FB signal in 28.63636 MHz clock cycles. (For a finer granularity delay of the FB signal, refer to the Address 0xEF [7:4]

section.)

FB_SP_ADJUST [3:0],

The default value of FB_DELAY [3:0] is 0100.

Color Space Converter Manual Adjust

FB_CSC_MAN, Address 0xEE [7]

As shown in Figure 9, the data from the CVBS and RGB sources are converted to YPbPr before being combined. For the RGB source, CSC must be used to perform this conversion. When SCART support is enabled, the parameters for CSC are automatically configured for this operation.

If the user wishes to use a different conversion matrix, this autoconfiguration can be disabled and the CSC can be manually programmed. For details on this manual configuration, contact an Analog Devices representative.

0 (default)—The CSC is configured automatically for the RGBto-YPrPb conversion.

The default value of FB_SP_ADJUST [3:0] is 0100.

1—The CSC can be configured manually (not recommended).

Table 16. FB_STATUS Functions

FB_STATUS [3:0] Bit Name Description

0 FB_STATUS.0

1 FB_STATUS.1

2 FB_STATUS.2 FB_STAT. The value of the FB input pin at the time of the read. 3 FB_STATUS.3

FB_RISE. A high value indicates that there has been a rising edge on FB since the last

C read. The value is cleared by an I2C read (this is a self-clearing bit).

I FB_FALL. A high value indicates that there has been a falling edge on FB since the last

C read. The value is cleared by an I2C read (this is a self-clearing bit).

FB_HIGH. A high value indicates that there has been a rising edge on FB since the last

C read. The value is cleared by an I2C read (this is a self-clearing bit).

Rev. A | Page 20 of 112

ADV7184

GLOBAL CONTROL REGISTERS

POWER-SAVING MODES

Power-Down

PDBP, Address 0x0F [2]

The digital core of the ADV7184 can be shut down by using the PWRDN of the two controls has the higher priority. The default is to give the pin (

ADV7184 powered down by default.

0 (default)—The digital core power is controlled by the PWRDN

1—The bit has priority (the pin is disregarded).

PWRDN, Address 0x0F [5]

Setting the PWRDN bit switches the ADV7184 into a chip-wide power-down mode. The power-down stops the clock from entering the digital section of the chip, thereby freezing its operation. No I PWRDN bit also affects the analog blocks and switches them into low current modes. The I and remains operational in power-down mode.

The ADV7184 leaves the power-down state if the PWRDN bit is set to 0 (via I

pin. Note that PDBP must be set to 1 for the PWRDN bit to power down the ADV7184.

0 (default)—The chip is operational.

1—The ADV7184 is in chip-wide power-down mode.

ADC Power-Down Control

The ADV7184 contains four 10-bit ADCs (ADC0, ADC1, ADC2, and ADC3). If required, it is possible to power down each ADC individually.

• In CVBS mode, ADC1 and ADC2 should be powered

• In S-video mode, ADC2 should be powered down to

PWRDN_ADC_0, Address 0x3A [3]

0 (default)—The ADC is in normal operation.

1—ADC0 is powered down.

PWRDN_ADC_1, Address 0x3A [2]

0 (default)—The ADC is in normal operation.

1—ADC1 is powered down.

pin or the PWRDN bit. The PDBP bit determines which

PWRDN

) priority. This allows the user to have the

pin (the bit is disregarded).

C bits are lost during power-down. The

C interface itself is unaffected

C) or if the overall part is reset using the

down to reduce power consumption.

reduce power consumption.

RESET

PWRDN_ADC_2, Address 0x3A [1]

0 (default)—The ADC is in normal operation.

1—ADC2 is powered down.

PWRDN_ADC_3, Address 0x3A [0]

0 (default)—The ADC is in normal operation.

1—ADC3 is powered down.

FB_PWRDN, Address 0x0F [1]

To achieve a very low power-down current, it is necessary to prevent activity on toggling input pins from reaching circuitry, where it could consume current. FB_PWRDN gates signals from the FB input pin.

0 (default)—The FB input is in normal operation.

1—The FB input is in the power-saving mode.

RESET CONTROL

RES, Chip Reset, Address 0x0F [7]

Setting this bit, which is equivalent to controlling the

on the ADV7184, issues a chip reset. All I

C registers are reset to

RESET

their default values, making these bits self-clearing. Some register bits do not have a reset value specified and instead keep the last value written to them. These bits are marked as having a reset value of x in the register tables. After the reset sequence, the part immediately starts to acquire the incoming video signal.

Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before performing subsequent I

C master controller receives a no acknowledge condition

The I

C writes.

on the ninth clock cycle when a chip reset is implemented. See the

MPU Port Description section for a full description.

0 (default)—Operation is normal.

1—The reset sequence starts.

GLOBAL PIN CONTROL

Three-State Output Drivers

TOD, Address 0x03 [6]

This bit allows the user to three-state the output drivers of the ADV7184. Upon setting the TOD bit, the P15 to P0, HS, VS, FIELD, and SFL pins are three-stated. The ADV7184 also supports three-stating via a dedicated pin,

drivers are three-stated if the TOD bit or the

The timing pins (HS, VS, and FIELD) can be forced active via the TIM_OE bit of Register 0x04. For more information on three-state control, refer to the

Three-State LLC Drivers and the

Timing Signals Output Enable sections. Individual drive

. The output

pin is set high.

Rev. A | Page 21 of 112

ADV7184

strength controls are provided by the DR_STR_S, DR_STR_C, and DR_STR bits of Register 0xF4.

0 (default)—The output drivers are enabled.

1—The output drivers are three-stated.

Three-State LLC Drivers

TRI_LLC, Address 0x1D [7]

This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7184 to be three-stated. For more information on three-state control, refer to the the

Timing Signals Output Enable sections. Individual drive strength controls are provided via the DR_STR_S, DR_STR_C, and DR_STR bits.

0 (default)—The LLC pin drivers work according to the DR_STR_C [1:0] setting (pin enabled).

1—The LLC pin drivers are three-stated.

Three-State Output Drivers and

Timing Signals Output Enable

TIM_OE, Address 0x04 [3]

The TIM_OE bit should be regarded as an addition to the TOD bit. Setting it high forces the output drivers for HS, VS, and FIELD into the active (that is, driving) state even if the TOD bit is set. If the TIM_OE bit is set to low, the HS, VS, and FIELD pins are three-stated depending on the TOD bit. This functionality is useful if the decoder is to be used only as a timing generator. This may be the case if only the timing signals are to be extracted from an incoming signal or if the part is in free-run mode, where, for example, a separate chip can output a company logo. For more information on three-state control, refer to the Drivers

and the Three-State LLC Drivers sections. Individual drive strength controls are provided via the DR_STR_S, DR_STR_C, and DR_STR bits.

0 (default)—HS, VS, and FIELD are three-stated according to the TOD bit.

1—HS, VS, and FIELD are forced active.

Three-State Output

Drive Strength Selection (Data)

DR_STR [1:0], Address 0xF4 [5:4]

Because of EMC and crosstalk factors, it may be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR [1:0] bits affect the P [15:0] output drivers.

For more information on three-state control, refer to the Strength Selection (Clock) (Sync)

sections.

Table 17. DR_STR Function

DR_STR [1:0] Description

01 (default) Medium-low drive strength (2×) 10 Medium-high drive strength (3×) 11 High drive strength (4×)

and the Drive Strength Selection

Drive

Drive Strength Selection (Clock)

DR_STR_C [1:0], Address 0xF4 [3:2]

The DR_STR_C [1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the Strength Selection (Data)

Table 18. DR_STR_C Function

DR_STR_C [1:0] Description

01 (default) Medium-low drive strength (2×) 10 Medium-high drive strength (3×) 11 High drive strength (4×)

Drive Strength Selection (Sync) and the Drive

sections.

Drive Strength Selection (Sync)

DR_STR_S [1:0], Address 0xF4 [1:0]

The DR_STR_S [1:0] bits allow the user to select the strength of the synchronization signals with which HS, VS, and FIELD are driven. For more information, refer to the Selection (Clock) sections.

Table 19. DR_STR_S Function

DR_STR_S [1:0] Description

01 (default) Medium-low drive strength (2×) 10 Medium-high drive strength (3×) 11 High drive strength (4×)

and the Drive Strength Selection (Data)

Drive Strength

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN, Address 0x04 [1]

The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as genlock) from the ADV7184 core to an encoder in a decoder/encoder back-to-back arrangement.

0 (default)—The subcarrier frequency lock output is disabled.

1—The subcarrier frequency lock information is presented on the SFL pin.

Polarity LLC Pin

PCLK, Address 0x37 [0]

The polarity of the clock that leaves the ADV7184 via the LLC1 and LLC2 pins can be inverted using the PCLK bit. Changing the polarity of the LLC clock output may be necessary to meet the setup time and hold time expectations of follow-on chips. This bit also inverts the polarity of the LLC2 clock.

0—The LLC output polarity is inverted.

1 (default)—The LLC output polarity is normal, as per the timing diagrams (see

Figure 2 to Figure 4).

Rev. A | Page 22 of 112

ADV7184

GLOBAL STATUS REGISTERS

Three registers provide summary information about the video decoder: Status Register 1, Status Register 2, and Status Register 3. These registers contain status bits that report operational information to the user.

Status Register 1 [7:0], Address 0x10 [7:0]

This read-only register provides information about the internal status of the ADV7184. See the Address 0x51 [2:0] Address 0x51 [5:3]

and the COL [2:0], Count-Out-of-Lock, sections for information on the timing.

Depending on the setting of the FSCLE bit, the IN_LOCK [0] and LOST_LOCK [1] bits of Status Register 1 are based solely on the horizontal timing information or on the horizontal timing and lock status of the color subcarrier. See the Enable, Address 0x51 [7]

AD_RESULT [2:0], Autodetection Result, Address 0x10 [6:4]

These bits report the findings from the autodetection block. For more information on enabling the autodetection block, see the

Table 21. Status Register 1 Function

Status Register 1 [7:0] Bit Name Description

0 IN_LOCK In lock (now). 1 LOST_LOCK Lost lock (since last read of this register). 2 FSC_LOCK FSC locked (now). 3 FOLLOW_PW AGC follows peak white algorithm. 4 AD_RESULT.0 Result of autodetection. 5 AD_RESULT.1 Result of autodetection. 6 AD_RESULT.2 Result of autodetection. 7 COL_KILL Color kill is active.

Table 22. Status Register 2 Function

Status Register 2 [7:0] Bit Name Description

0 MVCS DET Detected Macrovision color striping. 1 MVCS T3 Macrovision color striping protection. Conforms to Type 3 if high, Type 2 if low. 2 MV_PS DET Detected Macrovision pseudosync pulses. 3 MV_AGC DET Detected Macrovision AGC pulses. 4 LL_NSTD Line length is nonstandard. 5 FSC_NSTD FSC frequency is nonstandard. 6 Reserved

7 Reserved

Table 23. Status Register 3 Function

Status Register 3 [7:0] Bit Name Description

0 INST_HLOCK Horizontal lock indicator (instantaneous). 1 GEMD Gemstar detect. 2 SD_OP_50HZ Flags whether 50 Hz or 60 Hz is present at output. 3 CVBS Indicates if a CVBS signal is detected in composite/S-video autodetection configuration. 4 FREE_RUN_ACT

5 STD_FLD_LEN Field length is correct for currently selected video standard. 6 INTERLACED Interlaced video detected (field sequence found). 7 PAL_SW_LOCK Reliable sequence of swinging bursts detected.

CIL [2:0], Count-Into-Lock,

FSCLE, FSC Lock

section.

Indicates if the ADV7184 is in free-run mode. Outputs a blue screen by default. See the DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1] section for details about disabling this function.

Rev. A | Page 23 of 112

General Setup section. For information on configuring this block, see the

Autodetection of SD Modes section.

Table 20. AD_RESULT Function

AD_RESULT [2:0] Description

000 NTSC M/J 001 NTSC 443 010 PAL M 011 PAL 60 100 PAL B/G/H/I/D 101 SECAM 110 PAL Combination N 111 SECAM 525

Status Register 2 [7:0], Address 0x12 [7:0]

See Tab le 2 2.

Status Register 3 [7:0], Address 0x13 [7:0]

See Tab le 2 3.

ADV7184

STANDARD DEFINITION PROCESSOR (SDP)

STANDARD DEFINITION PROCESSOR

DIGITI ZED CVBS

DIGITI ZED Y (YC)

DIGITI ZED CVBS

DIGITI ZED C (YC)

MACROVISIO N

DETECT ION

LUMA

DIGITAL

FINE

CLAMP

CHROMA

DIGITAL

FINE

CLAMP

RECOVERY

CHROMA

DEMOD

Fsc

RECOVERY

VBI DATA

LUMA

FILTER

EXTRACT

CHROMA

FILTER

AUTODETECTION

SYNC

STANDARD

Figure 12. Block Diagram of the Standard Definition Processor

A block diagram of the ADV7184 standard definition processor (SDP) is shown in

Figure 12.

The SDP can handle standard definition video in CVBS, Y/C, and YPrPb formats. It can be divided into a luminance path and a chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input.

SD LUMA PATH

The input signal is processed by the following blocks:

• Luma Digital Fine Clamp. This block uses a high precision

algorithm to clamp the video signal.

• Luma Filter. This block contains a luma decimation filter

(YAA) with a fixed response and some luma-shaping filters (YSH) that have selectable responses.

• Luma Gain Control. The automatic gain control (AGC) can

operate on a variety of modes, including a mode based on the depth of the horizontal sync pulse, a mode based on the peak white mode, and a mode that uses a fixed manual gain.

• Luma Resample. To correct for errors and dynamic changes

in line lengths, the data is digitally resampled.

• Luma 2D Comb. The two-dimensional comb filter provides

Y/C separation.

• AV Code Insertion. At this point, the decoded luma (Y)

signal is merged with the retrieved chroma values. AV codes (as per ITU-R. BT-656) can be inserted.

LUMA

GAIN

CONTROL

LINE

LENGTH

PREDICTOR

CHROMA

GAIN

CONTROL

SLLC

CONTROL

LUMA

RESAMPLE

CONTRO L

CHROMA

RESAMPLE

LUMA

2D COMB

CHROMA 2D COMB

CODE

INSERTION

VIDEO DATA OUTPUT

MEASUREMENT BLOCK (= >I

VIDEO DATA PROCESSING BLOCK

05479-012

SD CHROMA PATH

The input signal is processed by the following blocks:

• Chroma Digital Fine Clamp. This block uses a high

precision algorithm to clamp the video signal.

• Chroma Demodulation. This block uses a color subcarrier

) recovery unit to regenerate the color subcarrier for

any modulated chroma scheme and then performs an AM demodulation for PAL and NTSC and an FM demodulation for SECAM.

• Chroma Filter. This block contains a chroma decimation

filter (CAA) with a fixed response and some chromashaping filters (CSH) that have selectable responses.

• Chroma Gain Control. Automatic gain control (AGC) can

operate on several modes, including a mode based on the color subcarrier’s amplitude, a mode based on the depth of the horizontal sync pulse on the luma channel, and a mode that uses a fixed manual gain.

• Chroma Resample. The chroma data is digitally resampled

to keep it aligned with the luma data. The resampling is done to correct for static and dynamic errors in the line lengths of the incoming video signal.

• Chroma 2D Comb. The two-dimensional, 5-line, super-

adaptive comb filter provides high quality Y/C separation in case the input signal is CVBS.

• AV Code Insertion. At this point, the demodulated chroma

(Cr and Cb) signal is merged with the retrieved luma values. AV codes (as per ITU-R. BT-656) can be inserted.

Rev. A | Page 24 of 112

ADV7184

SYNC PROCESSING

The ADV7184 extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction is optimized to support imperfect video sources, such as videocassette recorders with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this block is then used to drive the digital resampling section to ensure that the ADV7184 outputs 720 active pixels per line.

The sync processing on the ADV7184 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video.

• Vsync Processor. This block provides extra filtering of the

detected vsyncs to improve the vertical lock.

• Hsync Processor. The hsync processor is designed to filter

incoming hsyncs that have been corrupted by noise, providing much improved performance for video signals with a stable time base but poor SNR.

VBI DATA RECOVERY

The ADV7184 can retrieve the following information from the input video:

• Wide-screen signaling (WSS)

• Copy generation management system (CGMS)

• Closed captioning (CC)

• Macrovision protection presence

• Gemstar-compatible data slicing

• Te le t e xt

• VITC/VPS

The ADV7184 is also capable of automatically detecting the incoming video standard with respect to

• Color subcarrier frequency

• Field rate

• Line rate

The ADV7184 can configure itself to support PAL (B/G/H/I/D/M/N), PAL Combination N, NTSC M, NTSC J, SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60.

GENERAL SETUP

Video Standard Selection

The VID_SEL [3:0] bits allow the user to force the digital core into a specific video standard. Under normal circumstances, this should not be necessary. The VID_SEL [3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. The following section describes the autodetection system.

Autodetection of SD Modes

To guide the autodetection system, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being automatically detected. Instead, the system selects the closest of the remaining enabled standards. The results of the autodetection can be read back via the status registers. See the section for more information.

VID_SEL [3:0], Address 0x00 [7:4]

Table 24. VID_SEL Function

VID_SEL [3:0] Description

0000 (default)

0001

0010

0011

0100 NTSC J (1) 0101 NTSC M (1) 0110 PAL 60 0111 NTSC 4.43 (1) 1000 PAL B/G/H/I/D 1001 PAL N (PAL B/G/H/I/D without pedestal) 1010 PAL M (without pedestal) 1011 PAL M 1100 PAL Combination N 1101 PAL Combination N (with pedestal) 1110 SECAM 1111 SECAM (with pedestal)

Autodetect PAL (B/G/H/I/D), NTSC (without pedestal), SECAM

Autodetect PAL (B/G/H/I/D), NTSC M (with pedestal), SECAM

Autodetect PAL N (without pedestal), NTSC M (without pedestal), SECAM

Autodetect PAL N (with pedestal), NTSC M (with pedestal), SECAM

Global Status Registers

Rev. A | Page 25 of 112

ADV7184

AD_SEC525_EN, SECAM 525 Autodetect Enable, Address 0x07 [7]

0 (default)—Disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component.

1—Enables autodetection.