ANALOG DEVICES ADV7183B Service Manual

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FEATURES

Multiformat video decoder supports NTSC-(J, M, 4.43), PAL-(B/D/G/H/I/M/N), SECAM

Integrates three 54 MHz, 10-bit ADCs Clocked from a single 27 MHz crystal Line-locked clock-compatible (LLC) Adaptive Digital Line Length Tracking (ADLLT™), signal

processing, and enhanced FIFO management give mini-

TBC functionality 5-line adaptive comb filters Proprietary architecture for locking to weak, noisy, and

unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output

Integrated AGC with adaptive peak white mode Macrovision® copy protection detection Chroma transient improvement (CTI) Digital noise reduction (DNR) Multiple programmable analog input formats

Composite video (CVBS)

S-Video (Y/C)

YPrPb component (VESA, MII, SMPTE, and BetaCam) 12 analog video input channels Automatic NTSC/PAL/SECAM identification

Digital output formats (8-bit or 16-bit)

ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD

GENERAL DESCRIPTION

The ADV7183B integrated video decoder automatically detects and converts a standard analog baseband television signalcompatible with worldwide standards NTSC, PAL, and SECAM into 4:2:2 component video data-compatible with 16-/8-bit CCIR601/CCIR656.

The advanced and highly flexible digital output interface enables performance video decoding and conversion in linelocked clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security/surveillance cameras, and professional systems.

The 10-bit accurate A/D conversion provides professional quality video performance and is unmatched. This allows true 8-bit resolution in the 8-bit output mode.

The 12 analog input channels accept standard composite, S-Video, YPrPb video signals in an extensive number of

Multiformat SDTV Video Decoder

ADV7183B

0.5 V to 1.6 V analog signal input range Differential gain: 0.5% typ Differential phase: 0.5° typ Programmable video controls

Peak white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free-run mode (generates stable video output with no I/P)

VBI decode support for close captioning, WSS, CGMS, EDTV,

Gemstar® 1×/2× Power-down mode

2-wire serial MPU interface (I

3.3 V analog, 1.8 V digital core; 3.3 V IO supply 2 temperature grades: 0°C to +70°C and –40°C to +85°C 80-lead LQFP Pb-free package

APPLICATIONS

DVD recorders Video projectors HDD-based PVRs/DVDRs LCD T Vs Set-top boxes Security systems Digital televisions AVR rece ivers

combinations. AGC and clamp restore circuitry allow an input video signal peak-to-peak range of 0.5 V up to 1.6 V. Alternatively, these can be bypassed for manual settings.

The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise, accurate sampling and digital filtering. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ±5% line length variation. The output control signals allow glueless interface connections in almost any application. The ADV7183B modes are set up over a 2-wire, serial, bidirectional port (I

The ADV7183B is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation.

The ADV7183B is packaged in a small 80-lead LQFP Pb-free package.

C®-compatible)

C-compatible).

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADV7183B

TABLE OF CONTENTS

Introduction ...................................................................................... 4

Analog Front End......................................................................... 4

Standard Definition Processor (SDP)........................................ 4

Functional Block Diagram .......................................................... 5

specifications..................................................................................... 6

Electrical Characteristics ............................................................. 6

Video Specifications..................................................................... 7

Timing Specifications .................................................................. 8

Analog Specifications................................................................... 8

Thermal Specifications ................................................................ 9

Timing Diagrams.......................................................................... 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Analog Front End........................................................................... 13

VBI Data Recovery..................................................................... 21

General Setup.............................................................................. 21

Color Controls............................................................................ 23

Clamp Operation........................................................................ 25

Luma Filter.................................................................................. 26

Chroma Filter.............................................................................. 29

Gain Operation........................................................................... 30

Chroma Transient Improvement (CTI) .................................. 33

Digital Noise Reduction (DNR)............................................... 34

Comb Filters................................................................................ 35

AV Code Insertion and Controls ............................................. 37

Synchronization Output Signals............................................... 39

Sync Processing .......................................................................... 46

VBI Data Decode ....................................................................... 47

Pixel Port Configuration ............................................................... 59

Analog Input Muxing ................................................................ 13

Manual Input Muxing................................................................ 15

Global Control Registers ............................................................... 16

Power-Save Modes...................................................................... 16

Reset Control .............................................................................. 16

Global Pin Control..................................................................... 17

Global Status Registers................................................................... 19

Identification............................................................................... 19

Status 1......................................................................................... 19

Autodetection Result.................................................................. 19

Status 2......................................................................................... 19

Status 3......................................................................................... 19

Standard Definition Processor (SDP).......................................... 20

SD Luma Path ............................................................................. 20

SD Chroma Path......................................................................... 20

MPU Port Description................................................................... 60

C Sequencer.............................................................................. 61

IP2PC Register Maps ..................................................................... 62

C Register Map Details ........................................................... 118H66

52HI

C Programming Examples.......................................................... 119H88

53HExamples in this Section use a 28 MHz Clock. ...................... 120H88

54HExamples Using 27 MHz Clock................................................ 121H92

55HPCB Layout Recommendations.................................................... 122H94

56HAnalog Interface Inputs............................................................. 123H94

57HPower Supply Decoupling......................................................... 124H94

58HPLL ............................................................................................... 125H94

59HDigital Outputs (Both Data and Clocks) ................................ 126H94

60HDigital Inputs.............................................................................. 127H94

Sync Processing........................................................................... 21

Rev. B | Page 2 of 100

61HAntialiasing Filters ..................................................................... 128H95

ADV7183B

62HCrystal Load Capacitor Value Selection...................................129H95

64HOutline Dimensions........................................................................131H98

63HTypical Circuit Connection ...........................................................130H96

REVISION HISTORY

9/05—Rev. A to Rev. B

Changes to Table 1 ............................................................................6

Changes to Table 2 ............................................................................7

Changes to Table 3 and Table 4 .......................................................8

Changes to Table 5 ............................................................................9

Change to Figure 6..........................................................................13

Change Formatting of Table 15 to Table 17.................................19

Change to Figure 8..........................................................................21

Changes to Lock Related Controls Section..................................24

Changes to Table 34 ........................................................................32

Changes to Table Reference in BETACAM Section ...................33

Change to PAL Comb Filter Settings Section..............................37

Change to NFTOG Section............................................................44

Changes to Table 85 ........................................................................68

Changes to Table 86 ........................................................................72

6/05—Rev. 0 to Rev. A

Changed Crystal References to 28 MHz Crystal............ Universal

Changes to Features Section............................................................1

9/04—Revision 0: Initial Version

65HOrdering Guide...........................................................................132H98

Changes to Table 3 and Table 4.......................................................8

Changes to Analog Specifications Section..................................... 8

Changes to Table 7 ..........................................................................11

Changes to Clamp Operation Section..........................................26

Renamed Figure 14 and Figure 15................................................30

Changes to Table 31 ........................................................................31

Changed LAGC Register Address in Luma Gain Section .........32

Changed VSBHE VS Default .........................................................41

Changes to Table 55 ........................................................................43

Changes to Table 56 ........................................................................45

Changed Comments for CTAPSP[1:0] in Table 85....................81

Changes to Table 86 ........................................................................89

Changes to Table 87 ........................................................................90

Changes to Table 88 ........................................................................91

Changes to Table 89 ........................................................................92

Added Examples Using 27 MHz Clock Section..........................93

Added XTAL Load Capacitor Value Selection Section .............. 96

Changes to Ordering Guide...........................................................99

Rev. B | Page 3 of 100

ADV7183B

INTRODUCTION

The ADV7183B is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format.

The advanced and highly flexible digital output interface enables performance video decoding and conversion in line-locked, clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape based sources, broadcast sources, security/surveillance cameras, and professional systems.

ANALOG FRONT END

The ADV7183B analog front end comprises three 10-bit ADCs that digitize the analog video signal before applying it to the standard definition processor. The analog front end uses differential channels to each ADC to ensure high performance in mixed-signal applications.

The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7183B. Current and voltage clamps are positioned in front of each ADC to ensure the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7183B. The ADCs are configured to run in 4× oversampling mode.

STANDARD DEFINITION PROCESSOR (SDP)

The ADV7183B is capable of decoding a large selection of

baseband video signals in composite, S-Video, and component

formats. The video standards supported include PAL B/D/I/G/H,

PAL60, PA L M, PAL N, PA L Nc , NTS C M/J, NTSC 4 .43, and

SECAM B/D/G/K/L. The ADV7183B can automatically detect

the video standard and process it accordingly.

The ADV7183B has a 5-line, superadaptive, 2D comb filter that

gives superior chrominance and luminance separation when

decoding a composite video signal. This highly adaptive filter

automatically adjusts its processing mode according to video

standard and signal quality with no user intervention required.

Video user controls such as brightness, contrast, saturation, and

hue are also available within the ADV7183B.

The ADV7183B implements a patented adaptive digital line-

length tracking (ADLLT) algorithm to track varying video line

lengths from sources. ADLLT enables the ADV7183B to track

and decode poor quality video sources such as VCRs, noisy

sources from tuner outputs, VCD players, and camcorders. The

ADV7183B contains a chroma transient improvement (CTI)

processor that sharpens the edge rate of chroma transitions,

resulting in sharper vertical transitions.

The ADV7183B can process a variety of VBI data services, such

as closed captioning (CC), wide screen signaling (WSS), copy

generation management system (CGMS), EDTV, Gemstar 1×/2×,

and extended data service (XDS). The ADV7183B is fully

Macrovision® certified; detection circuitry enables Type I, II,

and III protection levels to be identified and reported to the

user. The decoder is also fully robust to all Macrovision signal

inputs.

Rev. B | Page 4 of 100

ADV7183B

FUNCTIONAL BLOCK DIAGRAM

FIELD

LLC1

LLC2

SFL

PIXEL

DATA

OUTPUT FORMATTER

INTRQ

LUMA

(4H MAX)

2D COMB

LUMA

RESAMPLE

GAIN

CONTROL

LUMA

FILTER

STANDARD DEFINITION PROCESSOR

FINE

LUMA

CLAMP

DIGITAL

L-DNR

LINE

CODE

INSERTION

CONTROL

RESAMPLE

LENGTH

PREDICTOR

SYNC

EXTRACT

CTI

C-DNR

RECOVERY

(4H MAX)

CHROMA

2D COMB

CHROMA

RESAMPLE

GAIN

CONTROL

FILTER

CHROMA

DEMOD

CHROMA

FINE

CLAMP

DIGITAL

CHROMA

FREE RUN

SYNTHESIZED

LLC CONTROL

OUTPUT CONTROL

STANDARD

AUTODETECTION

DETECTION

MACROVISION

VBI DATA RECOVERY GLOBAL CONTROL

DATA

PREPROCESSOR

A/DCLAMP

AIN1–

AIN12

FILTERS

DOWNSAMPLING

DECIMATION AND

A/DCLAMP10A/DCLAMP

MUX

INPUT

CVBS

YPrPb

S-VIDEO

SYNC AND

CLK CONTROL

CLOCK GENERATION

SYNC PROCESSING AND

Figure 1.

ADV7183B

CONTROL

AND DATA

SERIAL INTERFACE

CONTROL AND VBI DATA

SDA

SCLK

ALSB

04997-001

Rev. B | Page 5 of 100

ADV7183B

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise specified.

Table 1.

Parameter0F

1, 1F2

Symbol Test Conditions Min Typ Max Unit

STATIC PERFORMANCE

Resolution (each ADC) N 10 Bits Integral Nonlinearity INL BSL at 54 MHz –0.475/+0.6 ±3 LSB Differential Nonlinearity DNL BSL at 54 MHz –0.25/+0.5 –0.7/+2 LSB

DIGITAL INPUTS

Input High Voltage VIH 2 V Input Low Voltage VIL 0.8 V Input Current IIN Pins listed in Note 2F3 –50 +50 μA All other pins –10 +10 μA Input Capacitance CIN 10 pF

DIGITAL OUTPUTS

Output High Voltage VOH I Output Low Voltage VOL I High Impedance Leakage Current I All other pins 10 μA Output Capacitance C

POWER REQUIREMENTS4F5

Digital Core Power Supply D Digital I/O Power Supply D PLL Power Supply P Analog Power Supply A Digital Core Supply Current I Digital I/O Supply Current I PLL Supply Current I Analog Supply Current I YPrPb input6F7 180 mA Power-Down Current I Power-Up Time t

Temperature range: T

The min/max specifications are guaranteed over this range.

Pins 36 and 79.

Pins 1, 2, 5, 6, 8, 12, 17, 18 to 24, 32 to 35, 74 to 76, 80.

Guaranteed by characterization.

ADC1 powered on.

All three ADCs powered on.

to T

MIN

MAX

= 1.65 V to 2.0 V, D

VDD

, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ).

= 3.0 V to 3.6 V, P

VDDIO

SOURCE

SINK

Pins listed in Note 3F4 50 μA

LEAK

20 pF

OUT

1.65 1.8 2 V

VDD

3.0 3.3 3.6 V

VDDIO

1.65 1.8 2.0 V

VDD

3.15 3.3 3.45 V

VDD

82 mA

DVDD

2 mA

DVDDIO

10.5 mA

PVDD

CVBS input5F6 85 mA

AVDD

1.5 mA

PWRDN

20 ms

PWRUP

= 1.65 V to 2.0 V, operating temperature range, unless

VDD

= 0.4 mA 2.4 V

= 3.2 mA 0.4 V

Rev. B | Page 6 of 100

ADV7183B

VIDEO SPECIFICATIONS

At A

= 3.15 V to 3.45 V, D

VDD

otherwise specified.

Table 2.

Parameter7F

1, 8F2

Symbol Test Conditions Min Typ Max Unit

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS I/P, modulate 5-step 0.5 0.7 Degrees Differential Gain DG CVBS I/P, modulate 5-step 0.5 0.7 % Luma Nonlinearity LNL CVBS I/P, 5-step 0.5 0.7 %

NOISE SPECIFICATIONS

SNR Unweighted Luma ramp 54 56 dB Luma flat field 58 60 dB Analog Front End Crosstalk 60 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range –5 +5 % Vertical Lock Range 40 70 Hz FSC Subcarrier Lock Range ±1.3 Hz Color Lock In Time 60 Lines Sync Depth Range 20 200 % Color Burst Range 5 200 % Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines

CHROMA SPECIFICATIONS

Hue Accuracy HUE 1 Degrees Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.5 % Chroma Phase Error 0.4 Degrees Chroma Luma Intermodulation 0.2 %

LUMA SPECIFICATIONS

Luma Brightness Accuracy CVBS, 1 V I/P 1 % Luma Contrast Accuracy CVBS, 1 V I/P 1 %

Temperature range: T

The min/max specifications are guaranteed over this range.

to T

MIN

= 1.65 V to 2.0 V, D

VDD

, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ).

MAX

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V, operating temperature range, unless

VDD

Rev. B | Page 7 of 100

ADV7183B

TIMING SPECIFICATIONS

Guaranteed by characterization. At A operating temperature range, unless otherwise specified.

= 3.15 V to 3.45 V, D

VDD

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V,

VDD

Table 3.

Parameter9F

10F

Symbol Test Conditions Min Typ Max Unit

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency 28.6363 MHz Frequency Stability ±50 ppm

I2C PORT

SCLK Frequency 400 kHz SCLK Min Pulse Width High t1 0.6 μs SCLK Min Pulse Width Low t2 1.3 μs Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 μs

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC1 Mark Space Ratio t9:t10 45:55 55:45 % duty cycle LLC1 Rising to LLC2 Rising t11 0.5 ns LLC1 Rising to LLC2 Falling t12 0.5 ns

DATA AND CONTROL OUTPUTS

Data Output Transitional Time t13

Data Output Transitional Time t14

Negative clock edge to start of valid data; (t

ACCESS

= t

– t13)

End of valid data to negative clock edge; (t

= t9 + t14)

HOLD

3.4 ns

2.4 ns

Propagation Delay to Hi-Z t15 6 ns Max Output Enable Access Time t16 7 ns Min Output Enable Access Time t17 4 ns

Temperature range: T

The min/max specifications are guaranteed over this range.

to T

MIN

, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ).

MAX

ANALOG SPECIFICATIONS

Guaranteed by characterization. A temperature range, unless otherwise noted). Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.

Table 4.

Parameter11F

12F

Symbol Test Conditions Min Typ Max Unit

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF Input Impedance Clamps switched off 10 MΩ Large Clamp Source Current 0.75 mA Large Clamp Sink Current 0.75 mA Fine Clamp Source Current 60 μA Fine Clamp Sink Current 60 μA

Temperature range: T

The min/max specifications are guaranteed over this range.

to T

MIN

, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ).

MAX

= 3.15 V to 3.45 V, D

VDD

= 1.65 V to 2.0 V, D

VDD

Rev. B | Page 8 of 100

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V (operating

VDD

ADV7183B

THERMAL SPECIFICATIONS

Table 5.

Parameter13F

Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane 7.6 °C/W Junction-to-Ambient Thermal Resistance (Still Air) θJA 4-layer PCB with solid ground plane 38.1 °C/W

Temperature range: T

The min/max specifications are guaranteed over this range.

TIMING DIAGRAMS

14F

Symbol Test Conditions Min Typ Max Unit

to T

, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ).

MIN

MAX

SDA

SCLK

Figure 2. I

C Timing

04997-002

OUTPUT LLC 1

OUTPUT LLC 2

OUTPUTS P0–P15, VS,

HS, FIELD,

SFL

Figure 3. Pixel Port and Control Output Timing

04997-003

04997-004

P0–P15, HS,

VS, FIELD,

SFL

Figure 4.

Timing

Rev. B | Page 9 of 100

ADV7183B

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

to GND 4 V

VDD

to AGND 4 V

VDD

to DGND 2.2 V

VDD

to AGND 2.2 V

VDD

to DGND 4 V

VDDIO

to A

VDDIO

to D

VDD

VDDIO

– P

VDD

– D

VDD

Digital Inputs Voltage to DGND –0.3 V to D Digital Output Voltage to DGND –0.3 V to D Analog Input to AGND AGND – 0.3 V to A Maximum Junction Temperature

max)

Storage Temperature Range –65°C to +150°C Infrared Reflow Soldering (20 sec) 260°C

–0.3 V to +0.3 V

VDD

–0.3 V to +0.3 V

VDD

– P

–0.3 V to +2 V

VDD

– D

–0.3 V to +2 V

VDD

–0.3 V to +2 V

VDD

–0.3 V to +2 V

VDD

150°C

VDDIO

+ 0.3 V + 0.3 V

VDD

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 10 of 100

ADV7183B

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FIELD79OE78NC77NC76P1275P1374P1473P1572DVDD71DGND70NC69NC68SCLK67SDA66ALSB65NC64RESET63NC62AIN661AIN12

DGND

DVDDIO

P11

P10

DGND

DVDD

INTRQ

SFL

DGND

DVDDIO

NC = NO CONNECT

PIN 1

21P522P423P324P225NC26

Figure 5. 80-Lead LQFP Pin Configuration

LLC227LLC1

ADV7183B

TOP VIEW

(Not to Scale)

XTAL

DVDD

XTAL1

DGND

32P133P034NC35NC36

PWRDN

ELPF

PVDD

AGND40AGND

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AIN5 AIN11 AIN4 AIN10 AGND CAPC2 CAPC1 AGND CML REFOUT AVDD CAPY2 CAPY1 AGND AIN3 AIN9 AIN2 AIN8 AIN1 AIN7

04997-005

Rev. B | Page 11 of 100

ADV7183B

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type Description

3, 9, 14, 31, 71 DGND G Digital Ground. 39, 40, 47, 53, 56 AGND G Analog Ground. 4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V). 10, 30, 72 DVDD P Digital Core Supply Voltage (1.8 V). 50 AVDD P Analog Supply Voltage (3.3 V). 38 PVDD P PLL Supply Voltage (1.8 V). 42, 44, 46, 58, 60,

62, 41, 43, 45, 57, 59, 61

13, 16 to 18, 25, 34, 35, 63, 65, 69, 70, 77, 78

33, 32, 24, 23, 22, 21, 20, 19, 8, 7, 6, 5, 76, 75, 74, 73

2 HS O Horizontal Synchronization Output Signal. 1 VS O Vertical Synchronization Output Signal. 80 FIELD O Field Synchronization Output Signal. 67 SDA I/O I2C Port Serial Data Input/Output Pin. 68 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. 66 ALSB I

27 LLC1 O

26 LLC2 O

29 XTAL I

28 XTAL1 O

37 ELPF I

12 SFL O

51 REFOUT O

52 CML O

48, 49 CAPY1, CAPY2 I

54, 55 CAPC1, CAPC2 I

AIN1 to AIN12 I Analog Video Input Channels.

INTRQ

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video. See the interrupt register map in 133HTable 83.

NC No Connect Pins.

P0 to P15 O Video Pixel Output Port.

This pin selects the I

C address for the ADV7183B. ALSB set to Logic 0 sets the address for a

write as 0x40; for ALSB set to logic high, the address selected is 0x42.

RESET

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7183B circuitry.

This is a line-locked output clock for the pixel data output by the ADV7183B. Nominally 27 MHz, but varies up or down according to video line length.

This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7183B. Nominally 13.5 MHz, but varies up or down according to video line length.

This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V, 27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183B. In crystal mode, the crystal must be a fundamental crystal.

PWRDN

A logic low on this pin places the ADV7183B in a power-down mode. Refer to the 134HIP2PC Register Maps section for more options on power-down modes for the ADV7183B.

When set to a logic low, OE enables the pixel output bus, P15 to P0 of the ADV7183B. A logic high on the OE pin places Pins P15 to P0, HS, VS, SFL into a high impedance state.

The recommended external loop filter must be connected to this ELPF pin, as shown in

135HFigure 46.

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video encoder.

Internal Voltage Reference Output. Refer to for this pin.

The CML pin is a common-mode level for the internal ADCs. Refer to

recommended capacitor network for this pin.

ADC’s Capacitor Network. Refer to this pin.

136HFigure 46 for a recommended capacitor network

138HFigure 46 for a recommended capacitor network for

139HFigure 46 for a recommended capacitor network for

137HFigure 46 for a

Rev. B | Page 12 of 100

ADV7183B

ANALOG FRONT END

ADC_SW_MAN_EN INSEL[3:0]

AIN12

AIN6

AIN11

AIN5

AIN10

AIN4

AIN9

AIN3

AIN8

AIN2

AIN7

AIN1

AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12

AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12

1 0

ADC0_SW[3:0]

ADC0

ADC1_SW[3:0]

ADC1

INTERNAL

MAPPING

FUNCTIONS

Figure 6. Internal Pin Connections

ANALOG INPUT MUXING

The ADV7183B has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. muxing provided in the ADV7183B.

As seen in by functional registers (INSEL) or manually. Using INSEL[3:0] simplifies the setup of the muxes and minimizes crosstalk between channels by pre-assigning the input channels. This is referred to as ADI recommended input muxing.

Control via an I ADC0_sw, and ADC1_sw, ADC2_sw) is provided for applications with special requirements (for example, number/ combinations of signals) that would not be served by the preassigned input connections. This is referred to as manual input muxing.

140HFigure 6 outlines the overall structure of the input

141HFigure 6, the analog input muxes can be controlled

C manual override (ADC_sw_man_en,

AIN2 AIN8 AIN5 AIN11 AIN6 AIN12

ADC2_SW[3:0]

1 0

Refer to

ADC2

142HFigure 7 for an overview of the two methods of

04997-006

controlling the ADV7183B’s input muxing.

ADI Recommended Input Muxing

A maximum of 12 CVBS inputs can be connected and decoded by the ADV7183B. As seen in

143HFigure 5, this means the sources

will have to be connected to adjacent pins on the IC. This calls for a careful design of the PCB layout, such as ground shielding between all signals routed through tracks that are physically close together.

INSEL[3:0] Input Selection, Address 0x00[3:0]

The INSEL bits allow the user to select an input channel as well as the input format. Depending on the PCB connections, only a subset of the INSEL modes is valid. The INSEL[3:0] not only switches the analog input muxing, it also configures the standard definition processor core to process CVBS (Comp), S-Video (Y/C), or component (YPbPr) format.

Rev. B | Page 13 of 100

ADV7183B

CONNECTING

ANALOG SIGNALS

TO ADV7183B

YES NO

SET INSEL[3:0] FOR REQUIRED

MUXING CONFIGURATION

INPUT MUXING; SEE TABLE 9

Figure 7. Input Muxing Overview

Table 8. Input Channel Switching Using INSEL[3:0]

Description INSEL[3:0] Analog Input Pins Video Format

0000 (default) CVBS1 = AIN1 Composite 0001 CVBS2 = AIN2 Composite 0010 CVBS3 = AIN3 Composite 0011 CVBS4 = AIN4 Composite 0100 CVBS5 = AIN5 Composite 0101 CVBS6 = AIN6 Composite 0110 Y1 = AIN1 Y/C C1 = AIN4 Y/C 0111 Y2 = AIN2 Y/C C2 = AIN5 Y/C 1000 Y3 = AIN3 Y/C C3 = AIN6 Y/C 1001 Y1 = AIN1 YPrPb PB1 = AIN4 YPrPb PR1 = AIN5 YPrPb 1010 Y2 = AIN2 YPrPb PB2 = AIN3 YPrPb PR2 = AIN6 YPrPb 1011 CVBS7 = AIN7 Composite 1100 CVBS8 = AIN8 Composite 1101 CVBS9 = AIN9 Composite 1110 CVBS10 = AIN10 Composite 1111 CVBS11 = AIN11 Composite

ADI RECOMMENDED

SET INSEL[3:0] TO

CONFIGURE ADV7183B TO

DECODE VIDEO FORMAT:

CVBS: 0000

YC: 0110

YPrPb: 1001

USE MANUAL INPUT MUXING

(ADC_SW_MAN_EN, ADC0_SW,

ADC1_SW, ADC2_SW)

04997-007

Table 9. Input Channel Assignments

Input

Channel

ADI Recommended Input Muxing Control

No.

INSEL[3:0]

AIN7 41 CVBS7

AIN1 42 CVBS1 Y/C1-Y YPrPb1-Y

AIN8 43 CVBS8

AIN2 44 CVBS2 Y/C2-Y YPrPb2-Y

AIN9 45 CVBS9

AIN3 46 CVBS3 Y/C3-Y YPrPb2-Pb

AIN10 57 CVBS10

AIN4 58 CVBS4 Y/C1-C YPrPb1-Pb

AIN11 59 CVBS11

AIN5 60 CVBS5 Y/C2-C YPrPb1-Pr

AIN12 61 Not available

AIN6 62 CVBS6 Y/C3-C YPrPb2-Pr

ADI recommended input muxing is designed to minimize

crosstalk between signal channels and to obtain the highest

level of signal integrity.

144HTable 9 summarizes how the PCB layout

should connect analog video signals to the ADV7183B.

It is strongly recommended to connect any unused analog input

pins to AGND to act as a shield.

Inputs AIN7 to AIN11 should be connected to AGND when

only six input channels are used. This improves the quality of

the sampling due to better isolation between the channels.

AIN12 is not under the control of INSEL[3:0]. It can be routed

to ADC0/ADC1/ADC2 only by manual muxing. See

145HTabl e 10

for details.

Rev. B | Page 14 of 100

ADV7183B

MANUAL INPUT MUXING

By accessing a set of manual override muxing registers, the analog input muxes of the ADV7183B can be controlled directly. This is referred to as manual input muxing.

Manual input muxing overrides other input muxing control bits, such as INSEL.

The manual muxing is activated by setting the ADC_SW_MAN_EN bit. It affects only the analog switches in front of the ADCs. This means if the settings of INSEL and the manual input muxing registers (ADC0/ADC1/ADC2_sw) contradict each other, the ADC0/ADC1/ADC2_sw settings apply, and INSEL is ignored.

Manual input muxing controls only the analog input muxes. INSEL[3:0] still has to be set so the follow-on blocks process the video data in the correct format. This means INSEL must still be used to tell the ADV7183B whether the input signal is of component, Y/C, or CVBS format.

Table 10. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1)

ADC0_sw[3:0] ADC0 Connected to ADC1_sw[3:0] ADC1 Connected to ADC2_sw[3:0] ADC2 Connected to

0000 No connection 0000 No connection 0000 No connection 0001 AIN1 0001 No connection 0001 No connection 0010 AIN2 0010 No connection 0010 AIN2 0011 AIN3 0011 AIN3 0011 No connection 0100 AIN4 0100 AIN4 0100 No connection 0101 AIN5 0101 AIN5 0101 AIN5 0110 AIN6 0110 AIN6 0110 AIN6 0111 No connection 0111 No connection 0111 No connection 1000 No connection 1000 No connection 1000 No connection 1001 AIN7 1001 No connection 1001 No connection 1010 AIN8 1010 No connection 1010 AIN8 1011 AIN9 1011 AIN9 1011 No connection 1100 AIN10 1100 AIN10 1100 No connection 1101 AIN11 1101 AIN11 1101 AIN11 1110 AIN12 1110 AIN12 1110 AIN12 1111 No connection 1111 No connection 1111 No connection

Restrictions in the channel routing are imposed by the analog signal routing inside the IC; every input pin cannot be routed to each ADC. Refer to

146HFigure 6 for an overview on the routing

capabilities inside the chip. The three mux sections can be controlled by the reserved control signal buses ADC0/ADC1/ ADC2_sw[3:0].

147HTable 10 explains the control words used.

SETADC_sw_man_en, Manual Input Muxing Enable, Address 0xC4[7]

ADC0_sw[3:0], ADC0 mux configuration, Address 0xC3[3:0] ADC1_sw[3:0], ADC1 mux configuration, Address 0xC3[7:4] ADC2_sw[3:0], ADC2 mux configuration, Address 0xC4[3:0]

Rev. B | Page 15 of 100

ADV7183B

GLOBAL CONTROL REGISTERS

POWER-SAVE MODES

Power-Down

PDBP, Address 0x0F[2]

The digital core of the ADV7183B can be shut down by using the

PWRDN

controls which of the two pins has the higher priority. The default is to give priority to the

user to have the ADV7183B powered down by default.

pin and the PWRDN bit (see below). The PDBP

PWRDN

pin. This allows the

PWRDN_ADC_0, Address 0x3A[3]

When PWRDN_ADC_0 is 0 (default), the ADC is in normal

operation.

When PWRDN_ADC_0 is 1, ADC 0 is powered down.

PWRDN_ADC_1, Address 0x3A[2]

When PWRDN_ADC_1 is 0 (default), the ADC is in normal

operation.

When PWRDN_ADC_1 is 1, ADC 1 is powered down.

When PDBD is 0 (default), the digital core power is controlled by the

PWRDN

pin (the bit is disregarded).

When PDBD is 1, the bit has priority (the pin is disregarded).

PWRDN, Address 0x0F[5]

Setting the PWRDN bit switches the ADV7183B into a chipwide power-down mode. The power-down stops the clock from entering the digital section of the chip, thereby freezing its operation. No I

C bits are lost during power-down. The PWRDN bit also affects the analog blocks and switches them into low current modes. The I

C interface is unaffected and

remains operational in power-down mode.

The ADV7183B leaves the power-down state if the PWRDN

bit is set to 0 (via I

pin.

RESET

C), or if the overall part is reset using the

PDBP must be set to 1 for the PWRDN bit to power down the ADV7183B.

When PWRDN is 0 (default), the chip is operational.

When PWRDN is 1, the ADV7183B is in chip-wide power-down.

ADC Power-Down Control

The ADV7183B contains three 10-bit ADCs (ADC 0, ADC 1, and ADC 2). If required, each ADC can be powered down individually.

PWRDN_ADC_2, Address 0x3A[1]

When PWRDN_ADC_2 is 0 (default), the ADC is in normal operation.

When PWRDN_ADC_2 is 1, ADC 2 is powered down.

RESET CONTROL

Chip Reset (RES), Address 0x0F[7]

Setting this bit, equivalent to controlling the ADV7183B, issues a full chip reset. All I

C registers are reset to their default values. (Some register bits do not have a reset value specified. They keep their last written value. Those bits are marked as having a reset value of x in the register table.) After the reset sequence, the part immediately starts to acquire the incoming video signal.

After setting the RES bit (or initiating a reset via the pin), the part returns to the default mode of operation with respect to its primary mode of operation. All I

C bits are loaded with their

default values, making this bit self-clearing.

Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before any further I performed.

The I

C master controller receives a no acknowledge condition

on the ninth clock cycle when chip reset is implemented. See

148HMPU Port Description section.

the

RESET

pin on the

C writes are

The ADCs should be powered down when in:

• CVBS mode. ADC 1 and ADC 2 should be powered down

to save on power consumption.

• S-Video mode. ADC 2 should be powered down to save on

power consumption.

Rev. B | Page 16 of 100

When RES is 0 (default), operation is normal.

When RES is 1, the reset sequence starts.

ADV7183B

GLOBAL PIN CONTROL

Three-State Output Drivers

TOD, Address 0x03[6]

This bit allows the user to three-state the output drivers of the ADV7183B.

Upon setting the TOD bit, the P15 to P0, HS, VS, FIELD, and SFL pins are three-stated.

The timing pins (HS/VS/FIELD) can be forced active via the TIM_OE bit. For more information on three-state control, refer to the

149HThree-State LLC Driver and the 150HTiming Signals Output

Enable sections.

Individual drive strength controls are provided via the DR_STR_XX bits.

The ADV7183B supports three-stating via a dedicated pin. When set high, the

the P15 to P0, HS, VS, FIELD, and SFL pins. The output drivers are three-stated if the TOD bit or the

When TOD is 0 (default), the output drivers are enabled.

When TOD is 1, the output drivers are three-stated.

Three-State LLC Driver

TRI_LLC, Address 0x1D[7]

This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7183B to be three-stated. For more information on three-state control, refer to the the

152HTiming Signals Output Enable sections.

Individual drive strength controls are provided via the DR_STR_XX bits.

When TRI_LLC is 0 (default), the LLC pin drivers work according to the DR_STR_C[1:0] setting (pin enabled).

When TRI_LLC is 1, the LLC pin drivers are three-stated.

pin three-states the output drivers for

pin is set high.

151HThree-State Output Drivers and

Timing Signals Output Enable

TIM_OE, Address 0x04[3]

The TIM_OE bit should be regarded as an addition to the TOD bit. Setting it high forces the output drivers for HS, VS, and FIELD pins into the active (driving) state even if the TOD bit is set. If set to low, the HS, VS, and FIELD pins are three-stated, dependent on the TOD bit. This functionality is useful if the decoder is used as a timing generator only. This can happen when only the timing signals are to be extracted from an incoming signal, or if the part is in free-run mode where a separate chip can output, for an example, a company logo.

For more information on three-state control, refer to the State Output Drivers and the

154HThree-State LLC Driver sections.

153HThree-

Individual drive strength controls are provided via the DR_STR_XX bits.

When TIM_OE is 0 (default), the HS, VS, and FIELD pins are three-stated according to the TOD bit.

When TIM_OE is 1, HS, VS, and FIELD are forced active all the time.

Drive Strength Selection (Data)

DR_STR[1:0] Address 0xF4[5:4]

For EMC and crosstalk reasons, it can be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR[1:0] bits affect the P[15:0] output drivers.

For more information on three-state control, refer to the Strength Selection (Clock) and the

156HDrive Strength Selection

155HDrive

(Sync) sections.

Table 11. DR_STR Function

DR_STR[1:0] Description

00 Low drive strength (1×) 01 (default) Medium low drive strength (2×) 10 Medium high drive strength (3×) 11 High drive strength (4×)

Rev. B | Page 17 of 100

ADV7183B

Drive Strength Selection (Clock)

DR_STR_C[1:0] Address 0xF4[3:2]

The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the Strength Selection (Data) sections.

Table 12. DR_STR_C Function

DR_STR_C[1:0] Description

00 Low drive strength (1×) 01 (default) Medium low drive strength (2×) 10 Medium high drive strength (3×) 11 High drive strength (4×)

Drive Strength Selection (Sync)

DR_STR_S[1:0] Address 0xF4[1:0]

The DR_STR_S[1:0] bits allow the user to select the strength of the synchronization signals with which HS, VS, and F are driven. For more information, refer to the Selection (Clock) and the sections.

Table 13. DR_STR_S Function

DR_STR_S[1:0] Description

00 Low drive strength (1×) 01 (default) Medium low drive strength (2×) 10 Medium high drive strength (3×) 11 High drive strength (4×)

157HDrive Strength Selection (Sync) and the 158HDrive

159HDrive Strength

160HDrive Strength Selection (Data)

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN Address 0x04[1]

The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as GenLock) from the ADV7183B to an encoder in a decoder-encoder back-to-back arrangement.

When EN_SFL_PIN is 0 (default), the subcarrier frequency lock output is disabled.

When EN_SFL_PIN is 1, the subcarrier frequency lock information is presented on the SFL pin.

Polarity LLC Pin

PCLK Address 0x37[0]

The polarity of the clock that leaves the ADV7183B via the LLC1 and LLC2 pins can be inverted using the PCLK bit.

Changing the polarity of the LLC clock output can be necessary to meet the setup-and-hold time expectations of follow-on chips.

This bit also inverts the polarity of the LLC2 clock.

When PCLK is 0, the LLC output polarity is inverted.

When PCLK is 1 (default), the LLC output polarity is normal (as per the timing diagrams).

Rev. B | Page 18 of 100

ADV7183B

GLOBAL STATUS REGISTERS

Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7183B. The three other registers contain status bits regarding IC operation.

IDENTIFICATION

IDENT[7:0] Address 0x11[7:0]

This register provides identification of the revision of the ADV7183B.

An identification value of 0x11 indicates the ADV7183, released silicon.

An identification value of 0x13 indicates the ADV7183B silicon.

STATUS 1

STATUS_1[7:0] Address 0x10[7:0]

This read-only register provides information about the internal status of the ADV7183B.

See

161HVS_Coast[1:0] Address 0xF9[3:2], 162HCIL[2:0] Count Into

Lock, Address 0x51[2:0], and

163HCOL[2:0] Count Out-of-Lock,

Address 0x51[5:3] for information on the timing.

Depending on the setting of the FSCLE bit, the Status[0] and Status[1] bits are based solely on horizontal timing information on the horizontal timing and lock status of the color subcarrier.

164HFSCLE FSC Lock Enable, Address 0x51[7] section.

See the

AUTODETECTION RESULT

AD_RESULT[2:0] Address 0x10[6:4]

The AD_RESULT[2:0] bits report back on the findings from the autodetection block. For more information on enabling the autodetection block, see the information on configuring it, see the Modes section.

Table 14. AD_RESULT Function

AD_RESULT[2:0] Description

000 NTSM-MJ 001 NTSC-443 010 PAL-M 011 PAL-60 100 PAL-BGHID 101 SECAM 110 PAL-Combination N 111 SECAM 525

165HGeneral Setup section. For

166HAutodetection of SD

Table 15. STATUS 1 Function

STATUS 1[7:0] Bit Name Description

0 IN_LOCK In lock (right now) 1 LOST_LOCK

Lost lock (since last read of

this register) 2 FSC_LOCK FSC locked (right now) 3 FOLLOW_PW

AGC follows peak white

algorithm 4 AD_RESULT.0 Result of autodetection 5 AD_RESULT.1 Result of autodetection 6 AD_RESULT.2 Result of autodetection 7 COL_KILL Color kill active

STATUS 2

STATUS_2[7:0], Address 0x12[7:0]

Table 16. STATUS 2 Function

STATUS 2[7:0] Bit Name Description

0 MVCS DET

Detected Macrovision color striping

1 MVCS T3

Macrovision color striping protection. Conforms to Type 3 if high and to Type 2 if low

2 MV_PS DET

Detected Macrovision pseudo sync pulses

3 MV_AGC DET

Detected Macrovision AGC

pulses 4 LL_NSTD Line length is nonstandard 5 FSC_NSTD FSC frequency is nonstandard 6 Reserved

7 Reserved

STATUS 3

STATUS_3[7:0], Address 0x13[7:0]

Table 17. STATUS 3 Function

STATUS 3[7:0] Bit Name Description

0 INST_HLOCK Horizontal lock indicator

1 GEMD Gemstar detect. 2 SD_OP_50HZ Flags whether 50 Hz or

3 Reserved for future use. 4 FREE_RUN_ACT Outputs a blue screen (see the

5 STD_FLD_LEN Field length is correct for

6 INTERLACED Interlaced video detected

7 PAL_SW_LOCK Reliable sequence of swinging

(instantaneous).

60 Hz are present at output.

167HDEF_VAL_AUTO_EN Default

Value Automatic Enable, Address 0x0C[1] section).

currently selected video standard.

(field sequence found).

bursts detected.

Rev. B | Page 19 of 100

ADV7183B

STANDARD DEFINITION PROCESSOR (SDP)

STANDARD DEFINITION PROCESSOR

DIGITIZED CVBS

DIGITIZED Y (YC)

DIGITIZED CVBS

DIGITIZED C (YC)

MACROVISION

DETECTION

LUMA

DIGITAL

FINE

CLAMP

CHROMA

DIGITAL

FINE

CLAMP

RECOVERY

CHROMA

DEMOD

RECOVERY

VBI DATA

LUMA

FILTER

SYNC

EXTRACT

CHROMA

FILTER

STANDARD

AUTODETECTION

GAIN

CONTROL

LINE

LENGTH

PREDICTOR

GAIN

CONTROL

Figure 8. Block Diagram of the Standard Definition Processor

A block diagram of the ADV7183B’s standard definition processor (SDP) is shown in

168HFigure 8.

The SDP block can handle standard definition video in CVBS, Y/C, and YPrPb formats. It can be divided into a luminance and a chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input.

SD LUMA PATH

The input signal is processed by the following blocks:

• Digital Fine Clamp. This block uses a high precision

algorithm to clamp the video signal.

• Luma Filter Block. This block contains a luma decimation

filter (YAA) with a fixed response and some shaping filters (YSH) that have selectable responses.

• Luma Gain Control. The automatic gain control (AGC)

can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain.

• Luma Resample. To correct for line-length errors as well as

dynamic line-length changes, the data is digitally resampled.

• Luma 2D Comb. The two-dimensional comb filter

provides Y/C separation.

• AV Code Insertion. At this point, the decoded luma (Y)

signal is merged with the retrieved chroma values. AV codes (as per ITU-R. BT-656) can be inserted.

SLLC

CONTROL

LUMA

RESAMPLE

CONTROL

CHROMA

RESAMPLE

LUMA

2D COMB

CHROMA 2D COMB

CODE

INSERTION

VIDEO DATA OUTPUT

MEASUREMENT BLOCK (≥ I

VIDEO DATA PROCESSING BLOCK

04997-008

SD CHROMA PATH

The input signal is processed by the following blocks:

• Digital Fine Clamp. This block uses a high precision

algorithm to clamp the video signal.

• Chroma Demodulation. This block uses a color subcarrier

) recovery unit to regenerate the color subcarrier for

any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC, and an FM demodulation for SECAM.

• Chroma Filter Block. This block contains a chroma

decimation filter (CAA) with a fixed response and some shaping filters (CSH) that have selectable responses.

• Gain Control. Automatic gain control (AGC) can operate

on several different modes, including gain based on the color subcarrier’s amplitude, gain based on the depth of the horizontal sync pulse on the luma channel, or fixed manual gain.

• Chroma Resample. The chroma data is digitally resampled

to keep it perfectly aligned with the luma data. The resampling is done to correct for static and dynamic linelength errors of the incoming video signal.

• Chroma 2D Comb. The two-dimensional, 5-line,

superadaptive comb filter provides high quality Y/C separation when the input signal is CVBS.

• AV Code Insertion. At this point, the demodulated chroma

(Cr and Cb) signal is merged with the retrieved luma values. AV codes (as per ITU-R. BT-656) can be inserted.

Rev. B | Page 20 of 100

ADV7183B

SYNC PROCESSING

The ADV7183B extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources such as VCRs with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this is then used to drive the digital resampling section to ensure the ADV7183B outputs 720 active pixels per line.

The sync processing on the ADV7183B also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video.

• Vsync Processor. This block provides extra filtering of the

detected Vsyncs to give improved vertical lock.

• Hsync Processor. The Hsync processor is designed to filter

incoming Hsyncs that are corrupted by noise, providing much improved performance for video signals with stable time base but poor SNR.

VBI DATA RECOVERY

The ADV7183B can retrieve the following information from the input video:

• Wide-screen signaling (WSS)

• Copy generation management system (CGMS)

• Closed caption (CC)

• Macrovision protection presence

• EDTV data

• Gemstar-compatible data slicing

The ADV7183B is also capable of automatically detecting the incoming video standard with respect to

• Color subcarrier frequency

• Field rate

• Line rate

The SPD can configure itself to support PAL-B/G/H/I/D, PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz, NTSC4.43, and PAL60.

GENERAL SETUP

Video Standard Selection

The VID_SEL[3:0] bits allows the user to force the digital core into a specific video standard. Under normal circumstances, this should not be necessary. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. The following section describes the autodetection system.

Autodetection of SD Modes

To guide the autodetection system, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being detected automatically. Instead, the system picks the closest of the remaining enabled standards. The results of the autodetection can be read back via the status registers. See the Registers section for more information.

VID_SEL[3:0] Address 0x00[7:4]

Table 18. VID_SEL Function

VID_SEL Description

0000 (default)

0001

0010

0011

0100 NTSC-J (1) 0101 NTSC-M (1) 0110 PAL60 0111 NTSC-.43 (1) 1000 PAL-B/G/H/I/D 1001 PAL-N (= PAL BGHID (with pedestal)) 1010 PAL-M (without pedestal) 1011 PAL-M 1100 PAL-Combination N 1101 PAL COMBINATION N (with pedestal) 1110 SECAM 1111 SECAM (with pedestal)

Autodetect (PAL BGHID) <–> NTSC J (no pedestal), SECAM

Autodetect (PAL BGHID) <–> NTSC M (pedestal), SECAM

Autodetect (PAL N) (pedestal) <–> NTSC J (no pedestal), SECAM

Autodetect (PAL N) (pedestal) <–> NTSC M (pedestal), SECAM

AD_SEC525_EN Enable Autodetection of SECAM 525 Line Video, Address 0x07[7]

Setting AD_SEC525_EN to 0 (default) disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component.

Setting AD_SEC525_EN to 1 enables the detection.

169HGlobal Status

Rev. B | Page 21 of 100

ADV7183B

AD_SECAM_EN Enable Autodetection of SECAM, Address 0x07[6]

Setting AD_SECAM_EN to 0 disables the autodetection of SECAM.

Setting AD_SECAM_EN to 1 (default) enables the detection.

AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07[5]

Setting AD_N443_EN to 0 disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier.

Setting AD_N443_EN to 1 (default) enables the detection.

AD_P60_EN Enable Autodetection of PAL60, Address 0x07[4]

Setting AD_P60_EN to 0 disables the autodetection of PAL systems with a 60 Hz field rate.

Setting AD_P60_EN to 1 (default) enables the detection.

AD_PALN_EN Enable Autodetection of PAL N, Address 0x07[3]

Setting AD_PALN_EN to 0 disables the detection of the PAL N standard.

Setting AD_PALN_EN to 1 (default) enables the detection.

AD_PALM_EN Enable Autodetection of PAL M, Address 0x07[2]

Setting AD_PALM_EN to 0 disables the autodetection of PAL M.

Setting AD_PALM_EN to 1 (default) enables the detection.

AD_NTSC_EN Enable Autodetection of NTSC, Address 0x07[1]

Setting AD_NTSC_EN to 0 disables the detection of standard NTSC.

Setting AD_NTSC_EN to 1 (default) enables the detection.

AD_PAL_EN Enable Autodetection of PAL, Address 0x07[0]

Setting AD_PAL_EN to 0 disables the detection of standard PAL.

SFL_INV Subcarrier Frequency Lock Inversion

This bit controls the behavior of the PAL switch bit in the SFL (GenLock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves two problems.

First, the PAL switch bit is only meaningful in PAL. Some encoders (including ADI encoders) also look at the state of this bit in NTSC.

Second, there was a design change in ADI encoders from ADV717x to ADV719x. The older versions used the SFL (Genlock Telegram) bit directly, while the later ones invert the bit prior to using it. The reason for this is that the inversion compensated for the 1-line delay of an SFL (GenLock Telegram) transmission.

As a result, ADV717x encoders need the PAL switch bit in the SFL (Genlock Telegram) to be 1 for NTSC to work, and ADV7190/ADV7191/ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC. If the state of the PAL switch bit is wrong, a 180° phase shift occurs.

In a decoder/encoder back-to-back system in which SFL is used, this bit must be set up properly for the specific encoder used.

SFL_INV Address 0x41[6]

Setting SFL_INV to 0 makes the part SFL-compatible with ADV7190/ADV7191/ADV7194 encoders.

Setting SFL_INV to 1 (default), makes the part SFL-compatible with ADV717x/ADV7173x encoders.

Lock-Related Controls

Lock information is presented to the user through Bits[1:0] of the Status 1 register. See the section.

171HFigure 9 outlines the signal flow and the controls

170HSTATUS_1[7:0] Address 0x10[7:0]

available to influence the way the lock status information is generated.

Setting AD_PAL_EN to 1 (default) enables the detection.

SELECT THE RAW LOCK SIGNAL SRLS

TIME_WIN

FREE_RUN

LOCK

TAKE F

1 0

LOCK INTO ACCOUNT

FSCLE

Figure 9. Lock-Related Signal Path

FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0]

COUNTER INTO LOCK

COUNTER OUT OF LOCK

Rev. B | Page 22 of 100

MEMORY

STATUS 1 [0]

STATUS 1 [1]

04997-009

ADV7183B

SRLS Select Raw Lock Signal, Address 0x51[6]

Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits[1:0] in the Status 1 register).

• The time_win signal is based on a line-to-line evaluation of

the horizontal synchronization pulse of the incoming video. It reacts quite quickly.

• The free_run signal evaluates the properties of the

incoming video over several fields and takes vertical synchronization information into account.

Setting SRLS to 0 (default) selects the free_run signal.

Setting SRLS to 1 selects the time_win signal.

FSCLE FSC Lock Enable, Address 0x51[7]

The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits[1:0] in Status Register 1. This bit must be set to 0 when operating in YPrPb component mode to generate a reliable HLOCK status bit.

Setting FSCLE to 0 (default) makes the overall lock status dependent on only horizontal sync lock.

Setting FSCLE to 1 makes the overall lock status dependent on horizontal sync lock and F

lock.

VS_Coast[1:0] Address 0xF9[3:2]

These bits are used to set VS free-run (coast) frequency.

Table 19. VS_COAST[1:0] Function

VS_COAST[1:0] Description

00 (default)

01 Forces 50 Hz coast mode 10 Forces 60 Hz coast mode 11 Reserved

Auto coast mode—follows VS frequency from last video input

CIL[2:0] Count Into Lock, Address 0x51[2:0]

CIL[2:0] determines the number of consecutive lines for which the lock condition must be true before the system switches into the locked state, and reports this via Status 0[1:0]. It counts the value in lines of video.

Table 20. CIL Function

CIL[2:0] Description

000 1 001 2 010 5 011 10 100 (default) 100 101 500 110 1000 111 100000

COL[2:0] Count Out-of-Lock, Address 0x51[5:3]

COL[2:0] determines the number of consecutive lines for which the out-of-lock condition must be true before the system switches into unlocked state, and reports this via Status 0[1:0]. It counts the value in lines of video.

Table 21. COL Function

COL[2:0] Description

000 1 001 2 010 5 011 10 100 (default) 100 101 500 110 1000 111 100000

COLOR CONTROLS

These registers allow the user to control the picture appearance, including control of the active data in the event of video being lost. These controls are independent of any other controls. For instance, brightness control is independent from picture clamping, although both controls affect the signal’s dc level.

CON[7:0] Contrast Adjust, Address 0x08[7:0]

This allows the user to adjust the contrast of the picture.

Table 22. CON Function

CON[7:0] Description

0x80 (default) Gain on luma channel = 1 0x00 Gain on luma channel = 0 0xFF Gain on luma channel = 2

SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address 0xE3[7:0]

This register allows the user to control the gain of the Cb channel only. The user can adjust the saturation of the picture.

Table 23. SD_SAT_Cb Function

SD_SAT_Cb[7:0] Description

0x80 (default) Gain on Cb channel = 0 dB 0x00 Gain on Cb channel = −42 dB 0xFF Gain on Cb channel = +6 dB

Rev. B | Page 23 of 100

ADV7183B

SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4[7:0]

This register allows the user to control the gain of the Cr channel only. The user can adjust the saturation of the picture.

Table 24. SD_SAT_Cr Function

SD_SAT_Cr[7:0] Description

0x80 (default) Gain on Cr channel = 0 dB 0x00 Gain on Cb channel = −42 dB 0xFF Gain on Cb channel = +6 dB

SD_OFF_Cb[7:0] SD Offset Cb Channel, Address 0xE1[7:0]

This register allows the user to select an offset for data on the Cb channel only and adjust the hue of the picture. There is a functional overlap with the Hue[7:0] register.

Table 25.SD_OFF_Cb Function

SD_OFF_Cb[7:0] Description

0x80 (default) 0 offset applied to the Cb channel 0x00 −312 mV offset applied to the Cb channel 0xFF +312 mV offset applied to the Cb channel

SD_OFF_Cr[7:0] SD Offset Cr Channel, Address 0xE2[7:0]

This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture. There is a functional overlap with the Hue[7:0] register.

Table 26. SD_OFF_Cr Function

SD_OFF_Cr[7:0] Description

0x80 (default) 0 offset applied to the Cr channel 0x00 −312 mV offset applied to the Cr channel 0xFF +312 mV offset applied to the Cr channel

BRI[7:0] Brightness Adjust, Address 0x0A[7:0]

This register controls the brightness of the video signal. It allows the user to adjust the brightness of the picture.

Table 27. BRI Function

BRI[7:0] Description

0x00 (default) Offset of the luma channel = 0IRE 0x7F Offset of the luma channel = +100IRE 0xFF Offset of the luma channel = –100IRE

HUE[7:0] Hue Adjust, Address 0x0B[7:0]

This register contains the value for the color hue adjustment. It allows the user to adjust the hue of the picture.

HUE[7:0] has a range of ±90°, with 0x00 equivalent to an adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.

The hue adjustment value is fed into the AM color demodulation block. Therefore, it applies only to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb).

Table 28. HUE Function

HUE[7:0] Description 0x00 (default) Phase of the chroma signal = 0° 0x7F Phase of the chroma signal = –90° 0x80 Phase of the chroma signal = +90°

DEF_Y[5:0] Default Value Y, Address 0x0C[7:2]

If the ADV7183B loses lock on the incoming video signal or if there is no input signal, the DEF_Y[5:0] bits allow the user to specify a default luma value to be output. This value is used if

• The DEF_VAL_AUTO_EN bit is set to high and the

ADV7183B lost lock to the input video signal. This is the intended mode of operation (automatic mode).

• The DEF_VAL_EN bit is set, regardless of the lock status of

the video decoder. This is a forced mode that may be useful during configuration.

The DEF_Y[5:0] values define the 6 MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 8-bit mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.

DEF_Y[5:0] is 0x0D (blue) is the default value for Y.

DEF_C[7:0] Default Value C, Address 0x0D[7:0]

The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the 4 MSBs of Cr and Cb values to be output if

• The DEF_VAL_AUTO_EN bit is set to high and the

ADV7183B cannot lock to the input video (automatic mode).

• The DEF_VAL_EN bit is set to high (forced output).

The data that is finally output from the ADV7183B for the chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0}.

DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb.

Rev. B | Page 24 of 100

ADV7183B

DEF_VAL_EN Default Value Enable, Address 0x0C[0]

This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. In this mode, the decoder also outputs a stable 27 MHz clock, HS, and VS.

Setting DEF_VAL_EN to 0 (default) outputs a colored screen determined by user-programmable Y, Cr, and Cb values when the decoder free-runs. Free-run mode is turned on and off by the DEF_VAL_AUTO_EN bit.

Setting DEF_VAL_EN to 1 forces a colored screen output determined by user-programmable Y, Cr, and Cb values. This overrides picture data even if the decoder is locked.

DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C[1]

This bit enables the automatic usage of the default values for Y, Cr, and Cb when the ADV7183B cannot lock to the video signal.

Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If the decoder is unlocked, it outputs noise.

Setting DEF_VAL_EN to 1 (default) enables free-run mode. A colored screen set by the user-programmable Y, Cr, and Cb values is displayed when the decoder loses lock.

CLAMP OPERATION

The input video is ac-coupled into the ADV7183B through a

0.1 F capacitor. The recommended range of the input video signal is 0.5 V to 1.6 V (typically 1 V p-p). If the signal exceeds this range, it cannot be processed correctly in the decoder. Since the input signal is ac-coupled into the decoder, its dc value needs to be restored. This process is referred to as clamping the video. This section explains the general process of clamping on the ADV7183B and shows the different ways in which a user can configure its behavior.

The ADV7183B uses a combination of current sources and a digital processing block for clamping, as shown in The analog processing channel shown is replicated three times inside the IC. While only one single channel (and only one ADC) is needed for a CVBS signal, two independent channels are needed for Y/C (S-VHS) type signals, and three independent channels are needed to allow component signals (YPrPb) to be processed.

FINE CURRENT SOURCES

172HFigure 10.

COARSE CURRENT SOURCES

The clamping can be divided into two sections:

• Clamping before the ADC (analog domain): current sources

• Clamping after the ADC (digital domain): digital

processing block

The ADCs can digitize an input signal only if it resides within the ADC’s 1.6 V input voltage range. An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range.

The primary task of the analog clamping circuits is to ensure the video signal stays within the valid ADC input window so that the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range.

After digitization, the digital fine clamp block corrects for any remaining variations in dc level. Since the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations can occur. Furthermore, dynamic changes in the dc level almost certainly lead to visually objectionable artifacts and must therefore be prohibited.

The clamping scheme has to be able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation.

For quickly acquiring an unknown video signal, the large current clamps can be activated. (It is assumed that the amplitude of the video signal at this point is of a nominal value.) Control of the coarse and fine current clamp parameters is performed automatically by the decoder.

Standard definition video signals can have excessive noise on them. In particular, CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mV). A voltage clamp is unsuitable for this type of video signal. Instead, the ADV7183B uses a set of four current sources that can cause coarse (>0.5 mA) and fine (<0.1 mA) currents to flow into and away from the high impedance node that carries the video signal (see

173HFigure 10).

NALO

VIDEO

INPUT

ADC

Figure 10. Clamping Overview

Rev. B | Page 25 of 100

DATA

PRE-

PROCESSOR

(DPP)

CLAMP CONTROL

SDP

WITH DIGITAL

FINE CLAMP

04997-010

ADV7183B

The following sections describe the I2C signals that can be used to influence the behavior of the clamps on the ADV7183B.

Previous revisions of the ADV7183B had controls (FACL/FICL, fast and fine clamp length) to allow configuration of the length for which the coarse (fast) and fine current sources are switched on. These controls were removed on the ADV7183B-FT and replaced by an adaptive scheme.

CCLEN Current Clamp Enable, Address 0x14[4]

The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether. This can be useful if the incoming analog video signal is clamped externally.

When CCLEN is 0, the current sources are switched off.

When CCLEN is 1 (default), the current sources are enabled.

DCT[1:0] Digital Clamp Timing, Address 0x15[6:5]

The clamp timing register determines the time constant of the digital fine clamp circuitry. It is important to realize that the digital fine clamp reacts very quickly because it is supposed to immediately correct any residual dc level error for the active line. The time constant of the digital fine clamp must be much faster than the one from the analog blocks.

By default, the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal.

Table 29. DCT Function

DCT[1:0] Description

00 Slow (TC = 1 sec) 01 Medium (TC = 0.5 sec) 10 (default) Fast (TC = 0.1 sec) 11

DCFE Digital Clamp Freeze Enable, Address 0x15[4]

This register bit allows the user to freeze the digital clamp loop at any time. It is intended for users who would like to do their own clamping. Users should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the DCFE bit.

When DCFE is 0 (default), the digital clamp is operational.

When DCFE is 1, the digital clamp loop is frozen.

Determined by the ADV7183B, depending on the I/P video parameters

LUMA FILTER

Data from the digital fine clamp block is processed by three sets of filters. The data format at this point is CVBS for CVBS input or luma only for Y/C and YPrPb input formats.

• Luma Antialias Filter (YAA). The ADV7183B receives

video at a rate of 27 MHz. (For 4× oversampled video, the ADCs sample at 54 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the SDP core is always 27 MHz.) The ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video using a high quality, linear phase, low-pass filter that preserves the luma signal while at the same time attenuating out-of-band components. The luma antialias filter has a fixed response.

• Luma Shaping Filters (YSH). The shaping filter block is a

programmable low-pass filter with a wide variety of responses. It can be used to selectively reduce the luma video signal bandwidth (needed prior to scaling, for example). For some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. A follow-on video compression stage can work more efficiently if the video is low-pass filtered.

The ADV7183B has two responses for the shaping filter: one that is used for good quality CVBS, component, and S-VHS type sources, and a second for nonstandard CVBS signals.

The YSH filter responses also include a set of notches for PAL and NTSC. However, using the comb filters for Y/C separation is recommended.

• Digital Resampling Filter. This block is used to allow

dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is selected by the system, and user intervention is not required.

174HFigure 12 through 175HFigure 15 show the overall response of all

filters together. Unless otherwise noted, the filters are set into a typical wideband mode.

Rev. B | Page 26 of 100

ADV7183B

Y-Shaping Filter

For input signals in CVBS format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. Y/C separation must aim for best possible crosstalk reduction while still retaining as much bandwidth (especially on the luma component) as possible. High quality Y/C separation can be achieved by using the internal comb filters of the ADV7183B. Comb filtering, however, relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (F

). For good quality

CVBS signals, this relationship is known; the comb filter algorithms can be used to separate out luma and chroma with high accuracy.

For nonstandard video signals, the frequency relationship may be disturbed, and the comb filters may not be able to optimally remove all crosstalk artifacts without the assistance of the shaping filter block.

An automatic mode is provided. The ADV7183B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to manually override the automatic decisions in part or in full.

The luma shaping filter has three control registers:

• YSFM[4:0] allows the user to manually select a shaping

filter mode (applied to all video signals) or to enable an automatic selection (dependent on video quality and video standard).

• WYSFMOVR allows the user to manually override the

WYSFM decision.

• WYSFM[4:0] allows the user to select a different shaping

filter mode for good quality CVBS, component (YPrPb), and S-VHS (Y/C) input signals.

In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources, since they can successfully be combed, as well as for luma components of YPrPb and Y/C sources, since they need not be combed. For poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation to reduce visual artifacts.

The decisions of the control logic are shown in

176HFigure 11.

YSFM[4:0] Y-Shaping Filter Mode, Address 0x17[4:0]

The Y shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters. When switched in automatic mode, the filter is selected based on other register selections (for example, detected video standard) as well as properties extracted from the incoming video itself (for example, quality, time-base stability). The automatic selection always selects the widest possible bandwidth for the video input encountered.

If the YSFM settings specify a filter (where YSFM is set to values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality.

In automatic selection mode, the notch filters are used only for bad quality video signals. For all other video signals, wideband filters are used.

WYSFMOVR Wideband Y-Shaping Filter Override, Address 0x18[7]

Setting the WYSFMOVR bit enables the use of the WYSFM[4:0] settings for good quality video signals. For more information, refer to the general discussion of the luma shaping filters in the in

178HFigure 11.

177HY-Shaping Filter section and the flowchart shown

When WYSFMOVR is 0, the shaping filter for good quality video signals is selected automatically.

Setting WYSFMOVR to 1 enables manual override via WYSFM[4:0] (default).

Rev. B | Page 27 of 100

ADV7183B

SET YSFM

BAD GOOD

AUTO SELECT LUMA SHAPING FILTER TO

COMPLEMENT COMB

Table 30. YSFM Function

YSFM[4:0] Description

0'0000

Automatic selection including a wide notch response (PAL/NTSC/SECAM)

0'0001 (default)

Automatic selection including a narrow notch

response (PAL/NTSC/SECAM) 0'0010 SVHS 1 0'0011 SVHS 2 0'0100 SVHS 3 0'0101 SVHS 4 0'0110 SVHS 5 0'0111 SVHS 6 0'1000 SVHS 7 0'1001 SVHS 8 0'1010 SVHS 9 0'1011 SVHS 10 0'1100 SVHS 11 0'1101 SVHS 12 0'1110 SVHS 13 0'1111 SVHS 14 1'0000 SVHS 15 1'0001 SVHS 16 1'0010 SVHS 17 1'0011 SVHS 18 (CCIR 601) 1'0100 PAL NN 1 1'0101 PAL NN 2 1'0110 PAL NN 3 1'0111 PAL WN 1 1'1000 PAL WN 2 1'1001 NTSC NN 1 1'1010 NTSC NN 2 1'1011 NTSC NN 3 1'1100 NTSC WN 1 1'1101 NTSC WN 2 1'1110 NTSC WN 3 1'1111 Reserved

YES NO

VIDEO

QUALITY

1 0

SELECT WIDEBAND

FILTER AS PER

WYSFM[4:0]

Figure 11. YSFM and WYSFM Control Flowchart

YSFM IN AUTO MODE?

00000 OR 00001

WYSFMOVR

SELECT AUTOMATIC

WIDEBAND FILTER

WYSFM[4:0] Wideband Y-Shaping Filter Mode, Address 0x18[4:0]

The WYSFM[4:0] bits allow the user to manually select a shaping filter for good quality video signals, for example, CVBS with time-base stability, luma component of YPrPb and luma component of Y/C. The WYSFM bits are active only if the WYSFMOVR bit is set to 1. See the general discussion of the shaping filter settings in the

Table 31. WYSFM Function

WYSFM[4:0] Description

0'0000 Do not use 0'0001 Do not use 0'0010 SVHS 1 0'0011 SVHS 2 0'0100 SVHS 3 0'0101 SVHS 4 0'0110 SVHS 5 0'0111 SVHS 6 0'1000 SVHS 7 0'1001 SVHS 8 0'1010 SVHS 9 0'1011 SVHS 10 0'1100 SVHS 11 0'1101 SVHS 12 0'1110 SVHS 13 0'1111 SVHS 14 1'0000 SVHS 15 1'0001 SVHS 16 1'0010 SVHS 17 1'0011 (default) SVHS 18 (CCIR 601) 1'0100 to 1’1111 Do not use

USE YSFM SELECTED

FILTER REGARDLESS FOR

GOOD AND BAD VIDEO

179HY-Shaping Filter section.

04997-011

Rev. B | Page 28 of 100

ADV7183B

The filter plots in 180HFigure 12 show the S-VHS 1 (narrowest) to S-VHS 18 (widest) shaping filter settings.

181HFigure 14 shows the

PAL notch filter responses. The NTSC-compatible notches are shown in

182HFigure 15.

COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,

–10

–20

–30

–40

AMPLITUDE (dB)

–50

–60

–70

010864212

Figure 12. Y S-VHS Combined Responses

COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,

–20

–40

–60

AMPLITUDE (dB)

–80

–100

–120

010864212

Figure 13. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)

COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,

–10

–20

Y RESAMPLE

FREQUENCY (MHz)

Y RESAMPLE

FREQUENCY (MHz)

Y RESAMPLE

04997-012

04997-013

COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,

–10

–20

–30

–40

AMPLITUDE (dB)

–50

–60

–70

010864212

Figure 15. NTSC Notch Filter Response

Y RESAMPLE

FREQUENCY (MHz)

04997-015

CHROMA FILTER

Data from the digital fine clamp block is processed by three sets of filters. The data format at this point is CVBS for CVBS inputs, chroma only for Y/C, or U/V interleaved for YPrPb input formats.

• Chroma Antialias Filter (CAA). The ADV7183B over-

samples the CVBS by a factor of 2 and the Chroma/PrPb by a factor of 4. A decimating filter (CAA) is used to preserve the active video band and to remove any out-ofband components. The CAA filter has a fixed response.

• Chroma Shaping Filters (CSH). The shaping filter block

(CSH) can be programmed to perform a variety of lowpass responses. It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression.

• Digital Resampling Filter. This block is used to allow

The plots in

183HFigure 16 show the overall response of all filters

together.

–30

–40

AMPLITUDE (dB)

–50

–60

–70

010864212

Figure 14. PAL Notch Filter Response

FREQUENCY (MHz)

04997-014

Rev. B | Page 29 of 100

ADV7183B

CSFM[2:0] C- Shaping Filter Mode, Address 0x17[7]

The C-shaping filter mode bits allow the user to select from a range of low-pass filters, SH1 to SH5 and wideband mode for the chrominance signal. The autoselection options automatically select from the filter options to give the specified response. (See settings 000 and 001 in

Table 32. CSFM Function

CSFM[2:0] Description

000 (default) Autoselect 1.5 MHz bandwidth 001 Autoselect 2.17 MHz bandwidth 010 SH1 011 SH2 100 SH3 101 SH4 110 SH5 111 Wideband mode

COMBINED C ANTIALIAS, C SHAPING FILTER,

C RESAMPLER

184HTable 32).

GAIN OPERATION

The gain control within the ADV7183B is performed strictly on a digital basis. The input ADCs support a 10-bit range, mapped into a 1.6 V analog voltage range. Gain correction occurs after the digitization in the form of a digital multiplier.

One advantage of this architecture over the commonly used programmable gain amplifier (PGA) before the ADCs is that the gain is now completely independent of supply, temperature, and process variations.

As shown in signal providing it fits into the ADC window. Two components to this are the amplitude of the input signal and the dc level on which it resides. The dc level is set by the clamping circuitry (see the

If the amplitude of the analog video signal is too high, clipping can occur, resulting in visual artifacts. The analog input range of the ADC, together with the clamp level, determines the maximum supported amplitude of the video signal.

186HFigure 17, the ADV7183B can decode a video

187HClamp Operation section).

–10

–20

–30

–40

ATTENUATION (dB)

–50

–60

0543216

FREQUENCY (MHz)

Figure 16. Chroma Shaping Filter Responses

185HFigure 16 shows the responses of SH1 (narrowest) to SH5

(widest) and the wide band mode (in red).

MAXIMUM VOLTAGE

The minimum supported amplitude of the input video is determined by the ADV7183B’s ability to retrieve horizontal and vertical timing and to lock to the color burst, if present.

There are two gain control units, one each for luma and chroma data. Both can operate independently of each other. The chroma unit, however, can also take its gain value from the luma path.

The possible AGC modes are summarized in

It is possible to freeze the automatic gain control loops. This

04997-016

causes the loops to stop updating and the AGC determined gain, at the time of the freeze, to stay active. The ACG determined gain stays active until the automatic gain control loop is either unfrozen, or the gain mode of the operation is changed.

The currently active gain from any of the modes can be read back. Refer to the description of the dual function manual gain registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in

189HLuma Gain and 190HChroma Gain sections.

the

ANALOG VOLTAGE RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7189B)

188HTable 33.

MINIMUM VOLTAGE

CLAMP

LEVEL

DATA

ADC

PRE-

PROCESSOR

(DPP)

Figure 17. Gain Control Overview

Rev. B | Page 30 of 100

SDP (GAIN SELECTION ONLY)

GAIN

CONTROL

04983-017

+ 70 hidden pages

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