Analog Devices ADV7183B Datasheet
Multiformat SDTV Video Decoder
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 10-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™), signal
processing, and enhanced FIFO management give mini
TBC functionality
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats:
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
12 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit):
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
GENERAL DESCRIPTION
The ADV7183B integrated video decoder automatically detects
and converts a standard analog baseband television signalcompatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data-compatible with 16-/8-bit
CCIR601/CCIR656.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in linelocked clock-based systems. This makes the device ideally
suited for a broad range of applications with diverse analog
video characteristics, including tape based sources, broadcast
sources, security/surveillance cameras, and professional
systems.
The 10-bit accurate A/D conversion provides professional
quality video performance and is unmatched. This allows true
8-bit resolution in the 8-bit output mode.
The 12 analog input channels accept standard Composite,
S-Video, YPrPb video signals in an extensive number of
ADV7183B
0.5 V to 1.6 V analog signal input range
Differential gain: 0.5% typ
Differential phase: 0.5° typ
Programmable video controls:
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video ouput with no I/P)
VBI decode support for close captioning, WSS, CGMS, EDTV,
Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
2 temperature grades: –25°C to +70°C and –40°C to +85°C
80-lead LQFP Pb-free package
APPLICATIONS
DVD recorders
Video projectors
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
AVR receiver
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V up to 1.6 V.
Alternatively, these can be bypassed for manual settings.
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length variation.
The output control signals allow glueless interface connections
in almost any application. The ADV7183B modes are set up
over a 2-wire, serial, bidirectional port (I
The ADV7183B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7183B is packaged in a small 80-lead LQFP Pb-free
package.
2
C®-compatible)
2
C-compatible).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
ADV7183B
TABLE OF CONTENTS
Introduction ...................................................................................... 3
Analog Front End......................................................................... 3
Standard Definition Processor (SDP)........................................ 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Electrical Characteristics ............................................................. 5
Video Specifications..................................................................... 6
Timing Specifications .................................................................. 7
Analog Specifications................................................................... 7
Thermal Specifications ................................................................ 8
Timing Diagrams.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Analog Front End........................................................................... 12
Analog Input Muxing ................................................................ 12
Global Control Registers ............................................................... 15
Power-Save Modes...................................................................... 15
Reset Control .............................................................................. 15
Global Pin Control..................................................................... 16
Global Status Registers................................................................... 18
Identification............................................................................... 18
Status 1......................................................................................... 18
Autodetection Result.................................................................. 18
Status 2......................................................................................... 18
Status 3......................................................................................... 19
Standard Definition Processor (SDP).......................................... 20
SD Luma Path ............................................................................. 20
SD Chroma Path......................................................................... 20
Sync Processing........................................................................... 21
VBI Data Recovery..................................................................... 21
General Setup.............................................................................. 21
Color Controls............................................................................ 23
Clamp Operation........................................................................ 25
REVISION HISTORY
9/04—Revision 0: Initial Version
Luma Filter.................................................................................. 26
Chroma Filter.............................................................................. 29
Gain Operation........................................................................... 30
Chroma Transient Improvement (CTI) .................................. 33
Digital Noise Reduction (DNR)............................................... 34
Comb Filters................................................................................ 35
AV Code Insertion and Controls ............................................. 37
Synchronization Output Signals............................................... 39
Sync Processing .......................................................................... 46
VBI Data Decode ....................................................................... 47
Pixel Port Configuration ............................................................... 59
MPU Port Description................................................................... 60
Register Accesses........................................................................ 61
Register Programming............................................................... 61
2
I
C Sequencer.............................................................................. 61
2
P
IP
C Register Maps........................................................................... 62
2
P
IP
C Register Map Details ........................................................... 66
2
I
C Programming Examples.......................................................... 88
Mode 1 CVBS Input (Composite Video on AIN5)................ 88
Mode 2 S-Video Input (Y on AIN1 and C on AIN4)............ 88
Mode 3 525i/625i YPrPb Input (Y on AIN2, Pr on AIN3, and
Pb on AIN6)................................................................................ 89
Mode 4 CVBS Tuner Input PAL Only on AIN4 .................... 89
PCB Layout Recommendations.................................................... 90
Analog Interface Inputs............................................................. 90
Power Supply Decoupling......................................................... 90
PLL ............................................................................................... 90
Digital Outputs (Both Data and Clocks) ................................ 90
Digital Inputs.............................................................................. 91
Antialiasing Filters ..................................................................... 91
Typical Circuit Connection........................................................... 92
Outline Dimensions....................................................................... 94
Ordering Guide .......................................................................... 94
Rev. 0 | Page 2 of 96
ADV7183B
INTRODUCTION
The ADV7183B is a high quality, single chip, multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-Video, and
component video into a digital ITU-R BT.656 format.
The advanced and highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video characteristics, including tape based sources, broadcast sources,
security/surveillance cameras, and professional systems.
ANALOG FRONT END
The ADV7183B analog front end comprises three 10-bit ADCs
that digitize the analog video signal before applying it to the
standard definition processor. The analog front end employs
differential channels to each ADC to ensure high performance
in mixed-signal applications.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7183B. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping within the ADV7183B.
The ADCs are configured to run in 4× oversampling mode.
STANDARD DEFINITION PROCESSOR (SDP)
The ADV7183B is capable of decoding a large selection of
baseband video signals in composite, S-Video, and component
formats. The video standards supported include PAL B/D/I/G/H,
PAL60, PA L M , PAL N, PA L Nc , NTSC M / J, N T SC 4.43 , an d
SECAM B/D/G/K/L. The ADV7183B can automatically detect
the video standard and process it accordingly.
The ADV7183B has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
Video user controls such as brightness, contrast, saturation, and
hue are also available within the ADV7183B.
The ADV7183B implements a patented adaptive digital linelength tracking (ADLLT) algorithm to track varying video line
lengths from sources. ADLLT enables the ADV7183B to track
and decode poor quality video sources such as VCRs, noisy
sources from tuner outputs, VCD players, and camcorders. The
ADV7183B contains a chroma transient improvement (CTI)
processor that sharpens the edge rate of chroma transitions,
resulting in sharper vertical transitions.
The ADV7183B can process a variety of VBI data services, such
as closed captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), EDTV, Gemstar 1×/2×,
and extended data service (XDS). The ADV7183B is fully
Macrovision® certified; detection circuitry enables Type I, II,
and III protection levels to be identified and reported to the
user. The decoder is also fully robust to all Macrovision signal
inputs.
Rev. 0 | Page 3 of 96
ADV7183B
FUNCTIONAL BLOCK DIAGRAM
8
PIXEL
DATA
8
HS
VS
FIELD
OUTPUT FORMATTER
16
LLC1
LLC2
SFL
INTRQ
LUMA
(4H MAX)
2D COMB
LUMA
RESAMPLE
GAIN
CONTROL
LUMA
FILTER
STANDARD DEFINITION PROCESSOR
FINE
LUMA
CLAMP
DIGITAL
10
10
L-DNR
AV
LINE
CODE
INSERTION
CONTROL
RESAMPLE
LENGTH
PREDICTOR
SYNC
EXTRACT
F
CTI
SC
C-DNR
RECOVERY
(4H MAX)
CHROMA
2D COMB
CHROMA
RESAMPLE
GAIN
CONTROL
FILTER
CHROMA
DEMOD
CHROMA
FINE
CLAMP
DIGITAL
CHROMA
FREE RUN
SYNTHESIZED
LLC CONTROL
OUTPUT CONTROL
STANDARD
AUTODETECTION
DETECTION
MACROVISION
VBI DATA RECOVERY GLOBAL CONTROL
DATA
10
12
PREPROCESSOR
A/DCLAMP
AIN1–AIN12
FILTERS
DOWNSAMPLING
DECIMATION AND
10
A/DCLAMP10A/DCLAMP
MUX
INPUT
CVBS
YPrPb
S-VIDEO
SYNC AND
CLK CONTROL
CLOCK GENERATION
SYNC PROCESSING AND
Figure 1.
Rev. 0 | Page 4 of 96
ADV7183B
CONTROL
AND DATA
SERIAL INTERFACE
CONTROL AND VBI DATA
SDA
SCLK
ALSB
04997-0-001
ADV7183B
SPECIFICATIONS
Temperature range: T
ELECTRICAL CHARACTERISTICS
At A
= 3.15 V to 3.45 V, D
VDD
otherwise noted).
Table 1.
Parameter Symbol Test Conditions Min Typ Max Unit
STATIC PERFORMANCE
Resolution (Each ADC) N 10 Bits
Integral Nonlinearity INL BSL at 54 MHz –0.475/+0.6 ±3 LSB
Differential Nonlinearity DNL BSL at 54 MHz –0.25/+0.5 –0.7/+2 LSB
DIGITAL INPUTS
Input High Voltage VIH 2 V
Input Low Voltage VIL 0.8 V
Input Current IIN Pins listed in Note 1 –50 +50 µA
All other pins –10 +10 µA
Input Capacitance CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage VOH I
Output Low Voltage VOL I
High Impedance Leakage Current I
All other pins 10 µA
Output Capacitance C
POWER REQUIREMENTS3
Digital Core Power Supply D
Digital I/O Power Supply D
PLL Power Supply P
Analog Power Supply A
Digital Core Supply Current I
Digital I/O Supply Current I
PLL Supply Current I
Analog Supply Current I
YPrPb input5 180 mA
Power-Down Current I
Power-Up Time t
1
Pins 36 and 79.
2
Pins 1, 2, 5, 6, 8, 12, 17, 18–24, 32–35, 74–76, 80.
3
Guaranteed by characterization.
4
ADC1 powered on.
5
All three ADCs powered on.
MIN
to T
, –40°C to +85°C. The min/max specifications are guaranteed over this range.
MAX
= 1.65 V to 2.0 V, D
VDD
= 3.0 V to 3.6 V, P
VDDIO
= 0.4 mA 2.4 V
SOURCE
= 3.2 mA 0.4 V
SINK
Pins listed in Note 2 50 µA
LEAK
20 pF
OUT
1.65 1.8 2 V
VDD
3.0 3.3 3.6 V
VDDIO
1.65 1.8 2.0 V
VDD
3.15 3.3 3.45 V
VDD
82 mA
DVDD
2 mA
DVDDIO
10.5 mA
PVDD
CVBS input4 85 mA
AVDD
1.5 mA
PWRDN
20 ms
PWRUP
= 1.65 V to 2.0 V (operating temperature range, unless
VDD
Rev. 0 | Page 5 of 96
ADV7183B
VIDEO SPECIFICATIONS
Guaranteed by characterization. At A
(operating temperature range, unless otherwise noted).
Table 2.
Parameter Symbol Test Conditions Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS I/P, modulate 5-step 0.5 0.7 °
Differential Gain DG CVBS I/P, modulate 5-step 0.5 0.7 %
Luma Nonlinearity LNL CVBS I/P, 5-step 0.5 0.7 %
NOISE SPECIFICATIONS
SNR Unweighted Luma ramp 54 56 dB
Luma flat field 58 60 dB
Analog Front End Crosstalk 60 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range –5 +5 %
Vertical Lock Range 40 70 Hz
Fsc Subcarrier Lock Range ±1.3 Hz
Color Lock In Time 60 Lines
Sync Depth Range 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Autodetection Switch Speed 100 Lines
CHROMA SPECIFICATIONS
Hue Accuracy HUE 1 °
Color Saturation Accuracy CL_AC 1 %
Color AGC Range 5 400 %
Chroma Amplitude Error 0.5 %
Chroma Phase Error 0.4 °
Chroma Luma Intermodulation 0.2 %
LUMA SPECIFICATIONS
Luma Brightness Accuracy CVBS, 1 V I/P 1 %
Luma Contrast Accuracy CVBS, 1 V I/P 1 %
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDD
= 3.0 V to 3.6 V, P
VDDIO
= 1.65 V to 2.0 V
VDD
Rev. 0 | Page 6 of 96
ADV7183B
TIMING SPECIFICATIONS
Guaranteed by characterization. At A
(operating temperature range, unless otherwise noted).
Table 3.
Parameter Symbol Test Conditions Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency 27.00 MHz
Frequency Stability ±50 ppm
I2C PORT
SCLK Frequency 400 kHz
SCLK Min Pulse Width High t1 0.6 µs
SCLK Min Pulse Width Low t2 1.3 µs
Hold Time (Start Condition) t3 0.6 µs
Setup Time (Start Condition) t4 0.6 µs
SDA Setup Time t5 100 ns
SCLK and SDA Rise Time t6 300 ns
SCLK and SDA Fall Time t7 300 ns
Setup Time for Stop Condition t8 0.6 µs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio t9:t10 45:55 55:45
LLC1 Rising to LLC2 Rising t11 0.5 ns
LLC1 Rising to LLC2 Falling t12 0.5 ns
DATA AND CONTROL OUTPUTS
Data Output Transitional Time t13
Data Output Transitional Time t14
Propagation Delay to Hi-Z t15 6 ns
Max Output Enable Access Time t16 7 ns
Min Output Enable Access Time t17 4 ns
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDD
= 3.0 V to 3.6 V, P
VDDIO
Negative clock edge to start of valid
= t
data. (t
ACCESS
10
– t13)
End of valid data to negative clock
edge. (t
= t9 + t14)
HOLD
= 1.65 V to 2.0 V
VDD
% Duty
Cycle
3.4 ns
2.4 ns
ANALOG SPECIFICATIONS
Guaranteed by characterization. At A
(operating temperature range, unless otherwise noted).
Table 4.
Parameter Symbol Test Conditions Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 µF
Input Impedance Clamps switched off 10 MΩ
Large Clamp Source Current 0.75 mA
Large Clamp Sink Current 0.75 mA
Fine Clamp Source Current 60 µA
Fine Clamp Sink Current 60 µA
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDD
Rev. 0 | Page 7 of 96
= 3.0 V to 3.6 V, P
VDDIO
= 1.65 V to 2.0 V
VDD
ADV7183B
THERMAL SPECIFICATIONS
Table 5.
Parameter Symbol Test Conditions Min Typ Max Unit
Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane 7.6 °C/W
Junction-to-Ambient Thermal Resistance (Still Air) θJA 4-layer PCB with solid ground plane 38.1 °C/W
TIMING DIAGRAMS
SDA
SCLK
t
t
1
t
7
5
Figure 2. I
2
C Timing
t
3
t
6
t
2
t
3
t
4
t
8
04997-0-003
OUTPUT LLC 1
OUTPUT LLC 2
OUTPUTS P0–P15, VS,
HS, FIELD,
SFL
Figure 3. Pixel Port and Control Output Timing
t
9
t
11
t
10
t
12
t
13
t
14
04997-0-004
OE
t
15
04997-0-005
P0–P15, HS,
VS, FIELD,
SFL
t
17
t
16
Figure 4.
OE
Timing
Rev. 0 | Page 8 of 96
ADV7183B
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
A
to GND 4 V
VDD
A
to AGND 4 V
VDD
D
to DGND 2.2 V
VDD
P
to AGND 2.2 V
VDD
D
to DGND 4 V
VDDIO
D
to AVDD –0.3 V to +0.3 V
VDDIO
P
to D
VDD
D
VDDIO
D
VDDIO
A
VDD
A
VDD
Digital Inputs Voltage to DGND –0.3V to D
Digital Output Voltage to DGND –0.3V to D
Analog Inputs to AGND AGND – 0.3 V to A
Maximum Junction Temperature
(T
–0.3 V to +0.3 V
VDD
– P
–0.3V to +2 V
VDD
– D
–0.3V to +2 V
VDD
– P
–0.3V to +2 V
VDD
– D
–0.3V to +2 V
VDD
max)
J
150°C
VDDIO
VDDIO
+ 0.3 V
+ 0.3 V
VDD
+ 0.3 V
Storage Temperature Range –65°C to +150°C
Infrared Reflow Soldering (20 s) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 96
ADV7183B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FIELD80OE79NC78NC77P1276P1375P1474P1573DVDD72DGND71NC70NC69SCLK68SDA67ALSB66NC65RESET64NC63AIN662AIN12
VS 1
2
HS
3
DGND
DVDDIO 4
P11 5
P10 6
P9 7
8
P8
9
DGND
DVDD 10
11
INTRQ
SFL 12
NC 13
DGND 14
15
DVDDIO
16
NC
NC 17
NC 18
P7 19
P6 20
P521P422P323P2
NC = NO CONNECT
ADV7183B
TOP VIEW
(Not to Scale)
24NC25
27
28
LLC226LLC1
29
30
31P132P033NC34NC35
XTAL
DVDD
XTAL1
DGND
Figure 5. 80-Lead LQFP Pin Configuration
61
AIN560
59
AIN11
58
AIN4
AIN1057
AGND56
CAPC255
CAPC154
53
AGND
52
CML
REFOUT51
AVDD50
CAPY249
CAPY148
AGND47
46
AIN3
45
AIN9
AIN244
AIN843
AIN142
AIN741
36
37
38
40
ELPF
PVDD
PWRDN
AGND39AGND
04997-0-002
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type Function
3, 9, 14, 31, 71 DGND G Digital Ground.
39, 40, 47, 53, 56 AGND G Analog Ground.
4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V).
10, 30, 72 DVDD P Digital Core Supply Voltage (1.8 V).
50 AVDD P Analog Supply Voltage (3.3 V).
38 PVDD P PLL Supply Voltage (1.8 V).
42, 44, 46, 58, 60,
AIN1–AIN12 I Analog Video Input Channels.
62, 41, 43, 45, 57,
59, 61
11
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in Table 82.
13, 16–18, 25, 34,
NC No Connect Pins.
35, 63, 65, 69, 70,
77, 78
33, 32, 24, 23, 22,
P0–P15 O Video Pixel Output Port.
21, 20, 19, 8, 7, 6, 5,
76, 75, 74, 73
2 HS O Horizontal Synchronization Output Signal.
1 VS O Vertical Synchronization Output Signal.
80 FIELD O Field Synchronization Output Signal.
67 SDA I/O I2C Port Serial Data Input/Output Pin.
68 SCLK I I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).
66 ALSB I
This pin selects the I
2
C address for the ADV7183B. ALSB set to Logic 0 sets the address for a
write as 0x40; for ALSB set to logic high, the address selected is 0x42.
Rev. 0 | Page 10 of 96
ADV7183B
Pin No. Mnemonic Type Function
64
27 LLC1 O
26 LLC2 O
29 XTAL I
28 XTAL1 O
36
79
37 ELPF I
12 SFL O
51 REFOUT O
52 CML O
48, 49 CAPY1, CAPY2 I
54, 55 CAPC1, CAPC2 I
RESET
PWRDN
OE
I
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7183B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7183B. Nominally
27 MHz, but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the
ADV7183B. Nominally 13.5 MHz, but varies up or down according to video line length.
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 27 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183B. In crystal mode, the
crystal must be a fundamental crystal.
I
A logic low on this pin places the ADV7183B in a power-down mode. Refer to the I
Register Maps section for more options on power-down modes for the ADV7183B.
I
When set to a logic low, OE enables the pixel output bus, P15–P0 of the ADV7183B. A logic
high on the OE pin places Pins P15–P0, HS, VS, SFL/SYNC_OUT into a high impedance state.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 45.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital
video encoder.
Internal Voltage Reference Output. Refer to Figure 45 for a recommended capacitor
network for this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to Figure 45 for a
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 45 for a recommended capacitor network for
this pin.
ADC’s Capacitor Network. Refer to Figure 45 for a recommended capacitor network for
this pin.
2
C
Rev. 0 | Page 11 of 96
ADV7183B
ANALOG FRONT END
ANALOG INPUT MUXING
AIN1
AIN7
AIN2
AIN8
AIN3
AIN9
AIN4
ADC_SW_MAN_EN INSEL[3:0]
AIN12
AIN6
AIN11
AIN5
AIN10
AIN1
AIN7
AIN2
AIN8
AIN3
AIN9
AIN4
AIN10
AIN5
AIN11
AIN6
AIN12
AIN3
AIN9
AIN4
AIN10
AIN5
AIN11
AIN6
AIN12
1
0
1
0
ADC0_SW[3:0]
ADC0
ADC1_SW[3:0]
ADC1
INTERNAL
MAPPING
FUNCTIONS
Figure 6. Internal Pin Connections
The ADV7183B has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder. Figure 6 outlines the overall structure of the input
muxing provided in the ADV7183B.
As seen in Figure 6, the analog input muxes can be controlled
by functional registers (INSEL) or manually. Using INSEL[3:0]
simplifies the setup of the muxes, and minimizes crosstalk
between channels by pre-assigning the input channels. This is
referred to as ADI recommended input muxing.
2
Control via an I
C manual override (ADC_sw_man_en,
ADC0_sw, ADC1_sw, ADC2_sw) is provided for applications
with special requirements (for example, number/combinations
of signals) that would not be served by the pre-assigned input
connections. This is referred to as manual input muxing.
Refer to Figure 7 for an overview of the two methods of
controlling the ADV7183B’s input muxing.
AIN2
AIN8
AIN5
AIN11
AIN6
AIN12
ADC1_SW[3:0]
1
0
ADC2
04997-0-006
ADI Recommended Input Muxing
A maximum of 12 CVBS inputs can be connected and decoded
by the ADV7183B. As seen in Figure 5, this means the sources
will have to be connected to adjacent pins on the IC. This calls
for a careful design of the PCB layout, for example, ground
shielding between all signals routed through tracks that are
physically close together.
INSEL[3:0] Input Selection, Address 0x00 [3:0]
The INSEL bits allow the user to select an input channel as well
as the input format. Depending on the PCB connections, only a
subset of the INSEL modes are valid. Note that the INSEL[3:0]
does not only switch the analog input muxing, it also configures
the standard definition processor core to process CVBS (Comp),
S-Video (Y/C), or component (YPbPr) format.
Rev. 0 | Page 12 of 96
ADV7183B
CONNECTING
ANALOG SIGNALS
TO ADV7183B
YES NO
SET INSEL[3:0] FOR REQUIRED
MUXING CONFIGURATION
Table 8. Input Channel Switching Using INSEL[3:0]
Description
INSEL[3:0] Analog Input Pins Video Format
0000(default) CVBS1 = AIN1 Composite
0001 CVBS2 = AIN2 Composite
0010 CVBS3 = AIN3 Composite
0011 CVBS4 = AIN4 Composite
0100 CVBS5 = AIN5 Composite
0101 CVBS6 = AIN6 Composite
0110 Y1 = AIN1 YC
C1 = AIN4 YC
0111 Y2 = AIN2 YC
C2 = AIN5 YC
1000 Y3 = AIN3 YC
C3 = AIN6 YC
1001 Y1 = AIN1 YPrPb
PR1 = AIN4 YPrPb
PB1 = AIN5 YPrPb
1010 Y2 = AIN2 YPrPb
PR2 = AIN3 YPrPb
PB2 = AIN6 YPrPb
1011 CVBS7 = AIN7 Composite
1100 CVBS8 = AIN8 Composite
1101 CVBS9 = AIN9 Composite
1110 CVBS10 = AIN10 Composite
1111 CVBS11 = AIN11 Composite
ADI RECOMMENDED
INPUT MUXING; SEE TABLE 9
(ADC_SW_MAN_EN, ADC0_SW,
Figure 7. Input Muxing Overview
Table 9. Input Channel Assignments
Input
Channel
AIN7 41 CVBS7
AIN1 42 CVBS1 YC1-Y YPrPb1-Y
AIN8 43 CVBS8
AIN2 44 CVBS2 YC2-Y YPrPb2-Y
AIN9 45 CVBS9
AIN3 46 CVBS3 YC3-Y YPrPb2-Pb
AIN10 57 CVBS10
AIN4 58 CVBS4 YC1-C YPrPb1-Pb
AIN11 59 CVBS11
AIN5 60 CVBS5 YC2-C YPrPb1-Pr
AIN12 61 Not Available
AIN6 62 CVBS6 YC3-C YPrPb2-Pr
ADI recommended input muxing is designed to minimize
crosstalk between signal channels and to obtain the highest
level of signal integrity. Table 9 summarizes how PCB layout
should connect analog video signals to the ADV7183B.
It is strongly recommended to connect any unused analog input
pins to AGND to act as a shield.
Inputs AIN7 to AIN11 should be connected to AGND when
only six input channels are used. This improves the quality of
the sampling due to better isolation between the channels.
AIN12 is not under the control of INSEL[3:0]. It can be routed
to ADC0/ADC1/ADC2 only by manual muxing. See Table 10
for details.
SET INSEL[3:0] TO
CONFIGURE ADV7183B TO
DECODE VIDEO FORMAT:
CVBS: 0000
YC: 0110
YPrPb: 1001
USE MANUAL INPUT MUXING
ADC1_SW, ADC2_SW)
Pin
ADI Recommended Input Muxing Control
No.
04997-0-007
INSEL[3:0]
Rev. 0 | Page 13 of 96
ADV7183B
Manual Input Muxing
By accessing a set of manual override muxing registers, the
analog input muxes of the ADV7183B can be controlled
directly. This is referred to as manual input muxing.
Manual input muxing overrides other input muxing control
bits, for example, INSEL.
The manual muxing is activated by setting the
ADC_SW_MAN_EN bit. It only affects the analog switches in
front of the ADCs. This means if the settings of INSEL and the
manual input muxing registers (ADC0/ADC1/ACD2_sw)
contradict each other, the ADC0/ADC1/ADC2_sw settings
apply and INSEL is ignored.
Manual input muxing only controls the analog input muxes.
INSEL[3:0] still has to be set so the follow-on blocks process the
video data in the correct format. This means INSEL must still
be used to tell the ADV7183B whether the input signal is of
component, YC, or CVBS format.
Restrictions in the channel routing are imposed by the analog
signal routing inside the IC; every input pin cannot be routed to
each ADC. Refer to Figure 6 for an overview on the routing
capabilities inside the chip. The three mux sections can be
controlled by the reserved control signal buses ADC0/ADC1/
ADC2_sw[3:0]. Table 10 explains the control words used.
SETADC_sw_man_en, Manual Input Muxing Enable,
Address 0xC4 [7]
ADC0_sw[3:0], ADC0 mux configuration, Address 0xC3 [3:0]
ADC1_sw[3:0], ADC1 mux configuration, Address 0xC3 [7:4]
ADC2_sw[3:0], ADC2 mux configuration, Address 0xC4 [3:0]
Table 10. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1)
ADC0_sw[3:0] ADC0 Connected To: ADC1_sw[3:0] ADC1 Connected To: ADC2_sw[3:0] ADC2 Connected To:
0000 No Connection 0000 No Connection 0000 No Connection
0001 AIN1 0001 No Connection 0001 No Connection
0010 AIN2 0010 No Connection 0010 AIN2
0011 AIN3 0011 AIN3 0011 No Connection
0100 AIN4 0100 AIN4 0100 No Connection
0101 AIN5 0101 AIN5 0101 AIN5
0110 AIN6 0110 AIN6 0110 AIN6
0111 No Connection 0111 No Connection 0111 No Connection
1000 No Connection 1000 No Connection 1000 No Connection
1001 AIN7 1001 No Connection 1001 No Connection
1010 AIN8 1010 No Connection 1010 AIN8
1011 AIN9 1011 AIN9 1011 No Connection
1100 AIN10 1100 AIN10 1100 No Connection
1101 AIN11 1101 AIN11 1101 AIN11
1110 AIN12 1110 AIN12 1110 AIN12
1111 No Connection 1111 No Connection 1111 No Connection
Rev. 0 | Page 14 of 96
ADV7183B
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVE MODES
Power-Down
PWRDN_ADC_0, Address 0x3A [3]
When PWRDN_ADC_0 is 0 (default), the ADC is in normal
operation.
PDBP, Address 0x0F [2]
The digital core of the ADV7183B can be shut down by using a
pin (
PWRDN
) and a bit (PWRDN see below). The PDBP
controls which of the two has the higher priority. The default is
to give the pin (
PWRDN
) priority. This allows the user to have
the ADV7183B powered down by default.
When PDBD is 0 (default), the digital core power is controlled
by the
PWRDN
pin (the bit is disregarded).
When PDBD is 1, the bit has priority (the pin is disregarded).
PWRDN, Address 0x0F [5]
Setting the PWRDN bit switches the ADV7183B into a chipwide power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
2
operation. No I
C bits are lost during power-down. The
PWRDN bit also affects the analog blocks and switches them
2
into low current modes. The I
C interface itself is unaffected,
and remains operational in power-down mode.
The ADV7183B leaves the power-down state if the PWRDN bit
is set to 0 (via I
C), or if the overall part is reset using
RESET
pin.
2
Note that PDBP must be set to 1 for the PWRDN bit to power
down the ADV7183B.
When PWRDN is 0 (default), the chip is operational.
When PWRDN is 1, the ADV7183B is in chip-wide power-down.
ADC Power-Down Control
The ADV7183B contains three 10-bit ADCs (ADC 0, ADC 1,
and ADC 2). If required, it is possible to power down each ADC
individually.
When should the ADCs be powered down?
When PWRDN_ADC_0 is 1, ADC 0 is powered down.
PWRDN_ADC_1, Address 0x3A [2]
When PWRDN_ADC_1 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_1 is 1, ADC 1 is powered down.
PWRDN_ADC_2, Address 0x3A [1]
When PWRDN_ADC_2 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_2 is 1, ADC 2 is powered down.
RESET CONTROL
Chip Reset (RES), Address 0x0F [7]
Setting this bit, equivalent to controlling the
2
ADV7183B, issues a full chip reset. All I
C registers are reset to
their default values. (Some register bits do not have a reset value
specified. They keep their last written value. Those bits are
marked as having a reset value of x in the register table.) After
the reset sequence, the part immediately starts to acquire the
incoming video signal.
After setting the RES bit (or initiating a reset via the pin), the
part returns to the default mode of operation with respect to its
2
primary mode of operation. All I
C bits are loaded with their
default values, making this bit self-clearing.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I
performed.
2
C master controller receives a no acknowledge condition
The I
on the ninth clock cycle when chip reset is implemented. See
the MPU Port Description section.
RESET
pin on the
2
C writes are
• CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
• S-Video mode. ADC 2 should be powered down to save on
power consumption.
Rev. 0 | Page 15 of 96
When RES is 0 (default), operation is normal.
When RES is 1, the reset sequence starts.
ADV7183B
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03 [6]
This bit allows the user to three-state the output drivers of the
ADV7183B.
Upon setting the TOD bit, the P15–P0, HS, VS, FIELD, and SFL
pins are three-stated.
The timing pins (HS/VS/FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the Three-State LLC Driver and the Timing Signals Output
Enable sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
The ADV7183B supports three-stating via a dedicated pin.
When set high, the
P15–P0, HS, VS, FIELD, and SFL. The output drivers are threestated if the TOD bit or the
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are three-stated.
Three-State LLC Driver
TRI_LLC, Address 0x1D [7]
This bit allows the output drivers for the LLC1 and LLC2 pins
of the ADV7183B to be three-stated. For more information on
three-state control, refer to the Three-State Output Drivers and
the Timing Signals Output Enable sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are three-stated.
pin three-states the output drivers for
OE
pin is set high.
OE
Timing Signals Output Enable
TIM_OE, Address 0x04 [3]
The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD into the active (that is, driving) state even if the TOD bit
is set. If set to low, the HS, VS, and FIELD pins are three-stated,
dependent on the TOD bit. This functionality is useful if the
decoder is to be used as a timing generator only. This may be
the case if only the timing signals are to be extracted from an
incoming signal, or if the part is in free-run mode where a
separate chip can output, for instance, a company logo.
For more information on three-state control, refer to the ThreeState Output Drivers and the Three-State LLC Driver sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TIM_OE is 0 (default), HS, VS, and FIELD are threestated according to the TOD bit.
When TIM_OE is 1, HS, VS, and FIELD are forced active all the
time.
Drive Strength Selection (Data)
DR_STR[1:0] Address 0xF4 [5:4]
For EMC and crosstalk reasons, it may be desirable to
strengthen or weaken the drive strength of the output drivers.
The DR_STR[1:0] bits affect the P[15:0] output drivers.
For more information on three-state control, refer to the Drive
Strength Selection (Clock) and the Drive Strength Selection
(Sync) sections.
Table 11. DR_STR Function
DR_STR[1:0] Description
00 Low drive strength (1×).
01 (default) Medium low drive strength (2×).
10 Medium high drive strength (3×).
11 High drive strength (4×).
Rev. 0 | Page 16 of 96
ADV7183B
Drive Strength Selection (Clock)
Enable Subcarrier Frequency Lock Pin
DR_STR_C[1:0] Address 0xF4 [3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the Drive Strength Selection (Sync) and the Drive
Strength Selection (Data) sections.
Table 12. DR_STR_C Function
DR_STR_C[1:0] Description
00 Low drive strength (1×).
01 (default) Medium low drive strength (2×).
10 Medium high drive strength (3×).
11 High drive strength (4×).
Drive Strength Selection (Sync)
DR_STR_S[1:0] Address 0xF4 [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and F are
driven. For more information, refer to the Drive Strength
Selection (Clock) and the Drive Strength Selection (Data)
sections.
Table 13. DR_STR_S Function
DR_STR_S[1:0] Description
00 Low drive strength (1×).
01 (default) Medium low drive strength (2×).
10 Medium high drive strength (3×).
11 High drive strength (4×).
EN_SFL_PIN Address 0x04 [1]
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as GenLock) from the ADV7183B to
an encoder in a decoder-encoder back-to-back arrangement.
When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.
When EN_SFL_PIN is 1, the subcarrier frequency lock
information is presented on the SFL pin.
Polarity LLC Pin
PCLK Address 0x37 [0]
The polarity of the clock that leaves the ADV7183B via the
LLC1 and LLC2 pins can be inverted using the PCLK bit.
Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.
This bit also inverts the polarity of the LLC2 clock.
When PCLK is 0, the LLC output polarity is inverted.
When PCLK is 1 (default), the LLC output polarity is normal
(as per the timing diagrams).
Rev. 0 | Page 17 of 96
ADV7183B
GLOBAL STATUS REGISTERS
Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV7183B. The other three registers
contain status bits regarding IC operation.
Depending on the setting of the FSCLE bit, the Status[0] and
Status[1] bits are based solely on horizontal timing info or on
the horizontal timing and lock status of the color subcarrier. See
the FSCLE Fsc Lock Enable, Address 0x51 [7] section.
IDENTIFICATION
IDENT[7:0] Address 0x11 [7:0]
This register provides identification of the revision of the
ADV7183B.
An identification value of 0x11 indicates the ADV7183, released
silicon.
An identification value of 0x13 indicates the ADV7183B.
STATUS 1
STATUS_1[7:0] Address 0x10 [7:0]
This read-only register provides information about the internal
status of the ADV7183B.
See CIL[2:0] Count Into Lock, Address 0x51 [2:0] and COL[2:0]
Count Out of Lock, Address 0x51 [5:3] for information on the
timing.
Table 15. STATUS 1 Function
STATUS 1 [7:0] Bit Name Description
0 IN_LOCK In lock (right now).
1 LOST_LOCK Lost lock (since last read of this register).
2 FSC_LOCK Fsc locked (right now).
3 FOLLOW_PW AGC follows peak white algorithm.
4 AD_RESULT.0 Result of autodetection.
5 AD_RESULT.1 Result of autodetection.
6 AD_RESULT.2 Result of autodetection.
7 COL_KILL Color kill active.
AUTODETECTION RESULT
AD_RESULT[2:0] Address 0x10 [6:4]
The AD_RESULT[2:0] bits report back on the findings from the
autodetection block. For more information on enabling the
autodetection block, see the General Setup section. For
information on configuring it, see the Autodetection of SD
Modes section.
Table 14. AD_RESULT Function
AD_RESULT[2:0] Description
000 NTSM-MJ
001 NTSC-443
010 PAL-M
011 PAL-60
100 PAL-BGHID
101 SECAM
110 PAL-Combination N
111 SECAM 525
STATUS 2
STATUS_2[7:0], Address 0x12 [7:0]
Table 16. STATUS 2 Function
STATUS 2 [7:0] Bit Name Description
0 MVCS DET Detected Macrovision color striping.
1 MVCS T3 Macrovision color striping protection. Conforms to Type 3 if high, and to Type 2 if low.
2 MV_PS DET Detected Macrovision pseudo Sync pulses.
3 MV_AGC DET Detected Macrovision AGC pulses.
4 LL_NSTD Line length is nonstandard.
5 FSC_NSTD Fsc frequency is nonstandard.
6 Reserved
7 Reserved
Rev. 0 | Page 18 of 96
ADV7183B
STATUS 3
STATUS_3[7:0], Address 0x13 [7:0]
Table 17. STATUS 3 Function
STATUS 3 [7:0] Bit Name Description
0 INST_HLOCK Horizontal lock indicator (instantaneous).
1 GEMD Gemstar detect.
2 SD_OP_50HZ Flags whether 50 Hz or 60 Hz is present at output.
3 Reserved for future use.
4 FREE_RUN_ACT Output a blue screen (see the DEF_VAL_AUTO_EN section).
5 STD_FLD_LEN Field length is correct for currently selected video standard.
6 INTERLACED Interlaced video detected (field sequence found).
7 PAL_SW_LOCK Reliable sequence of swinging bursts detected.
Rev. 0 | Page 19 of 96
ADV7183B
STANDARD DEFINITION PROCESSOR (SDP)
STANDARD DEFINITION PROCESSOR
DIGITIZED CVBS
DIGITIZED Y (YC)
DIGITIZED CVBS
DIGITIZED C (YC)
MACROVISION
DETECTION
LUMA
DIGITAL
FINE
CLAMP
CHROMA
DIGITAL
FINE
CLAMP
RECOVERY
CHROMA
DEMOD
F
SC
RECOVERY
VBI DATA
FILTER
EXTRACT
CHROMA
FILTER
AUTODETECTION
LUMA
SYNC
STANDARD
Figure 8. Block Diagram of the Standard Definition Processor
A block diagram of the ADV7183B’s standard definition
processor (SDP) is shown in Figure 8.
The SDP block can handle standard definition video in CVBS,
YC, and YPrPb formats. It can be divided into a luminance and
a chrominance path. If the input video is of a composite type
(CVBS), both processing paths are fed with the CVBS input.
SD LUMA PATH
The input signal is processed by the following blocks:
• Digital Fine Clamp. This block uses a high precision
algorithm to clamp the video signal.
• Luma Filter Block. This block contains a luma decimation
filter (YAA) with a fixed response, and some shaping filters
(YSH) that have selectable responses.
• Luma Gain Control. The automatic gain control (AGC)
can operate on a variety of different modes, including gain
based on the depth of the horizontal sync pulse, peak white
mode, and fixed manual gain.
• Luma Resample. To correct for line-length errors as well as
dynamic line-length changes, the data is digitally resampled.
• Luma 2D Comb. The two-dimensional comb filter
provides YC separation.
• AV Code Insertion. At this point, the decoded luma (Y)
signal is merged with the retrieved chroma values. AV
codes (as per ITU-R. BT-656) can be inserted.
GAIN
CONTROL
LINE
LENGTH
PREDICTOR
GAIN
CONTROL
SLLC
CONTROL
LUMA
RESAMPLE
RESAMPLE
CONTROL
CHROMA
RESAMPLE
LUMA
2D COMB
CHROMA
2D COMB
AV
CODE
INSERTION
VIDEO DATA
OUTPUT
MEASUREMENT
BLOCK (= >1
VIDEO DATA
PROCESSING
BLOCK
2
C)
04997-0-008
SD CHROMA PATH
The input signal is processed by the following blocks:
• Digital Fine Clamp. This block uses a high precision
algorithm to clamp the video signal.
• Chroma Demodulation. This block employs a color
subcarrier (Fsc) recovery unit to regenerate the color
subcarrier for any modulated chroma scheme. The
demodulation block then performs an AM demodulation
for PAL and NTSC, and an FM demodulation for SECAM.
• Chroma Filter Block. This block contains a chroma
decimation filter (CAA) with a fixed response, and some
shaping filters (CSH) that have selectable responses.
• Gain Control. Automatic gain control (AGC) can operate
on several different modes, including gain based on the
color subcarrier’s amplitude, gain based on the depth of the
horizontal sync pulse on the luma channel, or fixed manual
gain.
• Chroma Resample. The chroma data is digitally resampled
to keep it perfectly aligned with the luma data. The
resampling is done to correct for static and dynamic linelength errors of the incoming video signal.
• Chroma 2D Comb. The two-dimensional, 5-line,
superadaptive comb filter provides high quality YC
separation in case the input signal is CVBS.
• AV Code Insertion. At this point, the demodulated chroma
(Cr and Cb) signal is merged with the retrieved luma
values. AV codes (as per ITU-R. BT-656) can be inserted.
Rev. 0 | Page 20 of 96
ADV7183B
SYNC PROCESSING
The ADV7183B extracts syncs embedded in the video data
stream. There is currently no support for external HS/VS
inputs. The sync extraction has been optimized to support
imperfect video sources such as videocassette recorders with
head switches. The actual algorithm used employs a coarse
detection based on a threshold crossing followed by a more
detailed detection using an adaptive interpolation algorithm.
The raw sync information is sent to a line-length measurement
and prediction block. The output of this is then used to drive
the digital resampling section to ensure that the ADV7183B
outputs 720 active pixels per line.
The sync processing on the ADV7183B also includes the
following specialized postprocessing blocks that filter and
condition the raw sync information retrieved from the digitized
analog video.
GENERAL SETUP
Video Standard Selection
The VID_SEL[3:0] bits allows the user to force the digital core
into a specific video standard. Under normal circumstances,
this should not be necessary. The VID_SEL[3:0] bits default to
an autodetection mode that supports PAL, NTSC, SECAM, and
variants thereof. The following section describes the autodetection system.
Autodetection of SD Modes
In order to guide the autodetect system, individual enable bits
are provided for each of the supported video standards. Setting
the relevant bit to 0 inhibits the standard from being detected
automatically. Instead, the system picks the closest of the
remaining enabled standards. The results of the autodetection
can be read back via the status registers. See the Global Status
Registers section for more information.
• VSYNC Processor. This block provides extra filtering of the
detected VSYNCs to give improved vertical lock.
• HSYNC Processor. The HSYNC processor is designed to
filter incoming HSYNCs that have been corrupted by
noise, providing much improved performance for video
signals with stable time base but poor SNR.
VBI DATA RECOVERY
The ADV7183B can retrieve the following information from the
input video:
• Wide-screen signaling (WSS)
• Copy generation management system (CGMS)
• Closed caption (CC)
• Macrovision protection presence
• EDTV data
• Gemstar-compatible data slicing
The ADV7183B is also capable of automatically detecting the
incoming video standard with respect to
• Color subcarrier frequency
• Field rate
• Line rate
The SPD can configure itself to support PAL-BGHID,
PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM
50 Hz/60 Hz, NTSC4.43, and PAL60.
VID_SEL[3:0] Address 0x00 [7:4]
Table 18. VID_SEL Function
VID_SEL Description
0000 (default)
0001
0010
0011
0100 NTSC J (1).
0101 NTSC M (1).
0110 PAL 60.
0111 NTSC 4.43 (1).
1000 PAL BGHID.
1001 PAL N (= PAL BGHID (with pedestal)).
1010 PAL M (without pedestal).
1011 PAL M.
1100 PAL combination N.
1101 PAL combination N (with pedestal).
1110 SECAM.
1111 SECAM (with pedestal).
Autodetect (PAL BGHID) <–> NTSC J (no
pedestal), SECAM.
Autodetect (PAL BGHID) <–> NTSC M
(pedestal), SECAM.
Autodetect (PAL N) (pedestal) <–> NTSC J (no
pedestal), SECAM.
Autodetect (PAL N) (pedestal) <–> NTSC M
(pedestal), SECAM.
AD_SEC525_EN Enable Autodetection of SECAM 525 Line
Video, Address 0x07 [7]
Setting AD_SEC525_EN to 0 (default) disables the autodetection
of a 525-line system with a SECAM style, FM-modulated color
component.
Setting AD_SEC525_EN to 1 enables the detection.
Rev. 0 | Page 21 of 96
ADV7183B
AD_SECAM_EN Enable Autodetection of SECAM,
Address 0x07 [6]
Setting AD_SECAM_EN to 0 disables the autodetection of
SECAM.
Setting AD_SECAM_EN to 1 (default) enables the detection.
AD_N443_EN Enable Autodetection of NTSC 443,
Address 0x07 [5]
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection.
AD_P60_EN Enable Autodetection of PAL60,
Address 0x07 [4]
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Setting AD_P60_EN to 1 (default) enables the detection.
AD_PALN_EN Enable Autodetection of PAL N,
Address 0x07 [3]
Setting AD_PALN_EN to 0 disables the detection of the PAL N
standard.
Setting AD_PALN_EN to 1 (default) enables the detection.
AD_PALM_EN Enable Autodetection of PAL M,
Address 0x07 [2]
Setting AD_PALM_EN to 0 disables the autodetection of PAL M.
Setting AD_PALM_EN to 1 (default) enables the detection.
AD_NTSC_EN Enable Autodetection of NTSC,
Address 0x07 [1]
Setting AD_NTSC_EN to 0 disables the detection of standard
NTSC.
Setting AD_NTSC_EN to 1 (default) enables the detection.
SFL_INV Subcarrier Frequency Lock Inversion
This bit controls the behavior of the PAL switch bit in the SFL
(GenLock Telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems.
First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(GenLock Telegram) bit directly, while the later ones invert the
bit prior to using it. The reason for this is that the inversion
compensated for the 1-line delay of an SFL (GenLock Telegram)
transmission.
As a result, ADV717x encoders need the PAL switch bit in the
SFL (GenLock Telegram) to be 1 for NTSC to work, and
ADV7190/ADV7191/ADV7194 encoders need the PAL switch
bit in the SFL to be 0 to work in NTSC.
If the state of the PAL switch bit is wrong, a 180° phase shift
occurs.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
SFL_INV Address 0x41 [6]
Setting SFL_INV to 0 makes the part SFL-compatible with
ADV7190/ADV7191/ADV7194 encoders.
Setting SFL_INV to 1 (default), makes the part SFL-compatible
with ADV717x/ADV7173x encoders.
Lock-Related Controls
Lock information is presented to the user through Bits [1:0] of
the Status 1 register. See the STATUS_1[7:0] Address 0x10 [7:0]
section. Figure 9 outlines the signal flow and the controls
available to influence the way the lock status information is
generated.
AD_PAL_EN Enable Autodetection of PAL,
Address 0x07 [0]
Setting AD_PAL_EN to 0 disables the detection of standard PAL.
Setting AD_PAL_EN to 1 (default) enables the detection.
SELECT THE RAW LOCK SIGNAL
SRLS
TIME_WIN
FREE_RUN
LOCK
F
SC
TAKE F
1
0
LOCK INTO ACCOUNT
SC
0
COUNTER OUT OF LOCK
1
FSCLE
Figure 9. Lock-Related Signal Path
Rev. 0 | Page 22 of 96
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
COUNTER INTO LOCK
MEMORY
STATUS 1 [0]
STATUS 1 [1]
04997-0-009
ADV7183B
SRLS Select Raw Lock Signal, Address 0x51 [6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits [1:0] in the Status 1 register).
• The time_win signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming video.
It reacts quite quickly.
• The free_run signal evaluates the properties of the
incoming video over several fields, and takes vertical
synchronization information into account.
Setting SRLS to 0 (default) selects the free_run signal.
Setting SRLS to 1 selects the time_win signal.
FSCLE Fsc Lock Enable, Address 0x51 [7]
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits [1:0] in Status
Register 1. This bit must be set to 0 when operating in YPrPb
component mode to generate a reliable HLOCK status bit.
Setting FSCLE to 0 (default) makes the overall lock status
dependent on only horizontal sync lock.
Setting FSCLE to 1 makes the overall lock status dependent on
horizontal sync lock and Fsc lock.
CIL[2:0] Count Into Lock, Address 0x51 [2:0]
CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state, and reports this via Status 0 [1:0]. It counts
the value in lines of video.
Table 19. CIL Function
CIL[2:0] Description
000 1
001 2
010 5
011 10
100 (default) 100
101 500
110 1000
111 100000
COL[2:0] Count Out of Lock, Address 0x51 [5:3]
COL[2:0] determines the number of consecutive lines for which
the out of lock condition must be true before the system switches
into unlocked state, and reports this via Status 0 [1:0]. It counts
the value in lines of video.
Table 20. COL Function
COL[2:0] Description
000 1
001 2
010 5
011 10
100 (default) 100
101 500
110 1000
111 100000
COLOR CONTROLS
These registers allow the user to control the picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture
clamping, although both controls affect the signal’s dc level.
CON[7:0] Contrast Adjust, Address 0x08 [7:0]
This allows the user to adjust the contrast of the picture.
Table 21. CON Function
CON[7:0] Description
0x80 (default) Gain on luma channel = 1.
0x00 Gain on luma channel = 0.
0xFF Gain on luma channel = 2.
SD_SAT_Cb[7:0] SD Saturation Cb Channel,
Address 0xE3 [7:0]
This register allows the user to control the gain of the Cb
channel only. The user can adjust the saturation of the picture.
Table 22. SD_SAT_Cb Function
SD_SAT_Cb[7:0] Description
0x80 (default) Gain on Cb channel = 0 dB.
0x00 Gain on Cb channel = −42 dB.
0xFF Gain on Cb channel = +6 dB.
Rev. 0 | Page 23 of 96
ADV7183B
SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4 [7:0]
This register allows the user to control the gain of the Cr channel
only. The user can adjust the saturation of the picture.
HUE[7:0] Hue Adjust, Address 0x0B [7:0]
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
Table 23. SD_SAT_Cr Function
SD_SAT_Cr[7:0] Description
0x80 (default) Gain on Cr channel = 0 dB.
0x00 Gain on Cb channel = −42 dB.
0xFF Gain on Cb channel = +6 dB.
SD_OFF_Cb[7:0] SD Offset Cb Channel,
Address 0xE1 [7:0]
This register allows the user to select an offset for data on the
Cb channel only and adjust the hue of the picture. There is a
functional overlap with the Hue [7:0] register.
Table 24.SD_OFF_Cb Function
SD_OFF_Cb[7:0] Description
0x80 (default) 0 offset applied to the Cb channel.
0x00 −312 mV offset applied to the Cb channel.
0xFF +312 mV offset applied to the Cb channel.
SD_OFF_Cr [7:0] SD Offset Cr Channel, Address 0xE2 [7:0]
This register allows the user to select an offset for data on the Cr
channel only and adjust the hue of the picture. There is a functional overlap with the Hue [7:0] register.
HUE[7:0] has a range of ±90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
The hue adjustment value is fed into the AM color demodulation
block. Therefore, it only applies to video signals that contain
chroma information in the form of an AM modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM and
does not work on component video inputs (YPrPb).
Table 27. HUE Function
HUE[7:0] Description
0x00 (default) Phase of the chroma signal = 0° .
0x7F Phase of the chroma signal = –90°.
0x80 Phase of the chroma signal = +90°.
DEF_Y[5:0] Default Value Y, Address 0x0C [7:2]
If the ADV7183B loses lock on the incoming video signal or if
there is no input signal, the DEF_Y[5:0] bits allows the user to
specify a default luma value to be output. This value is used
under the following conditions:
• If DEF_VAL_AUTO_EN bit is set to high and the
ADV7183B lost lock to the input video signal. This is the
intended mode of operation (automatic mode).
Table 25. SD_OFF_Cr Function
SD_OFF_Cr[7:0] Description
0x80 (default) 0 offset applied to the Cr channel.
0x00 −312 mV offset applied to the Cr channel.
0xFF +312 mV offset applied to the Cr channel.
BRI[7:0] Brightness Adjust, Address 0x0A [7:0]
This register controls the brightness of the video signal. It
allows the user to adjust the brightness of the picture.
Table 26. BRI Function
BRI[7:0] Description
0x00 (default) Offset of the luma channel = 0IRE.
0x7F Offset of the luma channel = 100IRE.
0xFF Offset of the luma channel = –100IRE.
• The DEF_VAL_EN bit is set, regardless of the lock status of
the video decoder. This is a forced mode that may be useful
during configuration.
The DEF_Y[5:0] values define the 6 MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.
DEF_Y[5:0] is 0x0D (Blue) is the default value for Y.
Register 0x0C has a default value of 0x36.
DEF_C[7:0] Default Value C, Address 0x0D [7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the 4 MSBs of Cr and Cb values to be output if
• The DEF_VAL_AUTO_EN bit is set to high and the
ADV7183B can’t lock to the input video (automatic mode).
• DEF_VAL_EN bit is set to high (forced output).
The data that is finally output from the ADV7183B for the
chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =
{DEF_C[3:0], 0, 0, 0, 0}.
DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb.
Rev. 0 | Page 24 of 96
ADV7183B
A
G
DEF_VAL_EN Default Value Enable, Address 0x0C [0]
This bit forces the use of the default values for Y, Cr, and Cb.
Refer to the descriptions for DEF_Y and DEF_C for additional
information. In this mode, the decoder also outputs a stable
27 MHz clock, HS, and VS.
Setting DEF_VAL_EN to 0 (default) outputs a colored screen
determined by user-programmable Y, Cr, and Cb values when
the decoder free-runs. Free-run mode is turned on and off by the
DEF_VAL_AUTO_EN bit.
Setting DEF_VAL_EN to 1 forces a colored screen output
determined by user-programmable Y, Cr, and Cb values. This
overrides picture data even if the decoder is locked.
DEF_VAL_AUTO_EN Default Value Automatic Enable,
Address 0x0C [1]
This bit enables the automatic usage of the default values for Y,
Cr, and Cb when the ADV7183B cannot lock to the video
signal.
Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If
the decoder is unlocked, it outputs noise.
Setting DEF_VAL_EN to 1 (default) enables free-run mode. A
colored screen set by the user-programmable Y, Cr, and Cb
values is displayed when the decoder loses lock.
CLAMP OPERATION
The input video is ac-coupled into the ADV7183B. Therefore,
its dc value needs to be restored. This process is referred to as
clamping the video. This section explains the general process of
clamping on the ADV7183B, and shows the different ways in
which a user can configure its behavior.
The ADV7183B uses a combination of current sources and a
digital processing block for clamping, as shown in Figure 10.
The analog processing channel shown is replicated three times
inside the IC. While only one single channel (and only one
ADC) would be needed for a CVBS signal, two independent
channels are needed for YC (S-VHS) type signals, and three
independent channels are needed to allow component signals
(YPrPb) to be processed.
FINE
CURRENT
SOURCES
COARSE
CURRENT
SOURCES
The clamping can be divided into two sections:
• Clamping before the ADC (analog domain): current
sources.
• Clamping after the ADC (digital domain): digital
processing block.
The ADCs can digitize an input signal only if it resides within
the ADC’s 1.6 V input voltage range. An input signal with a dc
level that is too large or too small is clipped at the top or bottom
of the ADC range.
The primary task of the analog clamping circuits is to ensure
that the video signal stays within the valid ADC input window
so that the analog-to-digital conversion can take place. It is not
necessary to clamp the input signal with a very high accuracy in
the analog domain as long as the video signal fits the ADC range.
After digitization, the digital fine clamp block corrects for any
remaining variations in dc level. Since the dc level of an input
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations may occur. Furthermore, dynamic changes in the dc level almost certainly lead to
visually objectionable artifacts, and must therefore be prohibited.
The clamping scheme has to be able to acquire a newly connected
video signal with a completely unknown dc level, and it must
maintain the dc level during normal operation.
For quickly acquiring an unknown video signal, the large current clamps may be activated. (It is assumed that the amplitude
of the video signal at this point is of a nominal value.) Control
of the coarse and fine current clamp parameters is performed
automatically by the decoder.
Standard definition video signals may have excessive noise on
them. In particular, CVBS signals transmitted by terrestrial
broadcast and demodulated using a tuner usually show very
large levels of noise (>100 mV). A voltage clamp would be
unsuitable for this type of video signal. Instead, the ADV7183B
employs a set of four current sources that can cause coarse
(>0.5 mA) and fine (<0.1 mA) currents to flow into and away
from the high impedance node that carries the video signal (see
Figure 10).
NALO
VIDEO
INPUT
ADC
Figure 10. Clamping Overview
Rev. 0 | Page 25 of 96
DATA
PRE-
PROCESSOR
(DPP)
CLAMP CONTROL
SDP
WITH DIGITAL
FINE CLAMP
04997-0-010
ADV7183B
The following sections describe the I2C signals that can be used
to influence the behavior of the clamps on the ADV7183B.
Previous revisions of the ADV7183B had controls (FACL/FICL,
fast and fine clamp length) to allow configuration of the length
for which the coarse (fast) and fine current sources are switched
on. These controls were removed on the ADV7183B-FT and
replaced by an adaptive scheme.
CCLEN Current Clamp Enable, Address 0x14 [4]
The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This may be
useful if the incoming analog video signal is clamped externally.
When CCLEN is 0, the current sources are switched off.
When CCLEN is 1 (default), the current sources are enabled.
DCT[1:0] Digital Clamp Timing, Address 0x15 [6:5]
The Clamp Timing register determines the time constant of the
digital fine clamp circuitry. It is important to realize that the
digital fine clamp reacts very quickly since it is supposed to
immediately correct any residual dc level error for the active
line. The time constant of the digital fine clamp must be much
quicker than the one from the analog blocks.
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
Table 28. DCT Function
DCT[1:0] Description
00 Slow (TC = 1 sec).
01 Medium (TC = 0.5 sec).
10 (default) Fast (TC = 0.1 sec).
11
DCFE Digital Clamp Freeze Enable, Address 0x15 [4]
This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who would like to do their
own clamping. Users should disable the current sources for
analog clamping via the appropriate register bits, wait until the
digital clamp loop settles, and then freeze it via the DCFE bit.
When DCFE to 0 (default), the digital clamp is operational.
Determined by the ADV7183B, depending on
the I/P video parameters.
LUMA FILTER
Data from the digital fine clamp block is processed by three sets
of filters. The data format at this point is CVBS for CVBS input
or luma only for Y/C and YPrPb input formats.
• Luma antialias filter (YAA). The ADV7183B receives video
at a rate of 27 MHz. (In the case of 4× oversampled video,
the ADCs sample at 54 MHz, and the first decimation is
performed inside the DPP filters. Therefore, the data rate
into the SDP core is always 27 MHz.) The ITU-R BT.601
recommends a sampling frequency of 13.5 MHz. The luma
antialias filter decimates the oversampled video using a
high quality, linear phase, low-pass filter that preserves the
luma signal while at the same time attenuating out-of-band
components. The luma antialias filter (YAA) has a fixed
response.
• Luma shaping filters (YSH). The shaping filter block is a
programmable low-pass filter with a wide variety of
responses. It can be used to selectively reduce the luma
video signal bandwidth (needed prior to scaling, for
example). For some video sources that contain high
frequency noise, reducing the bandwidth of the luma
signal improves visual picture quality. A follow-on video
compression stage may work more efficiently if the video is
low-pass filtered.
The ADV7183B has two responses for the shaping filter:
one that is used for good quality CVBS, component, and
S-VHS type sources, and a second for nonstandard CVBS
signals.
The YSH filter responses also include a set of notches for
PAL and NTSC. However, it is recommended to use the
comb filters for YC separation.
• Digital resampling filter. This block is used to allow
dynamic resampling of the video signal to alter parameters
such as the time base of a line of video. Fundamentally, the
resampler is a set of low-pass filters. The actual response is
chosen by the system with no requirement for user
intervention.
Figure 12 through Figure 15 show the overall response of all
filters together. Unless otherwise noted, the filters are set into a
typical wideband mode.
When DCFE is 1, the digital clamp loop is frozen.
Rev. 0 | Page 26 of 96
ADV7183B
Y Shaping Filter
For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. YC separation must aim for best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
YC separation can be achieved by using the internal comb filters
of the ADV7183B. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of the
video line rate) and the color subcarrier (Fsc). For good quality
CVBS signals, this relationship is known; the comb filter
algorithms can be used to separate out luma and chroma with
high accuracy.
In the case of nonstandard video signals, the frequency
relationship may be disturbed and the comb filters may not be
able to remove all crosstalk artifacts in an optimum fashion
without the assistance of the shaping filter block.
An automatic mode is provided. Here, the ADV7183B evaluates
the quality of the incoming video signal and selects the filter
responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.
The luma shaping filter has three control registers:
• YSFM[4:0] allows the user to manually select a shaping
filter mode (applied to all video signals) or to enable an
automatic selection (dependent on video quality and video
standard).
• WYSFMOVR allows the user to manually override the
WYSFM decision.
• WYSFM[4:0] allows the user to select a different shaping
filter mode for good quality CVBS, component (YPrPb),
and S-VHS (YC) input signals.
In automatic mode, the system preserves the maximum possible
bandwidth for good CVBS sources (since they can successfully
be combed) as well as for luma components of YPrPb and YC
sources, since they need not be combed. For poor quality
signals, the system selects from a set of proprietary shaping
filter responses that complements comb filter operation in order
to reduce visual artifacts.
The decisions of the control logic are shown in Figure 11.
YSFM[4:0] Y Shaping Filter Mode, Address 0x17 [4:0]
The Y shaping filter mode bits allow the user to select from a
wide range of low-pass and notch filters. When switched in
automatic mode, the filter is selected based on other register
selections (for example, detected video standard) as well as
properties extracted from the incoming video itself (for
example, quality, time base stability). The automatic selection
always picks the widest possible bandwidth for the video input
encountered.
If the YSFM settings specify a filter (that is, YSFM is set to
values other than 00000 or 00001), the chosen filter is applied to
all video, regardless of its quality.
In automatic selection mode, the notch filters are only used for
bad quality video signals. For all other video signals, wideband
filters are used.
WYSFMOVR Wideband Y Shaping Filter Override,
Address 0x18,[7]
Setting the WYSFMOVR bit enables the use of the
WYSFM[4:0] settings for good quality video signals. For more
information, refer to the general discussion of the luma shaping
filters in the Y Shaping Filter section and the flowchart shown
in Figure 11.
When WYSFMOVR is 0, the shaping filter for good quality
video signals is selected automatically.
Setting WYSFMOVR to 1 enables manual override via
WYSFM[4:0] (default).
Rev. 0 | Page 27 of 96
ADV7183B
SET YSFM
BAD GOOD
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB
Table 29. YSFM Function
YSFM[4:0] Description
0'0000
Automatic selection including a wide notch
response (PAL/NTSC/SECAM)
0'0001 (default)
Automatic selection including a narrow
notch response (PAL/NTSC/SECAM)
0'0010 SVHS 1
0'0011 SVHS 2
0'0100 SVHS 3
0'0101 SVHS 4
0'0110 SVHS 5
0'0111 SVHS 6
0'1000 SVHS 7
0'1001 SVHS 8
0'1010 SVHS 9
0'1011 SVHS 10
0'1100 SVHS 11
0'1101 SVHS 12
0'1110 SVHS 13
0'1111 SVHS 14
1'0000 SVHS 15
1'0001 SVHS 16
1'0010 SVHS 17
1'0011 SVHS 18 (CCIR 601)
1'0100 PAL NN 1
1'0101 PAL NN 2
1'0110 PAL NN 3
1'0111 PAL WN 1
1'1000 PAL WN 2
1'1001 NTSC NN 1
1'1010 NTSC NN 2
1'1011 NTSC NN 3
1'1100 NTSC WN 1
1'1101 NTSC WN 2
1'1110 NTSC WN 3
1'1111 Reserved
YES NO
VIDEO
QUALITY
1 0
SELECT WIDEBAND
FILTER AS PER
WYSFM[4:0]
Figure 11. YSFM and WYSFM Control Flowchart
YSFM IN AUTO MODE?
00000 OR 00001
WYSFMOVR
SELECT AUTOMATIC
WIDEBAND FILTER
WYSFM[4:0] Wide Band Y Shaping Filter Mode,
Address 0x18 [4:0]
The WYSFM[4:0] bits allow the user to manually select a shaping
filter for good quality video signals, for example, CVBS with
stable time base, luma component of YPrPb, luma component
of YC. The WYSFM bits are only active if the WYSFMOVR bit
is set to 1. See the general discussion of the shaping filter
settings in the Y Shaping Filter section.
Table 30. WYSFM Function
WYSFM[4:0] Description
0'0000 Do not use
0'0001 Do not use
0'0010 SVHS 1
0'0011 SVHS 2
0'0100 SVHS 3
0'0101 SVHS 4
0'0110 SVHS 5
0'0111 SVHS 6
0'1000 SVHS 7
0'1001 SVHS 8
0'1010 SVHS 9
0'1011 SVHS 10
0'1100 SVHS 11
0'1101 SVHS 12
0'1110 SVHS 13
0'1111 SVHS 14
1'0000 SVHS 15
1'0001 SVHS 16
1'0010 SVHS 17
1'0011 (default) SVHS 18 (CCIR 601)
1'0100–1’1111 Do not use
USE YSFM SELECTED
FILTER REGARDLESS FOR
GOOD AND BAD VIDEO
04997-0-011
Rev. 0 | Page 28 of 96
ADV7183B
–10
–20
–30
–40
AMPLITUDE (dB)
–50
–60
–70
v740a COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,
0
010864212
Y RESAMPLE
FREQUENCY (MHz)
04997-0-012
Figure 12. Y S-VHS Combined Responses
The filter plots in Figure 12 show the S-VHS 1 (narrowest) to
S-VHS 18 (widest) shaping filter settings. Figure 14 shows the
PAL notch filter responses. The NTSC-compatible notches are
shown in Figure 15.
v740a COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
0
Y RESAMPLE
v740a COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
0
–10
–20
–30
–40
AMPLITUDE (dB)
–50
–60
–70
010864212
Y RESAMPLE
FREQUENCY (MHz)
04997-0-015
Figure 15. Y S-VHS 18 Extra Wideband Filter (601)
CHROMA FILTER
Data from the digital fine clamp block is processed by three sets
of filters. The data format at this point is CVBS for CVBS inputs,
chroma only for Y/C, or U/V interleaved for YPrPb input
formats.
–20
–40
–60
AMPLITUDE (dB)
–80
–100
–120
010864212
FREQUENCY (MHz)
04997-0-013
• Chroma Antialias Filter (CAA). The ADV7183B over-
• Chroma Shaping Filters (CSH). The shaping filter block
• Digital Resampling Filter. This block is used to allow
Figure 13. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
v740a COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,
0
–10
–20
–30
–40
AMPLITUDE (dB)
–50
Y RESAMPLE
The plots in Figure 16 show the overall response of all filters
together.
samples the CVBS by a factor of 2 and the Chroma/PrPb
by a factor of 4. A decimating filter (CAA) is used to
preserve the active video band and to remove any out-ofband components. The CAA filter has a fixed response.
(CSH) can be programmed to perform a variety of lowpass responses. It can be used to selectively reduce the
bandwidth of the chroma signal for scaling or
compression.
dynamic resampling of the video signal to alter parameters
such as the time base of a line of video. Fundamentally, the
resampler is a set of low-pass filters. The actual response is
chosen by the system without user intervention.
–60
–70
010864212
FREQUENCY (MHz)
04997-0-014
Figure 14. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
Rev. 0 | Page 29 of 96
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