ANALOG DEVICES ADV7183 Service Manual

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Advanced Video Decoder with 10-Bit ADC

a

FEATURES
Analog Video to Digital YCrCb Video Decoder:

NTSC-(M/N), PAL-(B/D/G/H/I/M/N)

®

7183 Integrates Two 10-Bit Accurate ADCs

ADV
Clocked from a Single 27 MHz Crystal
Dual Video Clocking Schemes:

Line-Locked Clock Compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™)
Three-Line Chroma Comb Filter
Real-Time Clock and Status Information Output
Integrated AGC (Automatic Gain Control) and Clamping
Multiple Programmable Analog Input Formats:

CVBS (Composite Video)

SVHS (Y/C)

YCrCb Component (VESA, MII, SMPTE, and BetaCom)
6 Analog Input Video Channels
Automatic NTSC/PAL Identification
Differential Mode Video Input

FUNCTIONAL BLOCK DIAGRAM

and Component Input Support

ADV7183

Digital Output Formats 16-Bit Wide Bus):

YCrCb (4:2:2 or 4:1:1)
CCIR601/CCIR656 8-Bit or 16-Bit

0.5 V to 2.0 V p-p Input Range
Differential Gain, 0.4% Typ
Differential Phase, 0.6
Programmable Video Controls:

Peak White/Hue/Brightness/Saturation/Contrast

APPLICATIONS
Security Systems
Projectors
Digital Televisions
DVD-RAM Recorders and Players
PDP Displays
Video Decoders
Hybrid Analog/Digital Set-Top Boxes

o

Typ

(continued on page 9)

ISO

REFOUT

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

ADV7183

ANALOG I/P

MULTIPLEXING

AUTOMATIC

CONTROL

CLAMP AND

DC RESTORE

PWRDN

GAIN

(AGC)

SHAPING

AND

NOTCH LPF

10-BIT

ADC

27MHz

10-BIT

ADC

HSYNC FIELD VSYNC HREF VREF

LUMA

ANTIALIAS

LPF

SWITCH

VIDEO TIMING AND

CONTROL BLOCK

RECOVERY

ANTIALIAS

PEAKING

HPF/LPF

SUB-

CARRIER

DTO

CHROMA

LPF

RESAMPLING

HORIZONTAL

DETECTION

RESAMPLING

HORIZONTAL

27MHz XTAL

OSCILLATOR

BLOCK

CLOCK

CLOCK

AND

SCALING

SYNC

AND

SCALING

SHAPING

LPF

RESET

LUMA
DELAY
BLOCK

2H LINE

MEMORY

CHROMA

COMB
FILTER

2

C-COMPATIBLE

I

INTERFACE PORT

SDATA SCLOCK

O/P PORT

FIFO CONTROL

FORMATTER

ALSB

P15–P0

PIXEL

BLOCK

AND

PIXEL

OUTPUT

LLC
SYNTHESIS
WITH LINE-

LOCKED
OUTPUT

CLOCK

AFF

HFF/QCLK

AEF

DV

RD

OE

GL/CLKIN

LLC1

LLC2

LLCREF

ELPF

ADLLT is a trademark and ADV is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADV7183–SPECIFICATIONS

(VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, V

1

unless otherwise noted.)

= 3.15 V to 3.5 V, T

DDIO

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (each ADC) 10 Bits
Accuracy (each ADC)
Integral Nonlinearity
Differential Nonlinearity

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

3

3

3

INH

INL

IN

IN

3

OH

OL

2V

–10 +10 µA

2.4 V I

± 0.25 ± 0.5 LSB BSL, 2 V Input Range to ADC
± 0.08 ± 0.17 LSB 2 V Input Range to ADC

0.8 V

10 pF

= 3.2 mA

0.4 V I

SOURCE

= 0.4 mA

SINK

High Impedance Leakage Current 10 µA
Output Capacitance 30 pF

VOLTAGE REFERENCE

Reference Range, V

3

REFOUT

2.15 2.2 2.25 V I

VREFOUT

= 0 µA

POWER REQUIREMENTS

Digital Power Supply, V
Digital IO Power Supply, V
Analog Power Supply, V
Digital Supply Current, I
Digital IO Supply Current, I
Analog Supply Current, I

DD

AA

DD

AA

DDIO

DDIO

4

3.2 3.3 3.5 V

3.15 3.3 3.5 V

4.75 5.0 5.25 V
125 165 mA
7mA
150 180 mA

Power-Up Time 1 Field Sleep Mode until Powered Up

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over VAA= 4.75 V to 5.25 V, VDD = 3.2 to 3.5 V, and V

3.5 V range.

2

Temperature range T

3

Guaranteed by characterization.

4

IAA is total analog current taken by AVDD supply pins.

Specifications subject to change without notice.

MIN

to T

= 0°C to 70°C

MAX

DDIO

to T

MIN

MAX

= 3.15 V to

2

,

REV. 0–2–

ADV7183

VIDEO PERFORMANCE SPECIFICATIONS

(VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, V

1, 2

T

MIN

3

to T

, unless otherwise noted.)

MAX

= 3.15 V to 3.5 V,

DDIO

Parameter Min Typ Max Unit Test Conditions

NONLINEAR SPECIFICATIONS

2

Differential Phase 0.6 Degree CVBS, Comb/No Comb
Differential Gain 0.7 % CVBS, Comb/No Comb
Luma Nonlinearity 1.0 %

NOISE SPECIFICATIONS

2

SNR (Ramp) 61 54 dB CVBS
Analog Front End Channel Crosstalk 63 dB S-Video/YUV, Single-Ended
Analog Front End Channel Crosstalk 63 dB S-Video/YUV, Differential-Ended

LOCK TIME AND JITTER
SPECIFICATIONS

2

Horizontal Lock Time 50 Lines TV/VCR mode
Horizontal Recovery Time 50 Lines
Horizontal Lock Range ± 5%
Line Length Variation Over Field ± 1 % VCR Mode/Surveillance Mode
Line Length Variation Over Field ± 1 % TV Mode
HLock Lost Declared 10 HSync TV Mode, Number of Missing HSyncs
HLock Lost Declared 20 HSync VCR/Surveillance Mode, Number of

Missing HSyncs
Vertical Lock Time 2 VSync First Lock into Video Signal
VLock Lost Declared 1 VSync All Modes, Number of Missing VSyncs

Subcarrier Lock Range ± 400 Hz NTSC/PAL

F

SC

Color Lock Time 50 Lines HLock to Color Lock Time
LLC Clock Jitter (Short Time Jitter) 1 ns RMS Clock Jitter
LLC Clock Jitter (Frame Jitter) 37 ns RMS Clock Jitter

CHROMA-SPECIFIC
SPECIFICATIONS

2

Hue Accuracy 1.0 Degree
Color Saturation Accuracy 1.0 %
Color Gain Control Range –6 +18 dB S-Video, YUV, Overall CGC Range

(Analog and Digital)
Analog Color Gain Range –6 +6 dB S-Video, YUV
Digital Color Gain Range 0 12 dB CVBS, S-Video, YUV
Chroma Amplitude Error 0.1 %
Chroma Phase Error 0 Degree
Chroma Luma Intermodulation 0.1 %

LUMA-SPECIFIC SPECIFICATIONS

2

Luma Brightness Accuracy 1.0 % Video Input Range = 1.0 V p-p
Luma Contrast Accuracy 1.0 % Video Input Range = 1.0 V p-p

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over VAA= 4.75 V to 5.25 V, VDD = 3.2 to 3.5 V, and V

3.5 V range.

2

Guaranteed by characterization.

3

Temperature range T

Specifications subject to change without notice.

MIN

to T

= 0°C to 70°C

MAX

DDIO

= 3.15 V to

REV. 0

–3–

ADV7183

to T

MAX

2

TIMING SPECIFICATIONS

(VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, V

1

unless otherwise noted.)

= 3.15 V to 3.5 V, T

DDIO

MIN

Parameter Min Typ Max Unit Test Conditions

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency 27 MHz

2

C PORT

I

2

SCL Clock Frequency 0 400 kHz
SCL Min Pulsewidth High, t
SCL Min Pulsewidth Low, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SCL/SDA Rise Time, t
SCL/SDA Fall Time, t
Setup Time (Stop Condition), t

1

2

3

4

6

7

8

0.6 µs

1.3 µs

0.6 µs

0.6 µs
100 ns

300 ns
300 ns

0.6 µs

RESET FEATURE

Reset Pulse Input Width 74 ns

CLOCK OUTPUTS

LLC1 Cycle Time, t
LLC1 Cycle Time, t
LLC1 Cycle Time, t
LLC1 Min Low Period, t
LLC1 Min High Period, t
LLC1 Falling to LLCREF Falling, t
LLC1 Falling to LLCREF Rising, t
LLC1 Rising to LLC2 Rising, t
LLC1 Rising to LLC2 Falling, t
CLKIN Cycle Time, t

3

9

9

9

10

11

12

13

14

15

18

37 ns CCIR601 Mode 27 MHz

33.9 ns PAL Square Pixel Mode 29.5 MHz

40.8 ns NTSC Square Pixel Mode 24.5 MHz
18 ns CCIR601 Mode 27 MHz
18 ns CCIR601 Mode 27 MHz
4ns
6ns
35 ns
13 ns
37 ns SCAPI and CAPI Modes

DATA AND CONTROL OUTPUT

Data Output Hold Time, t
Data Output Access Time, t
Data Output Access Time, t
Data Output Hold Time, t
Propagation Delay to High Z, t
Max Output Enable Access Time, t
Min Output Enable Access Time, t

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over VAA= 4.75 V to 5.25 V, VDD = 3.2 to 3.5 V, and V

3.5 V range.

2

Temperature Range T

3

Guaranteed by characterization.

Specifications subject to change without notice.

MIN

to T

17

16

19

20

= 0°C to 70°C

MAX

21

22

23

ANALOG FRONT END SPECIFICATIONS

26 ns LLC Mode

30 33 ns LLC Mode
20 25 ns SCAPI and CAPI Modes

6 11 ns SCAPI and CAPI Modes

58 ns
811 ns

25 ns

(VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, V

1

unless otherwise noted.)

= 3.15 V to 3.5 V, T

DDIO

,

= 3.15 V to

DDIO

2

to T

MAX

,

MIN

Parameter Min Typ Max Unit Test Conditions

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 µF
Input Impedance 10 MΩ Clamp Switched Off
Voltage Clamp Level 1.4 V
Clamp Source Current 3 µA Signal Already Clamped (Fine Clamping)
Sink Current –3 µA Signal Already Clamped (Fine Clamping)
Source Current 0.9 mA Acquire Mode (Fast Clamping)
Clamp Sink Current –0.9 mA Acquire Mode (Fast Clamping)

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over VAA= 4.75 V to 5.25 V, VDD = 3.2 to 3.5 V, and V

3.5 V range.

2

Temperature range T

Specifications subject to change without notice.

MIN

to T

= 0°C to 70°C

MAX

DDIO

= 3.15 V to

REV. 0–4–

SDATA

SCLOCK

t

t

6

3

t

2

t

1

t

7

t

5

Figure 1. MPU Port Timing Diagram

t

9

t

10

LLC1

t

11

t

12

LLCREF

ADV7183

t

3

t

8

t

4

t

13

LLC2

OUTPUTS P0–P19, HREF, VREF,

VSYNC, HSYNC, FIELD, DV

t

14

t

17

t

16

t

15

Figure 2. LLC Clock, Pixel Port, and Control Outputs Timing Diagram

t

18

CLKIN

t

20

OUTPUTS P0–P15, HREF, VREF,

VSYNC, HSYNC, FIELD, DV

t

19

Figure 3. Pixel Port and Control Outputs in CAPI and SCAPI Mode Timing Diagram

OE

t

21

23

t

22

OUTPUTS P0–P15, HS,

VS, VREF, HREF, FIELD, DV

t

Figure 4.OE Timing Diagram

REV. 0

–5–

ADV7183

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

AA

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V

V

DDIO

Voltage on Digital Input Pins . . GND – 0.5 V to V
Storage Temperature (T
Junction Temperature (T

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 260°C

Analog Outputs to GND

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

) . . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . . . 150°C

J

2

. . . . . . . . . . . . GND – 0.5 V to V

1

+ 0.5 V

AA

AA

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Analog output short circuit to any power supply or common can be of an indefinite
duration.

PIN CONFIGURATION

P12

OE

DV

P13

P15

P14

LLC2

LLC1/PCLK

DVDD3

AD7183

TOP VIEW

(Not to Scale)

XTAL

XTAL1

VS/ACTIVE

HS/ACTIVE

DVSSIO

DVDDIO

P11

P10

DVSS2

DVDD2

AFF

HFF/QCLK/GL

AEF

DVSSIO

DVDDIO

CLKIN

GPO3

GPO2

RD

FIELD

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

P9

8

P8

9

10

11

12

13

14

15

16

17

18

19

P7

20

P6

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P5P4P3

P2

LLCREF

ORDERING GUIDE

Model Temperature Range Package

ADV7183KST 0°C to 70°C 80-LQFP

VREF/VRESET

HREF/HRESET

SCLK

DVSS3

DVDD1

DVSS1

SDATA

ALSB

ISO

AIN6

RESET

AVSS

AVSS6

60

AIN5

59

AVSS5

58

AIN4

57

AVSS4

56

AVSS

55

CAPC2

54

CAPC1

53

AVSS

52

CML

51

REFOUT

50

AV DD

49

CAPY2

48

CAPY1

47

AVSS

46

AIN3

45

AVSS3

44

AIN2

43

AVSS2

42

AIN1

41

AVSS1

P1

P0

GPO1

GPO0

ELPF

PWRDN

PVDD

PVSS

AVSS

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7183 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–6–

ADV7183

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Input/Output Function

1 VS/VACTIVE O VS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an

output signal that indicates a vertical sync with respect to the YUV pixel
data. The active period of this signal is six lines of video long. The polarity
of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video field. The polarity of VACTIVE is controlled by PVS bit.

2 HS/HACTIVE O HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a

programmable horizontal sync output signal. The rising and falling edges
can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity
of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video line. The active portion of a video line is programmable on
the ADV7183. The polarity of HACTIVE is controlled by PHS bit.

3, 14 DVSSIO G Digital I/O Ground

4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V)

5–8, 19–24, P15–P0 O Video Pixel Output Port. 8-bit multiplexed YCrCb pixel port (P15–P8),
32, 33, 73–76 16-bit YCrCb pixel port (P15–P8 = Y and P7–P0 = Cb,Cr).

9, 31, 71 DVSS1–3 G Ground for Digital Supply

10, 30, 72 DVDD1–3 P Digital Supply Voltage (3.3 V)

11 AFF O Almost Full Flag. A FIFO control signal indicating when the FIFO has

reached the almost full margin set by the user (use FFM[4:0]). The polarity
of this signal is controlled by the PFF bit.

12 HFF/QCLK/GL I/O Half Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO

control signal that indicates when the FIFO is half full. The QCLK
(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when
using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function
(Genlock output) is a signal that contains a serial stream of data that contains
information for locking the subcarrier frequency. The polarity of HFF signal
is controlled by PFF bit.

13 AEF O Almost Empty Flag. A FIFO control signal, it indicates when the FIFO

has reached the almost empty margin set by the user (use FFM[4:0]). The
polarity of this signal is controlled by PFF bit.

16 CLKIN I Asynchronous FIFO Clock. This asynchronous clock is used to output

data onto the P19-P0 bus and other control signals.

17, 18, 34, 35 GPO[3:0] O General-Purpose Outputs controlled via I

25 LLCREF O Clock Reference Output. This is a clock qualifier distributed by the inter-

nal CGC for a data rate of LLC2. The polarity of LLCREF is controlled
by the PLLCREF bit.

26 LLC2 O Line-Locked Clock System Output Clock/2 (13.5 MHz)

27 LLC1/PCLK O Line-Locked Clock System Output Clock. A dual-function pin

or a FIFO output clock ranging from 20 MHz to 35 MHz.

28 XTAL1 O Second terminal for crystal oscillator; not connected if external clock

source is used.

29 XTAL I Input terminal for 27 MHz crystal oscillator or connection for external

oscillator with CMOS-compatible square wave clock signal

36 PWRDN I Power-Down Enable. A logical low will place part in a power-down status.

37 ELPF I This pin is used for the External Loop Filter that is required for the LLC PLL.

38 PVDD P

39 PVSS G

2

C

(27 MHz ± 5%)

REV. 0

–7–

ADV7183

PIN FUNCTION DESCRIPTIONS (continued)

Pin Mnemonic Input/Output Function

40, 47, 53, 56, AVSS G Ground for Analog Supply
63

41, 43, 45, 57, AVSS1–6 G Analog Input Channels. Ground if single-ended mode is selected. These
59, 61 pins should be connected directly to REFOUT when differential mode is

selected.

42, 44, 46, 58, AIN1–6 I Video Analog Input Channels
60, 62

48, 49 CAPY1–2 I ADC Capacitor Network

50 AVDD P Analog Supply Voltage (5 V)

51 REFOUT O Internal Voltage Reference Output

52 CML O Common-Mode Level for ADC

54, 55 CAPC1–2 I ADC Capacitor Network
64 RESET I/O System Reset Input. Active Low.

65 ISO I Input Switch Over. A low to high transition on this input indicates to the

decoder core that the input video source has been changed externally and
configures the decoder to reacquire the new timing information of the new
source. This is useful in applications where external video muxes are used.
This input gives the advantage of faster locking to the external muxed
video sources. A low to high transition triggers this input.

66 ALSB I TTL Address Input. Selects the MPU address:

MPU address = 88h ALSB = 0, disables I
MPU address = 8Ah ALSB = 1, enables I

67 SDATA I/O MPU Port Serial Data Input/Output

68 SCLK I MPU Port Serial Interface Clock Input
69 VREF/VRESET O VREF or Vertical Reference Output Signal. Indicates start of next field.

VRESET or Vertical Reset Output is a signal that indicates the beginning
of a new field. In SCAPI/CAPI mode this signal is one clock wide and
active low relative to CLKIN. It immediately follows the HRESET pixel,
and indicates that the next active pixel is the first active pixel of the next
field.

70 HREF/HRESET O HREF or Horizontal Reference Output Signal. A dual-function pin

(enabled when Line-Locked Interface is selected, OM_SEL[1:0] = 0,0),
this signal is used to indicate data on the YUV output. The positive slope
indi

cates the beginning of a new active line; HREF is always 720 Y samples

. HRESET or Horizontal Reset Output (enabled when SCAPI or

long
CAPI is
beginning
cycle wide
active pixel

77 RD I

78 DV O DV or Data Valid Output Signal. In SCAPI/CAPI mode, DV performs two

79 OE I Output Enable Controls Pixel Port Outputs. A logic high will three-state

80 FIELD O ODD/EVEN Field Output Signal. An active state indicates that an even

Asynchronous FIFO Read Enable Signal. A logical high on this pin enables
a read from the output of the FIFO.

functions, depending on whether SCAPI or CAPI is selected. It toggles
high when the FIFO has reached the AFF margin set by the user, and
remains high until the FIFO is empty. The alternative mode is where it can
be used to control FIFO reads for bursting information out of the FIFO. In
API mode DV indicates valid data in the FIFO, which includes both pixel
information and control codes. The polarity of this pin is controlled via PDV.

P19–P0.

field is being digitized. The polarity of this signal is controlled by the PF bit.

selected, OM_SEL[1:0] = 0, 1 or 1, 0) is a signal that indicates the

of a new line of video. In SCAPI/CAPI this signal is one clock

and is output relative to CLKIN. It immediately follows the last
of a line. The polarity is controlled via PHVR.

2

C filter

2

C filter

REV. 0–8–

ADV7183

(FEATURES continued from page 1)

CCIR/Square Pixel Operation
Integrated On-Chip Video Timing Generator
Synchronous or Asynchronous Output Timing
Line-Locked Clock Output
Closed Captioning Passthrough Operation
Vertical Blanking Interval Support
Power-Down Mode
2-Wire Serial MPU Interface (I

2

C-Compatible)
5 V Analog 3.3 V Digital Supply Operation
80-Lead LQFP Package

GENERAL DESCRIPTION

The ADV7183 is an integrated video decoder that automatically
detects and converts a standard analog baseband television sig­nal compatible with worldwide standards NTSC or PAL into
4:2:2 or 4:1:1 component video data compatible with 16-/8-bit
CCIR601/CCIR656.

The advanced and highly flexible digital output interface
enables performance video decoding and conversion in both
frame-buffer-based and line-locked clock-based systems. This
makes the device ideally suited for a broad range of applica­tions with diverse analog video characteristics, including
tape-based sources, broadcast sources, security/surveillance
cameras, and professional systems.

Fully integrated line stores enable real-time horizontal and
vertical scaling of captured video down to icon size. The 10-bit
accurate A/D conversion provides professional quality SNR
performance. This allows true 8-bit resolution in the 8-bit out­put mode.

The six analog input channels accept standard composite,
S-video, and component YCrCb video signals in an extensive
number of combinations. AGC and clamp restore circuitry
allow an input video signal peak-to-peak range of 0.5 V up to
2 V. Alternatively, these can be bypassed for manual settings.

The fixed 27 MHz clocking of the ADCs and data path for all
modes allows very precise and accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line-locked even with ±5% line length varia­tion. The output control signals allow glueless interface
connection in almost any application.

The ADV7183 modes are set up over a 2-wire serial bidirec­tional port (I

2

C-compatible).

The ADV7183 is fabricated in a 5 V CMOS process. Its mono­lithic CMOS construction ensures greater functionality with
lower power dissipation.

The ADV7183 is packaged in a small 80-pin LQFP package.

ANALOG INPUT PROCESSING

The ADV7183 has six analog video input channels. These six
channels can be arranged in a variety of configurations to support
up to six CVBS input signals, three S-video input signals, and two
YCrCb component analog video input signals. The INSEL[3:0]
bits control the input type and channel selected.
front end includes three clamp circuits for DC restore.

The analog

There are
three sample-and-hold amplifiers prior to the ADC which are
used to enable simultaneous sampling of up to three channels in
a YCrCb input mode. Two 10-bit ADCs are used for sampling.
The entire analog front end is fully differential which ensures that
the video is captured to the highest quality possible. This is very
important in highly integrated systems such as video decoders.
Figure 5 shows the analog front end section of the ADV7183.

MUX 6CVBS 3YC 2YUV

1

CLAMP V

SHA

ⴛ 2

MUX

NOTES
ANALOG SIGNAL PATH KEPT FULLY DIFFERENTIAL
ADCs: 10-BIT ACCURATE; 12dB GAIN RANGE

1

CLAMP BLOCKS CONTAIN A SET OF CURRENT SOURCES FOR DC
RESTORATION; U AND V HAVE ONLY HALF BANDWIDTH (SAMPLED
SIMULTANEOUSLY, CONVERTED SEQUENTIALLY)

2

PIPELINED

CLAMP U

SHA

ⴛ 2

1

CLAMP Y

SHA

ⴛ 2

1

Y ADC

C ADC

10

2

10

2

Figure 5. Analog Front End Block Diagram

CLAMPING

The clamp control on the ADV7183 consists of a digitally
controlled analog current and voltage clamp and a digitally
controlled digital clamp circuit. The coupling capacitor on each
channel is used to store and filter the clamping voltage. A digital
controller controls the clamp up and down current sources that
charge the capacitor on every line. Four current sources are
used in the current clamp control, two large current sources are
used for coarse clamping, and two small current sources are used
for fine clamping. The voltage clamp, if enabled, is only used on
startup or if a channel is switched. This clamp pulls the video
into the midrange of the ADC, which results in faster clamping
and faster lock-in time for the decoder. The fourth clamp con­troller is fully digital and clamps the ADC output data, which
results in extremely accurate clamping. It also has the added
advantage of being fully digital, which results in very fast clamp
timing and makes the entire clamping process very robust in
terms of handling large amounts of hum that can be present on
real-world video signals.

REV. 0

–9–

ADV7183

In S-video mode there are two clamp controllers used to sepa­rately control the luminance clamping and the chrominance
clamping. Also in YCrCb component input mode there are two
clamp controllers used to control the luminance clamping and
the CrCb clamping separately; there are, however, individual
current clamps on the Cr and Cb inputs.

User programmability is built into the clamp controllers which
enable the current and digital clamp controllers to be set up to
user-defined conditions. Refer to analog clamp control register
(14H), digital clamp control register (15H), and digital color
clamp offset register (15H and 16H) for control settings.

ANALOG-TO-DIGITAL CONVERTERS

Two 10-bit ADCs are used in the ADV7183, and they run from
a 27 MHz input clock. An integrated band gap generates the
required reference voltages for the converters. If the decoder is
configured in CVBS mode, the second ADC can be switched off
to reduce power consumption, see PSC[1:0].

AUTOMATIC GAIN CONTROL

The AGC control block on the ADV7183 is a digitally based
system. This controller ensures that the input video signal
(CVBS, S-video, or YCrCb) is scaled to its correct value such
that the YCrCb digital output data matches the correct gain of
the video signal. The AGC has an analog input video range of

0.5 V p-p to 2.0 V p-p, which gives a –6 dB to +6 dB gain range.
Figure 6 demonstrates this range. This AGC range will compensate
for video signals that have been incorrectly terminated or have
been attenuated due to cable loss or other factors.

There are two main control blocks: one for the luminance chan­nel and one for the chrominance channel.

The luminance automatic gain control has eight modes of
operation:

1. Manual AGC mode where gain for the luminance path is set
manually using LGM[11:0].

2. Blank level to sync tip is used to set the luminance gain;
manual MIRE[2:0] controls the maximum value through the
luminance channel. There is no override of this mode when
white peak mode is detected.

3. Blank level to sync tip is used to set luminance gain; manual
MIRE[2:0] controls the maximum value through luminance
channel. There is override of this mode when white peak
mode is detected. White peak mode is activated when the
input video exceeds the maximum luminance range for long
periods; this mode is designed to prevent clipping of the
input video signal.

4. Blank level to sync tip is used to set luminance gain;
MIRE[2:0] is automatically controlled to set the maximum
value through the luminance channel. There is no override
of this mode when white peak mode is detected.

5. Blank level to sync tip is used to set luminance gain; manual
MIRE[2:0] is automatically controlled to set the maximum
value through the luminance channel. There is override of
this mode when white peak mode is detected. White peak
mode is activated when the input video exceeds the maxi­mum luminance range for long periods; this mode is designed
to prevent clipping of the input video signal.

6.

Based on active video peak white. PW_UPD sets the gain
update

frequency (once per field).

7.

Based on average active video. PW_RES sets what lines are used;
only relevant if the signal conforms to PAL 625 line standard.

8. The luminance channel gain is frozen at its present value.

MAXIMUM

6

0

0

CONTROLLED ADC INPUT LEVEL – dB

ANALOG INPUT LEVEL 2V p-p – dB

RANGE = 12dB

–6

MINIMUM

Figure 6. Analog Input Range

The chrominance automatic gain control has four modes of
operation:

1. Manual AGC mode where gain for chrominance path is set
manually using CGM[11:0].

2. Luminance gain used for chrominance channel.

3. Chrominance automatic gain based on color burst amplitude.

4. Chrominance gain frozen at its present setting.

Both the luminance and chrominance AGC controllers have a
programmable time constant that allows the AGC to operate in
four modes: slow, medium, fast, and video quality controlled.

The maximum IRE (MIRE[2:0]) control can be used to set the
maximum input video range that can be decoded. Table I shows
the selectable range.

Table I. MIRE Control

Function

MIRE[2:0] PAL (IRE) NTSC (IRE)

0 0 0 133 122
0 0 1 125 115
0 1 0 120 110
0 1 1 115 105
1 0 0 110 100
1 0 1 105 100
1 1 0 100 100
1 1 1 100 100

REV. 0–10–

ADV7183

LUMINANCE PROCESSING

Figure 7 shows the luminance data path. The 10-bit data from
the Y ADC is applied to an antialiasing low pass filter that is
designed to band-limit the input video signal such that aliasing
does not occur. This filter dramatically reduces the design on an
external analog antialaising filter; this filter need only remove
components in the input video signal above 22 MHz. The data
then passes through a shaping or notch filter.

When in CVBS mode a notch filter must be used to remove the
unwanted chrominance data that lies around the subcarrier
frequency. A wide variety of programmable notch filters for
both PAL and NTSC are available. The YSFM[4:0] control the
selection of these filters; refer to Figures 8 to 16 for plots of
these filters. If S-video or component mode is selected a notch
filter is not required. The ADV7183 offers 18 possible shaping
filters (SVHS1-18) with a range of low pass filter responses from

0.5 MHz up to 5.75 MHz. The YSFM[4:0] control the selec­tion of these filters. Please refer to Figures 8 through 16 for
filter plots.

The next stage in the luminance processing path is a peaking
filter; this filter offers a sharpness function on the luminance
path. The degree of sharpness can be selected using YPM[2:0].
If no sharpness is required, this filter can be bypassed.

The luminance data is then passed through a resampler to correct
for line length variations in the input video. This resampler is
designed to always output 720 pixels per line for standard PAL or
NTSC. The resampler used on the ADV7183 is of very high
quality as it uses 128 phases to resample the video, giving 1/128
pixel resolution. The resampler is controlled by a sync detection
block that calculates line length variations on the input video.

The final stage in the luminance path, before it is applied to an
output formatter block, is a two-line delay store that is used to
compensate for delays in the chroma data path when chroma
comb filter is selected.

ADC DATA

ANTI-

ALIASING

LPF

SYNC

DETECTION

0

SVHS1

–10

ATTENUATION – dB

–20

–30

–40

–50

–60

SVHS2

081

SVHS3

SVHS4

SVHS5

SVHS6

SVHS7

SVHS8

SVHS9

SVHS10

SVHS11

SVHS12

SVHS13

SVHS14

23 45 67

FREQUENCY – MHz

SVHS15

SVHS16

SVHS17

SVHS18

Figure 8. Luminance SVHS1–18 Shaping Filter
Responses

1.0

0.8

0.6

0.4

0.2

0

–0.2

ATTENUATION – dB

–0.4

–0.6

–0.8

–1.0

061

2345

FREQUENCY – MHz

Figure 9. Luminance SVHS1–SVHS18 Shaping
Filter Responses (Close-Up)

REV. 0

SHAPING

AND
NOTCH
FILTER

PEAKING

FILTER

RESAMPLE

Y

DELAY

LINE

STORES

Figure 7. Luminance Processing Path

–11–

0

NTSC WN1
NTSC WN2
NTSC WN3

–10

NTSC NN1
NTSC NN2
NTSC NN3

ATTENUATION – dB

–20

–30

–40

–50

–60

081

23 45 67

FREQUENCY – MHz

NTSC WN2
NTSC NN3
NTSC WN1
NTSC NN2
NTSC NN1
NTSC WN3

Figure 10. Luminance NTSC Narrow/Wide Notch
Shaping Filter

ADV7183

1.0

0.8

0.6

0.2

0.4

0

ATTENUATION – dB

–0.2

–0.4

–0.6

–0.8

–1.0

0

1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY – MHz

NTSC WN1
NTSC WN2
NTSC WN3
NTSC NN1
NTSC NN2
NTSC NN3

4.00.5

Figure 11. Luminance NTSC Narrow/Wide Notch
Shaping Filter (Close-Up)

0

PAL NN1

ATTENUATION – dB

–10

–20

–30

–40

–50

PAL NN2
PAL NN3

PAL W1
PAL W2

PAL NN1

PAL NN3
PAL W1
PAL W2
PAL NN2

10

8

6

4

2

0

–2

ATTENUATION – dB

–4

–6

–8

01234567

PS1

PS2

PS3

PS4

PS5

PS6

FREQUENCY – MHz

Figure 14. Luminance Peaking Filter Responses in
S-Video (SVHS17 Selected)

6

PC1

PC2

PC3

PC4
PC5

PC6

ATTENUATION – dB

4

2

0

–2

–4

–6

–8

–60

081

23 45 67

FREQUENCY – MHz

Figure 12. Luminance PAL Narrow/Wide Notch
Shaping Filter Responses

1.0

0.8

0.6

0.2

0.4

0

ATTENUATION – dB

–0.2

–0.4

–0.6

–0.8

–1.0

0

1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY – MHz

PAL NN1
PAL NN2

PAL NN3
PAL WN1
PAL WN2

Figure 13. Luminance PAL Narrow/Wide Notch
Shaping Filter Responses (Close-Up)

–10

0

FREQUENCY – MHz

7123456

Figure 15. Luminance Peaking Filter Responses in
CVBS (PAL NN3 Selected)

6

4

2

0

–2

ATTENUATION – dB

–4

–6

4.00.5

–8

0

PC1

PC2

PC3

PC4

PC5

PC6

2345

FREQUENCY – MHz

61

Figure 16. Luminance Peaking Filter Responses in
CVBS (NTSC NN3 Selected)

REV. 0–12–

ADV7183

CHROMINANCE PROCESSING

Figure 17 shows the chrominance data path. The 10-bit data
from the Y ADC (CVBS mode) or the C ADC (S-video) is first
demodulated. The demodulation is achieved by multiplying by
the locally generated quadrature subcarrier, where the sign of
the cos subcarrier is inverted from line to line according to the
PAL switch, and then low pass filtering is applied to removed
components at twice the subcarrier frequency. For NTSC, the
phase of the locally generated subcarrier during color burst is
the same as the phase of the color burst. For PAL, the phase of
the color burst changes from line to line, relative to the phase
during active video, and the phase of the locally generated
subcarrier is the average of these two values.

The chrominance data is then passed through an antialiasing
filter which is a band-pass filter to remove the unwanted lumi­nance data. This antialaising filter dramatically reduces the
external antialaising filter requirements as it has only to filter
components above 25 MHz. In component mode the demodu­lation block is bypassed.

The next stage of processing is a shaping filter that can be used
to limit the chrominance bandwidth to between 0.5 MHz
and 3 MHz; the CSFM[2:0] can be used to select these
responses. It should be noted that in CVBS mode a filter of no
greater than 1.5 MHz should be selected, as CVBS video is
typically band-limited to below 1.5 MHz. In S-video mode a
filter of up to 2 MHz can be used. In component mode a filter
of up to 3 MHz can be used as component video has higher
bandwidth than CVBS or S-video.

The chrominance data is then passed through a resampler to
correct for line length variations in the input video. This
resampler is designed to always output 720 pixels per line for
standard PAL or NTSC. The resampler used on the ADV7183
is of very high quality as it uses 64 phases to resample the video,
giving 1/64 pixel resolution. The resampler is controlled by a
sync detection block that calculates line length variations on the
input video.

The final stage in the chrominance path, before it is applied to
an output formatter block, is chroma comb filter.

0

–10

–20

SH2 SH3 SH4 SH5 SH6SH1

–30

–40

ATTENUATION – dB

–50

–60

0 4.00.5

1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY – MHz

Figure 18. Chrominance Shaping Filter Responses

1.0

0.8

0.6

0.2

0.4

0

–0.2

ATTENUATION – dB

–0.4

–0.6

–0.8

–1.0

SH2SH3 SH4 SH5SH1 SH6

0

1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY – MHz

4.00.5

Figure 19. Chrominance Shaping Filter Responses
(Close-Up)

CV/C

27MHz

REV. 0

SINE

INTERLEAVE

COSINE

ANTI-

ALIASING

ANTI-

ALIASING

SUBCARRIER

RECOVERY

LPF

LPF

13.5MHz

13.5MHz

DETECTION

SYNC

SHAPING

LPF

6.75MHz

RESAMPLE

U/V

CHROMA

COMB

FILTERS

Figure 17. Chrominance Processing Path

–13–