ANALOG DEVICES ADV7181D Service Manual

10-Bit, 10-Channel, Multiformat SDTV/HDTV

Video Decoder and RGB Graphics Digitizer

Data Sheet

FEATURES

Four 10-bit ADCs sampling up to 75 MHz 10 analog input channels SCART fast blank support Internal antialiasing filters NTSC, PAL, and SECAM color standards supported 525p/625p component progressive scan supported 720p/1080i component HDTV supported Digitizes RGB graphics up to 1024 × 768 at 70 Hz (XGA) 3 × 3 color space conversion matrix Industrial temperature range: −40°C to +85°C 12-bit 4:4:4 DDR, 8-/10-/16-/20-bit SDR pixel output interface Programmable interrupt request output pin Small package Low pin count Single front end for video and graphics VBI data slicer (including teletext) Qualified for automotive applications

APPLICATIONS

Automotive entertainment HDTVs LCD/DLP® projectors HDTV STBs with PVR DVD recorders with progressive scan input support AVR receivers

ADV7181D

GENERAL DESCRIPTION

The ADV7181D is a high quality, single-chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-Video into a digital ITU-R BT.656 format.

The ADV7181D also supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. Support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, and many other HD and SMPTE standards.

Graphics digitization is also supported by the ADV7181D; it is capable of digitizing RGB graphics signals from VGA to XGA rates and converting them into a digital DDR RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ability of the ADV7181D to simultaneously process CVBS and standard definition RGB signals. The mixing of these signals is controlled by the fast blank (FB) pin.

The ADV7181D contains two main processing sections. The first section is the standard definition processor (SDP), which processes all PAL, NTSC, and SECAM signal types. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADV7181D Data Sheet

REVISION HISTORY

12/11—Revision 0: Initial Version

Standard Definition Processor (SDP) Pixel Data Output

Modes ........................................................................................... 12

Component Processor (CP) Pixel Data Output Modes ........ 12

Composite and S-Video Processing ......................................... 12

Component Video Processing .................................................. 13

RGB Graphics Processing ......................................................... 13

General Features ......................................................................... 13

Detailed Descriptions .................................................................... 14

Analog Front End ....................................................................... 14

Standard Definition Processor (SDP) ...................................... 14

Component Processor (CP) ...................................................... 14

Analog Input Muxing ................................................................ 15

Pixel Output Formatting................................................................ 18

Recommended External Loop Filter Components .................... 19

Typical Connection Diagram ....................................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

Automotive Products ................................................................. 21



Rev. 0 | Page 2 of 24

Data Sheet ADV7181D

FUNCTIONAL BLOCK DIAGRAM

LUMA

VBI DATA RECOVERY

STANDARD

AUTODET ECTI ON

STANDARD DEFINITION PROCESSOR

09994-001

PIXEL

DATA

P19 TO

P10

P9 TO

P0

10

20

Y

(5H MAX)

2D COMB

LUMA

RESAMPLE

LUMA

FILTER

RESAMPLE

SYNC

HS/CS

VS

FIELD/DE

LLC

SFL/

SYNC_OUT

OUTPUT FI FO AND FORMATTER

AND

FAST

BLANK

AV CODE

OVERLAY

CONTRO L

INSERTION

Cr

Cb

CHROMA

2D COMB

CONTROL

EXTRACT

CHROMA

Y

Cr

FB

(4H MAX)

RESAMPLE

FILTER

Cb

INT

20

AV CODE

INSERTION

OFFSET

CONTROL

CGMS DATA

EXTRACTIO N

GAIN

COMPONENT PROCESSOR

DETECTIO N

MACROVISIO N

CONTROL

ADV7181D

AGC

101010

XTAL XTAL1

DIGITAL

FINE

COLOR SPACE

CLAMP

CONVERSION

SC

ADC1CLAMP

ALIASING

10

A

f

RECOVERY

10

AND

FILTERS

DECIMATION

DOWNSAMPLI NG

10

ADC2CLAMP

ANTI-

FILTER

ALIASING

MUX

INPUT

CVBS

YPrPb

SCART–

S-VIDEO

IN

(RGB + CVBS)

GRAPHICS RGB

DEMOD

CHROMA

Cb

Cr

C

CVBS

10

ADC3CLAMP

ANTI-

FILTER

ALIASING

FB

SERIAL INTERFACE

CONTROL AND VBI DATA

SCLK

SDATA

CLOCK GENERATIO N

SYNC PROCESSING AND

ALSB

HS_IN/

DETECTION

MACROVISIO N

CVBS/Y

101010

DATA

PREPROCESSOR

10

ADC0CLAMP

ANTI-

FILTER

ALIASING

10

1

IN

TO

A

AND

ACTIVE PEAK

STDI

SSPD

SOY

SOG

VS_IN

CS_IN

Figure 1.

Rev. 0 | Page 3 of 24

ADV7181D Data Sheet

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range = 1.6 V. T to T

= −40°C to +85°C, unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.

MAX

MIN

Table 1.

1

Parameter

STATIC PERFORMANCE

2, 3

Symbol Test Conditions/Comments Min Typ Max Unit

Resolution (Each ADC) N 10 Bits

Integral Nonlinearity INL BSL at 27 MHz (10-bit level) ±0.6 ±2.5 LSB BSL at 54 MHz (10-bit level) −0.6/+0.7 LSB BSL at 74 MHz (10-bit level) ±1.4 LSB

Differential Nonlinearity DNL At 27 MHz (10-bit level) −0.2/+0.25 −0.99/+2.5 LSB At 54 MHz (10-bit level) −0.2/+0.25 LSB At 74 MHz (10-bit level) ±0.9 LSB DIGITAL INPUTS

Input High Voltage

4

VIH 2 V

HS_IN, VS_IN low trigger mode 0.7 V

Input Low Voltage

5

VIL 0.8 V

HS_IN, VS_IN low trigger mode 0.3 V

Input Current IIN −10 +10 μA

Input Capacitance

6

CIN 10 pF

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

High Impedance Leakage Current I

7

V

VOH I

I

OL

Pin 1 60 μA

LEAK

= 0.4 mA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

All other output pins 10 μA

Output Capacitance POWER REQUIREMENTS

6

C

6

20 pF

OUT

Digital Core Power Supply DVDD 1.65 1.8 2.0 V

Digital I/O Power Supply DVDDIO 3.0 3.3 3.6 V

PLL Power Supply PVDD 1.71 1.8 1.89 V

Analog Power Supply AVDD 3.15 3.3 3.45 V

Digital Core Supply Current I

CVBS input sampling at 54 MHz 105 mA

DVDD

Graphics RGB sampling at 75 MHz 90 mA SCART RGB FB sampling at 54 MHz 106 mA

Digital I/O Supply Current I

CVBS input sampling at 54 MHz 4 mA

DVDDIO

Graphics RGB sampling at 75 MHz 38 mA

PLL Supply Current I

CVBS input sampling at 54 MHz 11 mA

PVDD

Graphics RGB sampling at 75 MHz 12 mA

Analog Supply Current

8

I

CVBS input sampling at 54 MHz 99 mA

AVDD

Graphics RGB sampling at 75 MHz 166 mA SCART RGB FB sampling at 54 MHz 200 mA

Power-Down Current I

Green Mode Power-Down I

Power-Up Time t

1

All specifications are obtained using the Analog Devices, Inc., recommended programming scripts.

2

All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%.

3

Maximum INL and DNL specifications obtained with part configured for component video input.

4

To obtain specified VIH level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIH on Pin 22 is 1.2 V.

5

To obtain specified VIL level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIL on Pin 22 is 0.4 V.

6

Guaranteed by characterization.

7

VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.

8

For CVBS current measurements only, ADC0 is powered up. For RGB current measurements only, ADC0, ADC1, and ADC2 are powered up. For SCART FB current

measurements, all four ADCs are powered up.

2.25 mA

PWRDN

Synchronization bypass function 16 mA

PWRDNG

20 ms

PWRUP

Rev. 0 | Page 4 of 24

Data Sheet ADV7181D

VIDEO SPECIFICATIONS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.

MIN

to T

= −40°C to +85°C,

MAX

Table 2.

Parameter

1

Symbol Test Conditions/Comments Min Typ Max Unit

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulated 5 step 0.5 Degrees Differential Gain DG CVBS input, modulated 5 step 0.5 % Luma Nonlinearity LNL CVBS input, 5 step 0.5 %

NOISE SPECIFICATIONS

Signal-to-Noise Ratio, Unweighted SNR Luma ramp 54 56 dB

Luma flat field 58 60 dB

Analog Front-End Crosstalk 60 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range −5 +5 % Vertical Lock Range 40 70 Hz fSC Subcarrier Lock Range ±1.3 kHz Color Lock-In Time 60 Lines Synchronization Depth Range

2

20 200 % Color Burst Range 5 200 % Vertical Lock Time 2 Fields Horizontal Lock Time 100 Lines

CHROMA SPECIFICATIONS

Hue Accuracy 1 Degrees Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.5 % Chroma Phase Error 0.4 Degrees Chroma Luma Intermodulation 0.2 %

LUMA SPECIFICATIONS

Luma Brightness Accuracy CVBS, 1 V input 1 % Luma Contrast Accuracy CVBS, 1 V input 1 %

1

Guaranteed by characterization.

2

Nominal synchronization depth is 300 mV at 100% synchronization depth range.

Rev. 0 | Page 5 of 24

ADV7181D Data Sheet

ANALOG SPECIFICATIONS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range. The recommended analog input video signal range is 0.5 V to 1.6 V, typically 1 V p-p.

MIN

to T

= −40°C to +85°C,

MAX

Table 3.

1

Parameter

Test Conditions/Comments Min Typ Max Unit

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF Input Impedance

All Pins Except for Pin 32 (FB) Clamps switched off 10 MΩ

Pin 32 (FB) 20 kΩ Common-Mode Level (CML) 1.86 V ADC Full-Scale Level CML + 0.8 V ADC Zero-Scale Level CML − 0.8 V ADC Dynamic Range 1.6 V Clamp Level (When Locked) CVBS input CML − 0.292 V

SCART RGB input (R, G, B signals) CML − 0.4 V S-Video input (Y signal) CML − 0.292 V S-Video input (C signal) CML V Component input (Y, Pr, Pb signals) CML − 0.3 V PC RGB input (R, G, B signals) CML − 0.3 V

Large Clamp Source Current SDP only 0.75 mA Large Clamp Sink Current SDP only 0.9 mA Fine Clamp Source Current SDP only 17 μA Fine Clamp Sink Current SDP only 17 μA

1

Guaranteed by characterization.

Rev. 0 | Page 6 of 24

Data Sheet ADV7181D

TIMING CHARACTERISTICS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T

unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.

MIN

to T

= −40°C to +85°C,

MAX

Table 4.

Parameter

1

Symbol Description Min Typ Max Unit

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency 28.63636 MHz Crystal Frequency Stability ±50 ppm Horizontal Sync Input Frequency 14.8 110 kHz LLC Frequency Range 12.825 75 MHz

I2C PORT

2

SCLK Frequency 400 kHz SCLK Minimum Pulse Width High t1 0.6 μs SCLK Minimum Pulse Width Low t2 1.3 μs Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs SDATA Setup Time t5 100 ns SCLK and SDATA Rise Time t6 300 ns SCLK and SDATA Fall Time t7 300 ns Setup Time (Stop Condition) t8 0.6 μs

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC Mark-Space Ratio t9:t10 45:55 55:45

% duty cycle

DATA AND CONTROL OUTPUTS

Data Output Transition Time

SDR (SDP)

t

SDR (CP)

t

DDR (CP) t t t

1

Guaranteed by characterization.

2

TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.

3

SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.

4

CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.

5

DDR timing specifications dependent on LLC output pixel clock; T

3

4

4, 5

t

t11 Negative clock edge to start of valid data 3.6 ns

End of valid data to negative clock edge 2.4 ns

12

t13 End of valid data to negative clock edge 2.8 ns

Negative clock edge to start of valid data 0.1 ns

14

Positive clock edge to end of valid data −4 + T

15

Positive clock edge to start of valid data 0.25 + T

16

Negative clock edge to end of valid data −2.95 + T

17

Negative clock edge to start of valid data −0.5 + T

18

/4 = 9.25 ns at LLC = 27 MHz.

LLC

/4 ns

LLC

/4 ns

LLC

/4 ns

LLC

/4 ns

LLC

Timing Diagrams

SDATA

t

3

t

5

t

3

t

6

1

SCLK

t

2

t

7

Figure 2. I

2

C Timing

t

4

t

8

09994-002

Rev. 0 | Page 7 of 24

ADV7181D Data Sheet

t

9

LLC

t

P0 TO P19, VS,

HS/CS, FI ELD/DE,

SFL/SYNC_OUT

12

Figure 3. Pixel Port and Control SDR Output Timing (SDP Core)

t

10

t

11

09994-003

LLC

P0 TO P19

t

9

t

13

t

10

t

14

09994-004

Figure 4. Pixel Port and Control SDR Output Timing (CP Core)

LLC

P6 TO P19

t

16

t

15

t

18

t

17

09994-005

Figure 5. Pixel Port and Control DDR Output Timing (CP Core)

Rev. 0 | Page 8 of 24

ANALOG DEVICES ADV7181D Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VIDEO SPECIFICATIONS

ANALOG SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagrams