ANALOG DEVICES ADV7181C Service Manual

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Video Decoder and RGB Graphics Digitizer
10-Bit, Integrated, Multiformat SDTV
FEATURES
Four 10-bit ADCs sampling up to 110 MHz 6 analog input channels SCART fast blank support Internal antialias filters NTSC, PAL, SECAM color standards support 525p/625p component progressive scan support 720p/1080i component HDTV support Digitizes RGB graphics up to 1280 × 1024 at 60 Hz (SXGA) 3 × 3 color space conversion matrix Industrial temperature range: −40°C to +85°C 12-bit 4:4:4 DDR, 8-/10-/16-/20-bit SDR pixel output interface Programmable interrupt request output pin Small package Low pin count Single front end for video and graphics
APPLICATIONS
Automotive entertainment HDTVs LCD/DLP projectors HDTV STBs with PVR DVD recorders with progressive scan input support AVR receivers
ADV7181C
GENERAL DESCRIPTION
The ADV7181C is a high quality, single-chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-Video into a digital ITU-R BT.656 format. The ADV7181C also supports the decoding of a com­ponent RGB/YPrPb video signal into a digital YCrCb or RGB DDR pixel output stream. The support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, and many other HD and SMPTE standards. Graphics digitization is also supported by the ADV7181C; it is capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital DDR RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ability of the ADV7181C to process simultaneously CVBS and standard definition RGB signals. The mixing of these signals is controlled by the fast blank pin.
The ADV7181C contains two main processing sections. The first section is the standard definition processor (SDP), which processes all PAL, NTSC, and SECAM signal types. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics.
Rev. 0
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADV7181C
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 4
Video Specifications ..................................................................... 5
Timing Characteristics ................................................................ 6
Analog Specifications ................................................................... 7
Absolute Maximum Ratings ............................................................ 8
Package Thermal Performance ................................................... 8
Thermal Specifications ................................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Detailed Functionality ................................................................... 11
Analog Front End ....................................................................... 11
SDP Pixel Data Output Modes ................................................. 11
CP Pixel Data Output Modes ................................................... 11
Composite and S-Video Processing ......................................... 11
Component Video Processing .................................................. 12
RGB Graphics Processing ......................................................... 12
General Features ......................................................................... 12
Detailed Description ...................................................................... 13
Analog Front End ....................................................................... 13
Standard Definition Processor (SDP) ...................................... 13
Component Processor (CP) ...................................................... 13
Analog Input Muxing ................................................................ 14
Pixel Output Formatting................................................................ 16
Recommended External Loop Filter Components .................... 17
Typical Connection Diagram ....................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADV7181C
FUNCTIONAL BLOCK DIAGRAM
VBI DATA RECOVERY
STANDARD
AUTODETECTI ON
STANDARD DEFINITION P ROCESSOR
07513-001
PIXEL
DATA
P19 TO
P10
P9 TO
P0
10
10
20
Y
LUMA
(5H MAX)
2D COMB
LUMA
RESAMPLE
LUMA
FILTER
RESAMPLE
SYNC
HS/CS
VS
FIELD/DE
LLC
SFL/
SYNCOUT
OUTPUT FI FO AND FORMAT TER
AND
FAST
BLANK
AV CODE
OVERLAY
CONTROL
INSERTION
Cr
Cb
CHROMA
2D COMB
CONTROL
EXTRACT
CHROMA
CHROMA
Y
Cr
Cb
(4H MAX)
RESAMPLE
FILTER
INT
20
AV CODE
INSERTION
OFFSET
CONTROL
CGMS DATA
EXTRACTIO N
GAIN
COMPONENT PROCESSOR
DETECTIO N
MACROVISIO N
CONTROL
ADV7181C
AGC
101010
XTAL
DIGITAL
FINE
COLORSPACE
CLAMP
CONVERSION
SC
ADC1CLAMP
6
A
ALIAS
INPUT
IN
DECIMATION
F
RECOVERY
10
AND
FILTERS
DOWNSAMPLI NG
10
ADC2CLAMP
ANTI-
ALIAS
FILTER
FILTER
MUX
CVBS
YPrPb
SCART–
S-VIDEO
(RGB + CVBS)
GRAPHICS RGB
DEMOD
CHROMA
Cb
Cr
C
CVBS
10
ADC3CLAMP
ANTI-
ALIAS
FILTER
FB
SERIAL INTERFACE
CONTROL AND VBI DATA
SCLK
SDATA
CLOCK GENERATION
SYNC PROCESSING AND
ALSB
HS_IN/
DETECTION
MACROVISIO N
CVBS/Y
101010
DATA
PREPROCESSOR
10
10
ADC0CLAMP
ANTI-
ANTI-
ALIAS
FILTER
6
IN1
TO
A
AND
ACTIVE PEAK
STDI
SSPD
VS_IN
CS_IN
SOG/SOY
Figure 1.
Rev. 0 | Page 3 of 20
ADV7181C
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. T
MIN
to T
= −40°C to +85°C, unless otherwise noted.
MAX
Table 1.
Parameter
STATIC PERFORMANCE
DIGITAL INPUTS5
DIGITAL OUTPUTS
POWER REQUIREMENTS5
1
The minimum/maximum specifications are guaranteed over this range.
2
All specifications are obtained using the Analog Devices, Inc., recommended programming scripts.
3
All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale + 12.5%.
4
Maximum INL and DNL specifications obtained with part configured for component video input.
5
Guaranteed by characterization.
6
To obtain specified VIH level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIH on Pin 22 is 1.2 V.
7
To obtain specified VIL level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIL on Pin 22 is 0.4 V.
8
VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
9
For CVBS current measurement only, ADC0 is powered up. For RGB current measurements only, ADC0, ADC1, and ADC2 are powered up. For SCART FB current
measurements, all ADCs are powered up.
1, 2
Symbol Test Conditions Min Typ Max Unit
3, 4
Resolution (each ADC) N 10 Bits Integral Nonlinearity INL BSL at 27 MHz (10-bit level) ±0.6 ±2.5 LSB BSL at 54 MHz (10-bit level) −0.6/+0.7 LSB BSL at 74 MHz (10-bit level) ±1.4 LSB BSL at 110 MHz (8-bit level)
±0.9 LSB Differential Nonlinearity DNL At 27 MHz (10-bit level) −0.2/+0.25 −0.99/+2.5 LSB At 54 MHz (10-bit level) −0.2/+0.25 LSB At 74 MHz (10-bit level) ±0.9 LSB At 110 MHz (8-bit level)
Input High Voltage6 V
2 V
IH
−0.2/+1.5 LSB
HS_IN, VS_IN low trigger mode 0.7 V Input Low Voltage7 V
0.8 V
IL
HS_IN, VS_IN low trigger mode 0.3 V Input Current IIN −10 +10 μA Input Capacitance5 C
Output High Voltage8 V Output Low Voltage8 V High Impedance Leakage Current I
10 pF
IN
I
OH
I
OL
Pin 1 60 μA
LEAK
= 0.4 mA 2.4 V
SOURCE
= 3.2 mA 0.4 V
SINK
All other output pins 10 μA Output Capacitance5 C
20 pF
OUT
Digital Core Power Supply DVDD 1.65 1.8 2 V Digital I/O Power Supply DVDDIO 3.0 3.3 3.6 V PLL Power Supply PVDD 1.71 1.8 1.89 V Analog Power Supply AVDD 3.15 3.3 3.45 V Digital Core Supply Current IDVDD CVBS input sampling at 54 MHz 105 mA Graphics RGB sampling at 110 MHz 113 mA SCART RGB FB sampling at 54 MHz 106 mA Digital I/O Supply Current IDVDDIO CVBS input sampling at 54 MHz 4 mA Graphics RGB sampling at 110 MHz 16 mA PLL Supply Current IPVDD CVBS input sampling at 54 MHz 11 mA Graphics RGB sampling at 110 MHz 12 mA Analog Supply Current9 IAVDD CVBS input sampling at 54 MHz 99 mA Graphics RGB sampling at 110 MHz 198 mA SCART RGB FB sampling at 54 MHz 269 mA Power-Down Current IPWRDN 2.25 mA Green Mode Power-Down IPWRDNG Synchronization bypass function 16 mA Power-Up Time TPWRUP 20 ms
Rev. 0 | Page 4 of 20
ADV7181C
VIDEO SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T unless otherwise noted.
MIN
to T
= −40°C to +85°C,
MAX
Table 2.
1, 2
Parameter
Symbol Test Conditions Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS input, modulated 5 step 0.5 Degrees Differential Gain DG CVBS input, modulated 5 step 0.5 % Luma Nonlinearity LNL CVBS input, 5 step 0.5 %
NOISE SPECIFICATIONS
SNR Unweighted
Luma ramp 54 56
dB
SNR Unweighted Luma flat field 58 60 dB Analog Front-End Crosstalk
60 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range −5 +5 % Vertical Lock Range 40
70 Hz
FSC Subcarrier Lock Range ±1.3 kHz Color Lock in Time 60 Lines Sync Depth Range
3
20 200 % Color Burst Range 5 200 % Vertical Lock Time 2 Fields Horizontal Lock Time 100 Lines
CHROMA SPECIFICATIONS
Hue Accuracy HUE 1 Degrees Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.5 % Chroma Phase Error
Chroma Luma Intermodulation
LUMA SPECIFICATIONS
Luma Brightness Accuracy Luma Contrast Accuracy
1
The minimum/maximum specifications are guaranteed over this range.
2
Guaranteed by characterization.
3
Nominal synchronization depth is 300 mV at 100% synchronization depth range.
0.4 Degrees
0.2 %
CVBS, 1 V input 1 % CVBS, 1 V input 1 %
Rev. 0 | Page 5 of 20
ADV7181C
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T unless otherwise noted.
MIN
to T
= −40°C to +85°C,
MAX
Table 3.
1, 2
Parameter
Symbol Test Conditions Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency 28.63636 MHz Crystal Frequency Stability ±50 ppm LLC Frequency Range
I2C PORT
4
3
12.825 110 MHz
SCLK Frequency 400 kHz SCLK Min Pulse Width High t1 0.6 μs SCLK Min Pulse Width Low t2 1.3 μs Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 μs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC Mark Space Ratio t9:t10 45:55 55:45 % duty cycle
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)
5
t11
Negative clock edge
3.6 ns
to start of valid data
Data Output Transition Time SDR (SDP)
5
t
12
End of valid data to
2.4 ns
negative clock edge
Data Output Transition Time SDR (CP)
6
t13
End of valid data to
2.8 ns
negative clock edge
Data Output Transition Time SDR (CP)
6
t
14
Negative clock edge
0.1 ns
to start of valid data
Data Output Transition Time DDR (CP)
6, 7
t
15
Positive clock edge to
−4 + TLLC/4 ns
end of valid data
Data Output Transition Time DDR (CP)
6, 7
t
16
Positive clock edge to
0.25 + TLLC/4 ns
start of valid data
Data Output Transition Time DDR (CP)
6, 7
t17
Negative clock edge
−2.95 + TLLC/4 ns
to end of valid data
6, 7
Data Output Transition Time DDR (CP)
t18
Negative clock edge
−0.5 + TLLC/4 ns
to start of valid data
1
The minimum/maximum specifications are guaranteed over this range.
2
Guaranteed by characterization.
3
Maximum LLC frequency is 110 MHz.
4
TTL input values are 0 V to 3 V, with rise/fall times of 3 ns, measured between the 10% and 90% points.
5
SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
6
CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
7
DDR timing specifications dependent on LLC output pixel clock; TLCC/4 = 9.25 ns at LLC = 27 MHz.
Rev. 0 | Page 6 of 20
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