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Video Decoder and RGB Graphics Digitizer
10-Bit, Integrated, Multiformat SDTV
FEATURES
Four 10-bit ADCs sampling up to 110 MHz
6 analog input channels
SCART fast blank support
Internal antialias filters
NTSC, PAL, SECAM color standards support
525p/625p component progressive scan support
720p/1080i component HDTV support
Digitizes RGB graphics up to 1280 × 1024 at 60 Hz (SXGA)
3 × 3 color space conversion matrix
Industrial temperature range: −40°C to +85°C
12-bit 4:4:4 DDR, 8-/10-/16-/20-bit SDR pixel output interface
Programmable interrupt request output pin
Small package
Low pin count
Single front end for video and graphics
APPLICATIONS
Automotive entertainment
HDTVs
LCD/DLP projectors
HDTV STBs with PVR
DVD recorders with progressive scan input support
AVR receivers
ADV7181C
GENERAL DESCRIPTION
The ADV7181C is a high quality, single-chip, multiformat
video decoder and graphics digitizer. This multiformat decoder
supports the conversion of PAL, NTSC, and SECAM standards
in the form of composite or S-Video into a digital ITU-R BT.656
format. The ADV7181C also supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB
DDR pixel output stream. The support for component video
includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i,
and many other HD and SMPTE standards. Graphics digitization
is also supported by the ADV7181C; it is capable of digitizing
RGB graphics signals from VGA to SXGA rates and converting
them into a digital DDR RGB or YCrCb pixel output stream.
SCART and overlay functionality are enabled by the ability of
the ADV7181C to process simultaneously CVBS and standard
definition RGB signals. The mixing of these signals is controlled
by the fast blank pin.
The ADV7181C contains two main processing sections. The
first section is the standard definition processor (SDP), which
processes all PAL, NTSC, and SECAM signal types. The second
section is the component processor (CP), which processes YPrPb
and RGB component formats, including RGB graphics.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADV7181C
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 4
Video Specifications ..................................................................... 5
Timing Characteristics ................................................................ 6
Analog Specifications ................................................................... 7
Absolute Maximum Ratings ............................................................ 8
Package Thermal Performance ................................................... 8
Thermal Specifications ................................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Detailed Functionality ................................................................... 11
Analog Front End ....................................................................... 11
SDP Pixel Data Output Modes ................................................. 11
CP Pixel Data Output Modes ................................................... 11
Composite and S-Video Processing ......................................... 11
Component Video Processing .................................................. 12
RGB Graphics Processing ......................................................... 12
General Features ......................................................................... 12
Detailed Description ...................................................................... 13
Analog Front End ....................................................................... 13
Standard Definition Processor (SDP) ...................................... 13
Component Processor (CP) ...................................................... 13
Analog Input Muxing ................................................................ 14
Pixel Output Formatting................................................................ 16
Recommended External Loop Filter Components .................... 17
Typical Connection Diagram ....................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADV7181C
FUNCTIONAL BLOCK DIAGRAM
VBI DATA RECOVERY
STANDARD
AUTODETECTI ON
STANDARD DEFINITION P ROCESSOR
07513-001
PIXEL
DATA
P19 TO
P10
P9 TO
P0
10
10
20
Y
LUMA
(5H MAX)
2D COMB
LUMA
RESAMPLE
LUMA
FILTER
RESAMPLE
SYNC
HS/CS
VS
FIELD/DE
LLC
SFL/
SYNCOUT
OUTPUT FI FO AND FORMAT TER
AND
FAST
BLANK
AV CODE
OVERLAY
CONTROL
INSERTION
Cr
Cb
CHROMA
2D COMB
CONTROL
EXTRACT
CHROMA
CHROMA
Y
Cr
Cb
(4H MAX)
RESAMPLE
FILTER
INT
20
AV CODE
INSERTION
OFFSET
CONTROL
CGMS DATA
EXTRACTIO N
GAIN
COMPONENT PROCESSOR
DETECTIO N
MACROVISIO N
CONTROL
ADV7181C
AGC
101010
XTAL
DIGITAL
FINE
COLORSPACE
CLAMP
CONVERSION
SC
ADC1CLAMP
6
A
ALIAS
INPUT
IN
DECIMATION
F
RECOVERY
10
AND
FILTERS
DOWNSAMPLI NG
10
ADC2CLAMP
ANTI-
ALIAS
FILTER
FILTER
MUX
CVBS
YPrPb
SCART–
S-VIDEO
(RGB + CVBS)
GRAPHICS RGB
DEMOD
CHROMA
Cb
Cr
C
CVBS
10
ADC3CLAMP
ANTI-
ALIAS
FILTER
FB
SERIAL INTERFACE
CONTROL AND VBI DATA
SCLK
SDATA
CLOCK GENERATION
SYNC PROCESSING AND
ALSB
HS_IN/
DETECTION
MACROVISIO N
CVBS/Y
101010
DATA
PREPROCESSOR
10
10
ADC0CLAMP
ANTI-
ANTI-
ALIAS
FILTER
6
IN1
TO
A
AND
ACTIVE PEAK
STDI
SSPD
VS_IN
CS_IN
SOG/SOY
Figure 1.
Rev. 0 | Page 3 of 20
ADV7181C
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V.
T
MIN
to T
= −40°C to +85°C, unless otherwise noted.
MAX
Table 1.
Parameter
STATIC PERFORMANCE
DIGITAL INPUTS5
DIGITAL OUTPUTS
POWER REQUIREMENTS5
1
The minimum/maximum specifications are guaranteed over this range.
2
All specifications are obtained using the Analog Devices, Inc., recommended programming scripts.
3
All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale + 12.5%.
4
Maximum INL and DNL specifications obtained with part configured for component video input.
5
Guaranteed by characterization.
6
To obtain specified VIH level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIH on Pin 22 is 1.2 V.
7
To obtain specified VIL level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIL on Pin 22 is 0.4 V.
8
VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
9
For CVBS current measurement only, ADC0 is powered up. For RGB current measurements only, ADC0, ADC1, and ADC2 are powered up. For SCART FB current
measurements, all ADCs are powered up.
1, 2
Symbol Test Conditions Min Typ Max Unit
3, 4
Resolution (each ADC) N 10 Bits
Integral Nonlinearity INL BSL at 27 MHz (10-bit level) ±0.6 ±2.5 LSB
BSL at 54 MHz (10-bit level) −0.6/+0.7 LSB
BSL at 74 MHz (10-bit level) ±1.4 LSB
BSL at 110 MHz (8-bit level)
±0.9 LSB
Differential Nonlinearity DNL At 27 MHz (10-bit level) −0.2/+0.25 −0.99/+2.5 LSB
At 54 MHz (10-bit level) −0.2/+0.25 LSB
At 74 MHz (10-bit level) ±0.9 LSB
At 110 MHz (8-bit level)
Input High Voltage6 V
2 V
IH
−0.2/+1.5 LSB
HS_IN, VS_IN low trigger mode 0.7 V
Input Low Voltage7 V
0.8 V
IL
HS_IN, VS_IN low trigger mode 0.3 V
Input Current IIN −10 +10 μA
Input Capacitance5 C
Output High Voltage8 V
Output Low Voltage8 V
High Impedance Leakage Current I
10 pF
IN
I
OH
I
OL
Pin 1 60 μA
LEAK
= 0.4 mA 2.4 V
SOURCE
= 3.2 mA 0.4 V
SINK
All other output pins 10 μA
Output Capacitance5 C
20 pF
OUT
Digital Core Power Supply DVDD 1.65 1.8 2 V
Digital I/O Power Supply DVDDIO 3.0 3.3 3.6 V
PLL Power Supply PVDD 1.71 1.8 1.89 V
Analog Power Supply AVDD 3.15 3.3 3.45 V
Digital Core Supply Current IDVDD CVBS input sampling at 54 MHz 105 mA
Graphics RGB sampling at 110 MHz 113 mA
SCART RGB FB sampling at 54 MHz 106 mA
Digital I/O Supply Current IDVDDIO CVBS input sampling at 54 MHz 4 mA
Graphics RGB sampling at 110 MHz 16 mA
PLL Supply Current IPVDD CVBS input sampling at 54 MHz 11 mA
Graphics RGB sampling at 110 MHz 12 mA
Analog Supply Current9 IAVDD CVBS input sampling at 54 MHz 99 mA
Graphics RGB sampling at 110 MHz 198 mA
SCART RGB FB sampling at 54 MHz 269 mA
Power-Down Current IPWRDN 2.25 mA
Green Mode Power-Down IPWRDNG Synchronization bypass function 16 mA
Power-Up Time TPWRUP 20 ms
Rev. 0 | Page 4 of 20
ADV7181C
VIDEO SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T
unless otherwise noted.
MIN
to T
= −40°C to +85°C,
MAX
Table 2.
1, 2
Parameter
Symbol Test Conditions Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS input, modulated 5 step 0.5 Degrees
Differential Gain DG CVBS input, modulated 5 step 0.5 %
Luma Nonlinearity LNL CVBS input, 5 step 0.5 %
NOISE SPECIFICATIONS
SNR Unweighted
Luma ramp 54 56
dB
SNR Unweighted Luma flat field 58 60 dB
Analog Front-End Crosstalk
60 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range −5 +5 %
Vertical Lock Range 40
70 Hz
FSC Subcarrier Lock Range ±1.3 kHz
Color Lock in Time 60 Lines
Sync Depth Range
3
20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Horizontal Lock Time 100 Lines
CHROMA SPECIFICATIONS
Hue Accuracy HUE 1 Degrees
Color Saturation Accuracy CL_AC 1 %
Color AGC Range 5 400 %
Chroma Amplitude Error 0.5 %
Chroma Phase Error
Chroma Luma Intermodulation
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
1
The minimum/maximum specifications are guaranteed over this range.
2
Guaranteed by characterization.
3
Nominal synchronization depth is 300 mV at 100% synchronization depth range.
0.4 Degrees
0.2 %
CVBS, 1 V input 1 %
CVBS, 1 V input 1 %
Rev. 0 | Page 5 of 20
ADV7181C
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T
unless otherwise noted.
MIN
to T
= −40°C to +85°C,
MAX
Table 3.
1, 2
Parameter
Symbol Test Conditions Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency 28.63636 MHz
Crystal Frequency Stability ±50 ppm
LLC Frequency Range
I2C PORT
4
3
12.825 110 MHz
SCLK Frequency 400 kHz
SCLK Min Pulse Width High t1 0.6 μs
SCLK Min Pulse Width Low t2 1.3 μs
Hold Time (Start Condition) t3 0.6 μs
Setup Time (Start Condition) t4 0.6 μs
SDA Setup Time t5 100 ns
SCLK and SDA Rise Time t6 300 ns
SCLK and SDA Fall Time t7 300 ns
Setup Time for Stop Condition t8 0.6 μs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC Mark Space Ratio t9:t10 45:55 55:45 % duty cycle
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)
5
t11
Negative clock edge
3.6 ns
to start of valid data
Data Output Transition Time SDR (SDP)
5
t
12
End of valid data to
2.4 ns
negative clock edge
Data Output Transition Time SDR (CP)
6
t13
End of valid data to
2.8 ns
negative clock edge
Data Output Transition Time SDR (CP)
6
t
14
Negative clock edge
0.1 ns
to start of valid data
Data Output Transition Time DDR (CP)
6, 7
t
15
Positive clock edge to
−4 + TLLC/4 ns
end of valid data
Data Output Transition Time DDR (CP)
6, 7
t
16
Positive clock edge to
0.25 + TLLC/4 ns
start of valid data
Data Output Transition Time DDR (CP)
6, 7
t17
Negative clock edge
−2.95 + TLLC/4 ns
to end of valid data
6, 7
Data Output Transition Time DDR (CP)
t18
Negative clock edge
−0.5 + TLLC/4 ns
to start of valid data
1
The minimum/maximum specifications are guaranteed over this range.
2
Guaranteed by characterization.
3
Maximum LLC frequency is 110 MHz.
4
TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.
5
SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
6
CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
7
DDR timing specifications dependent on LLC output pixel clock; TLCC/4 = 9.25 ns at LLC = 27 MHz.
Rev. 0 | Page 6 of 20
ADV7181C
ANALOG SPECIFICATIONS
AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T
unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.
MIN
to T
= −40°C to +85°C,
MAX
Table 4.
1, 2
Parameter
Test Conditions Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 μF
Input Impedance; Except Pin 34 (FB) Clamps switched off 10 MΩ
Input Impedance of Pin 34 (FB) 20 kΩ
CML 1.86 V
ADC Full-Scale Level CML + 0.8 V V
ADC Zero-Scale level CML − 0.8 V V
ADC Dynamic Range 1.6 V
Clamp Level (When Locked) CVBS input CML – 0.292 V V
SCART RGB input (R, G, B signals) CML – 0.4 V V
S-Video input (Y signal) CML – 0.292 V V
S-Video input (C signal) CML – 0 V V
Component input (Y, Pr, Pb signals) CML – 0.3 V V
PC RGB input (R, G, B signals) CML – 0.3 V V
Large Clamp Source Current SDP only 0.75 mA
Large Clamp Sink Current SDP only 0.9 mA
Fine Clamp Source Current SDP only 17 μA
Fine Clamp Sink Current SDP only 17 μA
1
The minimum/maximum specifications are guaranteed over this range.
2
Guaranteed by characterization.
Rev. 0 | Page 7 of 20
ADV7181C
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD to AGND 4 V
DVDD to DGND 2.2 V
PVDD to AGND 2.2 V
DVDDIO to DGND 4 V
DVDDIO to AVDD −0.3 V to +0.3 V
PVDD to DVDD −0.3 V to +0.3 V
DVDDIO to PVDD −0.3 V to +2 V
DVDDIO to DVDD −0.3 V to +2 V
AVDD to PVDD −0.3 V to +2 V
AVDD to DVDD −0.3 V to +2 V
Digital Inputs Voltage to DGND
DGND − 0.3 V to
DVDDIO + 0.3 V
Digital Outputs Voltage to DGND
DGND − 0.3 V to
DVDDIO + 0.3 V
Analog Inputs to AGND
AGND − 0.3 V to
AVDD + 0.3 V
Operating Temperature −40°C to +85°C
Maximum Junction Temperature (T
) 125°C
J MAX
Storage Temperature Range −65°C to +150°C
Infrared Reflow Soldering (20 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part the user is
advised to turn off any unused ADCs.
It is imperative that the recommended scripts be used for the
following high current modes: SCART, 720p, 1080i, and all
RGB graphic standards. Using the recommended scripts ensures
correct thermal performance. These scripts are available from
a local FAE.
The junction temperature must always stay below the
maximum junction temperature (T
) of 125°C. Using
J MAX
the following equation, calculate the junction temperature:
T
= T
J
+ (θJA × W
A MAX
MAX
)
where:
T
= 85°C.
A MAX
= 45.5°C/W.
θ
JA
W
= ((AV D D × IAVDD) + (DVDD × IDVDD) + (DVDDIO ×
MAX
IDVDDIO) + (PVDD × IPVDD)).
THERMAL SPECIFICATIONS
Table 6.
Package Type θ
64-Lead LQFP 45.5 9.2 °C/W
64-Lead LFCSP_VQ 20.3 1.2 °C/W
1
4-layer PCB with solid ground plane (still air).
2
4-layer PCB with solid ground plane.
1
θ
JA
2
Unit
JC
ESD CAUTION
Rev. 0 | Page 8 of 20
ADV7181C
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
6
FIELD/DE62P1661P1760P1859P1958DVDD57DGND56HS_IN/CS_IN55VS_IN54SCLK53SDATA52ALSB51RESET50SOG/SOY49A
64VS63
1
INT
HS/CS
DGND
DVDDIO
P15
P14
P13
P12
SFL/SYNC_OUT
DGND
DVDDIO
P11
P10
P9
P8
P7
NOTES
1. NC = NO CONNECT.
2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
17P618P519P420
21
LLC
XTAL1
ADV7181C
TOP VIEW
(Not to Scale)
22
23
24
XTAL
DVDD
DGND
25P326P227P128P029
PWRDWN
Figure 2. Pin Configuration
IN
48
AIN5
47
AIN4
46
AIN3
45
NC
44
CAPC2
43
AGND
42
CML
41
REFOUT
40
AVD D
39
CAPY2
38
CAPY1
37
AGND
36
AIN2
35
AIN1
34
FB
33
NC
30
31
32
ELPF
PVDD
AGND
07513-002
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1Description
3, 10, 24, 57 DGND G Digital Ground.
32, 37, 43 AGND G Analog Ground.
4, 11 DVDDIO P Digital I/O Supply Voltage (3.3 V).
23, 58 DVDD P Digital Core Supply Voltage (1.8 V ).
40 AVDD P Analog Supply Voltage (3.3 V).
31 PVDD P PLL Supply Voltage (1.8 V).
34 FB I Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
35, 36, 46, 47, 48, 49 AIN1 to AIN6 I Analog Video Input Channels.
28 to 25, 19 to 12,
P0 to P19 O Video Pixel Output Port. Refer to Table 1 0 for output configuration modes.
8 to 5, 62 to 59
1
INT
O
Interrupt. This pin can be active low or active high. When SDP/CP status bits
change, this pin is triggered. The set of events that triggers an interrupt is
under user control.
2 HS/CS O
HS: Horizontal Synchronization Output Signal (SDP and CP Modes).
CS: Digital Composite Synchronization Signal (CP Mode).
64 VS O Vertical Synchronization Output Signal (SDP and CP Modes).
63 FIELD/DE O
Field Synchronization Output Signal (All Interlaced Video Modes). This pin also
can be enabled as an data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
53 SDATA I/O I2C Port Serial Data Input/Output Pin.
54 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
52 ALSB I
This pin selects the I
2
C address for the ADV7181C control and VBI readback
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
Rev. 0 | Page 9 of 20
ADV7181C
Pin No. Mnemonic Type1Description
51
RESET
20 LLC O
22 XTAL I
21 XTAL1 O
30 ELPF O The recommended external loop filter must be connected to this ELPF pin.
9 SFL/SYNC_OUT O
41 REFOUT O
42 CML O
38, 39 CAPY1, CAPY2 I
44 CAPC2 I
56 HS_IN/CS_IN I
55 VS_IN I VS Input Signal. Used in CP mode for 5-wire timing mode.
50 SOG/SOY I Sync on Green/Sync on Luma Input. Used in embedded synchronization mode.
29
PWRDWN
33, 45 NC No Connect. These pins are not connected internally.
1
G = ground, I = input, O = output, I/O = input/output.
I
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7181C circuitry.
Line-Locked Output Clock. This pin is for the pixel data (the range is
12.825 MHz to 110 MHz).
Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,
28.63636 MHz clock oscillator source to clock the ADV7181C.
This pin should be connected to the 28.63636 MHz crystal or left as a no connect if
an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the
ADV7181C. In crystal mode, the crystal must be a fundamental crystal.
SFL: Subcarrier Frequency Lock. This pin contains a serial output stream that
can be used to lock the subcarrier frequency when this decoder is connected
to any Analog Devices digital video encoder.
SYNC_OUT: Sliced Synchronization Output Signal Available Only in CP Mode.
Internal Voltage Reference Output. See Figure 5 for a recommended capacitor
network for this pin.
Common-Mode Level Pin (CML) for the Internal ADCs. See Figure 5 for a
recommended capacitor network for this pin.
ADC Capacitor Network. See Figure 5 for a recommended capacitor network for
this pin.
ADC Capacitor Network. See Figure 5 for a recommended capacitor network for
this pin.
This pin can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode.
I A Logic 0 on this pin places the ADV7181C in a power-down mode.
Rev. 0 | Page 10 of 20
ADV7181C
DETAILED FUNCTIONALITY
ANALOG FRONT END
The analog front-end section contains four high quality 10-bit
ADCs, and the six analog input channel mux enables multisource
connection without the requirement of an external mux. It also
contains
• Four current and voltage clamp control loops to ensure
that any dc offsets are removed from the video signal
• SCART functionality and SD RGB overlay on CVBS that
are controlled by fast blank input
• Four internal antialias filters to remove out-of-band noise
on standard definition input video signals
SDP PIXEL DATA OUTPUT MODES
• 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, S, and FIELD
• 16-/20-bit YCrCb with embedded time codes and/or HS,
VS, and FIELD
CP PIXEL DATA OUTPUT MODES
CP pixel data output modes include single data rate (SDR) and
double data rate (DDR) as follows:
• SDR 8-/10-bit 4:2:2 YCrCb for 525i, 625i
• SDR 16-/20-bit 4:2:2 YCrCb for all standards
• DDR 8-/10-bit 4:2:2 YCrCb for all standards
• DDR 12-bit 4:4:4 RGB for graphics inputs
COMPOSITE AND S-VIDEO PROCESSING
Composite and S-Video processing features offer support for
NTSC M / J, NT S C 4 .4 3, PAL B /D /I /G /H , PAL 60 , PA L M , PA L
N, and SECAM (B, D, G, K, and L) standards in the form of
CVBS and S-Video as well as super-adaptive, 2D, 5-line comb
filters for NTSC and PAL give superior chrominance and
luminance separation for composite video. They also include
full automatic detection and autoswitching of all worldwide
standards (PAL, NTSC, and SECAM) and automatic gain
control with white peak mode to ensure the video is always
processed without loss of the video processing range. Other
features are
• Adaptive Digital Line Length Tracking (ADLLT™)
• Proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
• IF filter block to compensate for high frequency luma
attenuation due to tuner SAW filter
• Chroma transient improvement (CTI)
• Luminance digital noise reduction (DNR)
• Color controls including hue, brightness, saturation,
contrast, and Cr and Cb offset controls
• Certified Macrovision® copy protection detection on
composite and S-Video for all worldwide formats
(PAL/NTSC/SECAM)
• 4× oversampling (54 MHz) for CVBS, S-Video, and
YUV modes
• Line-locked clock output (LLC)
• Letterbox detection support
• Free-run output mode to provide stable timing when no
video input is present
• Vertical blanking interval data processor, including teletext,
video programming system (VPS), vertical interval time
codes (VITC), closed captioning (CC) and extended data
service (EDS), wide screen signaling (WSS), copy generation management system (CGMS), and compatibility with
GemStar™ 1×/2× electronic program guide
• Clocked from a single 28.63636 MHz crystal
• Subcarrier frequency lock (SFL) output for downstream
video encoder
• Differential gain typically 0.5%
• Differential phase typically 0.5°
Rev. 0 | Page 11 of 20
ADV7181C
COMPONENT VIDEO PROCESSING
Component video processing supports formats including 525i,
625i, 525p, 625p, 720p, 1080i, and many other HDTV formats,
as well as automatic adjustments that include gain (contrast)
and offset (brightness), and manual adjustment controls. Other
features supported by component video processing are
• Analog component YPrPb/RGB video formats with
embedded synchronization or with separate HS, VS, or CS
• Color space conversion matrix to support YCrCb-to-DDR
RGB and RGB-to-YCrCb
• Standard identification (STDI) enables system level
component format detection
• Synchronization source polarity detector (SSPD) to determine
the source and polarity of the synchronization signals that
accompany the input video
• Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
• Free-run output mode to provide stable timing when no
video input is present
• Arbitrary pixel sampling support for nonstandard video
sources
GENERAL FEATURES
General features of the ADV7181C include HS/CS, VS, and
FIELD/DE output signals with programmable position, polarity,
and width as well as a programmable interrupt request output
INT
pin,
• Low power consumption: 1.8 V digital core, 3.3 V analog
• Industrial temperature range of −40°C to +85°C
• 64-lead, 10 mm × 10 mm, Pb-free LQFP
• 3.3 V ADCs giving enhanced dynamic range and
, that signals SDP/CP status changes. Other features are
and digital I/O, low power, power-down mode, and green
PC mode
performance
RGB GRAPHICS PROCESSING
RGB graphics processing offers a 110 MSPS conversion rate
that supports RGB input resolutions up to 1280 × 1024 at 60 Hz
(SXGA), automatic or manual clamp and gain controls for
graphics modes, and contrast and brightness controls. Other
features include
• 32-phase DLL to allow optimum pixel clock sampling
• Automatic detection of synchronization source and
polarity by SSPD block
• Standard identification enabled by the STDI block
• RGB that can be color space converted to YCrCb and
decimated to a 4:2:2 format for video centric back-end
IC interfacing
• Data enable (DE) output signal supplied for direct
connection to HDMI/DVI Tx IC
• Arbitrary pixel sampling support for nonstandard
video sources
• RGB graphics supported on 12-bit DDR format
Rev. 0 | Page 12 of 20
ADV7181C
DETAILED DESCRIPTION
ANALOG FRONT END
The ADV7181C analog front end comprises four 10-bit ADCs
that digitize the analog video signal before applying it to the
SDP or CP. The analog front end uses differential channels to
each ADC to ensure high performance in a mixed-signal
application.
The front end also includes a 6-channel input mux that enables
multiple video signals to be applied to the ADV7181C. Current
and voltage clamps are positioned in front of each ADC to ensure
that the video signal remains within the range of the converter.
Fine clamping of the video signals is performed downstream by
digital fine clamping in either the CP or SDP.
Optional antialiasing filters are positioned in front of each ADC.
These filters can be used to band-limit standard definition
video signals, removing spurious out-of-band noise.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-Video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
antialiasing filters with the benefit of an increased signal-tonoise ratio (SNR).
The ADV7181C can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under the control of the
2
I
C registers and the fast blank pin.
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of
baseband video signals in composite S-Video and YUV
formats. The video standards supported by the SDP include
PAL B/D/ I /G / H, PAL60 , PA L M , PA L N , NTSC M / J, N T S C
4.43, and SECAM B/D/G/K/L. The ADV7181C automatically
detects the video standard and processes it accordingly.
The SDP has a 5-line super adaptive 2D comb filter that gives
superior chrominance and luminance separation when decoding a
composite video signal. This highly adaptive filter automatically
adjusts its processing mode according to video standards and
signal quality with no user intervention required. The SDP has
an IF filter block that compensates for attenuation in the high
frequency luma spectrum due to the tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7181C implements a patented Adaptive-Digital-LineLength-Tracking (ADLLT) algorithm to track varying video
line lengths from sources such as a VCR. ADLLT enables the
ADV7181C to track and decode poor quality video sources
such as VCRs, noisy sources from tuner outputs, VCD players,
and camcorders. The SDP also contains a chroma transient
improvement (CTI) processor. This processor increases the
edge rate on chroma transitions, resulting in a sharper
video image.
The SDP can process a variety of VBI data services, such as
teletext, closed captioning (CC), wide screen signaling (WSS),
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS), GemStar
1×/2×, and extended data service (XDS). The ADV7181C SDP
section has a Macrovision 7.1 detection circuit that allows it
to detect Type I, Type II, and Type III protection levels. The
decoder is also fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, graphics up to SXGA at 60 Hz, and many other standards.
The CP s
When no embedded synchronization is present, the video
gain can be set manually. The AGC section is followed by a
digital clamp circuit that ensures the video signal is clamped to
the correct blanking level. Automatic adjustments within the
CP include gain (contrast) and offset (brightness); manual
adjustment controls are also supported.
A fixed mode graphics RGB to component output is available.
A color space conversion matrix is placed between the analog
front end and the CP section. This enables YPrPb-to-DDR RGB
and RGB-to-YCrCb conversions. Many other standards of color
space can be implemented using the color space converter.
The output section of the CP is highly flexible. It can be configured in SDR mode with one data packet per clock cycle or in
a DDR mode where data is presented on the rising and falling
edges of the clock. In SDR mode, a 20-bit 4:2:2 is possible. In
these modes, HS/CS, VS, and FIELD/DE (where applicable)
timing reference signals are provided. In DDR mode, the
ADV7181C can be configured in an 8-bit 4:2:2 YCrCb or
12-bit 4:4:4 RGB pixel output interface with corresponding
timing signals.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of component data is performed by the CP
section of the ADV7181C for interlaced, progressive, and high
definition scanning rates. The data extracted can be read back
over the I
ection of the ADV7181C contains an AGC block.
2
C interface.
Rev. 0 | Page 13 of 20
ADV7181C
ANALOG INPUT MUXING
The ADV7181C has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder.
Figure 3 outlines the overall structure of the input muxing provided in the ADV7181C.
6
5
4
3
2
1
IN
IN
IN
A
A
A
IN
IN
IN
A
A
ADC_SW_MAN_EN
A
A
IN
A
IN
A
IN
A
IN
A
IN
AIN6
A
IN
A
IN
A
IN
A
IN
1
1
ADC0_SW[3:0]
ADC0
ADC1_SW[3:0]
ADC1
1
2
3
4
5
3
4
5
6
1
1
ADC2_SW[3:0]
ADC3_SW[3:0]
A
2
IN
4
A
IN
5
A
IN
A
6
IN
4
A
IN
Figure 3. ADV7181C Internal Pin Connections
ADC2
ADC3
07513-003
Rev. 0 | Page 14 of 20
ADV7181C
On the ADV7181C, it is recommended to use the ADC mapping shown in Table 8 .
Table 8. Recommended ADC Mapping
Mode Required ADC Mapping AIN Channel Core Configuration
1
CVBS ADC0 CVBS = AIN1 SD INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
YC/YC auto Y = ADC0 Y = AIN2 SD INSEL[3:0] = 0000
C = ADC1 C = AIN3 SDM_SEL[1:0] = 11
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
Component YUV Y = ADC0 Y = AIN6 SD INSEL[3:0] = 1001
U = ADC2 U = AIN4 SDM_SEL[1:0] = 00
V = ADC1 V = AIN5 PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
Component YUV Y = ADC0 Y = AIN6 CP INSEL[3:0] = 0000
U = ADC2 U = AIN4 SDM_SEL[1:0] = 00
V = ADC1 V = AIN5 PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 1010
SCART RGB CBVS = ADC0 CVBS = AIN2 SD INSEL[3:0] = 0000
G = ADC1 G = AIN6 SDM_SEL[1:0] = 00
B = ADC3 B = AIN4 PRIM_MODE[3:0] = 0000
R = ADC2 R = AIN5 VID_STD[3:0] = 0010
Graphics G = ADC0 G = AIN6 CP INSEL[3:0] = 0000
RGB Mode B = ADC2 B = AIN4 SDM_SEL[1:0] = 00
R = ADC1 R = AIN5 PRIM_MODE[3:0] = 0001
VID_STD[3:0] = 1100
1
Configuration to format follow-on blocks in correct format.
Table 9. Manual MUX Settings for All ADCs
ADC_SWITCH_MAN to 1
ADC0
ADC0_SW_SEL[3:0]
0001 AIN1 0001 N/A 0001 N/A 0001 N/A
0010 AIN2 0010 N/A 0010 AIN2 0010 N/A
0100 AIN4 0100 AIN4 0100 AIN4 0100 AIN4
0101 AIN5 0101 AIN5 0101 AIN5 0101 N/A
0110 AIN6 0110 AIN6 0110 AIN6 0110 N/A
1100 AIN3 1100 AIN3 1100 N/A 1100 N/A
Connection
ADC1_SW_SEL[3:0]
ADC1
Connection
ADC2_SW_SEL[3:0]
ADC2
Connection
ADC3_SW_SEL[3:0]
ADC3
Connection
The analog input muxes of the ADV7181C must be controlled
directly. This is referred to as manual input muxing. The manual
muxing is activated by setting the ADC_SWITCH_MAN bit
(see Tabl e 9). It affects only the analog switches in front of the
ADCs. INSEL, SDM_SEL, PRIM_MODE, and VID_STD still
have to be set so that the follow-on blocks process the video
data in the correct format.
Not every input pin can be routed to any ADC. There are
restrictions in the channel routing imposed by the analog
signal routing inside the IC. See Tab le 9 for an overview of
the routing capabilities inside the chip. The three mux
sections can be controlled by the reserved control signal
buses ADC0_SW[3:0]/ ADC1_SW[3:0]/ADC2_SW[3:0].
Tabl e 9 explains the ADC mapping configuration for the
following:
• ADC_SWITCH_MAN, manual input muxing enable,
IO map, Address 0C[7]
• ADC0_SW[3:0], ADC0 mux configuration, IO map,
Address 0D[3:0]
• ADC1_SW[3:0], ADC1 mux configuration, IO map,
Address 0D[7:4]
• ADC2_SW[3:0], ADC2 mux configuration, IO map,
Address 0E[3:0]
• ADC3_SW[3:0], ADC3 mux configuration, IO map,
Address 0E[7:4]
Rev. 0 | Page 15 of 20
ADV7181C
PIXEL OUTPUT FORMATTING
Table 10. Pixel Output Formats
Processor, Format,
and Mode
SDP
SDP
SDP
SDP
CP
CP
CP
1
↑ indicates data clocked on the rising edge of LLC, ↓ indicates data clocked on the falling edge of LLC.
Video output
8-bit 4:2:2
Video output
10-bit 4:2:2
Video output
16-bit 4:2:2
Video output
20-bit 4:2:2
Video output
12-bit 4:4:4
RGB DDR
Video output
16-bit 4:2:2
Video output
20-bit 4:2:2
Pixel Port Pins P[19:0]
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
YCrCb[7:0]
YCrCb[9:0]
Y[7:0]
Y[9:0] CrCb[7:0]
D71
D61
D51
D41
D31
D21
D11
B[7]↑
B[6]↑
B[5]↑
B[4]↑
B[3]↑
B[2]↑
B[1]↑
R[3]↓
R[2]↓
R[1]↓
R[0]↓
G[7]↓
G[6]↓
G[5]↓
CHA[7:0] (for example, Y[7:0])
CHA[9:0] (for example, Y[9:0]) CHB/C[9:0] (for example, Cr/Cb[9:0])
D01
B[0]↑
G[4]↓
CrCb[7:0]
1
D10
G[2]↑
R[6]↓
1
D91
G[1]↑
R[5]↓
D81
G[0]↑
R[4]↓
D11
G[3]↑
R[7]↓
CHB/C[7:0] (for example, Cr/Cb[7:0])
Rev. 0 | Page 16 of 20
ADV7181C
RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
The external loop filter components for the ELPF pin should be placed as close as possible to the respective pins. Figure 4 shows the
recommended component values.
30
ELPF
1.69kΩ
10nF
82nF
PVDD = 1.8V
Figure 4. ELPF Components
07513-004
Rev. 0 | Page 17 of 20
ADV7181C
TYPICAL CONNECTION DIAGRAM
07513-005
Figure 5. ADV7181C Typical Connection
Rev. 0 | Page 18 of 20
ADV7181C
OUTLINE DIMENSIONS
12.20
PIN 1
12.00 SQ
11.8 0
4964
48
0.75
0.60
0.45
1.60
MAX
1
PIN 1
INDICATOR
1.00
0.85
0.80
SEATING
PLANE
1.45
1.40
1.35
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
12° MAX
TOP VIEW
(PINS DOWN)
0.20
0.09
7°
3.5°
0°
0.08
COPLANARIT Y
COMPLIANT TO J EDEC STANDARDS MS-026-BCD
VIEW A
16
17
0.50
BSC
LEAD PITCH
Figure 6. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64)
Dimensions shown in millimeters
49
48
33
32
0.60 MAX
EXPOSED PAD
(BOTTOM VIEW)
9.00
BSC SQ
TOP VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC S TANDARDS MO-220-VMMD-4
8.75
BSC SQ
0.20 REF
0.60
MAX
0.50
BSC
0.50
0.40
0.30
0.05 MAX
0.02 NOM
Figure 7. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad (CP-64-3)
Dimensions shown in millimeters
10.20
10.00 SQ
33
32
0.27
0.22
0.17
64
1
16
17
7.50
REF
FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIO NS
SECTION OF THIS DATA SHEET.
9.80
PIN 1
INDICATOR
7.25
7.10 SQ
6.95
0.25 MIN
051706-A
080108-C
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADV7181CBCPZ
ADV7181CBCPZ-REEL
ADV7181CBSTZ
ADV7181CBSTZ-REEL
ADV7181WBCPZ
ADV7181WBCPZ-REEL
ADV7181WBSTZ
ADV7181WBSTZ_REEL
1
Z = RoHS Compliant Part.
1
1
−40°C to +85°C 64-Lead LFCSP_VQ CP-64-3
1
−40°C to +85°C 64 –Lead LQFP ST-64
1
−40°C to +85°C 64–Lead LQFP ST-64
1
−40°C to +85°C 64-Lead LFCSP_VQ CP-64-3
1
1
−40°C to +85°C 64–Lead LQFP ST-64
1
−40°C to +85°C 64–Lead LFCSP_VQ CP-64-3
−40°C to +85°C 64-Lead LFCSP_VQ CP-64-3
−40°C to +85°C 64 –Lead LQFP ST-64
Rev. 0 | Page 19 of 20
ADV7181C
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07513-0-8/08(0)
Rev. 0 | Page 20 of 20
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