Datasheet ADV7180 Datasheet (ANALOG DEVICES)

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10-Bit, 4× Oversampling

FEATURES

Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling

for Y/C mode, and 2× oversampling for YPrPb (per channel)
Three video input channels with on-chip antialiasing filter
CVBS (composite), Y/C (S-video), and YPrPb (component)

video input support
5-line adaptive comb filters and CTI/DNR video

enhancement
Adaptive Digital Line Length Tracking (ADLLT™),

signal processing, and enhanced FIFO management give

mini-TBC functionality
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
NTSC/PAL/SECAM autodetection
8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, FIELD

1.0 V analog input signal range
Four general-purpose outputs (GPO)

2

Full feature VBI data slicer with teletext support (WST)
Power-down mode and ultralow sleep mode current
2-wire serial MPU interface (I

2

C® compatible)

1.8 V analog, 1.8 V PLL, 1.8 V digital, 3.3 V I/O supply

−40°C to +85°C temperature grade
Two package types:

40-lead, 6 mm × 6 mm, Pb-free LFCSP

64-lead, 10 mm × 10 mm, Pb-free LQFP

GENERAL DESCRIPTION

The ADV7180 automatically detects and converts standard
analog baseband television signals compatible with worldwide
NTSC, PAL, and SECAM standards into 4:2:2 component video
data compatible with the 8-bit ITU-R BT.656 interface standard.

The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devices, Inc., digital video encoders, such as the
ADV7179. External HS, VS, and FIELD signals provide timing
references for LCD controllers and other video ASICs, if
required

The accurate 10-bit analog-to-digital conversion provides
professional quality video performance for consumer applications
with true 8-bit data resolution. Three analog video input channels
accept standard composite, S-video, or component video
signals, supporting a wide range of consumer video sources.

1

The ADV7180 LFCSP-40 uses one pin to output VS or FIELD.

2

ADV7180 LQFP-64 only.

1

SDTV Video Decoder

ADV7180

APPLICATIONS

Digital camcorders and PDAs
Low-cost SDTV PIP decoder for digital TVs
Multichannel DVRs for video security
AV receivers and video transcoding
PCI-/USB-based video capture and TV tuner cards
Personal media players and recorders
Smartphone/multimedia handsets
In-car/automotive infotainment units
Rearview camera/vehicle safety systems

FUNCTIONAL BLOCK DIAGRAM

XTAL1

XTAL

ANALOG

VIDEO

INPUTS

AIN1

A

2

IN

A

3

IN

1

A

4

IN

1

AIN5

AIN6

1

ONLY AVAILABLE ON 64-LEAD PACKAGE.

2

40-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD.

1

MUX BLOCK

ADV7180

AGC and clamp-restore circuitry allow an input video signal
peak-to-peak range up to 1.0 V. Alternatively, these can be
bypassed for manual settings.

The line-locked clock output allows the output data rate, timing
signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length
variation. Output control signals allow glueless interface
connections in many applications. The ADV7180 is programmed
via a 2-wire, serial, bidirectional port (I

The ADV7180 is fabricated in a 1.8 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. A chip-scale, 40-lead, Pb-free
LFCSP package option makes the decoder ideal for space­constrained portable applications. A 64-lead LQFP package is
also available (pin compatible with ADV7181B).

CLOCK PROCESSI NG BLOCK

10-BIT, 86MHz

AA

FILTER

AA

FILTER

AA

FILTER

REFERENCE

PLL ADLLT PROCESSING

DIGITAL

ADC

SHA A/D

PROCESSING

BLOCK

2D COMB

VBI SLICER

COLOR

DEMOD

2

C/CONTROL

I

SCLK SDATA ALSB RESET PWRDWN

Figure 1.

2

C compatible).

LLC

1

8-BIT/16

-BIT

PIXEL DATA

P7 TO P0

FIFOOUTPUT BLOCK

VS

HS

2

FIELD

1

GPO

SFL

INTRQ

05700-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADV7180

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 3

Introduction ...................................................................................... 4

Analog Front End......................................................................... 4

Standard Definition Processor ................................................... 4

Comparison with the ADV7181B.............................................. 5

Functional Block Diagrams............................................................. 6

Specifications..................................................................................... 7

Electrical Characteristics............................................................. 7

Video Specifications..................................................................... 8

Timing Specifications .................................................................. 9

Analog Specifications................................................................... 9

Thermal Specifications ................................................................ 9

Timing Diagrams........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions .........................12

40-Lead LFCSP ...........................................................................12

64-Lead LQFP............................................................................. 13

Analog Front End........................................................................... 15

Input Configuration................................................................... 16

INSEL[3:0], Input Selection, Address 0x00 [3:0] ...................16

Analog Input Muxing ................................................................ 17

Antialiasing Filters ..................................................................... 18

Global Control Registers ............................................................... 19

Power-Saving Modes .................................................................. 19

Reset Control .............................................................................. 19

Global Pin Control..................................................................... 19

Global Status Register .................................................................... 21

Identification............................................................................... 21

Status 1 .........................................................................................21

Autodetection Result.................................................................. 21

Status 2 .........................................................................................21

Status 3 .........................................................................................21

Video Processor .............................................................................. 22

SD Luma Path ............................................................................. 22

SD Chroma Path ......................................................................... 22

Sync Processing .......................................................................... 23

VBI Data Recovery..................................................................... 23

General Setup.............................................................................. 23

Color Controls............................................................................ 25

Clamp Operation........................................................................ 27

Luma Filter .................................................................................. 28

Chroma Filter.............................................................................. 31

Gain Operation........................................................................... 32

Chroma Transient Improvement (CTI) .................................. 36

Digital Noise Reduction (DNR) and Luma Peaking Filter... 37

Comb Filters................................................................................ 38

IF Filter Compensation ............................................................. 40

AV Code Insertion and Controls ............................................. 41

Synchronization Output Signals............................................... 43

Sync Processing .......................................................................... 50

VBI Data Decode ....................................................................... 50

2

I

C Readback Registers .............................................................. 59

Pixel Port Configuration ............................................................... 72

GPO Control................................................................................... 73

MPU Port Description................................................................... 74

Register Access............................................................................ 75

Register Programming............................................................... 75

2

I

C Sequencer.............................................................................. 75

2

I

C Register Maps........................................................................... 76

2

I

C Programming Examples........................................................ 106

ADV7180 LQFP-64 .................................................................. 106

ADV7180 LFCSP-40................................................................ 107

PCB Layout Recommendations.................................................. 108

Analog Interface Inputs........................................................... 108

Power Supply Decoupling .......................................................108

PLL ............................................................................................. 108

VREFN and VREFP................................................................. 108

Digital Outputs (Both Data and Clocks) .............................. 108

Digital Inputs ............................................................................ 108

Typical C i r c uit Conne c tion ......................................................... 109

Outline Dimensions .....................................................................111

Ordering Guide ........................................................................ 111

Rev. A | Page 2 of 112

ADV7180

REVISION HISTORY

11/06—Rev. 0 to Rev. A

Changes to Table 10 and Table 11 .................................................16

Changes to Table 30 ........................................................................28

Changes to Gain Operation Section .............................................33

Changes to Table 43 ........................................................................35

Changes to Table 97 ........................................................................72

Changes to Table 99 ........................................................................73

Changes to Table 103 ......................................................................80

Changes to Figure 54 ....................................................................110

1/06—Revision 0: Initial Version

Rev. A | Page 3 of 112

ADV7180

INTRODUCTION

The ADV7180 is a versatile one-chip multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-video, and
component video into a digital ITU-R BT.656 format.

The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devides digital video encoders, such as the ADV7179.
External HS, VS, and FIELD signals provide timing references
for LCD controllers and other video ASICs that do not support
the ITU-R BT.656 interface standard.

ANALOG FRONT END

The ADV7180 analog front end comprises a single high speed,
10-bit, analog-to-digital converter (ADC) that digitizes the
analog video signal before applying it to the standard definition
processor. The analog front end employs differential channels
to the ADC to ensure high performance in mixed-signal
applications.

The front end also includes a 3-channel input mux that enables
multiple composite video signals to be applied to the ADV7180.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see
is performed downstream by digital fine clamping within
the ADV7180.

Tabl e 1 shows the three ADC clocking rates, which are determined
by the video input format to be processed—that is, INSEL[3:0].
These clock rates ensure 4× oversampling per channel for CVBS
mode and 2× oversampling per channel for Y/C and YPrPb modes.

Table 1. ADC Clock Rates

Input Format ADC Clock Rate

CVBS 57.27 MHz 4×
Y/C (S-Video)
YPrPb 86 MHz 2×

1

Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins.

2

Refer to INSEL[3:0] in Table 103 for the mandatory write for Y/C (S-video) mode.

Figure 24). Fine clamping of the video signal

Oversampling

1

Rate per Channel

2

86 MHz 2×

STANDARD DEFINITION PROCESSOR

The ADV7180 is capable of decoding a large selection of
baseband video signals in composite, S-video, and component
formats. The video standards supported by the video processor
include PA L B/D/I / G /H, PAL 6 0 , PAL M, PA L N, PAL Nc,
NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The
ADV7180 can automatically detect the video standard and
process it accordingly.

The ADV7180 has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the
video standard and signal quality without requiring user
intervention. Video user controls such as brightness, contrast,
saturation, and hue are also available with the ADV7180.

The ADV7180 implements a patented Adaptive Digital Line
Length Tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7180 to track and decode poor quality video sources such
as VCRs and noisy sources from tuner outputs, VCD players,
and camcorders. The ADV7180 contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.

The video processor can process a variety of VBI data services,
such as closed captioning (CCAP), wide-screen signaling
(WSS), copy generation management system (CGMS), EDTV,
Gemstar® 1×/2×, and extended data service (XDS). Teletext data
slicing for world standard teletext (WST), along with program
delivery control (PDC) and video programming service (VPS),
are provided. Data is transmitted via the 8-bit video output port
as ancillary data packets (ANC). The ADV7180 is fully
Macrovision certified; detection circuitry enables Type I,
Type II, and Type III protection levels to be identified and
reported to the user. The decoder is also fully robust to all
Macrovision signal inputs.

Rev. A | Page 4 of 112

ADV7180

COMPARISON WITH THE ADV7181B

In comparison with the ADV7181B, the ADV7180 LQFP-64 has
the following additional features:

• Improved VCR and weak tuner locking capabilities

• Three on-chip antialiasing filters

• Four general-purpose outputs (GPOs)

• 1.8 V analog supply voltage

• 40-lead LFCSP option

• Automatic power-down of unused channels when using

INSEL[3:0]

Pin Compatibility with the ADV7181B

The ADV7180 LQFP-64 is pin compatible with the ADV7181B.

A complete ADV7181B-to-ADV7180 change over document is
available on request that specifies software changes required to
make the transition. Contact Analog Devices local field
engineers for more information.

Please note that the ADV7180 has a different ADC reference
decoupling circuit (shown in

0.1µF

Figure 2. ADV7180 ADC Reference Decoupling Circuit

Figure 2) than the ADV7181B.

0.1µF

0.1µF

VREFN

VREFP

05700-002

Rev. A | Page 5 of 112

ADV7180

ANA

A

FUNCTIONAL BLOCK DIAGRAMS

CLOCK PROCESSING BL OCK

PLL ADLLT PROCESSING

10-BIT, 86MHz

AA

AA

AA

ADC

SHA A/D

REFERENCE

DIGITAL

PROCESSING

BLOCK

2D COMB

VBI SLICER

COLOR
DEMOD

2

I

C/CONTROL

SCLK S DATA ALSB RESET PWRDWN

FIFOOUTPUT BLOCK

LLC

16-BIT
PIXEL DATA

P15 TO P0

HS

VS

FIELD

GPO0 TO GPO3

SFL

INTRQ

05700-003

LOG

VIDEO

INPUTS

XTAL1

XTAL

AIN1

A

IN

A

IN

A

IN

A

IN

A

IN

MUX BLOCK

FILTER

FILTER

FILTER

2

3

4

5

6

Figure 3. Functional Block Diagram (64-Lead LQFP)

CLOCK PROCESSI NG BLOCK

PLL ADLLT PROCESSING

10-BIT, 86MHz

AA

AA

AA

ADC

SHA A/D

DIGITAL

PROCESSING

BLOCK

2D COMB

VBI SLICER

COLOR

DEMOD

FIFOOUTPUT BLO CK

LLC

8-BIT
PIXEL DATA

P7 TO P0

HS

VS/FIELD

SFL

NALOG

VIDEO

INPUTS

XTAL1

XTAL

AIN1

AIN2

AIN3

MUX BLOCK

FILTER

FILTER

FILTER

REFERENCE

2

I

C/CONTROL

SCLK SDATA ALSB RESET PWRDWN

Figure 4. Functional Block Diagram (40-Lead LFCSP)

Rev. A | Page 6 of 112

INTRQ

05700-004

ADV7180

SPECIFICATIONS

Temperature range: T

ELECTRICAL CHARACTERISTICS

At A
range, unless otherwise noted.

Table 2.

Parameter Symbol Test Conditions Min Typ Max Unit

STATIC PERFORMANCE

DIGITAL INPUTS

DIGITAL OUTPUTS

POWER REQUIREMENTS

1

2

= 1.71 V to 1.89 V, D

VDD

Resolution (Each ADC) N 10 Bits
Integral Nonlinearity INL BSL in CVBS mode 2 LSB
Differential Nonlinearity DNL CVBS mode −0.6/+0.6 LSB

Input High Voltage V
Input Low Voltage V

Crystal Inputs V

Crystal Inputs V
Input Current I
Input Capacitance C

Output High Voltage V
Output Low Voltage V
High Impedance Leakage Current I
Output Capacitance C

Digital Power Supply D
Digital I/O Power Supply D
PLL Power Supply P
Analog Power Supply A
Digital Supply Current I
Digital I/O Supply Current I
PLL Supply Current I
Analog Supply Current I
Y/C input 59 mA
YPrPb input 77 mA
Power-Down Current I
I
I
I
Total Power Dissipation in Power-Down Mode2 15 μW
Power-Up Time t

Guaranteed by characterization.
ADV7180 clocked.

MIN

to T

1

is −40°C to +85°C. The min/max specifications are guaranteed over this range.

MAX

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

IH

IL

IH

IL

IN

IN

OH

OL

LEAK

OUT

= 1.65 V to 2.0 V, specified at operating temperature

VDD

2 V

0.8 V

1.2 V

0.4 V
–10 +10 μA
10 pF

I

= 0.4 mA 2.4 V

SOURCE

I

= 3.2 mA 0.4 V

SINK

10 μA
20 pF

VDD

VDDIO

VDD

VDD

DVDD

DVDDIO

PVDD

AVDD

DVDD

DVDDIO

PVDD

AVDD

PWRUP

1.65 1.8 2 V

3.0 3.3 3.6 V

1.65 1.8 2.0 V

1.71 1.8 1.89 V
77 mA
3 mA
12 mA
CVBS input 33 mA

6 μA

0.1 μA
1 μA
1 μA

20 ms

Rev. A | Page 7 of 112

ADV7180

VIDEO SPECIFICATIONS

Guaranteed by characterization. At A
specified at operating temperature range, unless otherwise noted.

Table 3.

Parameter Symbol Test Conditions Min Typ Max Unit

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulate 5-step [NTSC] 0.6 Degrees
Differential Gain DG CVBS input, modulate 5-step [NTSC] 0.5 %
Luma Nonlinearity LNL CVBS input, 5-step [NTSC] 2.0 %

NOISE SPECIFICATIONS

SNR Unweighted Luma ramp 57.1 dB
Luma flat field 58 dB
Analog Front-End Crosstalk 60 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range –5 +5 %
Vertical Lock Range 40 70 Hz
FSC Subcarrier Lock Range ±1.3 kHz
Color Lock-In Time 60 Lines
Sync Depth Range 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Autodetection Switch Speed 100 Lines
Chroma Lima Gain Delay CVBS 2.9 ns
Y/C 5.6 ns
YPrPb −3.0 ns

LUMA SPECIFICATIONS

Luma Brightness Accuracy CVBS, 1 V input 1 %
Luma Contrast Accuracy CVBS, 1 V input 1 %

= 1.71 V to 1.89 V, D

VDD

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V,

VDD

Rev. A | Page 8 of 112

ADV7180

TIMING SPECIFICATIONS

Guaranteed by characterization. At A
specified at operating temperature range, unless otherwise noted.

Table 4.

Parameter Symbol Test Conditions Min Typ Max Unit

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency 28.6363 MHz
Frequency Stability ±50 ppm

I2C PORT

SCLK Frequency 400 kHz
SCLK Minimum Pulse Width High t
SCLK Minimum Pulse Width Low t
Hold Time (Start Condition) t
Setup Time (Start Condition) t
SDA Setup Time t
SCLK and SDA Rise Times t
SCLK and SDA Fall Times t
Setup Time for Stop Condition t

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC1 Mark Space Ratio t9:t

DATA AND CONTROL OUTPUTS

Data Output Transitional Time t

Data Output Transitional Time t

= 1.71 V to 1.89 V, D

VDD

1

2

3

4

5

6

7

8

10

11

12

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V,

VDD

0.6 μs

1.3 μs

0.6 μs

0.6 μs
100 ns
300 ns
300 ns

0.6 μs

45:55 55:45 % duty cycle

Negative clock edge to start of valid data
(t

= t10 – t11)

ACCESS

End of valid data to negative clock edge

= t9 + t12)

(t

HOLD

3.6 ns

2.4 ns

ANALOG SPECIFICATIONS

Guaranteed by characterization. At A
specified at operating temperature range, unless otherwise noted.

Table 5.

Parameter Test Conditions Min Typ Max Unit

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF
Input Impedance Clamps switched off 10 MΩ
Large-Clamp Source Current 0.4 mA
Large-Clamp Sink Current 0.4 mA
Fine Clamp Source Current 10 μA
Fine Clamp Sink Current 10 μA

= 1.71 V to 1.89 V, D

VDD

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V,

VDD

THERMAL SPECIFICATIONS

Table 6.

Parameter Symbol Test Conditions Min Typ Max Unit

THERMAL CHARACTERISTICS

Junction-to-Ambient Thermal

Resistance (Still Air)
Junction-to-Case Thermal Resistance θ

Junction-to-Ambient Thermal

Resistance (Still Air)
Junction-to-Case Thermal Resistance θ

θ

JA

4-layer PCB with solid ground plane,
40-lead LFCSP

JC

4-layer PCB with solid ground plane,
40-lead LFCSP

θ

JA

4-layer PCB with solid ground plane,
64-lead LQFP

JC

4-layer PCB with solid ground plane,
64-lead LQFP

30 °C/W

3 °C/W

47 °C/W

11.1 °C/W

Rev. A | Page 9 of 112

ADV7180

S

TIMING DIAGRAMS

t

t

1

t

7

5

Figure 5. I

2

C Timing

DATA

SCLK

t

3

t

6

t

2

OUTPUT LLC

OUTPUTS P0–P15, VS,

HS, FIE LD,

SFL

t

9

t

12

Figure 6. Pixel Port and Control Output Timing

t

t

11

t

3

t

4

10

t

8

05700-005

05700-006

Rev. A | Page 10 of 112

ADV7180

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

A

to AGND 2.2 V

VDD

D

to DGND 2.2 V

VDD

P

to AGND 2.2 V

VDD

D

to DGND 4 V

VDDIO

D

to A
P
D
D
A
A

VDDIO

VDD

VDDIO

VDDIO

VDD

VDD

to D

to P

to D

to P
to D

VDD

VDD

VDD

VDD

VDD

VDD

Digital Inputs Voltage DGND − 0.3 V to D
Digital Output Voltage DGND − 0.3 V to D
Analog Inputs to AGND AGND − 0.3 V to A
Maximum Junction Temperature

(T

max)

J

−0.3 V to +2 V

−0.3 V to +0.9 V
–0.3 V to +2 V

−0.3 V to +2 V

−0.3 V to +0.3 V

−0.3 V to +0.9 V

125°C

VDDIO

VDDIO

+ 0.3 V

VDD

+ 0.3 V
+ 0.3 V

Storage Temperature Range −65°C to +150°C
Infrared Reflow Soldering (20 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

ESD CAUTION

Rev. A | Page 11 of 112

ADV7180

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

40-LEAD LFCSP

B

SDATA34SCLK35DGND36DVDD37VS/FIELD38INTRQ

ALS

RESET

32

31

33

30

AIN3

29

AIN2

28

AGND

27

AVD D

26

VREFN

25

VREFP

24

AGND

23

AIN1

22

TEST_0

21

AGND

15

17P016P118

19

20

N

ND

DW

ELPF

DG

PVDD

R

PW

05700-007

DVDDIO

SFL

DGND

DVDDIO

P7
P6
P5
P4
P3
P2

ND

DG

39HS40

PIN 1

1

INDICATOR

2
3
4
5
6
7
8
9

10

ADV7180

LFCSP

TOP VIEW

(Not to Scale)

11

12

13

14

LLC

XTAL

DVDD

XTAL1

Figure 7. 40-Lead LFCSP Pin Configuration

Table 8. Pin Function Descriptions for the ADV7180 LFCSP-40

Pin No. Mnemonic Type Function

3, 15, 35, 40 DGND G Ground for Digital Supply.
21, 24, 28 AGND G Ground for Analog Supply.
1, 4 DVDDIO P Digital I/O Supply Voltage (3.3 V).
14, 36 DVDD P Digital Supply Voltage (1.8 V ).
27 AVDD P Analog Supply Voltage (1.8 V).
20 PVDD P PLL Supply Voltage (1.8 V).
23, 29, 30 AIN1 to AIN3 I Analog Video Input Channels.
5 to 10, 16, 17 P7 to P2, P1, P0 O Video Pixel Output Port.
39 HS O Horizontal Synchronization Output Signal.
38

INTRQ

O

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see

Table 104).
37 VS/FIELD O Vertical Synchronization Output Signal/Field Synchronization Output Signal.
33 SDATA I/O I2C Port Serial Data Input/Output Pin.
34 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
32 ALSB I

Selects the I

2

C Address for the ADV7180. For ALSB set to Logic 0, the address selected for a

write is 0xTBC; for ALSB set to logic high, the address selected is 0xTBC.

31

RESET

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.

11 LLC O

Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz, but varies up or
down according to video line length.

13 XTAL I

Input Pin for the 28.6363 MHz Crystal. Can be overdriven by an external 1.8 V, 28.6363 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

12 XTAL1 O

This pin should be connected to the 28.6363 MHz crystal, or not connected if an external

1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.

18

PWRDWN

19 ELPF I

I A logic low on this pin places the ADV7180 into power-down mode.

The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 53.

2 SFL O

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital video

encoder.
26 VREFN O Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
25 VREFP O Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
22 TEST_0 I This pin must be tied to DGND.

Rev. A | Page 12 of 112

ADV7180

64-LEAD LQFP

6

FIELD62P1261P1360P1459P1558DVDD57DGND56GPO255GPO354SCLK53SDATA52ALSB51RESET50NC49A

64VS63

1

INTRQ

HS

DGND

DVDDIO

P11
P10

P9
P8

SFL

DGND

DVDDIO

GPO1
GPO0

P7
P6
P5

NC = NO CONNECT

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

PIN 1

17P418P319P220

21

LLC

ADV7180

TOP VIEW

(Not to Scale)

22

23

XTAL

XTAL1

LQFP

24

25P126P027NC28NC29

DVDD

DGND

PWRDWN

Figure 8. 64-Lead LQFP Pin Configuration

IN

48

AIN5

47

AIN4

46

AIN3

45

NC

44

NC

43

AGND

42

NC

41

NC

40

AVDD

39

VREFN

38

VREFP

37

AGND

36

AIN2

35

AIN1

34

TEST_0

33

NC

30

31

32

ELPF

PVDD

AGND

05700-008

Table 9. Pin Function Description for the ADV7180 LQFP-64

Pin No. Mnemonic Type Function

3, 10, 24, 57 DGND G Digital Ground.
32, 37, 43 AGND G Analog Ground.
4, 11 DVDDIO P Digital I/O Supply Voltage (3.3 V).
23, 58 DVDD P Digital Supply Voltage (1.8 V).
40 AVDD P Analog Supply Voltage (1.8 V).
31 PVDD P PLL Supply Voltage (1.8 V).
38 VREFP O Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
39 VREFN O Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
35, 36, 46 to 49 AIN1 to AIN6 I Analog Video Input Channels.

27, 28, 33, 41, 42,
44, 45, 50

5 to 8, 14 to 19,
25, 26, 59 to 62

NC

P11 to P8,
P7 to P2, P1,

O

No Connect Pins. These pins are not connected internally.

Video Pixel Output Port. See Table 96 for output configuration for 8-bit and 16-bit modes.

P0, P15 to P12

2 HS O Horizontal Synchronization Output Signal.
64 VS O Vertical Synchronization Output Signal.
63 FIELD O Field Synchronization Output Signal.
1

INTRQ

O

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).

53 SDATA I/O I2C Port Serial Data Input/Output Pin.
54 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
52 ALSB I

29

PWRDWN

I A logic low on this pin places the ADV7180 in power-down mode.

30 ELPF I

This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address
selected for a write is 0x40; for ALSB set to logic high, the address selected is 0x42.

The recommended external loop filter must be connected to the ELPF pin, as shown in
Figure 54.

51

RESET

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.

Rev. A | Page 13 of 113

ADV7180

Pin No. Mnemonic Type Function

9 SFL O

20 LLC O

21 XTAL1 O

22 XTAL I

12, 13, 55, 56 GPO0 to GPO3 O

34 TEST_0 I This pin must be tied to DGND.

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.

This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz, but varies up or down according to video line length.

This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an
external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal
mode, the crystal must be a fundamental crystal.

This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external

1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a
fundamental crystal.

General-Purpose Outputs. These pins can be configured via I
devices.

2

C to allow control of external

Rev. A | Page 14 of 113

ADV7180

ANALOG FRONT END

2

IN

A

A

IN

IN

IN

IN

IN

A

A

A

A

5

6

3

4

1

3

2

1

IN

IN

IN

A

A

A

MAN_MUX_EN

AIN2
AIN1
AIN4
AIN3
AIN6
AIN5

AIN4
AIN3
AIN6
AIN5

AIN6
AIN5

MUX_0[3:0]

MUX_1[3:0]

MUX_2[3:0]

Figure 9. Internal Pin Connections LQFP-64

MAN_MUX_EN

ADC

05700-009

AIN1
AIN2
AIN3

AIN2
AIN3

AIN3

MUX_0[3:0]

MUX_1[3:0]

MUX_2[3:0]

ADC

05700-010

Figure 10. Internal Pin Connections LFCSP-40

Rev. A | Page 15 of 112

ADV7180

INPUT CONFIGURATION

There are two key steps for configuring the ADV7180 to
correctly decode the input video.

1. Use INSEL[3:0] to configure routing and format decoding

(CVBS, Y/C, or YPrPb). For the ADV7180 LQFP-64, see
Tabl e 10 . For ADV7180 LFCSP-40, see Ta ble 11 .

2. If the input requirements are not met using the INSEL[3:0]

options, the analog input muxing section must be
configured manually to correctly route the video from the
analog input pins to the ADC. The standard definition
processor block, which decodes the digital data, should be
configured to process either CVBS, Y/C, or YPrPb format.
This is performed by INSEL[3:0] selection.

CONNECT ANA LOG V IDEO

SIGNAL S TO ADV7180.

SET INSE L[3:0] TO CONFIG URE

VIDEO FORMAT. USE PREDEFI NED

FORMAT/ROUTING.

NO

YES

LQFP-64 LFCSP-40

CONFIGUR E ADC INPUTS US ING

MANUAL MUXI NG CONTROL BI TS:

REFER TO

TABLE 10

REFER T O

TABLE 11

Figure 11. Signal Routing Options

MUX_0[3:0], MUX_1[3:0] , MUX_2[ 3:0].

SEE TABL E 12.

INSEL[3:0], INPUT SELECTION, ADDRESS 0x00
[3:0]

The INSEL bits allow the user to select the input format. They
also configure the standard definition processor core to process
composite (CVBS), S-video (Y/C), or component (YPrPb)
format.

INSEL[3:0] has predefined analog input routing schemes that
do not require manual mux programming (see
Tabl e 11 ). This allows the user to route the various video signal
types to the decoder and select them using INSEL[3:0] only.
The added benefit is that if, for example, CVBS input is selected,
the remaining channels are powered down.

Table 1 0 and

05700-011

Table 10. ADV7180 LQFP-64 INSEL[3:0]

INSEL[3:0] Video Format Analog Input

0000 Composite
0001 Composite
0010 Composite
0011 Composite
0100 Composite
0101 Composite
0110 Y/C (S-video)

0111 Y/C (S-video)

1000 Y/C (S-video)

1001 YPrPb

1010 YPrPb

CVBS → AIN1
CVBS → A

IN

CVBS → AIN3
CVBS → A

IN

CVBS → AIN5
CVBS → AIN6
Y → AIN1

4

C → A

IN

Y → AIN2
C → AIN5
Y → AIN3
C → AIN6
Y → AIN1
Pb → AIN4
Pr → AIN5
Y → AIN2
Pr → AIN6
Pb → AIN3

2

4

1011 to 1111 Not used Not used

Table 11. ADV7180 LFCSP-40 INSEL[3:0]

INSEL[3:0] Video Format Analog Input

0000 Composite

CVBS → AIN1
0001 to 0010 Not used Not used
0011 Composite
0100 Composite

CVBS → AIN2

CVBS → AIN3
0101 Not used Not used
0110 Y/C (S-video)

Y → AIN1

C → AIN2
0111 to 1000 Not used Not used
1001 YPrPb

Y → AIN1

Pr → A

IN

Pb → A

3

2

IN

1010 to 1111 Not used Not used

Rev. A | Page 16 of 112

ADV7180

ANALOG INPUT MUXING

The ADV7180 has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder.
of the input muxing provided in the ADV7180.

A maximum of six CVBS inputs can be connected to and
decoded by the ADV7180BSTZ (64-lead LQFP) and a
maximum of three for ADV7180BCPZ (40-lead LFCSP). As
shown in the
section, these analog input pins lie in close proximity to one
another. This calls for a careful design of the PCB layout; for
example, ground shielding between all signals should be routed
through tracks that are physically close together. It is strongly
recommended to connect any unused analog input pins to
AGND to act as a shield.

Figure 9 and Figure 10 outline the overall structure

Pin Configurations and Function Description

MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4 [7]

To configure the ADV7180 analog muxing section, the user
must select the analog input A

1 to AIN3 (ADV7180BCPZ) that is to be processed by the

A

IN

1 to AIN6 (ADV7180BSTZ) or

IN

ADC. MAN_MUX_EN must be set to 1 to enable the following
muxing blocks:

• MUX_0[3:0], ADC Mux Configuration, Address 0xC3 [3:0]

• MUX_1[3:0], ADC Mux Configuration, Address 0xC3 [7:4]

• MUX_2[3:0], ADC Mux Configuration, Address 0xC4 [3:0]

The three mux sections are controlled by the signal buses
SW_0/1/2[3:0].

Tabl e 12 explains the control words used.

The input signal that contains the timing information (HS and
VS) must be processed by MUX_0. For example, in a Y/C input
configuration, MUX0 should be connected to the Y channel
and MUX1 to the C channel. When one or more muxes are not
used to process video, such as CVBS input, the idle mux and
associated channel clamps and buffers should be powered down
(see the description of Register 0x3A in

Tabl e 1 0 3).

Table 12. Manual Mux Settings for the ADC (MAN_MUX_EN Must be Set to 1)

ADC Connected to ADC Connected to ADC Connected to
MUX_0[3:0] LQFP-64 LFCSP-40 MUX_1[3:0] LQFP-64 LFCSP-40 MUX_2[3:0] LQFP-64 LFCSP-40

000 No connect No connect 000 No connect No connect 000 No connect No connect
001 AIN1 AIN1 001 No connect No connect 001 No connect No connect
010 AIN2 No connect 010 No connect No connect 010 AIN2 No connect
011 AIN3 No connect 011 AIN3 No connect 011 No connect No connect
100 AIN4 AIN2 100 AIN4 AIN2 100 No connect No connect
101 AIN5 AIN3 101 AIN5 AIN3 101 AIN5 AIN3
110 AIN6 No connect 110 AIN6 No connect 110 AIN6 No connect
111 No connect No connect 111 No connect No connect 111 No connect No connect

Note the following:

• CVBS can only be processed by MUX_0.

• Y/C can only be processed by MUX_0 and MUX_1, respectively.

• YPrPb can only be processed by MUX_0, MUX_1, and MUX_2, respectively.

Rev. A | Page 17 of 112

ADV7180

A

A

A

–

–12–

–

–24–28–

–

–

–

–

–

ANTIALIASING FILTERS

The ADV7180 has optional on-chip antialiasing filters on each
of the three channels that are multiplexed to the ADC (see
Figure 12). The filters are designed for standard definition video
up to 10 MHz bandwidth.

Figure 13 and Figure 14 show the

filter magnitude and phase characteristics.

The antialiasing filters are enabled by default and the selection
of INSEL[3:0] determines which filters are powered up at any
given time. For example, if CVBS mode is selected, the filter
circuits for the remaining input channels are powered down to
conserve power. However, the antialiasing filters can be disabled
or bypassed using the AA_FILT_MAN_OVR control.

10-BIT, 86MHz

AIN1

A

A

IN

IN

IN

AA

MUX BLOCK

FILTER 1

AA

FILTER 2

AA

FILTER 3

2

IN

3

IN

1

4

1

5

1

6

1

ONLY AVAIL ABLE IN 64-LE AD PACKAGE

ADC

SHA A/D

05700-012

Figure 12. Antialias Filter Configuration

AA_FILT_MAN_OVR, Antialiasing Filter Override,
Address 0xF3 [3]

This feature allows the user to override the antialiasing filters
on/off settings, which are automatically selected by INSEL[3:0].

AA_FILT_EN, Antialiasing Filter Enable, Address 0xF3 [2:0]

These bits allow the user to enable or disable the antialiasing
filters on each of the three input channels multiplexed to the
ADC. When disabled, the analog signal bypasses the AA filter
and is routed directly to the ADC.

AA_FILT_EN, Address 0xF3 [0]

When AA_FILT_EN[0] is 0, AA Filter 1 is bypassed.

When AA_FILT_EN[0] is 1, AA Filter 1 is enabled.

AA_FILT_EN, Address 0xF3 [1]

When AA_FILT_EN[1] is 0, AA Filter 2 is bypassed.

When AA_FILT_EN[1] is 1, AA Filter 2 is enabled.

AA_FILT_EN, Address 0xF3 [2]

When AA_FILT_EN[2] is 0, AA Filter 3 is bypassed.

When AA_FILT_EN[2] is 1, AA Filter 3 is enabled.

0

–4

–8

16

20

32

36

1k

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 13. Antialiasing Filter Magnitude Response

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

100

–110

120

130

140

150

1k

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 14. Antialiasing Filter Phase Response

100M

100M

05700-013

05700-014

Rev. A | Page 18 of 112

ADV7180

GLOBAL CONTROL REGISTERS

Register control bits listed in this section affect the whole chip.

POWER-SAVING MODES

Power-Down

PDBP, Address 0x0F [2]

The digital supply of the ADV7180 can be shut down by using
the (

PWRDWN

controls whether the I
priority. The default is to give the pin (

) pin or via I2C (PWRDWN, see below). PDBP

2

C control or the pin has the higher

PWRDWN

) priority.

This allows the user to have the ADV7180 powered down by
default at power-up without the need for an I

2

C write.

When PDBD is 0 (default), the digital supply power is controlled
by the

PWRDWN

pin (the PWRDWN bit is disregarded).

When PDBD is 1, the PWRDWN bit, 0x0F[5], has priority
(the pin is disregarded).

PWRDWN, Address 0x0F [5]

When PDBP is set to 1, setting the PWRDWN bit switches the
ADV7180 to a chip-wide power-down mode. The power-down
stops the clock from entering the digital section of the chip,
thereby freezing its operation. No I

2

C bits are lost during
power-down. The PWRDWN bit also affects the analog blocks
and switches them into low current modes. The I

2

C interface is

unaffected and remains operational in power-down mode.

The ADV7180 leaves the power-down state if the PWRDWN bit is
set to 0 (via I

2

C) or if the ADV7180 is reset using the

RESET

pin.

PDBP must be set to 1 for the PWRDWN bit to power down
the ADV7180.

When PWRDWN is 0 (default), the chip is operational.
When PWRDWN is 1, the ADV7180 is in a chip-wide
power-down mode.

RESET CONTROL

RESET, Chip Reset, Address 0x0F [7]

Setting this bit, which is equivalent to controlling the
pin on the ADV7180, issues a full chip reset. All I
are reset to their default/power-up values. Note that some
register bits do not have a reset value specified. They keep their
last written value. Those bits are marked as having a reset value
of x in the register tables (

Table 103 and Ta b le 1 04 ). After the
reset sequence, the part immediately starts to acquire the
incoming video signal.

RESET

2

C registers

After setting the RESET bit (or initiating a reset via the
the part returns to the default for its primary mode of operation.

2

All I

C bits are loaded with their default values, making this bit

self-clearing.

Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I
performed.

2

C master controller receives a no acknowledge condition

The I
on the ninth clock cycle when chip reset is implemented. See
the

MPU Port Description section.

When RESET is 0 (default), operation is normal.

When RESET is 1, the reset sequence starts.

GLOBAL PIN CONTROL

Three-State Output Drivers

TOD, Address 0x03 [6]

This bit allows the user to three-state the output drivers of the
ADV7180.

Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the
ADV7180 LFCSP-40), HS, VS, FIELD (VS/FIELD pin for the
ADV7180 LFCSP-40), and SFL pins are three-stated.

The timing pins (HS, VS, FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the

Three-State LLC Driver and the Timing Signals Output

Enable

sections.

Individual drive strength controls are provided via the
DR_STR_XX bits.

When TOD is 0 (default), the output drivers are enabled.

When TOD is 1, the output drivers are three-stated.

Three-State LLC Driver

TRI_LLC, Address 0x1D [7]

This bit allows the output drivers for the LLC pin of the
ADV7180 to be three-stated. For more information on three­state control, refer to the
Timing Signals Output Enable sections.

Individual drive strength controls are provided via the
DR_STR_XX bits.

When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).

When TRI_LLC is 1, the LLC pin drivers are three-stated.

Three-State Output Drivers and the

RESET

pin),

2

C writes are

Rev. A | Page 19 of 112

ADV7180

Timing Signals Output Enable

TIM_OE, Address 0x04 [3]

The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD into the active state (that is, driving state) even if the
TOD bit is set. If TIM_OE is set to low, the HS, VS, and FIELD
pins are three-stated depending on the TOD bit. This
functionality is beneficial if the decoder is to be used as a
timing generator only. This may be the case if only the timing
signals are to be extracted from an incoming signal, or if the
part is in free-run mode, where a separate chip can output a
company logo, for example.

For more information on three-state control, refer to the
Three-State Output Drivers section and the Three-State LLC
Driver

section.

Individual drive strength controls are provided via the
DR_STR_XX bits.

When TIM_OE is 0 (default), HS, VS, and FIELD are three­stated according to the TOD bit.

When TIM_OE is 1, HS, VS, and FIELD are forced active all the
time.

Drive Strength Selection (Data)

DR_STR[1:0], Address 0xF4 [5:4]

For EMC and crosstalk reasons, it may be desirable to
strengthen or weaken the drive strength of the output drivers.
The DR_STR[1:0] bits affect the P[15:0] output drivers.

For more information on three-state control, refer to the
Strength Selection (Clock)
(Sync)

sections.

Table 13. DR_STR Function

DR_STR[1:0] Description

00 Low drive strength (1×)
01 (default) Medium-low drive strength (2×)
10 Medium-high drive strength (3×)
11 High drive strength (4×)

and the Drive Strength Selection

Drive

Drive Strength Selection (Clock)

DR_STR_C[1:0], Address 0xF4 [3:2]

The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the
Strength Selection (Data)

Drive Strength Selection (Sync) and the Drive

sections.

Table 14. DR_STR_C Function

DR_STR_C[1:0] Description

00 Low drive strength (1×)
01 (default) Medium-low drive strength (2×)
10 Medium-high drive strength (3×)
11 High drive strength (4×)

Drive Strength Selection (Sync)

DR_STR_S[1:0], Address 0xF4 [1:0]

The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and FIELD are
driven. For more information, refer to the
Selection (Data)

Table 15. DR_STR_S Function

DR_STR_S[1:0] Description

00 Low drive strength (1×)
01 (default) Medium-low drive strength (2×)
10 Medium-high drive strength (3×)
11 High drive strength (4×)

section.

Drive Strength

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN, Address 0x04 [1]

The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as Genlock) from the ADV7180 core
to an encoder in a decoder/encoder back-to-back arrangement.

When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.

When EN_SFL_PIN is 1, the subcarrier frequency lock
information is presented on the SFL pin.

Polarity LLC Pin

PCLK, Address 0x37 [0]

The polarity of the clock that leaves the ADV7180 via the LLC
pin can be inverted using the PCLK bit.

Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.

When PCLK is 0, the LLC output polarity is inverted.

When PCLK is 1 (default), the LLC output polarity is normal
(see the

Timing Specifications section).

Rev. A | Page 20 of 112

ADV7180

GLOBAL STATUS REGISTER

Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV7180. The other three registers contain
status bits from the ADV7180.

IDENTIFICATION

IDENT[7:0], Address 0x11 [7:0]

The register identification of the revision of the ADV7180. An
identification value of 0x18 indicates the ADV7180.

STATUS 1

STATUS_1[7:0], Address 0x10 [7:0]

This read-only register provides information about the internal
status of the ADV7180.

See the
and the

CIL[2:0], Count Into Lock, Address 0x51 [2:0] section

COL[2:0], Count Out of Lock, Address 0x51 [5:3]

section for details on timing.

Depending on the setting of the FSCLE bit, the Status Register 0
and Status Register 1 are based solely on horizontal timing infor­mation or on the horizontal timing and lock status of the color
subcarrier. See the

FSCLE, FSC Lock Enable, Address 0x51 [7]

section.

AUTODETECTION RESULT

AD_RESULT[2:0], Address 0x10 [6:4]

The AD_RESULT[2:0] bits report back on the findings from the
ADV7180 autodetection block. Consult the
section for more information on enabling the autodetection
block and the

Autodetection of SD Modes section for more

information on how to configure it.

Table 16. AD_RESULT Function

AD_RESULT[2:0] Description

000 NTSM M/J
001 NTSC 4.43
010 PAL M
011 PAL 60
100 PAL B/G/H/I/D
101 SECAM
110 PAL Combination N
111 SECAM 525

General Setup

Table 17. Status_1 Function

STATUS_1
[7:0]

0 IN_LOCK In lock (now)
1 LOST_LOCK

2 FSC_LOCK FSC locked (now)
3 FOLLOW_PW

4 AD_RESULT[0] Result of autodetection
5 AD_RESULT[1] Result of autodetection
6 AD_RESULT[2] Result of autodetection
7 COL_KILL Color kill active

Bit Name Description

Lost lock (since last read of this
register)

AGC follows peak white
algorithm

STATUS 2

STATUS_2[7:0], Address 0x12 [7:0]

Table 18. STATUS_2 Function

STATUS_2
[7:0]

0 MVCS DET Detected Macrovision color striping
1 MVCS T3

2 MV PS DET

3 MV AGC DET Detected Macrovision AGC pulses
4 LL NSTD Line length is nonstandard
5 FSC NSTD FSC frequency is nonstandard
6 Reserved

7 Reserved

Bit Name Description

Macrovision color striping
protection; conforms to Type 3 if
high, Type 2 if low

Detected Macrovision pseudo
sync pulses

STATUS 3

STATUS_3[7:0], Address 0x13 [7:0]

Table 19. STATUS_3 Function

STATUS_3
[7:0]

0 INST_HLOCK

1 GEMD Gemstar detect
2 SD_OP_50Hz

3 Reserved for future use
4 FREE_RUN_ACT

5 STD FLD LEN

6 INTERLACED

7 PAL_SW_LOCK

Bit Name Description

Horizontal lock indicator
(instantaneous)

Flags whether 50 Hz or 60 Hz is
present at output

ADV7180 outputs a blue screen
(see the
Value Enable, Address 0x0C [0]
section)

Field length is correct for
currently selected video standard

Interlaced video detected (field
sequence found)

Reliable sequence of swinging
bursts detected

DEF_VAL_EN, Default

Rev. A | Page 21 of 112

ADV7180

VIDEO PROCESSOR

STANDARD DEFINITION PROCESSOR

DIGITIZE D CVBS

DIGITIZED Y (YC)

DIGITIZE D CVBS

DIGITIZED C (YC)

MACROVISIO N

DETECTIO N

LUMA

DIGITAL

FINE

CLAMP

CHROMA

DIGITAL

FINE

CLAMP

RECOVERY

CHROMA

DEMOD

F

SC

RECOVERY

VBI DATA

FILTER

EXTRACT

CHROMA

FILTER

AUTODETECTION

LUMA

SYNC

STANDARD

PREDICTOR

Figure 15. Block Diagram of the Video Processor

Figure 15 shows a block diagram of the ADV7180 video processor.
The ADV7180 can handle standard definition video in CVBS,
Y/C, and YPrPb formats. It can be divided into a luminance and
chrominance path. If the input video is of a composite type
(CVBS), both processing paths are fed with the CVBS input.

SD LUMA PATH

The input signal is processed by the following blocks:

• Luma Digital Fine Clamp.

This block uses a high precision algorithm to clamp the
video signal.

• Luma Filter.

This block contains a luma decimation filter (YAA) with a
fixed response and some shaping filters (YSH) that have
selectable responses.

• Luma Gain Control.

The automatic gain control (AGC) can operate on a variety
of different modes, including gain based on the depth of
the horizontal sync pulse, peak white mode, and fixed
manual gain.

• Luma Resample.

To correct for line-length errors as well as dynamic line­length changes, the data is digitally resampled.

• Luma 2D Comb.

The two-dimensional comb filter provides Y/C separation.

• AV Code Insertion.

At this point, the decoded luma (Y) signal is merged with
the retrieved chroma values. AV codes can be inserted
(as per ITU-R BT.656).

LUMA

GAIN

CONTRO L

LINE

LENGTH

CHROMA

GAIN

CONTRO L

SLLC

CONTROL

LUMA

RESAMPLE

RESAMPLE

CONTROL

CHROMA

RESAMPLE

LUMA

2D COMB

CHROMA
2D COMB

AV

CODE

INSERTION

VIDEO DAT A
OUTPUT

MEASUREMENT
BLOCK ( I

VIDEO DAT A
PROCESSING
BLOCK

SD CHROMA PATH

The input signal is processed by the following blocks:

• Chroma Digital Fine Clamp.

This block uses a high precision algorithm to clamp the
video signal.

• Chroma Demodulation.

This block employs a color subcarrier (F
regenerate the color subcarrier for any modulated chroma
scheme. The demodulation block then performs an AM
demodulation for PAL and NTSC, and an FM demodulation
for SECAM.

• Chroma Filter.

This block contains a chroma decimation filter (CAA) with
a fixed response and some shaping filters (CSH) that have
selectable responses.

• Chroma Gain Control.

Automatic gain control (AGC) can operate on several
different modes, including gain based on the color subcarrier
amplitude, gain based on the depth of the horizontal sync
pulse on the luma channel, or fixed manual gain.

• Chroma Resample.

The chroma data is digitally resampled to keep it perfectly
aligned with the luma data. The resampling is done to
correct for static and dynamic line-length errors of the
incoming video signal.

• Chroma 2D Comb.

The 2D, 5-line, superadaptive comb filter provides high
quality Y/C separation in case the input signal is CVBS.

) recovery unit to

SC

2

C)

05700-015

Rev. A | Page 22 of 112

ADV7180

• AV Code Insertion.

At this point, the demodulated chroma (Cr and Cb) signal
is merged with the retrieved luma values. AV codes can be
inserted (as per ITU-R BT.656).

SYNC PROCESSING

The ADV7180 extracts syncs embedded in the analog input
video signal. There is currently no support for external HS/VS
inputs. The sync extraction is optimized to support imperfect
video sources, such as videocassette recorders with head
switches. The actual algorithm used employs a coarse detection
based on a threshold crossing, followed by a more detailed
detection using an adaptive interpolation algorithm. The raw
sync information is sent to a line-length measurement and
prediction block. The output of this is then used to drive the
digital resampling section to ensure that the ADV7180 outputs
720 active pixels per line.

The sync processing on the ADV7180 also includes the
following specialized postprocessing blocks that filter and
condition the raw sync information retrieved from the digitized
analog video:

• VSYNC Processor.

This block provides extra filtering of the detected VSYNCs
to improve vertical lock.

• HSYNC Processor.

The HSYNC processor is designed to filter incoming
HSYNCs that have been corrupted by noise, providing
much improved performance for video signals with a
stable time base but poor SNR.

VBI DATA RECOVERY

The ADV7180 can retrieve the following information from the
input video:

• Wide-screen signaling (WSS)

• Copy generation management system (CGMS)

• Closed captioning (CCAP)

• Macrovision protection presence

• EDTV data

• Gemstar-compatible data slicing

• Te l e te x t

• VITC/VPS

The ADV7180 is also capable of automatically detecting the
incoming video standard with respect to

• Color subcarrier frequency

• Field rate

• Line rate

The ADV7180 can configure itself to support PAL B/G/H/I/D,
PAL M/N, PAL Combination N, NTSC M, NTSC J, SECAM
50 Hz/60 Hz, NTSC 4.43, and PAL 60.

Rev. A | Page 23 of 112

GENERAL SETUP

Video Standard Selection

The VID_SEL[3:0] register allows the user to force the digital
core into a specific video standard. Under normal circumstances,
this is not necessary. The VID_SEL[3:0] bits default to an auto­detection mode that supports PAL, NTSC, SECAM, and variants
thereof. The following section provides more information on
the autodetection system.

Autodetection of SD Modes

To guide the autodetect system of the ADV7180, individual
enable bits are provided for each of the supported video standards.
Setting the relevant bit to 0 inhibits the standard from being
detected automatically. Instead, the system picks the closest of
the remaining enabled standards. The results of the autodetection
block can be read back via the status registers. See the
Status Register

section for more information.

VID_SEL[3:0], Address 0x00 [7:4]

Table 20. VID_SEL Function

VID_SEL[3:0] Description

0000 (default)

0001

0010

0011

0100 NTSC J (1)
0101 NTSC M (1)
0110 PAL 60
0111 NTSC 4.43 (1)
1000 PAL B/G/H/I/D
1001 PAL N = PAL B/G/H/I/D (with pedestal)
1010 PAL M (without pedestal)
1011 PAL M
1100 PAL Combination N
1101 PAL Combination N (with pedestal)
1110 SECAM
1111 SECAM (with pedestal)

Autodetect (PAL B/G/H/I/D) <–> NTSC J
(no pedestal), SECAM

Autodetect (PAL B/G/H/I/D) <–> NTSC M
(pedestal), SECAM

Autodetect (PAL N) (pedestal) <–> NTSC J
(no pedestal), SECAM

Autodetect (PAL N) (pedestal) <–> NTSC M
(pedestal), SECAM

AD_SEC525_EN, Enable Autodetection of SECAM 525
Line Video, Address 0x07 [7]

Setting AD_SEC525_EN to 0 (default) disables the
autodetection of a 525-line system with a SECAM-style, FM­modulated color component.

Setting AD_SEC525_EN to 1 enables the detection of a
SECAM-style, FM-modulated color component.

Global

ADV7180

K

AD_SECAM_EN, Enable Autodetection of SECAM,
Address 0x07 [6]

Setting AD_SECAM_EN to 0 (default) disables the
autodetection of SECAM.

Setting AD_SECAM_EN to 1 enables the detection of SECAM.

AD_N443_EN, Enable Autodetection of NTSC 4.43,
Address 0x07 [5]

Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.

Setting AD_N443_EN to 1 (default) enables the detection of
NTSC style systems with a 4.43 MHz color subcarrier.

AD_P60_EN, Enable Autodetection of PAL 60,
Address 0x07 [4]

Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.

Setting AD_P60_EN to 1 (default) enables the detection of PAL
systems with a 60 Hz field rate.

AD_PALN_EN, Enable Autodetection of PAL N,
Address 0x07 [3]

Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.

Setting AD_PALN_EN to 1 enables the detection of the PAL N
standard.

AD_PALM_EN, Enable Autodetection of PAL M,
Address 0x07 [2]

Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.

Setting AD_PALM_EN to 1 enables the detection of PAL M.

AD_NTSC_EN, Enable Autodetection of NTSC,
Address 0x07 [1]

Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.

Setting AD_NTSC_EN to 1 enables the detection of standard
NTSC.

SIGNAL

0

COUNTER INTO LOCK

COUNTER OUT O F LOCK

1

TIME_WIN

FREE_RUN

F

LOCK

SC

SELECT THE RAW LOC
SRLS

1

0

AD_PAL_EN, Enable Autodetection of PAL,
Address 0x07 [0]

Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.

Setting AD_PAL_EN to 1 enables the detection of standard PAL.

SFL_INV, Subcarrier Frequency Lock Inversion

This bit controls the behavior of the PAL switch bit in the SFL
(Genlock Telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems.

First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.

Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(Genlock Telegram) bit directly, whereas the later ones invert
the bit prior to using it. The reason for this is that the inversion
compensated for the one-line delay of an SFL (Genlock
Telegram) transmission.

As a result, ADV717x encoders need the PAL switch bit in the
SFL (GenLock Telegram) to be 1 for NTSC to work. Also,
ADV7190/ADV7191/ADV7194 encoders need the PAL switch
bit in the SFL to be 0 to work in NTSC. If the state of the PAL
switch bit is wrong, a 180° phase shift occurs.

In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.

SFL_INV, Subcarrier Frequency Lock Inversion,
Address 0x41 [6]

Setting SFL_INV to 0 (default) makes the part SFL-compatible
with ADV7190/ADV7191/ADV7194 encoders.

Setting SFL_INV to 1 makes the part SFL-compatible with
ADV717x and ADV7173x encoders.

Lock Related Controls

Lock information is presented to the user through Bits[1:0] of
the Status Register 1. See the
section.

Figure 16 outlines the signal flow and the controls

STATUS_1[7:0], Address 0x10 [7:0]

available to influence the way the lock status information is
generated.

FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]

STATUS_1 [0]

MEMORY

STATUS_1 [1]

TAKE F

LOCK INTO ACCOUNT

SC

FSCLE

Figure 16. Lock Related Signal Path

Rev. A | Page 24 of 112

05700-016

ADV7180

SRLS, Select Raw Lock Signal, Address 0x51 [6]

Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status Register 1).
Refer to

Figure 16.

• The TIME_WIN signal is based on a line-to-line evaluation

of the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.

• The FREE_RUN signal evaluates the properties of the

incoming video over several fields, taking vertical
synchronization information into account.

Setting SRLS to 0 (default) selects the FREE_RUN signal.

Setting SRLS to 1 selects the TIME_WIN signal.

FSCLE, FSC Lock Enable, Address 0x51 [7]

The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in Status
Register 1. This bit must be set to 0 when operating the
ADV7180 in YPrPb component mode in order to generate a
reliable HLOCK status bit.

When FSCLE is set to 0 (default), only the overall lock status is
dependent on horizontal sync lock.

When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and F

lock.

SC

CIL[2:0], Count Into Lock, Address 0x51 [2:0]

CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state and reports this via Status 0 [1:0]. The bit
counts the value in lines of video.

Table 21. CIL Function

CIL[2:0] Number of Video Lines

000 1
001 2
010 5
011 10
100 (default) 100
101 500
110 1000
111 100,000

COL[2:0], Count Out of Lock, Address 0x51 [5:3]

COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into the unlocked state and reports this via Status 0 [1:0]. It counts
the value in lines of video.

Table 22. COL Function

COL[2:0] Number of Video Lines

000 1
001 2
010 5
011 10
100 (default) 100
101 500
110 1000
111 100,000

COLOR CONTROLS

These registers allow the user to control picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture clamping,
although both controls affect the dc level of the signal.

CON[7:0], Contrast Adjust, Address 0x08 [7:0]

This register allows the user to control contrast adjustment of
the picture.

Table 23. CON Function

CON[7:0] Description

0x80 (default) Gain on luma channel = 1
0x00 Gain on luma channel = 0
0xFF Gain on luma channel = 2

SD_SAT_Cb[7:0], SD Saturation Cb Channel,
Address 0xE3 [7:0]

This register allows the user to control the gain of the Cb
channel only, which in turn adjusts the saturation of the picture.

Table 24. SD_SAT_Cb Function

SD_SAT_Cb[7:0] Description

0x80 (default) Gain on Cb channel = 0 dB
0x00 Gain on Cb channel = −42 dB
0xFF Gain on Cb channel = +6 dB

Rev. A | Page 25 of 112

ADV7180

SD_SAT_Cr[7:0], SD Saturation Cr Channel,
Address 0xE4 [7:0]

This register allows the user to control the gain of the Cr
channel only, which in turn adjusts the saturation of the picture.

Table 25. SD_SAT_Cr Function

SD_SAT_Cr[7:0] Description

0x80 (default) Gain on Cr channel = 0 dB
0x00 Gain on Cr channel = −42 dB
0xFF Gain on Cr channel = +6 dB

SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1 [7:0]

This register allows the user to select an offset for the Cb
channel only and to adjust the hue of the picture. There is a
functional overlap with the HUE[7:0] register.

Table 26. SD_OFF_Cb Function

SD_OFF_Cb[7:0] Description

0x80 (default) 0 offset applied to the Cb channel
0x00 −312 mV offset applied to the Cb channel
0xFF +312 mV offset applied to the Cb channel

SD_OFF_Cr [7:0], SD Offset Cr Channel, Address 0xE2 [7:0]

This register allows the user to select an offset for the Cr channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.

Table 27. SD_OFF_Cr Function

SD_OFF_Cr[7:0] Description

0x80 (default) 0 offset applied to the Cr channel
0x00 −312 mV offset applied to the Cr channel
0xFF +312 mV offset applied to the Cr channel

BRI[7:0], Brightness Adjust, Address 0x0A [7:0]

This register controls the brightness of the video signal. It
allows the user to adjust the brightness of the picture.

Table 28. BRI Function

BRI[7:0] Description

0x00 (default) Offset of the luma channel = 0IRE
0x7F Offset of the luma channel = +100IRE
0x80 Offset of the luma channel = –100IRE

HUE[7:0], Hue Adjust, Address 0x0B [7:0]

This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.

HUE[7:0] has a range of ±90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.

The hue adjustment value is fed into the AM color demodula­tion block. Therefore, it only applies to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM and
does not work on component video inputs (YPrPb).

Table 29. HUE Function

HUE[7:0] Description (Adjust Hue of the Picture)
0x00 (default) Phase of the chroma signal = 0°
0x7F Phase of the chroma signal = −90°
0x80 Phase of the chroma signal = +90°

DEF_Y[5:0], Default Value Y, Address 0x0C [7:2]

When the ADV7180 loses lock on the incoming video signal or
when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:

• If DEF_VAL_AUTO_EN bit is set to high and the ADV7180

has lost lock to the input video signal, this is the intended
mode of operation (automatic mode).

• The DEF_VAL_EN bit is set, regardless of the lock status of

the video decoder. This is a forced mode that may be
useful during configuration.

The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.

For DEF_Y[5:0], 0x0D (blue) is the default value for Y.

Register 0x0C has a default value of 0x36.

DEF_C[7:0], Default Value C, Address 0x0D [7:0]

The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the four MSBs of Cr and Cb values to be output if

• The DEF_VAL_AUTO_EN bit is set to high and the

ADV7180 cannot lock to the input video (automatic mode).

• DEF_VAL_EN bit is set to high (forced output).

The data that is finally output from the ADV7180 for the
chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =
{DEF_C[3:0], 0, 0, 0, 0}.

For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.

DEF_VAL_EN, Default Value Enable, Address 0x0C [0]

This bit forces the use of the default values for Y, Cr, and Cb.
Refer to the descriptions in the
Address 0x0C [7:2]
0x0D [7:0]

sections for additional information. In this mode,

and DEF_C[7:0], Default Value C, Address

DEF_Y[5:0], Default Value Y,

the decoder also outputs a stable 27 MHz clock, HS, and VS.

Setting DEF_VAL_EN to 0 (default) outputs a colored screen
determined by user-programmable Y, Cr, and Cb values when
the decoder free-runs. Free-run mode is turned on and off by
the DEF_VAL_AUTO_EN bit.

Setting DEF_VAL_EN to 1 forces a colored screen output
determined by user-programmable Y, Cr, and Cb values. This
overrides picture data even if the decoder is locked.

Rev. A | Page 26 of 112

ADV7180

DEF_VAL_AUTO_EN, Default Value Automatic Enable,
Address 0x0C [1]

This bit enables the automatic use of the default values for Y, Cr,
and Cb when the ADV7180 cannot lock to the video signal.

Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If
the decoder is unlocked, it outputs noise.

Setting DEF_VAL_EN to 1 (default) enables free-run mode and
a colored screen set by user-programmable Y, Cr, and Cb values
is displayed when the decoder loses lock.

CLAMP OPERATION

The input video is ac-coupled into the ADV7180. Therefore, its
dc value needs to be restored. This process is referred to as
clamping the video. This section explains the general process of
clamping on the ADV7180 and shows the different ways in
which a user can configure its behavior.

The ADV7180 uses a combination of current sources and a
digital processing block for clamping, as shown in
The analog processing channel shown is replicated three times
inside the IC. While only one single channel is needed for a
CVBS signal, two independent channels are needed for Y/C
(S-VHS) type signals, and three independent channels are
needed to allow component signals (YPrPb) to be processed.

The clamping can be divided into two sections:

• Clamping before the ADC (analog domain): current

sources.

• Clamping after the ADC (digital domain): digital

processing block.

The ADC can digitize an input signal only if it resides within
the ADC 1.0 V input voltage range. An input signal with a dc
level that is too large or too small is clipped at the top or bottom
of the ADC range.

The primary task of the analog clamping circuits is to ensure that
the video signal stays within the valid ADC input window so that
the analog-to-digital conversion can take place. It is not necessary
to clamp the input signal with a very high accuracy in the analog
domain as long as the video signal fits within the ADC range.

Figure 17.

After digitization, the digital fine clamp block corrects for any
remaining variations in dc level. Because the dc level of an input
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations may occur. Further­more, dynamic changes in the dc level almost certainly lead to
visually objectionable artifacts, and must therefore be prohibited.

The clamping scheme has to complete two tasks. It must acquire
a newly connected video signal with a completely unknown dc
level, and it must maintain the dc level during normal operation.

To acquire an unknown video signal quickly, the large current
clamps should be activated. It is assumed that the amplitude of
the video signal at this point is of a nominal value. Control of
the coarse and fine current clamp parameters is performed
automatically by the decoder.

Standard definition video signals may have excessive noise on
them. In particular, CVBS signals transmitted by terrestrial
broadcast and demodulated using a tuner usually show very
large levels of noise (>100 mV). A voltage clamp would be
unsuitable for this type of video signal. Instead, the ADV7180
employs a set of four current sources that can cause coarse
(>0.5 mA) and fine (<0.1 mA) currents to flow into and away
from the high impedance node that carries the video signal
(see

Figure 17).

2

The following sections describe the I

C signals that can be used

to influence the behavior of the clamping block.

CCLEN, Current Clamp Enable, Address 0x14 [4]

The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This may be
useful if the incoming analog video signal is clamped externally.

When CCLEN is 0, the current sources are switched off.

When CCLEN is 1 (default), the current sources are enabled.

COARSE CURRENT SOURCESFINE CURRENT SOURCES

ANALOG

VIDEO

INPUT

ADC

Figure 17. Clamping Overview

Rev. A | Page 27 of 112

DATA
PRE-

PROCESSOR

(DPP)

CLAMP CONT ROL

VIDEO PRO CESSOR

WITH DIGITAL

FINE CL AMP

05700-017

ADV7180

DCT[1:0], Digital Clamp Timing, Address 0x15 [6:5]

The clamp timing register determines the time constant of the
digital fine clamp circuitry. It is important to note that the
digital fine clamp reacts very quickly because it is supposed to
immediately correct any residual dc level error for the active
line. The time constant from the digital fine clamp must be
much quicker than the one from the analog blocks.

By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.

Table 30. DCT Function

DCT[1:0] Description

00 (default) Slow (TC = 1 sec)
01 Medium (TC = 0.5 sec)
10 Fast (TC = 0.1 sec)
11

Determined by ADV7180, depending on the
input video parameters

DCFE, Digital Clamp Freeze Enable, Address 0x15 [4]

This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who would like to do their
own clamping. Users should disable the current sources for
analog clamping via the appropriate register bits, wait until the
digital clamp loop settles, and then freeze it via the DCFE bit.

When DCFE to 0 (default), the digital clamp is operational.

When DCFE is 1, the digital clamp loop is frozen.

LUMA FILTER

Data from the digital fine clamp block is processed by three sets
of filters. Note that the data format at this point is CVBS for
CVBS input or luma only for Y/C and YPrPb input formats.

• Luma Antialias Filter (YAA).

The ADV7180 receives video at a rate of 27 MHz. (In the case
of 4× oversampled video, the ADC samples at 57.27 MHz,
and the first decimation is performed inside the DPP filters.
Therefore, the data rate into the ADV7180 is always 27 MHz.)
The ITU-R BT.601 recommends a sampling frequency of

13.5 MHz. The luma antialias filter decimates the oversampled
video using a high quality linear phase, low-pass filter that
preserves the luma signal while at the same time attenuating
out-of-band components. The luma antialias filter (YAA)
has a fixed response.

• Luma Shaping Filters (YSH).

The shaping filter block is a programmable low-pass filter
with a wide variety of responses. It can be used to
selectively reduce the luma video signal bandwidth
(needed prior to scaling, for example). For some video
sources that contain high frequency noise, reducing the
bandwidth of the luma signal improves visual picture
quality. A follow-on video compression stage may work
more efficiently if the video is low-pass filtered.

The ADV7180 has two responses for the shaping filter:
one that is used for good quality composite, component,
and S-VHS type sources, and a second for nonstandard
CVBS signals.

The YSH filter responses also include a set of notches for
PAL and NTSC. However, using the comb filters for Y/C
separation is recommended.

• Digital Resampling Filter.

This block allows dynamic resampling of the video signal
to alter parameters such as the time base of a line of video.
Fundamentally, the resampler is a set of low-pass filters.
The actual response is chosen by the system with no
requirement for user intervention.

Figure 19 through Figure 22 show the overall response of all
filters together. Unless otherwise noted, the filters are set into a
typical wideband mode.

Y Shaping Filter

For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. Y/C separation must aim for best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
Y/C separation can be achieved by using the internal comb
filters of the ADV7180. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of
the video line rate) and the color subcarrier (F

). For good

SC

quality CVBS signals, this relationship is known; the comb filter
algorithms can be used to separate luma and chroma with high
accuracy.

In the case of nonstandard video signals, the frequency
relationship may be disturbed and the comb filters may not be
able to remove all crosstalk artifacts in the best fashion without
the assistance of the shaping filter block.

Rev. A | Page 28 of 112

ADV7180

An automatic mode is provided that allows the ADV7180 to
evaluate the quality of the incoming video signal and select the
filter responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.

The luma shaping filter has three control registers:

• YSFM[4:0] allows the user to manually select a shaping

filter mode (applied to all video signals) or to enable an
automatic selection (depending on video quality and video
standard).

• WYSFMOVR allows the user to manually override the

WYSFM decision.

• WYSFM[4:0] allows the user to select a different shaping

filter mode for good quality composite (CVBS), component
(YPrPb), and S-VHS (Y/C) input signals.

In automatic mode, the system preserves the maximum
possible bandwidth for good CVBS sources (because they can
be successfully combed) as well as for luma components of
YPrPb and Y/C sources (because they need not be combed).
For poor quality signals, the system selects from a set of
proprietary shaping filter responses that complements comb
filter operation in order to reduce visual artifacts.

The decisions of the control logic are shown in

Figure 18.

YSFM[4:0], Y Shaping Filter Mode, Address 0x17 [4:0]

The Y shaping filter mode bits allow the user to select from a
wide range of low-pass and notch filters. When switched in
automatic mode, the filter selection is based on other register
selections, such as detected video standard, as well as properties
extracted from the incoming video itself, such as quality and
time base stability. The automatic selection always selects the
widest possible bandwidth for the video input encountered.

• If the YSFM settings specify a filter (that is, YSFM is set to

values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.

• In automatic selection mode, the notch filters are only used

for bad quality video signals. For all other video signals,
wideband filters are used.

WYSFMOVR, Wideband Y Shaping Filter Override,
Address 0x18 [7]

Setting the WYSFMOVR bit enables the use of the
WYSFM[4:0] settings for good quality video signals. For more
information, refer to the general discussion of the luma shaping
filters in the
in

Figure 18.

Y Shaping Filter section and the flowchart shown

When WYSFMOVR is 0, the shaping filter for good quality
video signals is selected automatically.

Setting WYSFMOVR to 1 (default) enables manual override via
WYSFM[4:0].

SET YSFM

YSFM IN AUTO MODE?

00000 OR 00001

WYSFMOVR

SELECT AUTOMATIC

WIDEBAND FILTER

USE YSFM SELECTED

FILTER REGARDLESS O F

VIDEO QUAL ITY

05700-018

VIDEO

BAD GOOD

AUTO SELECT LUMA
SHAPING FILTER TO

COMPLEME NT COMB

QUALITY

1 0

SELECT WIDEBAND

FILTER AS PER

WYSFM[ 4:0]

Figure 18. YSFM and WYSFM Control Flowchart

YES NO

Rev. A | Page 29 of 112

ADV7180

A

Table 31. YSFM Function

YSFM[4:0] Description

0'0000

Automatic selection including a wide-notch
response (PAL/NTSC/SECAM)

0'0001
(default)

Automatic selection including a narrow-notch

response (PAL/NTSC/SECAM)
0'0010 SVHS 1
0'0011 SVHS 2
0'0100 SVHS 3
0'0101 SVHS 4
0'0110 SVHS 5
0'0111 SVHS 6
0'1000 SVHS 7
0'1001 SVHS 8
0'1010 SVHS 9
0'1011 SVHS 10
0'1100 SVHS 11
0'1101 SVHS 12
0'1110 SVHS 13
0'1111 SVHS 14
1'0000 SVHS 15
1'0001 SVHS 16
1'0010 SVHS 17
1'0011 SVHS 18 (CCIR 601)
1'0100 PAL NN1
1'0101 PAL NN2
1'0110 PAL NN3
1'0111 PAL WN1
1'1000 PAL WN2
1'1001 NTSC NN1
1'1010 NTSC NN2
1'1011 NTSC NN3
1'1100 NTSC WN1
1'1101 NTSC WN2
1'1110 NTSC WN3
1'1111 Reserved

WYSFM[4:0], Wideband Y Shaping Filter Mode,
Address 0x18 [4:0]

The WYSFM[4:0] bits allow the user to manually select a
shaping filter for good quality video signals, for example, CVBS
with stable time base, luma component of YPrPb, and luma
component of Y/C. The WYSFM bits are only active if the
WYSFMOVR bit is set to 1. See the general discussion of the
shaping filter settings in the

Y Shaping Filter section.

Table 32. WYSFM Function

WYSFM[4:0] Description

0'0000 Do not use
0'0001 Do not use
0'0010 SVHS 1
0'0011 SVHS 2
0'0100 SVHS 3
0'0101 SVHS 4
0'0110 SVHS 5
0'0111 SVHS 6
0'1000 SVHS 7
0'1001 SVHS 8
0'1010 SVHS 9
0'1011 SVHS 10
0'1100 SVHS 11
0'1101 SVHS 12
0'1110 SVHS 13
0'1111 SVHS 14
1'0000 SVHS 15
1'0001 SVHS 16
1'0010 SVHS 17
1'0011 (default) SVHS 18 (CCIR 601)
1'0100 to 1’1111 Do not use

The filter plots in
S-VHS 18 (widest) shaping filter settings.

Figure 19 show the S-VHS 1 (narrowest) to

Figure 21 shows the
PAL notch filter responses. The NTSC-compatible notches are
shown in

Figure 22.

COMBINED Y

0

–10

–20

–30

–40

AMPLITUDE ( dB)

–50

–60

–70

0186421

Figure 19. Y S-VHS Combined Responses

NTIALIAS, S-VHS LOW-PASS FILTERS,

Y RESAMPLE

FREQUENCY (MHz)

02

05700-019

Rev. A | Page 30 of 112

ADV7180

A

CHROMA FILTER

Data from the digital fine clamp block is processed by three sets
of filters. Note that the data format at this point is CVBS for
CVBS inputs, chroma only for Y/C, or U/V interleaved for
YPrPb input formats.

• Chroma Antialias Filter (CAA).

The ADV7180 oversamples the CVBS by a factor of 4 and
the chroma/YPrPb by a factor of 2. A decimating filter (CAA)
is used to preserve the active video band and to remove any
out-of-band components. The CAA filter has a fixed response.

COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,

0

YRESAMPLE

• Chroma Shaping Filters (CSH).

The shaping filter block (CSH) can be programmed to
perform a variety of low-pass responses. It can be used to
selectively reduce the bandwidth of the chroma signal for
scaling or compression.

• Digital Resampling Filter.

This block allows dynamic resampling of the video signal
to alter parameters such as the time base of a line of video.
Fundamentally, the resampler is a set of low-pass filters.
The actual response is chosen by the system without user
intervention.

Figure 23 shows the overall response of all filters together.

COMBINED Y ANTIALIAS, NTSC NOTCH FIL TERS,

0

Y RESAMPLE

–20

–40

–60

AMPLI TUDE (d B)

–80

–100

–120

0186421

FREQUENCY (MHz)

02

Figure 20. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)

COMBINED Y ANTIALIAS, PAL NO TCH FIL TERS,

0

–10

–20

–30

–40

AMPLI TUDE (d B)

–50

–60

–70

0186421

Figure 21. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)

Y RESAMPLE

02

FREQUENCY (MHz)

–10

–20

–30

–40

AMPLITUDE ( dB)

–50

–60

05700-020

–70

0186421

FREQUENCY (MHz)

02

05700-022

Figure 22. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)

COMBINED C ANT IALIAS, C SH

0

–10

–20

–30

–40

ATTENUATION (dB)

–50

05700-021

–60

0543216

C RESAMPLER

FREQUENCY (MHz)

Figure 23. Chroma Shaping Filter Responses

PING FILTER,

05700-023

Rev. A | Page 31 of 112

ADV7180

ANA

O

ANA

CSFM[2:0], C Shaping Filter Mode, Address 0x17 [7:5]

The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see Settings 000
and 001 in Tabl e 33 ).

Table 33. CSFM Function

CSFM[2:0] Description

000 (default) Autoselect 1.5 MHz bandwidth
001 Autoselect 2.17 MHz bandwidth
010 SH1
011 SH2
100 SH3
101 SH4
110 SH5
111 Wideband mode

Figure 23 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (shown in red).

GAIN OPERATION

The gain control within the ADV7180 is done on a purely
digital basis. The input ADC supports a 10-bit range mapped
into a 1.0 V analog voltage range. Gain correction takes place
after the digitization in the form of a digital multiplier.

Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADC include
the fact that the gain is now completely independent of supply,
temperature, and process variations.

As shown in
as long as it fits into the ADC window. The components to this
are the amplitude of the input signal and the dc level it resides
on. The dc level is set by the clamping circuitry (see the
Operation

If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.

Figure 24 shows a typical voltage divider network that is
required to keep the input video signal within the allowed range

Figure 25, the ADV7180 can decode a video signal

Clamp

section).

MAXIMUM
VOLTAGE

RANGE SUPPO RTED BY ADC (1V RANGE F OR ADV7180)

LOGVOLTAGE

of the ADC, 0 V to 1 V. This circuit should be placed before all
analog inputs to the ADV7180.

LOGVIDE

INPUT

36

Figure 24. Input Voltage Divider Network

39

100nF

AIN_OF_ADV7180

05700-024

The minimum supported amplitude of the input video is
determined by the ability of the ADV7180 to retrieve horizontal
and vertical timing and to lock to the color burst, if present.

There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.

The possible AGC modes are shown in

Tabl e 34 .

Table 34. AGC Modes

Input
Video Type Luma Gain

Chroma Gain

Any Manual gain luma Manual gain chroma
CVBS

Dependent on
horizontal sync depth

Dependent on color­burst amplitude
taken from luma path

Peak white

Dependent on color­burst amplitude
taken from luma path

Y/C

Dependent on
horizontal sync depth

Dependent on color­burst amplitude
taken from luma path

Peak white

Dependent on color­burst amplitude

YPrPb

Dependent on

Taken from luma path

horizontal sync depth

It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating and the AGC determined gain
at the time of the freeze to stay active until the loop is either
unfrozen or the gain mode of operation is changed.

The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the
Luma Gain and Chroma Gain sections.

MINIMUM
VOLTAGE

CLAMP

LEVEL

ADC

Figure 25. Gain Control Overview

Rev. A | Page 32 of 112

DATA PRE-

PROCESSOR

(DPP)

VIDEO PROCESSOR

(GAIN SELECTION ONLY)

GAIN

CONTROL

05700-025

ADV7180

≤

≤

≤

Luma Gain

LAGC[2:0], Luma Automatic Gain Control,
Address 0x2C [6:4]

The luma automatic gain control mode bits select the operating
mode for the gain control in the luma path.

There are internal parameters (Analog Devices proprietary
algorithms) to customize the peak white gain control. Contact
local Analog Devices field applications engineers or local
Analog Devices distributor for more information.

Table 35. LAGC Function

LAGC[2:0] Description

000 Manual fixed gain (use LMG[11:0])
001 Reserved
010 (default)

011 Reserved
100

101 Reserved
110 Reserved
111 Freeze gain

AGC (blank level to sync tip), peak white
algorithm on

AGC (blank level to sync tip), peak white
algorithm off

LAGT[1:0], Luma Automatic Gain Timing,
Address 0x2F [7:6]

The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. Note that this register only has an effect if the
LAGC[2:0] register is set to 001, 010, 011, or 100 (automatic
gain control modes).

If peak white AGC is enabled and active (see the
Address 0x10 [7:0]

section), the actual gain update speed is

STATUS_1[7:0],

dictated by the peak white AGC loop and, as a result, the LAGT
settings have no effect. As soon as the part leaves peak white
AGC, LAGT becomes relevant again.

The update speed for the peak white algorithm can be
customized by the use of internal parameters. Contact Analog
Devices local field engineers for more information.

Table 36. LAGT Function

LAGT[1:0] Description

00 Slow (TC = 2 sec)
01 Medium (TC = 1 sec)
10 Fast (TC = 0.2 sec)
11 (default) Adaptive

LG[11:0], Luma Gain, Address 0x2F [3:0],
Address 0x30 [7:0]; LMG[11:0], Luma Manual Gain,
Address 0x2F [3:0], Address 0x30 [7:0]

Luma gain [11:0] is a dual-function register. If all of these
registers are written to, a desired manual luma gain can be
programmed. This gain becomes active if the LAGC[2:0] mode
is switched to manual fixed gain. Equation 1 shows how to
calculate a desired gain.

If read back, this register returns the current gain value.
Depending on the setting in the LAGC[2:0] bits, the value is
one of the following:

• Luma manual gain value (LAGC[2:0] set to luma manual

gain mode)

• Luma automatic gain value (LAGC[2:0] set to any of the

automatic modes)

Table 37. LG/LMG Function

LG[11:0]/LMG[11:0] Read/Write Description

LMG[11:0] = X Write

LG[11:0] Read Actual used gain

525iGainLuma

)( K≅

<≅LMG

Manual gain for luma
path

)4095]0:11[1024(

1410

)( K≅

NTSCGainLuma

iPALGainLuma

<≅LMG

1470

)625/(

<≅LMG

1535

66.266.0

K≅

)4095]0:11[1024(

)4095]0:11[1024(

(1)

For example, with a 525i input applied, program the ADV7180
into manual fixed gain mode with a desired gain of 0.89 as
follows:

1.

Use Equation 1 to convert the gain:

0.89 × 1410 = 1254.9

2.

Truncate to integer value:

= 1255d

3.

Convert to hexadecimal:

1255d = 0x04E7

4. Split into two registers and program:

Luma Gain Control 1 [3:0] = 0x4
Luma Gain Control 2 [7:0] = 0xE7

Enable manual fixed gain mode:

5.
Set LAGC[2:0] to 000

9.272.0

78.27.0

Rev. A | Page 33 of 112

ADV7180

BETACAM, Enable Betacam Levels, Address 0x01 [5]

If YPrPb data is routed through the ADV7180, the automatic
gain control modes can target different video input levels, as
outlined in

Tabl e 40 . Note that the BETACAM bit is valid only if
the input mode is YPrPb (component). The BETACAM bit sets
the target value for AGC operation.

A review of the following sections is useful:

•

MAN_MUX_EN, Manual Input Muxing Enable,

Address 0xC4 [7]

for how component video (YPrPb)

can be routed through the ADV7180.

•

Video Standard Selection to select the various standards,

for example, with and without pedestal.

The automatic gain control (AGC) algorithms adjust the levels
based on the setting of the BETACAM bit (see

Tabl e 38 ).

Table 38. BETACAM Function

BETACAM Description

0 (default) Assuming YPrPb is selected as input format
Selecting PAL with pedestal selects MII
Selecting PAL without pedestal selects SMPTE
Selecting NTSC with pedestal selects MII
Selecting NTSC without pedestal selects SMPTE
1 Assuming YPrPb is selected as input format
Selecting PAL with pedestal selects BETACAM
Selecting PAL without pedestal selects BETACAM variant
Selecting NTSC with pedestal selects BETACAM
Selecting NTSC without pedestal selects BETACAM variant

PW_UPD, Peak White Update, Address 0x2B [0]

The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0]
must be set to the appropriate mode to enable the peak white or
average video mode in the first place. For more information,
refer to the
Address 0x2C [6:4]

LAGC[2:0], Luma Automatic Gain Control,

section.

Setting PW_UPD to 0 updates the gain once per video line.

Setting PW_UPD to 1 (default) updates the gain once per field.

Chroma Gain

CAGC[1:0], Chroma Automatic Gain Control,
Address 0x2C [1:0]

The two bits of color automatic gain control mode select the
basic mode of operation for automatic gain control in the
chroma path.

Table 39. CAGC Function

CAGC[1:0] Description

00 Manual fixed gain (use CMG[11:0])
01 Use luma gain for chroma
10 (default) Automatic gain (based on color burst)
11 Freeze chroma gain

Table 40. Betacam Levels

Name Betacam (mV) Betacam Variant (mV) SMPTE (mV) MII (mV)

Y 0 to 714 (incl. 7.5% pedestal) 0 to 714 0 to 700 0 to 700 (incl. 7.5% pedestal)
Pb and Pr –467 to +467 –505 to +505 –350 to +350 –324 to +324
Sync Depth 286 286 300 300

Rev. A | Page 34 of 112

ADV7180

CAGT[1:0], Chroma Automatic Gain Timing,
Address 0x2D [7:6]

The chroma automatic gain timing register allows the user to
influence the tracking speed of the chroma automatic gain
control. This register has an effect only if the CAGC[1:0]
register is set to 10 (automatic gain).

Table 41. CAGT Function

CAGT[1:0] Description

00 Slow (TC = 2 sec)
01 Medium (TC = 1 sec)
10 Fast (TC = 0.2 sec)
11 (default) Adaptive

CG[11:0], Chroma Gain, Address 0x2D [3:0],
Address 0x2E [7:0]; CMG[11:0], Chroma Manual Gain,
Address 0x2D [3:0], Address 0x2E [7:0]

Chroma gain [11:0] is a dual-function register. If written to, a
desired manual chroma gain can be programmed. This gain
becomes active if the CAGC[1:0] mode is switched to manual
fixed gain. Refer to Equation 2 for calculating a desired gain.

If read back, this register returns the current gain value.
Depending on the setting in the CAGC[1:0] bits, this is either:

•

The chroma manual gain value (CAGC[1:0] set to chroma

manual gain mode).

The chroma automatic gain value (CAGC[1:0] set to any of

•

the automatic modes).

Table 42. CG/CMG Function

CG[11:0]/CMG[11:0] Read/Write Description

CMG[11:0] Write

CG[11:0] Read Currently active gain

Chroma_Gain

≅

650

Manual gain for chroma
path

)40950( CG

≤<

≅

0 . . . 6.29 (2)

For example, freezing the automatic gain loop and reading back
the CG[11:0] register results in a value of 0x47A as follows:

Convert the readback value to decimal:

1.
0x47A = 1146d

2.

Apply Equation 2 to convert the readback value:

1146/1024 = 1.12

CKE, Color Kill Enable, Address 0x2B [6]

The color kill enable bit allows the optional color kill function
to be switched on or off.

For QAM-based video standards (PAL and NTSC) as well as
FM-based systems (SECAM), the threshold for the color kill
decision is selectable via the CKILLTHR[2:0] bits.

If color kill is enabled and the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
lines with a color burst greater than the threshold are required.

The color kill option only works for input signals with a
modulated chroma part. For component input (YPrPb), there is
no color kill.

Setting CKE to 0 disables color kill.

Setting CKE to 1 (default) enables color kill.

CKILLTHR[2:0], Color Kill Threshold, Address 0x3D
[6:4]

The CKILLTHR[2:0] bits allow the user to select a threshold for
the color kill function. The threshold applies to only QAM­based (NTSC and PAL) or FM-modulated (SECAM) video
standards.

To enable the color kill function, the CKE bit must be set. For
Settings 000, 001, 010, and 011, chroma demodulation inside
the ADV7180 may not work satisfactorily for poor input video
signals.

Table 43. CKILLTHR Function

CKILLTHR[2:0] SECAM NTSC, PAL
000 No color kill Kill at <0.5%
001 Kill at <5% Kill at <1.5%
010 Kill at <7% Kill at <2.5%
011 (default) Kill at <8% Kill at <4.0%
100 Kill at <9.5% Kill at <8.5%
101 Kill at <15% Kill at <16.0%
110 Kill at <32% Kill at <32.0%
111

Reserved for Analog Devices internal use only.
Do not select.

Description

Rev. A | Page 35 of 112

ADV7180

CHROMA TRANSIENT IMPROVEMENT (CTI)

The signal bandwidth allocated for chroma is typically much
smaller than that of luminance. In the past, this was a valid way
to fit a color video signal into a given overall bandwidth because
the human eye is less sensitive to chrominance than to luminance.

The uneven bandwidth, however, may lead to visual artifacts in
sharp color transitions. At the border of two bars of color, both
components (luma and chroma) change at the same time (see
Figure 26). Due to the higher bandwidth, the signal transition
of the luma component is usually much sharper than that of the
chroma component. The color edge is not sharp and can be
blurred, in the worst case, over several pixels.

LUMA SIGNAL WITH A

LUMA SIGNAL

DEMODULATED

CHROMA SIGNAL

Figure 26. CTI Luma/Chroma Transition

TRANSITIO N, ACCOMPANIED
BY A CHROMA T RANSITION

ORIGINAL, SLOW CHROMA
TRANSITION PRIOR TO CTI

SHARPENED CHROMA
TRANSITION AT THE
OUTPUT OF CTI

The chroma transient improvement block examines the input
video data. It detects transitions of chroma and can be
programmed to create steeper chroma edges in an attempt to
artificially restore lost color bandwidth. The CTI block,
however, operates only on edges above a certain threshold to
ensure that noise is not emphasized. Care has also been taken to
ensure that edge ringing and undesirable saturation or hue
distortion are avoided.

Chroma transient improvements are needed primarily for
signals that have severe chroma bandwidth limitations. For
those types of signals, it is strongly recommended to enable the
CTI block via CTI_EN.

CTI_EN, Chroma Transient Improvement Enable,
Address 0x4D [0]

Setting CTI_EN to 0 disables the CTI block.

Setting CTI_EN to 1 (default) enables the CTI block.

05700-026

CTI_AB_EN, Chroma Transient Improvement
Alpha Blend Enable, Address 0x4D [1]

The CTI_AB_EN bit enables an alpha blend function within the
CTI block. If set to 1, the alpha blender mixes the transient
improved chroma with the original signal. The sharpness of the
alpha blending can be configured via the CTI_AB[1:0] bits.

For the alpha blender to be active, the CTI block must be
enabled via the CTI_EN bit.

Setting CTI_AB_EN to 0 disables the CTI alpha blender.

Setting CTI_AB_EN to 1 (default) enables the CTI alpha-blend
mixing function.

CTI_AB[1:0], Chroma Transient Improvement Alpha
Blend, Address 0x4D [3:2]

The CTI_AB[1:0] controls the behavior of alpha blend circuitry
that mixes the sharpened chroma signal with the original one. It
thereby controls the visual impact of CTI on the output data.

For CTI_AB[1:0] to become active, the CTI block must be
enabled via the CTI_EN bit and the alpha blender must be
switched on via CTI_AB_EN.

Sharp blending maximizes the effect of CTI on the picture, but
may also increase the visual impact of small amplitude, high
frequency chroma noise.

Table 44. CTI_AB Function

CTI_AB[1:0] Description

00

01 Sharp mixing
10 Smooth mixing
11 (default) Smoothest alpha blend function

Sharpest mixing between sharpened and original
chroma signal

CTI_C_TH[7:0], CTI Chroma Threshold,
Address 0x4E [7:0]

The CTI_C_TH[7:0] value is an unsigned, 8-bit number speci­fying how big the amplitude step in a chroma transition has to
be in order to be steepened by the CTI block. Programming a
small value into this register causes even smaller edges to be
steepened by the CTI block. Making CTI_C_TH[7:0] a large
value causes the block to improve large transitions only.

The default value for CTI_C_TH[7:0] is 0x08, indicating the
threshold for the chroma edges prior to CTI.

Rev. A | Page 36 of 112

ADV7180

T

AK

R

DIGITAL NOISE REDUCTION (DNR) AND LUMA
PEAKING FILTER

Digital noise reduction is based on the assumption that high
frequency signals with low amplitude are probably noise and
that their removal, therefore, improves picture quality. There are
two DNR blocks in the ADV7180: the DNR1 block before the
luma peaking filter and the DNR2 block after the luma peaking
filter, as shown in

Figure 27.

PEAKING_GAIN[7:0], Luma Peaking Gain,
Address 0xFB [7:0]

This filter can be manually enabled. The user can select to boost
or attenuate the mid region of the Y spectrum around 3 MHz.
The peaking filter can visually improve the picture by showing
more definition on the picture details that contain frequency
components around 3 MHz. The default value on this register
passes through the luma data unaltered. A lower value
attenuates the signal, and a higher value gains the luma signal.
A plot of the filter’s responses is shown in

Figure 28.

LUMA

SIGNAL

DNR1

Figure 27. DNR and Peaking Block Diagram

LUMA PEAKING

FILTER

DNR2

LUMA
OUTPU

05700-051

DNR_EN, Digital Noise Reduction Enable,
Address 0x4D [5]

The DNR_EN bit enables the DNR block or bypasses it.

Table 45. DNR_EN Function

Setting Description

0 Bypasses DNR (disable)
1 (Default) Enables digital noise reduction on the luma data

DNR_TH[7:0], DNR Noise Threshold, Address 0x50 [7:0]

The DNR1 block is positioned before the luma peaking block.
The DNR_TH[7:0] value is an unsigned, 8-bit number used to
determine the maximum edge that is interpreted as noise and
therefore blanked from the luma data. Programming a large
value into DNR_TH[7:0] causes the DNR block to interpret
even large transients as noise and remove them. As a result, the
effect on the video data is more visible. Programming a small
value causes only small transients to be seen as noise and to be
removed.

Table 46. DNR_TH[7:0] Function

Setting Description

0x08 (Default)

Threshold for maximum luma edges to be
interpreted as noise

Table 47. PEAKING_GAIN[7:0] Function

Setting Description

0x40 (Default) 0 dB response

15

10

5

0

–5

–10

FILTER RESPONSE (dB)

–15

–20

0

PE

123456

Figure 28. Peaking Filter Responses

ING GAIN USING BP FILTE

FREQUENCY (MHz)

05700-052

7

DNR_TH2[7:0], DNR Noise Threshold 2,
Address 0xFC [7:0]

The DNR2 block is positioned after the luma peaking block
and, therefore, affects the gained luma signal. It operates in the
same way as the DNR1 block, but there is an independent
threshold control, DNR_TH2[7:0], for this block. This value is
an unsigned, 8-bit number used to determine the maximum
edge that is interpreted as noise and therefore blanked from the
luma data. Programming a large value into DNR_TH2[7:0]
causes the DNR block to interpret even large transients as noise
and remove them. As a result, the effect on the video data is
more visible. Programming a small value causes only small
transients to be seen as noise and to be removed.

Table 48. DNR_TH2[7:0] Function

Setting Description

0x04 (Default)

Threshold for maximum luma edges to be
interpreted as noise

Rev. A | Page 37 of 112

ADV7180

COMB FILTERS

The comb filters of the ADV7180 have been greatly improved to
automatically handle video of all types, standards, and levels of
quality. The NTSC and PAL configuration registers allow the
user to customize comb filter operation, depending on which
video standard is detected (by autodetection) or selected (by
manual programming). In addition to the bits listed in this
section, there are some further internal controls (based on
Analog Devices proprietary algorithms); contact local Analog
Devices field engineers for more information.

CTAPSN[1:0] Chroma Comb Taps NTSC, Address 0x38 [7:6]

Table 50. CTAPSN Function

CTAPSN[1:0] Description

00 Do not use
01 NTSC chroma comb adapts three lines (three taps) to two lines (two taps)
10 (default) NTSC chroma comb adapts five lines (five taps) to three lines (three taps)
11 NTSC chroma comb adapts five lines (five taps) to four lines (four taps)

CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38 [5:3]

NTSC Comb Filter Settings

Used for NTSC M/J CVBS inputs.

NSFSEL[1:0], Split Filter Selection NTSC, Address 0x19
[3:2]

The NSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A narrow split filter selection
results in better performance on diagonal lines, but more dot
crawl in the final output image. The opposite is true for selecting
a wide bandwidth split filter.

Table 49. NSFSEL Function

NSFSEL[1:0] Description

00 (default) Narrow
01 Medium
10 Medium
11 Wide

Table 51. CCMN Function

CCMN[2:0] Description Configuration
0xx (default) Adaptive comb mode

100 Disable chroma comb
101 Fixed chroma comb (top lines of line memory)

110 Fixed chroma comb (all lines of line memory)

111 Fixed chroma comb (bottom lines of line memory)

Adaptive 3-line chroma comb for CTAPSN = 01
Adaptive 4-line chroma comb for CTAPSN = 10
Adaptive 5-line chroma comb for CTAPSN = 11

Fixed 2-line chroma comb for CTAPSN = 01
Fixed 3-line chroma comb for CTAPSN = 10
Fixed 4-line chroma comb for CTAPSN = 11
Fixed 3-line chroma comb for CTAPSN = 01
Fixed 4-line chroma comb for CTAPSN = 10
Fixed 5-line chroma comb for CTAPSN = 11
Fixed 2-line chroma comb for CTAPSN = 01
Fixed 3-line chroma comb for CTAPSN = 10
Fixed 4-line chroma comb for CTAPSN = 11

Rev. A | Page 38 of 112

ADV7180

YCMN[2:0], Luma Comb Mode NTSC, Address 0x38 [2:0]

CCMP[2:0], Chroma Comb Mode PAL, Address 0x39 [5:3]

Table 52. YCMN Function

YCMN[2:0] Description Configuration

0xx
(default)

100 Disable luma comb

101

110

111

Adaptive comb mode

Fixed luma comb (top
lines of line memory)

Fixed luma comb (all
lines of line memory)

Fixed luma comb
(bottom lines of line
memory)

Adaptive 3-line (three
taps) luma comb

Use low-pass/notch
filter; see the
Filter

section

Fixed 2-line (two taps)
luma comb

Fixed 3-line (three taps)
luma comb

Fixed 2-line (two taps)
luma comb

Y Shaping

PAL Comb Filter Settings

Use d fo r PAL B/G / H /I/D, PAL M , PA L Combi n a t i on al N,
PAL 60, and NTSC 4.43 CVBS inputs.

PSFSEL[1:0], Split Filter Selection PAL, Address 0x19 [1:0]

The PSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A wide split filter selection
eliminates dot crawl, but shows imperfections on diagonal lines.
The opposite is true for selecting a narrow bandwidth split filter.

Table 53. PSFSEL Function

PSFSEL[1:0] Description

00 Narrow
01 (default) Medium
10 Wide
11 Widest

CTAPSP[1:0], Chroma Comb Taps PAL, Address 0x39 [7:6]

Table 54. CTAPSP Function

CTAPSP[1:0] Description

00 Do not use
01

10

11 (default)

PAL chroma comb adapts five lines (three taps)
to three lines (two taps); cancels cross luma only

PAL chroma comb adapts five lines (five taps) to
three lines (three taps); cancels cross luma and
hue error less well

PAL chroma comb adapts five lines (five taps) to
four lines (four taps); cancels cross luma and hue
error well

Table 55. CCMP Function

CCMP[2:0] Description Configuration

0xx
(default)

100

101

110

111

Adaptive comb
mode

Disable chroma
comb

Fixed chroma comb
(top lines of line
memory)

Fixed chroma comb
(all lines of line
memory)

Fixed chroma comb
(bottom lines of line
memory)

Adaptive 3-line chroma
comb for CTAPSP = 01

Adaptive 4-line chroma
comb for CTAPSP = 10

Adaptive 5-line chroma
comb for CTAPSP = 11

Fixed 2-line chroma
comb for CTAPSP = 01

Fixed 3-line chroma
comb for CTAPSP = 10

Fixed 4-line chroma
comb for CTAPSP = 11

Fixed 3-line chroma
comb for CTAPSP = 01

Fixed 4-line chroma
comb for CTAPSP = 10

Fixed 5-line chroma
comb for CTAPSP = 11

Fixed 2-line chroma
comb for CTAPSP = 01

Fixed 3-line chroma
comb for CTAPSP = 10

Fixed 4-line chroma
comb for CTAPSP = 11

YCMP[2:0], Luma Comb Mode PAL, Address 0x39 [2:0]

Table 56. YCMP Function

YCMP[2:0] Description Configuration

0xx
(default)

100 Disable luma comb

101

110

111

Adaptive comb mode

Fixed luma comb
(top lines of line
memory)

Fixed luma comb
(all lines of line
memory)

Fixed luma comb
(bottom lines of line
memory)

Adaptive five lines (three
taps) luma comb

Use low-pass/notch filter;

Y Shaping Filter

see the
section.

Fixed three lines (two taps)
luma comb

Fixed five lines (three taps)
luma comb

Fixed three lines (two taps)
luma comb

Rev. A | Page 39 of 112

ADV7180

C

C

IF FILTER COMPENSATION

IFFILTSEL[2:0], IF Filter Select, Address 0xF8 [2:0]

The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input, as would be
observed on tuner outputs.
filter compensation for NTSC and PAL, respectively.

The options for this feature are as follows:

• Bypass mode

NTSC—consists of three filter characteristics

•

PAL—consists of three filter characteristics

•

Table 103 for programming details.

See

Figure 29 and Figure 30 show IF

IF COMP FILTERS NTSC ZOOMED AROUND FS

6

4

2

0

–2

–4

AMPLITUDE (dB)

–6

–8

–10

–12

2.0 5. 0

2.53.03.54.04.5
FREQUENCY (MHz)

Figure 29. NTSC IF Filter Compensation

6

4

2

0

–2

AMPLITUDE (dB)

–4

IF COMP FILTERS PAL ZOOMED AROUND FS

05700-053

–6

–8

3.0 6. 0

3.54.04.55.05.5
FREQUENCY (MHz)

Figure 30. PAL IF Filter Compensation

05700-054

Rev. A | Page 40 of 112

ADV7180

C

V

A

V

AV CODE INSERTION AND CONTROLS

This section describes the I2C-based controls that affect

Insertion of AV codes into the data stream

•

Data blanking during the vertical blank interval (VBI)

•

The range of data values permitted in the output data

•

stream

The relative delay of luma vs. chroma signals

•

Note that some of the decoded VBI data is inserted during the
horizontal blanking interval. See the

Gemstar Data Recovery

section for more information.

BT.656-4, ITU-R BT.656-4 Enable, Address 0x04 [7]

Between Revision 3 and Revision 4 of the ITU-R BT.656 standards,
the ITU has changed the toggling position for the V bit within
the SAV EAV codes for NTSC. The ITU-R BT.656-4 standard
bit allows the user to select an output mode that is compliant
with either the previous or new standard. For further information,
visit the International Telecommunication Union’s website.

Note that the standard change only affects NTSC and has no
bearing on PAL.

When ITU-R BT.656-4 is 0 (default), the ITU-R BT.656-3
specification is used. The V bit goes low at EAV of Line 10
and Line 273.

When ITU-R BT.656-4 is 1, the ITU-R BT.656-4 specification is
used. The V bit goes low at EAV of Line 20 and Line 283.

SD_DUP_AV, Duplicate AV Codes, Address 0x03 [0]

Depending on the output interface width, it may be necessary to
duplicate the AV codes from the luma path into the chroma path.

In an 8-bit-wide output interface (Cb/Y/Cr/Y interleaved data),
the AV codes are defined as FF/00/00/AV, with AV being the
transmitted word that contains information about H/V/F.

SD_DUP_A

YDATABUS 00 AV YFF 00 00 AV Y

r/Cb D ATA BUS 00 00 AV Cb FF 00 Cb

FF

AV CODE SECTION AV CODE SECTION

=1 SD_DUP_

Figure 31. AV Code Duplication Control (ADV7180 LQFP-64 Only)

In this output interface mode, the following assignment takes
place: Cb = FF, Y = 00, Cr = 00, and Y = AV.

In a 16-bit output interface (ADV7180 LQFP-64 only) where Y
and Cr/Cb are delivered via separate data buses, the AV code is
spread over the whole 16 bits. The SD_DUP_AV bit allows the
user to replicate the AV codes on both buses, so the full AV
sequence can be found on the Y bus as well as on the Cr/Cb bus
(see

Figure 31).

When SD_DUP_AV is 0 (default), the AV codes are in single
fashion (to suit 8-bit interleaved data output).

When SD_DUP_AV is 1, the AV codes are duplicated (for
16-bit interfaces).

VBI_EN, Vertical Blanking Interval Data Enable,
Address 0x03 [7]

The VBI enable bit allows data such as intercast and closed
caption data to be passed through the luma channel of the
decoder with a minimal amount of filtering. All data for Line 1
to Line 21 is passed through and available at the output port.
The ADV7180 does not blank the luma data and automatically
switches all filters along the luma data path into their widest
bandwidth. For active video, the filter settings for YSH and YPK
are restored.

See the

BL_C_VBI, Blank Chroma During VBI, Address 0x04

[2]

section for information on the chroma path.

When VBI_EN is 0 (default), all video lines are filtered/scaled.

When VBI_EN is 1, only the active video region is
filtered/scaled.

=0

8-BIT INT ERFACE16-BIT INTERFACE16-BIT INTERFACE

Cb/Y/Cr/Y

INTERLEAVED

FF 00 00 AV Cb

AV CODE SECTI ON

5700-027

Rev. A | Page 41 of 112

ADV7180

BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2]

Setting BL_C_VBI high, blanks the Cr and Cb values of all VBI
lines. This is done so any data that may arrive during VBI is not
decoded as color and is output through Cr and Cb. As a result,
it is possible to send VBI lines into the decoder, and then output
them through an encoder again, undistorted. Without this
blanking, any color that is incorrectly decoded would be
encoded by the video encoder, thus distorting the VBI lines.

Setting BL_C_VBI to 0 decodes and outputs color during VBI.

Setting BL_C_VBI to 1 (default) blanks Cr and Cb values
during VBI.

RANGE, Range Selection, Address 0x04 [0]

AV codes (as per ITU-R BT.656, formerly known as CCIR-656)
consist of a fixed header made up of 0xFF and 0x00 values.
These two values are reserved and therefore are not to be used
for active video. Additionally, the ITU specifies that the
nominal range for video should be restricted to values between
16 to 235 for luma and 16 to 240 for chroma.

The RANGE bit allows the user to limit the range of values
output by the ADV7180 to the recommended value range. In
any case, it ensures that the reserved values of 255d (0xFF) and
00d (0x00) are not presented on the output pins unless they are
part of an AV code header.

Table 57. RANGE Function

RANGE Description

0 16 ≤ Y ≤ 235 16 ≤ C/P ≤ 240
1 (default) 1 ≤ Y ≤ 254 1 ≤ C/P ≤ 254

AUTO_PDC_EN, Automatic Programmed Delay Control,
Address 0x27 [6]

Enabling AUTO_PDC_EN activates a function within the
ADV7180 that automatically programs the LTA[1:0] and
CTA[2:0] to have the chroma and luma data match delays for
all modes of operation. If set, manual registers LTA[1:0] and
CTA[2:0] are not used. If the automatic mode is disabled (by
setting the AUTO_PDC_EN bit to 0), the values programmed
into LTA[1:0] and CTA[2:0] registers become active.

When AUTO_PDC_EN is 0, the ADV7180 uses the LTA[1:0] and
CTA[2:0] values for delaying luma and chroma samples. Refer to
the

LTA[1:0], Luma Timing Adjust, Address 0x27 [1:0] section

and the

CTA[2:0], Chroma Timing Adjust, Address 0x27 [5:3]

section.

When AUTO_PDC_EN is 1 (default), the ADV7180 automati­cally determines the LTA and CTA values to have luma and
chroma aligned at the output.

LTA[1:0], Luma Timing Adjust, Address 0x27 [1:0]

The luma timing adjust register allows the user to specify a
timing difference between chroma and luma samples.

Note that there is a certain functionality overlap with the
CTA[2:0] register. For manual programming, use the
following defaults:

CVBS input LTA[1:0] = 00

•

Y/C input LTA[1:0] = 01

•

• YPrPb input LTA[1:0] = 01

Table 58. LTA Function

LTA[1:0] Description

00 (default) No delay
01 Luma 1 clock (37 ns) late
10 Luma 2 clock (74 ns) early
11 Luma 1 clock (37 ns) early

CTA[2:0], Chroma Timing Adjust, Address 0x27 [5:3]

The chroma timing adjust register allows the user to specify a
timing difference between chroma and luma samples. This may
be used to compensate for external filter group delay differences
in the luma vs. chroma path and to allow a different number of
pipeline delays while processing the video downstream. Review
this functionality together with the LTA[1:0] register.

The chroma can be delayed or advanced only in chroma pixel
steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, where one can
no longer delay by luma pixel steps.

For manual programming, use the following defaults:

•

CVBS input CTA[2:0] = 011

Y/C input CTA[2:0] = 101

•

YPrPb input CTA[2:0] = 110

•

Table 59. CTA Function

CTA[2:0] Description

000 Not used
001 Chroma + 2 chroma pixel (early)
010 Chroma + 1 chroma pixel (early)
011 (default) No delay
100 Chroma – 1 chroma pixel (late)
101 Chroma – 2 chroma pixel (late)
110 Chroma – 3 chroma pixel (late)
111 Not used

Rev. A | Page 42 of 112

ADV7180

SYNCHRONIZATION OUTPUT SIGNALS

HS Configuration

The following controls allow the user to configure the behavior
of the HS output pin only:

• Beginning of HS signal via HSB[10:0]

• End of HS signal via HSE[10:0]

• Polarity of HS using PHS

The HS begin (HSB) and HS end (HSE) registers allow the user
to freely position the HS output (pin) within the video line. The
values in HSB[10:0] and HSE[10:0] are measured in pixel units
from the falling edge of HS. Using both values, the user can
program both the position and length of the HS output signal.

HSB[10:0], HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]

The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 32). HSB is set to
00000000010b, which is two LLC1 clock cycles from count [0].

The default value of HSB[10:0] is 0x002, indicating that the HS
pulse starts two pixels after the falling edge of HS.

HSE[10:0], HS End, Address 0x34 [2:0], Address 0x36 [7:0]

The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 32). HSE is set to
00000000000b, which is 0 LLC1 clock cycles from count [0].

The default value of HSE[10:0] is 000, indicating that the HS
pulse ends 0 pixels after the falling edge of HS.

For example,

• To shift the HS toward active video by 20 LLC1s, add

20 LLC1s to both HSB and HSE—that is,
HSB[10:0] = [00000010110], HSE[10:0] = [00000010100].

• To shift the HS away from active video by 20 LLC1s, add

1696 LLC1s to both HSB and HSE (for NTSC)—that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
Therefore, 1696 is derived from the NTSC total number of
pixels, 1716.

• To move 20 LLC1s away from active video, subtract 20 from

1716 and add the result in binary to both HSB[10:0] and
HSE[10:0].

PHS, Polarity HS, Address 0x37 [7]

The polarity of the HS pin can be inverted using the PHS bit.

When PHS is 0 (default), HS is active high.

When PHS is 1, HS is active low.

Table 60. HS Timing Parameters (See Figure 32)

Characteristic

HS to Active Video

Standard

NTSC 00000000010b 00000000000b 272 720Y + 720C = 1440 1716
NTSC Square Pixel 00000000010b 00000000000b 276 640Y + 640C = 1280 1560
PAL 00000000010b 00000000000b 284 720Y + 720C = 1440 1728

HS Begin Adjust
HSB[10:0] (Default)

HS End Adjust
HSE[10:0] (Default)

LLC1 Clock Cycles,
C in Figure 32 (Default)

Active Vi deo
Samples/Line,
D in Figure 32

Total LLC1
Clock Cycles,
E in Figure 32

Figure 32. HS Timing

Rev. A | Page 43 of 112

ADV7180

VS and FIELD Configuration

The following controls allow the user to configure the behavior
of the VS and FIELD output pins, as well as the generation of
embedded AV codes.

Note that the ADV7180 LQFP-64 has separate VS and FIELD pins.
The ADV7180 LFCSP-40 does not have separate VS and FIELD
pins, but can output either one on Pin 37, the VS/FIELD pin.

VSYNC/FIELD SELECT, Address 0x58 [0]

This feature is used for the ADV7180 LFCSP-40 (ADV7180BCPZ)
only. The polarity of this bit determines what signal appears on
the VS/FIELD pin.

When this bit is set to 0 (default), the FIELD signal is output.

When this bit is set to 1, the VSYNC signal is output.

The ADV7180 LQFP-64 (ADV7180BSTZ) has dedicated FIELD
and VSYNC pins.

ADV encoder-compatible signals via NEWAVMODE are

PVS, PF

•

HVSTIM

•

VSBHO, VSBHE

•

VSEHO, VSEHE

•

For NTSC control,

NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0]

•

NVENDDELO, NVENDDELE, NVENDSIGN,

•

NVEND[4:0]

NFTOGDELO, NFTOGDELE, NFTOGSIGN,

•

NFTOG[4:0]

For PAL control,

PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0]

•

PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0]

•

PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0]

•

NEWAVMODE, New AV Mode, Address 0x31 [4]

When NEWAVMODE is 0, EAV/SAV codes are generated to
suit Analog Devices encoders. No adjustments are possible.

Setting NEWAVMODE to 1 (default) enables the manual position
of the VSYNC, FIELD, and AV codes using Register 0x34 to
Register 0x37 and Register 0xE5 to Register 0xEA. Default register
settings are CCIR656 compliant; see
Figure 38 for PAL. For recommended manual user settings,
see

Tabl e 61 and Figure 34 for NTSC and Tabl e 62 and Figure 39

for PAL.

Figure 33 for NTSC and

HVSTIM, Horizontal VS Timing, Address 0x31 [3]

The HVSTIM bit allows the user to select where the VS signal is
asserted within a line of video. Some interface circuitry may
require VS to go low while HS is low.

When HVSTIM is 0 (default), the start of the line is relative to
HSE.

When HVSTIM is 1, the start of the line is relative to HSB.

VSBHO, VS Begin Horizontal Position Odd, Address 0x32 [7]

The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.

When VSBHO is 0 (default), the VS pin goes high at the middle
of a line of video (odd field).

When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).

VSBHE, VS Begin Horizontal Position Even, Address 0x32 [6]

The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.

When VSBHE is 0 (default), the VS pin goes high at the middle
of a line of video (even field).

When VSBHE is 1, the VS pin changes state at the start of a line
(even field).

VSEHO, VS End Horizontal Position Odd, Address 0x33 [7]

The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.

When VSEHO is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (odd field).

When VSEHO is 1, the VS pin changes state at the start of a line
(odd field).

VSEHE, VS End Horizontal Position Even, Address 0x33 [6]

The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.

When VSEHE is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (even field).

When VSEHE is 1, the VS pin changes state at the start of a line
(even field).

Rev. A | Page 44 of 112

ADV7180

PVS, Polarity VS, Address 0x37 [5]

The polarity of the VS pin can be inverted using the PVS bit.

When PVS is 0 (default), VS is active high.

When PVS is 1, VS is active low.

PF, Polarity FIELD, Address 0x37 [3]

The polarity of the FIELD pin can be inverted using the PF bit.

The FIELD pin can be inverted using the PF bit.

When PF is 0 (default), FIELD is active high.

When PF is 1, FIELD is active low.

FIELD 1

OUTPUT

VIDEO

H

5251 2 3 4 5 6 7 8 9 10111213 19 202122

Table 61. User Settings for NTSC (See Figure 34)

Register Register Name Write

0x31 VS/FIELD Control 1 0x1A
0x32 VS/FIELD Control 2 0x81
0x33 VS/FIELD Control 3 0x84
0x34 HS Position Control 1 0x00
0x35 HS Position Control 2 0x00
0x36 HS Position Control 3 0x7D
0x37 Polarity 0xA1
0xE5 NTSV V Bit Begin 0x41
0xE6 NTSC V Bit End 0x84
0xE7 NTSC F Bit Toggle 0x06

OUTPUT

VIDEO

OUTPUT

VIDEO

HS

OUTPUT

VS

OUTPUT

FIELD

OUTPUT

OUTPUT

VIDEO

HS

OUTPUT

VS

OUTPUT

FIELD

OUTPUT

V

NVBEG[4:0] = 0x5

F

NFTOG[ 4:0] = 0x3

FIELD 2

262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 283 284 285

H

V

NVBEG[4: 0] = 0x5 NVEND[4:0] = 0x4

F

1

APPLIES IF NEWAVMODE = 0:
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.

NFTOG[4:0] = 0x3

NVEND[4:0] = 0x4

1

BT.656-4
REG 0x04, BIT 7 = 1

1

BT.656-4
REG 0x04, BIT 7 = 1

Figure 33. NTSC Default, ITU-R BT.656 (the Polarity of H, V, and F is Embedded in the Data)

FIELD 1

525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 21 22

NVBEG[4:0] = 0x0 NVEND[4:0] = 0x3

FIELD 2

262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 284 285

NVBEG[4:0] = 0x0 NVEND[4:0] = 0x3

Figure 34. NTSC Typical VSYNC/FIELD Positions Using Register Writes in

NFTOG[4:0] = 0x5

NFTOG[4:0] = 0x5

Table 61

05700-029

05700-030

Rev. A | Page 45 of 112

ADV7180

NVBEGDELO, NTSC VSYNC Begin Delay on Odd Field,
Address 0xE5 [7]

When NVBEGDELO is 0 (default), there is no delay.

Setting NVBEGDELO to 1 delays VSYNC going high on an odd
field by a line relative to NVBEG.

For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC on the VS pin are modified.

NVENDSIGN

01

ADVANCE BEGIN OF

VSYNC BY NVBEG[4:0]

NOT VALID FOR USER

PROGRAMMING

NVBEGDELO

ADDITIONAL

DELAY BY

1LINE

VSBHO

ADVANCE BY

0.5 LI NE

NVBEGSI GN

ODD FIELD?

1 0

1 0

VSYNC BEGIN

01

DELAY BEGIN OF

VSYNC BY NVBEG[4:0]

NOYES

NVBEGDE LE

10

ADDITIONAL

DELAY BY

1LINE

VSBHE

10

ADVANCE BY

0.5 LI NE

05700-031

Figure 35. NTSC Vsync Begin

NVBEGDELE, NTSC Vsync Begin Delay on Even Field,
Address 0xE5 [6]

When NVBEGDELE is 0 (default), there is no delay.

Setting NVBEGDELE to 1 delays vsync going high on an even
field by a line relative to NVBEG.

NVBEGSIGN, NTSC Vsync Begin Sign, Address 0xE5 [5]

Setting NVBEGSIGN to 0 delays the start of vsync. Set for user
manual programming.

Setting NVBEGSIGN to 1 (default) advances the start of vsync.
Not recommended for user programming.

NVBEG[4:0], NTSC Vsync Begin, Address 0xE5 [4:0]

The default value of NVBEG is 00101, indicating the NTSC
vsync begin position.

ADVANCE END OF

VSYNC BY NVEND[4:0]

NOT VALID FOR USER

PROGRAMMING

NVENDDELO

ADDITIONAL

DELAY BY

1LINE

VSEHO

ADVANCE BY

0.5 LI NE

ODD FIELD?

1 0

1 0

VSYNC END

DELAY END OF VSYNC

BY NVEND[4:0]

NOYES

NVENDDELE

10

ADDITIONAL

DELAY BY

1LINE

VSEHE

10

ADVANCE BY

0.5 LI NE

05700-032

Figure 36. NTSC Vsync End

NVENDDELO, NTSC Vsync End Delay on Odd Field,
Address 0xE6 [7]

When NVENDDELO is 0 (default), there is no delay.

Setting NVENDDELO to 1 delays vsync from going low on an
odd field by a line relative to NVEND.

NVENDDELE, NTSC Vsync End Delay on Even Field,
Address 0xE6 [6]

When NVENDDELE is set to 0 (default), there is no delay.

Setting NVENDDELE to 1 delays vsync from going low on an
even field by a line relative to NVEND.

NVENDSIGN, NTSC Vsync End Sign, Address 0xE6 [5]

Setting NVENDSIGN to 0 (default) delays the end of vsync.
Set for user manual programming.

Setting NVENDSIGN to 1 advances the end of vsync. Not
recommended for user programming.

Rev. A | Page 46 of 112

ADV7180

O

O

NVEND[4:0], NTSC Vsync End, Address 0xE6 [4:0] NFTOG[4:0], NTSC Field Toggle, Address 0xE7 [4:0]

The default value of NVEND is 00100, indicating the NTSC
vsync end position.

For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.

NFTOGDELO, NTSC FIELD Toggle Delay on Odd Field,
Address 0xE7 [7]

When NFTOGDELO is 0 (default), there is no delay.

Setting NFTOGDELO to 1 delays the field toggle/transition on
an odd field by a line relative to NFTOG.

NFTOGDELE, NTSC Field Toggle Delay on Even Field,
Address 0xE7 [6]

When NFTOGDELE is 0, there is no delay.

Setting NFTOGDELE to 1 (default) delays the field toggle/
transition on an even field by a line relative to NFTOG.

NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]

Setting NFTOGSIGN to 0 delays the field transition. Set for
user manual programming.

Setting NFTOGSIGN to 1 (default) advances the field
transition. Not recommended for user programming.

The default value of NFTOG is 00011, indicating the NTSC
field toggle position.

For all NTSC/PAL field timing controls, both the F bit in the
AV code and the field signal on the FIELD/DE pin are modified.

ADVANCE TOGGLE OF

FIELD BY NFTOG[4:0]

NOT VALID FOR USER

PROGRAMMING

NFTOGDELO

ADDITIONAL

DELAY BY

1LINE

NFTOGSIGN

ODD FIELD?

1 0

01

DELAY TOGGLE OF

FIELD BY NFTOG[4:0]

NOYES

NFTOGDELE

10

ADDITIONAL

DELAY BY

1LINE

FIELD

TOGGLE

05700-033

Figure 37. NTSC FIELD Toggle

FIELD 1

UTPUT

VIDEO

UTPUT

VIDEO

622 623 624 625 1 2 3 4 5 6 7 8 9 10 22 23 24

H

V

PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4

F

310 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337

H

V

PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4

F

PFTOG[ 4:0] = 0x3

FIELD 2

PFTOG[ 4:0] = 0x3

05700-034

Figure 38. PAL Default, ITU-R BT.656 (the Polarity of H, V, and F is Embedded in the Data)

Rev. A | Page 47 of 112

ADV7180

OUTPUT

VIDEO

OUTPUT

OUTPUT

FIELD

OUTPUT

OUTPUT

VIDEO

OUTPUT

OUTPUT

FIELD

OUTPUT

HS

VS

HS

VS

622 623 624

310 311 312

FIELD 1

123 45 678 91011 2324

625

PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4

FIELD 2

314 315 316 317 318 319 320 321 322 323 336 337

313

PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4

Figure 39. PAL Typical VS/FIELD Positions Using Register Writes Shown in

Table 62. User Settings for PAL

Register Register Name Write

0x31 VS/FIELD Control 1 0x1A
0x32 VS/FIELD Control 2 0x81
0x33 VS/FIELD Control 3 0x84
0x34 HS Position Control 1 0x00
0x35 HS Position Control 2 0x00
0x36 HS Position Control 3 0x7D
0x37 Polarity 0xA1
0xE8 PAL V Bit Begin 0x41
0xE9 PAL V Bit End 0x84
0xEA PAL F Bit Toggle 0x06

PVBEGDELO, PAL Vsync Begin Delay on Odd Field,
Address 0xE8 [7]

When PVBEGDELO is 0 (default), there is no delay.

Setting PVBEGDELO to 1 delays vsync going high on an odd
field by a line relative to PVBEG.

PVBEGDELE PAL, Vsync Begin Delay on Even Field,
Address 0xE8 [6]

When PVBEGDELE is 0, there is no delay.

Setting PVBEGDELE to 1 (default) delays vsync going high on
an even field by a line relative to PVBEG.

PVBEGSIGN PAL, Vsync Begin Sign, Address 0xE8 [5]

Setting PVBEGSIGN to 0 delays the beginning of vsync. Set for
user manual programming.

Setting PVBEGSIGN to 1(default) advances the beginning of
vsync. Not recommended for user programming.

PFTOG[4: 0] = 0x6

PFTOG[4: 0] = 0x6

05700-035

Table 62

PVBEG[4:0], PAL Vsync Begin, Address 0xE8 [4:0]

The default value of PVBEG is 00101, indicating the PAL vsync
begin position. For all NTSC/PAL vsync timing controls, the
V bit in the AV code and the vsync on the VS pin are modified.

ADVANCE BEGIN OF

VSYNC BY PVBEG[4:0]

NOT VALID FO R USER

PROGRAMMING

PVBEGDELO

ADDITIONA L

DELAY BY

1LINE

VSBHO

ADVANCE BY

0.5 LINE

PVBEGSIGN

ODD FIELD?

1 0

1 0

VSYNC BEGIN

Figure 40. PAL Vsync Begin

01

DELAY BEGIN OF

VSYNC BY PVBEG[4:0]

NOYES

PVBEGDELE

10

ADDITIONA L

DELAY BY

1LINE

VSBHE

10

ADVANCE BY

0.5 LINE

05700-036

Rev. A | Page 48 of 112

ADV7180

PFTOGDELO, PAL Field Toggle Delay on Odd Field,
Address 0xEA [7]

When PFTOGDELO is 0 (default), there is no delay.

Setting PFTOGDELO to 1 delays the F toggle/transition on an
odd field by a line relative to PFTOG.

PFTOGDELE, PAL Field Toggle Delay on Even Field,
Address 0xEA [6]

When PFTOGDELE is 0, there is no delay.

Setting PFTOGDELE to 1 (default) delays the F toggle/transition
on an even field by a line relative to PFTOG.

PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]

Setting PFTOGSIGN to 0 delays the field transition. Set for user
manual programming.

Setting PFTOGSIGN to 1 (default) advances the field transition.
Not recommended for user programming.

PFTOG, PAL Field Toggle, Address 0xEA [4:0]

The default value of PFTOG is 00011, indicating the PAL field
toggle position.

For all NTSC/PAL field timing controls, the F bit in the AV
code and the field signal on the FIELD/DE pin are modified.

ADVANCE END OF

VSYNC BY PVEND[4:0]

NOT VALID FOR USER

PROGRAMMING

PVENDDELO

ADDITIONAL

DELAY BY

1LINE

VSEHO

ADVANCE BY

0.5 LI NE

1 0

1 0

PVENDSIGN

ODD FIELD?

01

DELAY END OF VSYNC

BY PVEND[4:0]

NOYES

PVENDDELE

10

ADDITIONAL

DELAY BY

1LINE

VSEHE

10

ADVANCE BY

0.5 LI NE

VSYNC END

05700-037

Figure 41. PAL Vsync End

PVENDDELO, PAL Vsync End Delay on Odd Field,
Address 0xE9 [7]

When PVENDDELO is 0 (default), there is no delay.

Setting PVENDDELO to 1 delays vsync going low on an odd
field by a line relative to PVEND.

PVENDDELE, PAL Vsync End Delay on Even Field,
Address 0xE9 [6]

When PVENDDELE is 0 (default), there is no delay.

Setting PVENDDELE to 1 delays vsync going low on an even
field by a line relative to PVEND.

PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]

Setting PVENDSIGN to 0 (default) delays the end of vsync. Set
for user manual programming.

Setting PVENDSIGN to 1 advances the end of vsync. Not
recommended for user programming.

PVEND[4:0], PAL Vsync End, Address 0xE9 [4:0]

The default value of PVEND is 10100, indicating the PAL vsync
end position.

For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.

ADVANCE TOGGLE OF

FIELD BY PFTOG[4:0]

NOT VALID FOR USER

PROGRAMMING

PFTOGDELO

ADDITIONAL

DELAY BY

1LINE

PFTOGSIGN

ODD FIELD?

1 0

FIELD

TOGGLE

Figure 42. PAL F Toggle

01

DELAY TOGGLE OF

FIELD BY PFTOG[4:0]

NOYES

PFTOGDELE

10

ADDITIONAL

DELAY BY

1LINE

05700-038

Rev. A | Page 49 of 112

ADV7180

SYNC PROCESSING

The ADV7180 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I

2

C bits.

ENHSPLL, Enable Hsync Processor, Address 0x01 [6]

The HSYNC processor is designed to filter incoming hsyncs
that have been corrupted by noise, providing improved per­formance for video signals with stable time bases but poor SNR.

Setting ENHSPLL to 0 disables the hsync processor.

Setting ENHSPLL to 1 (default) enables the hsync processor.

ENVSPROC, Enable Vsync Processor, Address 0x01 [3]

This block provides extra filtering of the detected vsyncs to
improve vertical lock.

Setting ENVSPROC to 0

disables the vsync processor.

Setting ENVSPROC to 1(default) enables the vsync processor.

VBI DATA DECODE

There are two VBI data slicers on the ADV7180. The first is
called the VBI data processor (VDP), and the second is called
VBI System 2.

The VDP can slice both low bandwidth standards and high
bandwidth standards such as teletext. VBI System 2 can slice
low data rate VBI standards only.

The VDP is capable of slicing multiple VBI data standards on
SD video. It decodes the VBI data on the incoming CVBS and
Y/C or YUV data. The decoded results are available as ancillary
data in output 656 data stream. For low data rate VBI standards
like CC/WSS/CGMS, users can read the decoded data bytes

2

from I

C registers.

The VBI data standards that can be decoded by the VDP are
listed in

Table 63. PAL

Feature Standard

Teletext System A, C, or D ITU-R BT.653
Teletext System B/WST ITU-R BT.653
Video Programming System (VPS) ETSI EN 300 231 V 1.3.1
Vertical Interval Time Codes ( VITC) –
Wide Screen Signaling (WSS)

Closed Captioning (CCAP) –

Table 6 3 and Ta b le 6 4.

ITU-R BT.1119-1/
ETSI EN.300294

Table 64. NTSC

Feature Standard

Teletext System B and D ITU-R BT.653
Teletext System C/NABTS ITU-R BT.653/EIA-516
Vertical Interval Time Codes (VITC ) –
Copy Generation Management

System (CGMS)
Gemstar –
Closed Captioning (CCAP) EIA-608

EIA-J CPR-1204/IEC 61880

The VBI data standard that the VDP decodes on a particular
line of incoming video has been set by default as described in
Tabl e 65 . This can be overridden manually and any VBI data
can be decoded on any line. The details of manual
programming are described in

Tabl e 66 .

VDP Default Configuration

The VDP can decode different VBI data standards on a line-to­line basis. The various standards supported by default on
different lines of VBI are explained in

Tabl e 65 .

VDP Manual Configuration

MAN_LINE_PGM, Enable Manual Line Programming of
VBI Standards, Address 0x64 [7], User Sub Map

The user can configure the VDP to decode different standards on
a line-to-line basis through manual line programming. For this,
the user has to set the MAN_LINE_PGM bit. The user needs to
write into all the line programming registers VBI_DATA_Px_Ny
(see Register 0x64 to Register 0x77 in

(default)—The VDP decodes default standards on lines, as

0
shown in

Tabl e 65 .

Table 104).

1—VBI standards to be decoded are manually programmed.

VBI_DATA_Px_Ny [3:0], VBI Standard to be Decoded on
Line X for PAL, Line Y for NTSC, Addresses 0x64 to 0x77,
User Sub Map

These are related 4-bit clusters in Register 0x64 to Register 0x77
of the User Sub Map. These 4-bit, line programming registers,
named VBI_DATA_Px_Ny, identify the VBI data standard that
would be decoded on Line X in PAL or on Line Y in NTSC
mode. The different types of VBI standards decoded by
VBI_DATA_Px_Ny are shown in

Tabl e 66 . Note that the X or Y

value depends on whether the ADV7180 is in PAL or NTSC mode.

Rev. A | Page 50 of 112

ADV7180

Table 65. Default Standards on Lines for PAL and NTSC

PAL—625/50 NTSC—525/60

Default VBI

Line No.

6 WST 318 VPS 23 Gemstar_1× – –
7 WST 319 WST 24 Gemstar_1× 286 Gemstar_1×
8 WST 320 WST 25 Gemstar_1× 287 Gemstar_1×
9 WST 321 WST – – 288 Gemstar_1×
10 WST 322 WST – – – –
11 WST 323 WST – – – –
12 WST 324 WST 10 NABTS 272 NABTS
13 WST 325 WST 11 NABTS 273 NABTS
14 WST 326 WST 12 NABTS 274 NABTS
15 WST 327 WST 13 NABTS 275 NABTS
16 VPS 328 WST 14 VITC 276 NABTS
17 - 329 VPS 15 NABTS 277 VITC
18 - 330 - 16 VITC 278 NABTS
19 VITC 331 - 17 NABTS 279 VITC
20 WST 332 VITC 18 NABTS 280 NABTS
21 WST 333 WST 19 NABTS 281 NABTS
22 CCAP 334 WST 20 CGMS 282 NABTS
23 WSS 335 CCAP 21 CCAP 283 CGMS
24 + full

odd field

DATA Decoded

WST 336 WST

Line No.

337 + full
even field

Default VBI
DATA Decoded

WST

Line No.

22 + full
odd field

Default VBI
DATA Decoded

NABTS 284 CCAP

Line No.

285 + full
even field

Default VBI
DATA Decoded

NABTS

Table 66. VBI Data Standards for Manual Configuration

VBI_DATA_Px_Ny 625/50—PAL 525/60—NTSC

0000 Disable VDP Disable VDP
0001 Teletext system identified by VDP_TTXT_TYPE Teletext system identified by VDP_TTXT_TYPE
0010 VPS – ETSI EN 300 231 V 1.3.1 Reserved
0011 VITC VITC
0100 WSS ITU-R BT.1119-1/ETSI.EN.300294 CGMS EIA-J CPR-1204/IEC 61880
0101 Reserved Gemstar_1×
0110 Reserved Gemstar_2×
0111 CCAP CCAP EIA-608
1000 to 1111 Reserved Reserved

Rev. A | Page 51 of 112

ADV7180

Table 67.VBI Data Standards to be Decoded on Line Px (PAL) or Line Ny (NTSC)

Signal Name Register Location Dec Address Hex Address
VBI_DATA_P6_N23 VDP_LINE_00F[7:4] 101 0x65
VBI_DATA_P7_N24 VDP_LINE_010[7:4] 102
VBI_DATA_P8_N25 VDP_LINE_011[7:4] 103
VBI_DATA_P9 VDP_LINE_012[7:4] 104
VBI_DATA_P10 VDP_LINE_013[7:4] 105
VBI_DATA_P11 VDP_LINE_014[7:4] 106
VBI_DATA_P12_N10 VDP_LINE_015[7:4] 107
VBI_DATA_P13_N11 VDP_LINE_016[7:4] 108
VBI_DATA_P14_N12 VDP_LINE_017[7:4] 109
VBI_DATA_P15_N13 VDP_LINE_018[7:4] 110
VBI_DATA_P16_N14 VDP_LINE_019[7:4] 111
VBI_DATA_P17_N15 VDP_LINE_01A[7:4] 112
VBI_DATA_P18_N16 VDP_LINE_01B[7:4] 113
VBI_DATA_P19_N17 VDP_LINE_01C[7:4] 114
VBI_DATA_P20_N18 VDP_LINE_01D[7:4] 115
VBI_DATA_P21_N19 VDP_LINE_01E[7:4] 116
VBI_DATA_P22_N20 VDP_LINE_01F[7:4] 117
VBI_DATA_P23_N21 VDP_LINE_020[7:4] 118
VBI_DATA_P24_N22 VDP_LINE_021[7:4] 119
VBI_DATA_P318 VDP_LINE_00E[3:0] 100
VBI_DATA_P319_N286 VDP_LINE_00F[3:0] 101
VBI_DATA_P320_N287 VDP_LINE_010[3:0] 102
VBI_DATA_P321_N288 VDP_LINE_011[3:0] 103
VBI_DATA_P322 VDP_LINE_012[3:0] 104
VBI_DATA_P323 VDP_LINE_013[3:0] 105
VBI_DATA_P324_N272 VDP_LINE_014[3:0] 106
VBI_DATA_P325_N273 VDP_LINE_015[3:0] 107
VBI_DATA_P326_N274 VDP_LINE_016[3:0] 108
VBI_DATA_P327_N275 VDP_LINE_017[3:0] 109
VBI_DATA_P328_N276 VDP_LINE_018[3:0] 110
VBI_DATA_P329_N277 VDP_LINE_019[3:0] 111
VBI_DATA_P330_N278 VDP_LINE_01A[3:0] 112
VBI_DATA_P331_N279 VDP_LINE_01B[3:0] 113
VBI_DATA_P332_N280 VDP_LINE_01C[3:0] 114
VBI_DATA_P333_N281 VDP_LINE_01D[3:0] 115
VBI_DATA_P334_N282 VDP_LINE_01E[3:0] 116
VBI_DATA_P335_N283 VDP_LINE_01F[3:0] 117
VBI_DATA_P336_N284 VDP_LINE_020[3:0] 118
VBI_DATA_P337_N285 VDP_LINE_021[3:0] 119

Note that full field detection (lines other than VBI lines) of any standard can also be enabled by writing into the registers
VBI_DATA_P24_N22[3:0] and VBI_DATA_P337_N285[3:0]. So, if VBI_DATA_P24_N22[3:0] is programmed with any teletext
standard, then teletext is decoded off for the entire odd field. The corresponding register for the even field is VBI_DATA_P337_N285[3:0].

For teletext system identification, VDP assumes that if teletext is present in a video channel, all the teletext lines comply with a single
standard system. Thus, the line programming using VBI_DATA_Px_Ny registers identifies whether the data in line is teletext; the actual
standard is identified by the VDP_TTXT_TYPE_MAN bit. To program the VDP_TTXT_TYPE_MAN bit, the
VDP_TTXT_TYPE_MAN_ENABLE bit must be set to 1.

0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77

Rev. A | Page 52 of 112

ADV7180

VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual
Selection of Teletext Type, Address 0x60 [2], User Sub Map

0 (default)—Manual programming of the teletext type is
disabled.

1—Manual programming of the teletext type is enabled.

VDP_TTXT_TYPE_MAN[1:0], Specify the Teletext Type,
Address 0x60 [1:0], User Sub Map

These bits specify the teletext type to be decoded. These bits are
functional only if VDP_TTXT_TYPE_MAN_ENABLE is set to 1.

Table 68. VDP_TTXT_TYPE_MAN Function

VDP_TTXT_
TYPE_MAN[1:0]

00 (default)

01

10

11

625/50 (PAL) 525/60 (NTSC)

Teletext-ITU-BT.653­625/50-A

Teletext-ITU-BT.653­625/50-B (WST)

Teletext-ITU-BT.653­625/50-C

Teletext-ITU-BT.653­625/50-D

Reserved

Teletext-ITU-BT.653­525/60-B

Teletext-ITU-BT.653­525/60-C or EIA516
(NABTS)

Teletext-ITU-BT.653­525/60-D

VDP Ancillary Data Output

Reading the data back via I2C may not be feasible for VBI data
standards with high data rates (for example, teletext). An
alternative is to place the sliced data in a packet in the line
blanking of the digital output CCIR656 stream. This is available
for all standards sliced by the VDP module.

When data has been sliced on a given line, the corresponding
ancillary data packet is placed immediately after the next EAV
code that occurs at the output (that is, data sliced from multiple
lines are not buffered up and then emitted in a burst). Note that,
due to the vertical delay through the comb filters, the line
number on which the packet is placed differs from the line
number on which the data was sliced.

The user can enable or disable the insertion of VDP decoded
results into the 656 ancillary streams by using the
ADF_ENABLE bit.

ADF_ENABLE, Enable Ancillary Data Output Through
656 Stream, Address 0x62 [7], User Sub Map

0 (default)—Disables insertion of VBI decoded data into
ancillary 656 stream.

1—Enables insertion of VBI decoded data into ancillary 656
stream.

The user may select the data identification word (DID) and the
secondary data identification word (SDID) through
programming the ADF_DID[4:0] and ADF_SDID[5:0]

bits,

respectively, as explained in the following sections.

ADF_DID[4:0], User-Specified Data ID Word in Ancillary
Data, Address 0x62 [4:0], User Sub Map

This bit selects the data ID word to be inserted into the
ancillary data stream with the data decoded by the VDP.

The default value of ADF_DID[4:0] is 10101.

ADF_SDID[5:0], User-Specified Secondary Data ID Word
in Ancillary Data, Address 0x63 [5:0], User Sub Map

These bits select the secondary data ID word to be inserted in
the ancillary data stream with the data decoded by the VDP.

The default value of ADF_SDID[5:0] is 101010.

DUPLICATE_ADF, Enable Duplication/Spreading of
Ancillary Data over Y and C Buses, Address 0x63 [7], User
Sub Map

This bit determines whether the ancillary data is duplicated
over both Y and C buses or if the data packets are spread
between the two channels.

(default)—The ancillary data packet is spread across the Y and

0
C data streams.

1—The ancillary data packet is duplicated on the Y and C data
streams.

ADF_MODE[1:0], Determine the Ancillary Data Output
Mode, Address 0x62 [6:5], User Sub Map

These bits determine if the ancillary data output mode is in byte
mode or nibble mode.

Table 69.

ADF_MODE[1:0] Description

00 (default) Nibble mode
01 Byte mode, no code restrictions
10

11 Reserved

Byte mode, but 0x00 and 0xFF prevented
(0x00 replaced by 0x01, 0xFF replaced by
0xFE)

Rev. A | Page 53 of 112

ADV7180

The ancillary data packet sequence is explained in Tab l e 7 0 and
Tabl e 71 . The nibble output mode is the default mode of output
from the ancillary stream when ancillary stream output is
enabled. This format is in compliance with ITU-R BT.1364.

These abbreviations are used in

Tabl e 70 and Table 7 1:

• EP—Even parity for Bit B8 to Bit B2. This means that the

parity bit’s EP is set so that an even number of 1s are in
Bit B8 to Bit B2, including the parity bit, D8.

CS—Checksum word. The CS word is used to increase

•

confidence of the integrity of the ancillary data packet
from the DID, SDID, and DC through user data-words
(UDWs). It consists of 10 bits: a 9-bit calculated value and
B9 as the inverse of B8. The checksum value B8 to B0 is
equal to the nine LSBs of the sum of the nine LSBs of the
DID, SDID, and DC and all UDWs in the packet. Prior to
the start of the checksum count cycle, all checksum and
carry bits are preset to 0. Any carry resulting from the
checksum count cycle is ignored.

Table 70. Ancillary Data in Nibble Output Format

Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Description

0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
2 1 1 1 1 1 1 1 1 1 1

3

4

5

6

7

8

9

10

11

12

13

14

. . . . . . . . . . .

. . . . . . . . . . .

. . . . . . . . . . .

n − 3 1 0 0 0 0 0 0 0 0 0
n − 2 1 0 0 0 0 0 0 0 0 0
n − 1

EP

EP

EP

EP

EP

EP

EP

EP

EP

EP

EP

EP

B8

EP 0 I

EP I

EP 0 DC[4:0] 0 0 Data count.

EP padding[1:0] VBI_DATA_STD[3:0] 0 0 ID0 (User Data-Word 1).

EP 0 Line_number[9:5] 0 0 ID1 (User Data-Word 2).

EP Even_Field Line_number[4:0] 0 0 ID2 (User Data-Word 3).

EP 0 0 0 0 VDP_TTXT_TYPE[1:0] 0 0 ID3 (User Data-Word 4).

EP 0 0 VBI_WORD_1[7:4] 0 0 ID4 (User Data-Word 5).

EP 0 0 VBI_WORD_1[3:0] 0 0 ID5 (User Data-Word 6).

EP 0 0 VBI_WORD_2[7:4] 0 0 ID6 (User Data-Word 7).

EP 0 0 VBI_WORD_2[3:0] 0 0 ID7 (User Data-Word 8).

EP 0 0 VBI_WORD_3[7:4] 0 0 ID8 (User Data-Word 9).

Checksum 0 0 CS (checksum word).

2

C_DID6_2[4:0] 0 0

2

C_SDID7_2[5:0] 0 0

EP

•

—The MSB, B9, is the inverse of EP. This ensures that

restricted Codes 0x00 and 0xFF do not occur.

Line_number[9:0]—The line number of the line that

•

immediately precedes the ancillary data packet. The line
number is from the numbering system in ITU-R BT.470.
The line number runs from 1 to 625 in a 625-line system
and from 1 to 263 in a 525-line system. Note that, due to
the vertical delay through the comb filters, the line number
on which the packet is output differs from the line number
on which the VBI data was sliced.

•

Data Count—The data count specifies the number of

UDWs in the ancillary stream for the standard. The total
number of user data-words is four times the data count.
Padding words may be introduced to make the total
number of UDWs divisible by 4.

Ancillary data preamble.

DID (data identification
word).

SDID (secondary data
identification word).

Pad 0x200. These
padding words may be
present depending on
ancillary data type. User
data-word xx.

Rev. A | Page 54 of 112

ADV7180

Table 71. Ancillary Data in Byte Output Format1

Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Description

0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
2 1 1 1 1 1 1 1 1 1 1
3

4

5

6

7

8

9
10 VBI_WORD_1[7:0] 0 0 ID4 (User Data-Word 5).
11 VBI_WORD_2[7:0] 0 0 ID5 (User Data-Word 6).
12 VBI_WORD_3[7:0] 0 0 ID6 (User Data-Word 7).
13 VBI_WORD_4[7:0] 0 0 ID7 (User Data-Word 8).
14 VBI_WORD_5[7:0] 0 0 ID8 (User Data-Word 9).

. . . . . . . . . . .

. . . . . . . . . . .

. . . . . . . . . . .

n − 3 1 0 0 0 0 0 0 0 0 0
n − 2 1 0 0 0 0 0 0 0 0 0
n − 1

1

This mode does not fully comply with ITU-R BT.1364.

Structure of VBI Words in Ancillary Data Stream

Each VBI data standard has been split into a clock-run-in
(CRI), a framing code (FC), and a number of data bytes (n).
The data packet in the ancillary stream includes only the FC
and data bytes.
in the ancillary data stream.

EP

EP

EP

EP

EP

EP

EP

B8

EP 0 I2C_DID6_2[4:0] 0 0 DID.

EP I2C_SDID7_2[5:0] 0 0 SDID.

EP 0 DC[4:0] 0 0 Data count.

EP padding[1:0] VBI_DATA_STD[3:0] 0 0 ID0 (User Data-Word 1).

EP 0 Line_number[9:5] 0 0 ID1 (User Data-Word 2).

EP Even_Field Line_number[4:0] 0 0 ID2 (User Data-Word 3).

EP 0 0 0 0 VDP_TTXT_TYPE[1:0] 0 0 ID3 (User Data-Word 4).

Checksum 0 0 CS (checksum word).

Tabl e 72 shows the format of the VBI_WORD_x

Tabl e 73 shows the framing code and its valid length for VBI
data standards supported by VDP.

Example

For teletext (B-WST), the framing code byte is 11100100
(0xE4), with bits shown in the order of transmission. For
VBI_WORD_1 = 0x27, VBI_WORD_2 = 0x00, and
VBI_WORD_3 = 0x00 translated into UDWs in the ancillary

Table 72. Structure of VBI Data-Words in Ancillary Stream

Ancillary Data
Byte Number

VBI_WORD_1 FC0 Framing code [23:16]
VBI_WORD_2 FC1 Framing code [15:8]
VBI_WORD_3 FC2 Framing code [7:0]
VBI_WORD_4 DB1 1st data byte

… … …

VBI_WORD_N + 3 DBn Last (nth) data byte

Byte Type Description

VDP Framing Code

The length of the actual framing code depends on the VBI data
standard. For uniformity, the length of the framing code
reported in the ancillary data stream is always 24 bits. For
standards with a smaller framing code length, the extra LSB bits

data stream for nibble mode is as follows:

UDW5 [5:2] = 0010

UDW6 [5:2] = 0111

UDW7 [5:2] = 0000 (undefined bits set to 0)

UDW8 [5:2] = 0000 (undefined bits set to 0)

UDW9 [5:2] = 0000 (undefined bits set to 0)

UDW10 [5:2] = 0000 (undefined bits set to 0)

For byte mode:

UDW5 [9:2] = 0010_0111

UDW6 [9:2] = 0000_0000 (undefined bits set to 0)

UDW7 [9:2] = 0000_0000 (undefined bits set to 0)

are set to 0. The valid length of the framing code can be
decoded from the VBI_DATA_STD bit available in ID0
(UDW 1). The framing code is always reported in the inverse­transmission order.

Ancillary data preamble.

Pad 0x200. These
padding words may be
present depending on
ancillary data type. User
data-word xx.

Rev. A | Page 55 of 112

ADV7180

Data Bytes

The VBI_WORD_4 to VBI_WORD_N + 3 contains the data­words that were decoded by the VDP in the transmission order.
The position of bits in bytes is in the inverse transmission order.

For example, closed captioning has two user data bytes, as
shown in

Tabl e 78 .

Table 73. Framing Code Sequence for Different VBI Standards

Error-Free Framing Code Bits

VBI Standard Length in Bits

(In Order of Transmission)

TTXT_SYSTEM_A (PAL) 8 11100111 11100111
TTXT_SYSTEM_B (PAL) 8 11100100 00100111
TTXT_SYSTEM_B (NTSC) 8 11100100 00100111
TTXT_SYSTEM_C (PAL and NTSC) 8 11100111 11100111
TTXT_SYSTEM_D (PAL and NTSC) 8 11100101 10100111
VPS (PAL) 16 10001010100011001 1001100101010001
VITC (NTSC and PAL) 1 0 0
WSS (PAL) 24 000111100011110000011111 111110000011110001111000
GEMSTAR_1× (NTSC) 3 001 100
GEMSTAR_2× (NTSC) 11 1001_1011_101 101_1101_1001
CCAP (NTSC and PAL) 3 001 100
CGMS (NTSC) 1 0 0

Table 74. Total User Data-Words for Different VBI Standards

1

VBI Standard ADF Mode Framing Code UDWs VBI Data-Words No. of Padding Words Total UDWs

00 (nibble mode) 6 74 0 84 TTXT_SYSTEM_A (PAL)
01,10 (byte mode) 3 37 0 44
00 (nibble mode) 6 84 2 96 TTXT_SYSTEM_B (PAL)
01,10 (byte mode) 3 42 3 52
00 (nibble mode) 6 68 2 80 TTXT_SYSTEM_B (NTSC)
01,10 (byte mode) 3 34 3 44
00 (nibble mode) 6 66 0 76 TTXT_SYSTEM_C (PAL and NTSC)
01,10 (byte mode) 3 33 2 42
00 (nibble mode) 6 68 2 80 TTXT_SYSTEM_D (PAL and NTSC)
01,10 (byte mode) 3 34 3 44
00 (nibble mode) 6 26 0 36 VPS (PAL)
01,10 (byte mode) 3 13 0 20
00 (nibble mode) 6 18 0 28 VITC (NTSC and PAL)
01,10 (byte mode) 3 9 0 16
00 (nibble mode) 6 4 2 16 WSS (PAL)
01,10 (byte mode) 3 2 3 12
00 (nibble mode) 6 4 2 16 GEMSTAR_1× (NTSC)
01,10 (byte mode) 3 2 3 12
00 (nibble mode) 6 8 2 20 GEMSTAR_2× (NTSC)
01,10 (byte mode) 3 4 1 12
00 (nibble mode) 6 4 2 16 CCAP (NTSC and PAL)
01,10 (byte mode) 3 2 3 12
00 (nibble mode) 6 6 0 16 CGMS (NTSC)

1

The first four UDWs are always the ID.

01,10 (byte mode) 3 3 + 3 2 12

The data bytes in the ancillary data stream are as follows:

VBI_WORD_4 = Byte 1 [7:0]
VBI_WORD_5 = Byte 2 [7:0]

The number of VBI_WORDS for each VBI data standard and
the total number of UDWs in the ancillary data stream is shown

Tabl e 74 .

in

Error-Free Framing Code Reported by VDP
(In Reverse Order of Transmission)

Rev. A | Page 56 of 112

ADV7180

I2C Interface

Dedicated I2C readback registers are available for CCAP,
CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. Because
teletext is a high data rate standard, data extraction is supported
only through the ancillary data packet. The details of these
registers and their access procedure are described next.

User Interface for I2C Readback Registers

The VDP decodes all enabled VBI data standards in real time.

2

Because the I

C access speed is much lower than the decoded
rate, when the registers are accessed, they may be updated with
data from the next line. To avoid this, VDP has a self-clearing
CLEAR bit and an AVAILABLE status bit accompanying all

2

I

C readback registers.

2

The user has to clear the I

C readback register by writing a high
to the CLEAR bit. This resets the state of the AVAILABLE bit to
low and indicates that the data in the associated readback
registers is not valid. After the VDP decodes the next line of the
corresponding VBI data, the decoded data is placed into the I

2

C
readback register and the AVAILABLE bit is set to high to
indicate that valid data is now available.

Though the VDP decodes this VBI data in subsequent lines if
present, the decoded data is not updated to the readback
registers until the CLEAR bit is set high again. However, this
data is available through the 656 ancillary data packets.

The CLEAR and AVAILABLE bits are in the VDP_CLEAR
(0x78, User Sub Map, write only) and VDP_STATUS (0x78,
User Sub Map, read only) registers.

Example I2C Readback Procedure

The following tasks have to be performed to read one packet
(line) of PDC data from the decoder:

Write 10 to I

1.

Map) to specify that PDC data has to be updated to I

2

C_GS_VPS_PDC_UTC[1:0] (0x9C, User Sub

2

C

registers.

2.

Write high to the GS_PDC_VPS_UTC_CLEAR bit (0x78,

User Sub Map) to enable I

Poll the GS_PDC_VPS_UTC_AVL bit (0x78, User Sub

3.

2

C register updating.

Map) going high to check the availability of the PDC
packets.

Read the data bytes from the PDC I

4.

2

C registers. Repeat

Step 1 to Step 3 to read another line or packet of data.

To read a packet of CCAP, CGMS, or WSS data, only Step 1 to
Step 3 are required because they have dedicated registers.

VDP—Content-Based Data Update

For certain standards like WSS, CGMS, Gemstar, PDC, UTC,
and VPS, the information content in the signal transmitted
remains the same over numerous lines, and the user may want

to be notified only when there is a change in the information
content or loss of the information content. The user needs to
enable content-based updating for the required standard
through the GS_VPS_PDC_UTC_CB_CHANGE and
WSS_CGMS_CB_CHANGE bits. Therefore, the AVAILABLE
bit shows the availability of that standard only when its content
has changed.

Content-based updating also applies to lines with lost data.
Therefore, for standards like VPS, Gemstar, CGMS, and WSS, if no
data arrives in the next four lines programmed, the corresponding
AVAILABLE bit in the VDP_STATUS register is set high and
the content in the I

2

C registers for that standard is set to 0. The
user has to write high to the corresponding CLEAR bit so that
when a valid line is decoded after some time, the decoded results
are available in the I

2

C registers, with the AVAILABLE status

bit set high.

If content-based updating is enabled, the AVAILABLE bit is set
high (assuming the CLEAR bit was written) in the following cases:

The data contents have changed.

•

Data was being decoded and four lines with no data have

•

been detected.

No data was being decoded and new data is now being

•

decoded.

GS_VPS_PDC_UTC_CB_CHANGE, Enable Content­Based Updating for Gemstar/VPS/PDC/UTC,
Address 0x9C [5], User Sub Map

0—Disables content-based updating.

1 (default)—Enables content-based updating.

WSS_CGMS_CB_CHANGE, Enable Content-Based
Updating for WSS/CGMS, Address 0x9C [4],
User Sub Map

0—Disables content-based updating.

1 (default)—Enables content-based updating.

VDP—Interrupt-Based Reading of VDP I2C Registers

Some VDP status bits are also linked to the interrupt request
controller so that the user does not have to poll the AVAILABLE
status bit. The user can configure the video decoder to trigger
an interrupt request on the INTRQ pin in response to the valid
data available in I

2

C registers. This function is available for the

following data types:

•

CGMS or WSS: The user can select either triggering

an interrupt request each time sliced data is available
or triggering an interrupt request only when the
sliced data has changed. Selection is made via the
WSS_CGMS_CB_CHANGE bit.

Rev. A | Page 57 of 112

ADV7180

• Gemstar, PDC, VPS, or UTC: The user can select to

trigger an interrupt request each time sliced data is
available or to trigger an interrupt request only when
the sliced data has changed. Selection is made via the
GS_VPS_PDC_UTC_CB_ CHANGE bit.

The sequence for the interrupt-based reading of the VDP I

2

C

data registers is as follows for the CCAP standard:

User unmasks CCAP interrupt mask bit (0x50 Bit 0, User

1.
Sub Map = 1). CCAP data occurs on the incoming video.
VDP slices CCAP data and places it into the VDP readback
registers.

2.

The VDP CCAP AVAILABLE bit goes high, and the VDP

module signals to the interrupt controller to stimulate an
interrupt request (for CCAP in this case).

3.

The user reads the interrupt status bits (User Sub Map) and

sees that new CCAP data is available (0x4E Bit 0, User Sub
Map = 1).

4.

The user writes 1 to the CCAP interrupt clear bit (0x4F

Bit 0, User Sub Map = 1) in the interrupt I

2

C space (this is a
self-clearing bit). This clears the interrupt on the INTRQ
pin but does not have an effect in the VDP I

5.

The user reads the CCAP data from the VDP I
The user writes to Bit CC_CLEAR in the VDP_STATUS[0]

6.

2

C area.

2

C area.

register, (0x78 Bit 0, User Sub Map = 1) to signify the CCAP
data has been read (therefore the VDP CCAP can be
updated at the next occurrence of CCAP).

7. Back to Step 2.

Interrupt Mask Register Details

The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.

VDP_CCAPD_MSKB, Address 0x50 [0], User Sub Map

0 (default)—Disables interrupt on VDP_CCAPD_Q signal.

1—Enables interrupt on VDP_CCAPD_Q signal.

VDP_CGMS_WSS_CHNGD_MSKB, Address 0x50 [2],
User Sub Map

0 (default)—Disables interrupt on VDP_CGMS_WSS_
CHNGD_Q signal.

1—Enables interrupt on VDP_CGMS_WSS_CHNGD_Q
signal.

VDP_GS_VPS_PDC_UTC_CHNG_MSKB,
Address 0x50 [4], User Sub Map

0 (default)—Disables interrupt on
VDP_GS_VPS_PDC_UTC_CHNG_Q signal.

1—Enables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q
signal.

VDP_VITC_MSKB, Address 0x50 [6], User Sub Map

0 (default)—Disables interrupt on VDP_VITC_Q signal.

1—Enables interrupt on VDP_VITC_Q signal.

Interrupt Status Register Details

The following read-only bits contain data detection information
from the VDP module since the status bit was last cleared or
unmasked.

VDP_CCAPD_Q, Address 0x4E [0], User Sub Map

0 (default)—CCAP data has not been detected.

1—CCAP data has been detected.

VDP_CGMS_WSS_CHNGD_Q, Address 0x4E [2],
User Sub Map

0 (default)—CGMS or WSS data has not been detected.

1—CGM or WSS data has been detected.

VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E [4],
User Sub Map

0 (default)—Gemstar, PDC, UTC, or VPS data has not been
detected.

1—Gemstar, PDC, UTC, or VPS data has been detected.

VDP_VITC_Q, Address 0x4E [6], User Sub Map,
Read Only

0 (default)—VITC data has not been detected.

1—VITC data has been detected.

Interrupt Status Clear Register Details

It is not necessary to write 0 to these write-only bits because
they automatically reset after they have been set to 1 (self­clearing).

VDP_CCAPD_CLR, Address 0x4F [0], User Sub Map

1—Clears VDP_CCAP_Q bit.

VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F [2],
User Sub Map

1—Clears VDP_CGMS_WSS_CHNGD_Q bit.

VDP_GS_VPS_PDC_UTC_CHNG_CLR,
Address 0x4F [4], User Sub Map

1—Clears VDP_GS_VPS_PDC_UTC_CHNG_Q bit.

VDP_VITC_CLR, Address 0x4F [6], User Sub Map

1—Clears VDP_VITC_Q bit.

Rev. A | Page 58 of 112

ADV7180

I2C READBACK REGISTERS

Teletext

Because teletext is a high data rate standard, the decoded bytes
are available only as ancillary data. However, a TTXT_AVL bit
has been provided in I
VDP has detected teletext or not. Note that the TTXT_AVL bit
is a plain status bit and does not use the protocol identified in
the

I C Interface2 section.

TTXT_AVL, Teletext Detected Status, Address 0x78 [7],
User Sub Map, Read Only

0—Teletext was not detected.

1—Teletext was detected.

WST Packet Decoding

For WST only, the VDP decodes the magazine and row address
of teletext packets and further decodes the packet’s 8 × 4
hamming coded words. This feature can be disabled using the
WST_PKT_ DECODE_ DISABLE
Sub Map). This feature is valid for WST only.

2

C so that the user can check whether the

bit (Bit 3, Register 0x60, User

WST_PKT_DECODE_DISABLE, Disable Hamming
Decoding of Bytes in WST, Address 0x60 [3], User Sub
Map

0—Enables hamming decoding of WST packets.

1 (default)—Disables hamming decoding of WST packets.

For hamming-coded bytes, the dehammed nibbles are output
along with some error information from the hamming decoder
as follows:

•

Input hamming coded byte: {D3, P3, D2, P2, D1, P1, D0,

P0} (bits in decoded order)

•

Output dehammed byte: {E1, E0, 0, 0, D3', D2', D1', D0'}

(Di' – corrected bits, Ei error information).

Table 75. Error Bits in the Dehammed Output Byte

Output Data Bits

E[1:0] Error Information

00 No errors detected Okay
01 Error in P4 Okay
10 Double error Bad
11 Single error found and corrected Okay

in Nibble

Tabl e 76 describes the WST packets that are decoded.

Table 76. WST Packet Description

Packet Byte Description

Header Packet
(X/00)

Tex t Packets
(X/01 to X/25)

8/30 (Format 1) Packet
Design Code = 0000 or 0001
UTC

8/30 (Format 2) Packet
Design Code = 0010 or 0011
PDC

X/26, X/27, X/28, X/29, X/30, X/31

1

For X/26, X/28, and X/29 further decoding needs 24 × 18 hamming decoding. Not supported at present.

1

1st Magazine number—Dehammed Byte 4
2nd Row number—Dehammed Byte 5
3rd Page number—Dehammed Byte 6
4th Page number—Dehammed Byte 7
5th to 10th Control Bytes—Dehammed Byte 8 to Byte 13

th

to 42nd Raw data bytes

11
1st Magazine number—Dehammed Byte 4
2nd Row number—Dehammed Byte 5

rd

to 42nd Raw data bytes

3
1st Magazine number—Dehammed Byte 4
2nd Row number—Dehammed Byte 5
3rd Design Code—Dehammed Byte 6
4th to 10th Dehammed initial teletext page, Byte 7 to Byte 12
11th to 23rd UTC bytes—Dehammed Bytes 13 to Byte 25

th

to 42nd Raw status bytes

24
1st Magazine number—Dehammed Byte 4
2nd Row number—Dehammed Byte 5
3rd Design Code—Dehammed Byte 6
4th to 10th Dehammed initial teletext page, Byte 7 to Byte 12
11th to 23rd PDC bytes—Dehammed Byte 13 to Byte 25

th

to 42nd Raw status bytes

24
1st Magazine number—Dehammed Byte 4
2nd Row number—Dehammed Byte 5
3rd Design Code—Dehammed Byte 6
4th to 42nd Raw data bytes

Rev. A | Page 59 of 112

ADV7180

V

CGMS and WSS

The CGMS and WSS data packets convey the same type of
information for different video standards. WSS is for PAL and
CGMS is for NTSC, so the CGMS and WSS readback registers
are shared. WSS is biphase coded; the VDP does a biphase
decoding to produce the 14 raw WSS bits in the CGMS/WSS
readback I

2

C registers and to set the CGMS_WSS_AVL bit.

CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78 [2],
User Sub Map, Write Only, Self-Clearing

1—Reinitializes the CGMS/WSS readback registers.

VDP_CGMS_WSS_DATA_2

0 1 2 3 4 5 6 7 0 1 2 3 4 5

CODE

38.4µs

42.5µs

11.0 µs

RUN-IN

SEQUENCE

START

Figure 43. WSS Waveform

+100 IRE

+70 IRE

VDP_CGMS_WSS_DATA_2REF

012 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3

CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78 [2],
User Sub Map, Read Only

0—CGMS/WSS was not detected.

1—CGMS/WSS was detected.

CGMS_WSS_DATA_0[3:0], Address 0x7D [3:0];

CGMS_WSS_DATA_1[7:0], Address 0x7E [7:0];

CGMS_WSS_DATA_2[7:0], Address 0x7F [7:0];
User Sub Map, Read Only

These bits hold the decoded CGMS or WSS data.

Refer to

Figure 43 and Figure 44 for the I2C to WSS and CGMS

bit mapping.

DP_CGMS_WSS_

DATA_1[5:0]

ACTIVE

VIDEO

5700-039

VDP_CGMS_WSS_DATA_1

VDP_CGMS_WSS_
DATA_0[3:0]

0 IRE

–40 IRE

11.2 µs

2.235µs ± 20ns

Figure 44. CGMS Waveform

49.1µs ± 0.5µs

CRC SEQUENCE

05700-040

Table 77. CGMS Readback Registers

1

Signal Name Register Location Address (User Sub Map)

CGMS_WSS_DATA_0[3:0] VDP_CGMS_WSS_DATA_0[3:0] 125 0x7D
CGMS_WSS_DATA_1[7:0] VDP_CGMS_WSS_DATA_1[7:0] 126 0x7E
CGMS_WSS_DATA_2[7:0] VDP_CGMS_WSS_DATA_2[7:0] 127 0x7F

1

The register is a readback register; default value does not apply.

Rev. A | Page 60 of 112

ADV7180

CCAP

Two bytes of decoded closed caption data are available in the

2

I

C registers. The field information of the decoded CCAP data

can be obtained from the CC_EVEN_FIELD bit (Register 0x78).

CC_CLEAR, Closed Caption Clear, Address 0x78 [0],
User Sub Map, Write Only, Self-Clearing

1—Reinitializes the CCAP readback registers.

CC_AVL, Closed Caption Available, Address 0x78 [0],
User Sub Map, Read Only

0—Closed captioning was not detected.

1—Closed captioning was detected.

10.5 ± 0. 25µs 12.91µs

OF 0.5035MHz

(CLOCK RUN -IN)

50 IRE

7CYCLES

CC_EVEN_FIELD, Address 0x78 [1], User Sub Map,
Read Only

Identifies the field from which the CCAP data was decoded.

0—Closed captioning was detected on an odd field.

1—Closed captioning was detected on an even field.

VDP_CCAP_DATA_0, Address 0x79 [7:0], User Sub Map,
Read Only

Decoded Byte 1 of CCAP data.

VDP_CCAP_DATA_1, Address 0x7A [7:0], User Sub Map,
Read Only

Decoded Byte 2 of CCAP data.

0

1

2 3 4 5 6 7 0 1 2 3 4 5 67
S
T
A
R
T

P
A
R

I
T
Y

P
A
R

I
T
Y

40 IRE

REFERENCE CO LOR BURST

FREQUENCY = F

(9 CYCLES)

= 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003µs

27.382µs

VDP_CCAP_D ATA_0

33.764µs

VDP_CCAP_D ATA_1

05700-041

Figure 45. CCAP Waveform and Decoded Data Correlation

Table 78. CCAP Readback Registers

1

Signal Name Register Location Address (User Sub Map)
CCAP_BYTE_1[7:0] VDP_CCAP_DATA_0[7:0] 121 0x79
CCAP_BYTE_2[7:0] VDP_CCAP_DATA_1[7:0] 122 0x7A

1

The register is a readback register; default value does not apply.

Rev. A | Page 61 of 112

ADV7180

VITC

VITC has a sequence of 10 syncs in between each data byte.
The VDP strips these syncs from the data stream to output
only the data bytes. The VITC results are available in Register
VDP_VITC_DATA_0 to Register VDP_VITC_DATA_8
(Register 0x92 to Register 0x9A, User Sub Map).

The VITC has a CRC byte at the end; the syncs in between each
data byte are also used in this CRC calculation. Because the
syncs in between each data byte are not output, the CRC is
calculated internally. The calculated CRC is available for the
user in the VITC_CALC_CRC register (Resister 0x9B, User Sub
Map). Once the VDP completes decoding the VITC line, the
VITC_DATA and VITC_CALC_CRC registers are updated and
the VITC_AVL bit is set.

VITC_CLEAR, VITC Clear, Address 0x78 [6],
User Sub Map, Write Only, Self-Clearing

1—Reinitializes the VITC readback registers.

VITC_AVL, VITC Available, Address 0x78 [6],
User Sub Map

0—VITC data was not detected.

1—VITC data was detected.

VITC Readback Registers

See Figure 46 for the I2C to VITC bit mapping.

BIT0, BI T1 BIT88, BI T89

Figure 46. VITC Waveform and Decoded Data Correlation

TO

VITC WAVEFORM

05700-042

Table 79. VITC Readback Registers

1

Signal Name Register Location Address (User Sub Map)

VITC_DATA_0[7:0] VDP_VITC_DATA_0[7:0] (VITC Bits [9:2]) 146 0x92
VITC_DATA_1[7:0] VDP_VITC_DATA_1[7:0] (VITC Bits [19:12]) 147 0x93
VITC_DATA_2[7:0] VDP_VITC_DATA_2[7:0] (VITC Bits [29:22]) 148 0x94
VITC_DATA_3[7:0] VDP_VITC_DATA_3[7:0] (VITC Bits [39:32]) 149 0x95
VITC_DATA_4[7:0] VDP_VITC_DATA_4[7:0] (VITC Bits [49:42]) 150 0x96
VITC_DATA_5[7:0] VDP_VITC_DATA_5[7:0] (VITC Bits [59:52]) 151 0x97
VITC_DATA_6[7:0] VDP_VITC_DATA_6[7:0] (VITC Bits [69:62]) 152 0x98
VITC_DATA_7[7:0] VDP_VITC_DATA_7[7:0] (VITC Bits [79:72]) 153 0x99
VITC_DATA_8[7:0] VDP_VITC_DATA_8[7:0] (VITC Bits [89:82]) 154 0x9A
VITC_CALC_CRC[7:0] VDP_VITC_CALC_CRC[7:0] 155 0x9B

1

The register is a readback register; default value does not apply.

Rev. A | Page 62 of 112

ADV7180

VPS/PDC/UTC/GEMSTAR

The readback registers for VPS, PDC, and UTC are shared.
Gemstar is a high data rate standard and is available only
through the ancillary stream. However, for evaluation purposes,
any one line of Gemstar is available through the I

2

C registers
sharing the same register space as PDC, UTC, and VPS.
Therefore, only VPS, PDC, UTC, or Gemstar can be read
through the I

To identify the data that should be made available in the I
registers, the user must program I

2

C at a time.

2

2

C_GS_VPS_PDC_UTC[1:0]

C

(Register Address 0x9C, User Sub Map).

I2C_GS_VPS_PDC_UTC [1:0] (VDP), Address 0x9C [6:5],
User Sub Map

Specifies which standard result is available for I2C readback.

GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear,
Address 0x78 [4], User Sub Map, Write Only, Self-Clearing

1—Reinitializes the GS/PDC/VPS/UTC data readback registers.

GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available,
Address 0x78 [4], User Sub Map, Read Only

0—One of GS, PDC, VPS, or UTC data was not detected.

1—One of GS, PDC, VPS, or UTC data was detected.

VDP_GS_VPS_PDC_UTC, Readback Registers,
Addresses 0x84 to 0x87

See Tab le 8 1.

VPS

The VPS data bits are biphase decoded by the VDP. The
decoded data is available in both the ancillary stream and in the

2

I

C readback registers. VPS decoded data is available in the
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers (Address 0x84 to Address 0x90, User Sub Map). The
GS_VPS_ PDC_UTC_AVL bit is set if the user programmed

2

I

C_GS_VPS_PDC_UTC to 01, as explained in Tab l e 8 0 .

GEMSTAR

The Gemstar-decoded data is made available in the ancillary

2

stream, and any one line of Gemstar is also available in the I

C
registers for evaluation purposes. To read Gemstar results
through the I

2

I

C_GS_VPS_PDC_UTC to 00, as explained in Tab l e 8 0 .

2

C registers, the user must program

Table 80. I2C_GS_VPS_PDC_UTC[1:0] Function

I2C_GS_VPS_PDC_UTC[1:0] Description

00 (default) Gemstar 1×/2×
01 VPS
10 PDC
11 UTC

VDP supports autodetection of the Gemstar standard, either
Gemstar 1× or Gemstar 2×, and decodes accordingly. For the
autodetection mode to work, the user must set the
AUTO_DETECT_GS_TYPE I

2

C bit (Register 0x61, User
Sub Map) and program the decoder to decode Gemstar 2× on
the required lines through line programming. The type of
Gemstar decoded can be determined by observing the
GS_DATA_TYPE bit (Register 0x78, User Sub Map).

AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map

0 (default)—Disables autodetection of Gemstar type.

1—Enables autodetection of Gemstar type.

GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only

Identifies the decoded Gemstar data type.

0—Gemstar 1× mode is detected. Read 2 data bytes from 0x84.

1—Gemstar 2× mode is detected. Read 4 data bytes from 0x84.

2

The Gemstar data that is available in the I

C register could be
from any line of the input video on which Gemstar was
decoded. To read the Gemstar data on a particular video line,
the user should use the manual configuration described in
Tabl e 66 and Table 6 7 and enable Gemstar decoding only on the
required line.

PDC/UTC

PDC and UTC are data transmitted through Teletext Packet 8/30
Format 2 (Magazine 8, Row 30, Design Code 2 or 3), and Packet
8/30 Format 1 (Magazine 8, Row 30, Design Code 0 or 1). Thus,
if PDC or UTC data is to be read through I

2

C, the corresponding
teletext standard (WST or PAL System B) should be decoded by
VDP. The whole teletext decoded packet is output on the ancillary
data stream. The user can look for the magazine number, row
number, and design code and qualify the data as PDC, UTC, or
neither of these.

If PDC/UTC packets have been identified, Byte 0 to Byte 12 are
updated to the GS_VPS_PDC_UTC_0 to VPS_PDC_UTC_12
registers, and the GS_VPS_PDC_UTC_AVL bit is set. The full
packet data is also available in the ancillary data format.

2

Note that the data available in the I

C register depends on the
status of the WST_PKT_DECODE_DISABLE bit (Bit 3,
Subaddress 0x60, User Sub Map).

Rev. A | Page 63 of 112

ADV7180

Table 81. GS/VPS/PDC/UTC Readback Registers

Signal Name Register Location Dec Address (User Sub Map) Hex Address (User Sub Map)

GS_VPS_PDC_UTC_BYTE_0[7:0] VDP_GS_VPS_PDC_UTC_0[7:0] 132d 0x84
GS_VPS_PDC_UTC_BYTE_1[7:0] VDP_GS_VPS_PDC_UTC_1[7:0] 133d 0x85
GS_VPS_PDC_UTC_BYTE_2[7:0] VDP_GS_VPS_PDC_UTC_2[7:0] 134d 0x86
GS_VPS_PDC_UTC_BYTE_3[7:0] VDP_GS_VPS_PDC_UTC_3[7:0] 135d 0x87
VPS_PDC_UTC_BYTE_4[7:0] VDP_VPS_PDC_UTC_4[7:0] 136d 0x88
VPS_PDC_UTC_BYTE_5[7:0] VDP_VPS_PDC_UTC_5[7:0] 137d 0x89
VPS_PDC_UTC_BYTE_6[7:0] VDP_VPS_PDC_UTC_6[7:0] 138d 0x8A
VPS_PDC_UTC_BYTE_7[7:0] VDP_VPS_PDC_UTC_7[7:0] 139d 0x8B
VPS_PDC_UTC_BYTE_8[7:0] VDP_VPS_PDC_UTC_8[7:0] 140d 0x8C
VPS_PDC_UTC_BYTE_9[7:0] VDP_VPS_PDC_UTC_9[7:0] 141d 0x8D
VPS_PDC_UTC_BYTE_10[7:0] VDP_VPS_PDC_UTC_10[7:0] 142d 0x8E
VPS_PDC_UTC_BYTE_11[7:0] VDP_VPS_PDC_UTC_11[7:0] 143d 0x8F
VPS_PDC_UTC_BYTE_12[7:0] VDP_VPS_PDC_UTC_12[7:0] 144d 0x90

1

The default value does not apply to readback registers.

VBI System 2

The user has an option of using a different VBI data slicer called
VBI System 2. This data slicer is used to decode Gemstar and
closed caption VBI signals only.

Using this system, the Gemstar data is only available in the
ancillary data stream. A special mode enables one line of data to
be read back through I

2

C. For details about using I2C readback
with the VBI System 2 data slicer, contact local Analog Devices
field applications engineers or local Analog Devices distributor.

Gemstar Data Recovery

The Gemstar-compatible data recovery block (GSCD) supports
1× and 2× data transmissions. In addition, it can serve as a
closed caption decoder. Gemstar-compatible data transmissions
can occur only in NTSC. Closed caption data can be decoded in
both PAL and NTSC.

The block can be configured via I

2

C as follows:

• GDECEL[15:0] allows data recovery on selected video lines

on even fields to be enabled or disabled.

GDECOL[15:0] enables the data recovery on selected lines

•

for odd fields.

•

GDECAD configures the way in which data is embedded

in the video data stream.

The recovered data is not available through I

2

C, but is inserted into
the horizontal blanking period of an ITU-R BT.656-compatible
data stream. The data format is intended to comply with the
recommendation by the International Telecommunications
Union, ITU-R BT.1364. For more information, visit the
International Telecommunication Union website. See

1

Figure 47.

GDE_SEL_OLD_ADF, Address 0x4C [3], User Sub Map

The ADV7180 has a new ancillary data output block that can be
used by the VDP data slicer and the VBI System 2 data slicer.
The new ancillary data formatter is used by setting
GDE_SEL_OLD_ADF to 0 (default). If this bit is set low, refer
to

Tabl e 70 and Tabl e 71 for information about how the data is

packaged in the ancillary data stream.

To use the old ancillary data formatter (to be backward compatible
with the ADV7183B), set GDE_SEL_OLD_ADF to 1. The ancillary
data format in this section refers to the ADV7183B-compatible
ancillary data formatter.

0 (default)—Enables new ancillary data system for use with
VDP and VBI System 2.

1—Enables old ancillary data system for use with VBI System 2
only (ADV7183B compatible).

The format of the data packet depends on the following criteria:

Transmission is 1× or 2×.

•

• Data is output in 8-bit or 4-bit format (see the description

of the bit).

•

Data is closed caption (CCAP) or Gemstar compatible.

Data packets are output if the corresponding enable bit is set
(see the GDECEL[15:0] and GDECOL[15:0] descriptions) the
decoder detects the presence of data. This means that for video
lines where no data has been decoded, no data packet is output
even if the corresponding line enable bit is set.

Rev. A | Page 64 of 112

ADV7180

Each data packet starts immediately after the EAV code of the
preceding line.

Figure 47 and Tab l e 82 show the overall

structure of the data packet.

Entries within the packet are as follows:

Fixed preamble sequence of 0x00, 0xFF, and 0xFF.

•

Data identification word (DID). The value for the DID

•

marking a Gemstar or CCAP data packet is 0x140 (10-bit
value).

Secondary data identification word (SDID), which contains

•

information about the video line from which data was
retrieved, whether the Gemstar transmission was of 1× or
2× format, and whether it was retrieved from an even or
odd field.

DATA IDENTIFICATION

SECONDARY DATAIDENTIFICATION

•

Data count byte, giving the number of user data-words that

follow.

User dat a section.

•

Optional padding to ensure that the length of the user

•

data-word section of a packet is a multiple of 4 bytes
(requirement as set in ITU-R BT.1364).

Checksum byte.

•

Tabl e 82 lists the values within a generic data packet that is
output by the ADV7180 in 8-bit format.

00 FF FF DID SDID

PREAMBLE FO R ANCILLARY DATA

Figure 47. Gemstar and CCAP Embedded Data Packet (Generic)

DATA

COUNT

USER DATA

USER DATA (4 OR 8 WORDS)

OPTIONAL PADDING

BYTES

CHECK

SUM

05700-043

Table 82. Generic Data Output Packet

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6

7

8

9

10

11

12

13

14

EP

EP

EP

EP

EP

EP

EP

EP

EP

EP

CS[8]

EP EF 2X 0 0 SDID

line[3:0]
EP 0 0 0 0 DC[1] DC[0] 0 0 Data count (DC)

EP 0 0 0 0

EP 0 0 0 0 User data-words

EP 0 0 0 0 User data-words

EP 0 0 0 0 User data-words

EP 0 0 0 0 User data-words

EP 0 0 0 0 User data-words

EP 0 0 0 0 User data-words

EP 0 0 0 0 User data-words

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] 0 0 Checksum

word1[7:4] User data-words

word1[3:0]

word2[7:4]

word2[3:0]

word3[7:4]

word3[3:0]

word4[7:4]

word4[3:0]

Table 83. Data Byte Allocation

Raw Information Bytes

2× GDECAD Padding Bytes DC[1:0]

Retrieved from the Video Line

User Data-Words
(Including Padding)

1 4 0 8 0 10
1 4 1 4 0 01
0 2 0 4 0 01
0 2 1 4 2 01

Rev. A | Page 65 of 112

ADV7180

Gemstar Bit Names

• DID—The data identification value is 0x140 (10-bit value).

Care has been taken so that in 8-bit systems, the two LSBs
do not carry vital information.

•

EP and

EP

—The EP bit is set to ensure even parity on
data-word D[8:0]. Even parity means there is always an
even number of 1s within the D[8:0] bit arrangement. This
includes the EP bit.
and is output on D[9]. The

EP

describes the logic inverse of EP

EP

is output to ensure that the

reserved codes of 00 and FF do not occur.

•

EF—Even field identifier. EF = 1 indicates that the data was

recovered from a video line on an even field.

•

2×—This bit indicates whether the data sliced was in

Gemstar 1× or 2× format. A high indicates 2× format.
The 2× bit determines whether the raw information
retrieved from the video line was two bytes or four bytes.
The state of the GDECAD bit affects whether the bytes are
transmitted straight (that is, two bytes transmitted as two
bytes) or whether they are split into nibbles (that is, two
bytes transmitted as four half bytes). Padding bytes are
then added where necessary.

•

line[3:0]—This entry provides a code that is unique for

each of the possible 16 source lines of video from which
Gemstar data may have been retrieved. Refer to
and

Tabl e 93 .

Tabl e 92

•

DC[1:0]—Data count value. The number of UDWs in the

packet divided by 4. The number of UDWs in any packet
must be an integral number of 4. Padding may be required
at the end, as set in ITU-R BT.1364. See

•

CS[8:2]—The checksum is provided to determine the

Tabl e 83 .

integrity of the ancillary data packet. It is calculated by
summing up D[8:2] of DID, SDID, the data count byte, and
all UDWs, and ignoring any overflow during the
summation. Because all data bytes that are used to
calculate the checksum have their 2 LSBs set to 0, the
CS[1:0] bits are also always 0.

CS

[8]—describes the logic inversion of CS[8]. The value CS[8]
is included in the checksum entry of the data packet to ensure
that the reserved values of 0x00 and 0xFF do not occur.

Tabl e 84 to Tabl e 8 9 outline the possible data packages.

Gemstar_2× Format, Half-Byte Output Mode

Half-byte output mode is selected by setting CDECAD to 0;
full-byte output mode is selected by setting CDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C [0] section.

Gemstar_1× Format

Half-byte output mode is selected by setting CDECAD to 0,
full-byte output mode is selected by setting CDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C [0] section.

Table 84. Gemstar_2× Data, Half-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6

7

8

9

10

11

12

13

14

EP

EP

EP

EP

EP

EP

EP

EP

EP

EP

CS[8]

EP EF 1

EP 0 0 0 0 1 0 0 0 Data count

EP 0 0

EP 0 0

EP 0 0

EP 0 0

EP 0 0

EP 0 0

EP 0 0

EP 0 0

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

line[3:0]

Gemstar word1[7:4]

Gemstar word1[3:0]

Gemstar word2[7:4]

Gemstar word2[3:0]

Gemstar word3[7:4]

Gemstar word3[3:0]

Gemstar word4[7:4]

Gemstar word4[3:0]

0 0 SDID

0 0

0 0 User data-words

0 0 User data-words

0 0 User data-words

0 0 User data-words

0 0 User data-words

0 0 User data-words

0 0 User data-words

User data-words

Rev. A | Page 66 of 112

ADV7180

Table 85. Gemstar_2× Data, Full-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6 Gemstar word1[7:0] 0 0 User data-words
7 Gemstar word2[7:0] 0 0 User data-words
8 Gemstar word3[7:0] 0 0 User data-words
9 Gemstar word4[7:0] 0 0 User data-words
10

EP

EP

CS[8]

Table 86. Gemstar_1× Data, Half-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6

7

8

9

10

EP

EP

EP

EP

EP

EP

CS[8]

EP EF 1

EP 0 0 0 0 0 1 0 0 Data count

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

EP EF 0

EP 0 0 0 0 0 1 0 0 Data count

EP 0 0

EP 0 0

EP 0 0

EP 0 0

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

line[3:0]

line[3:0]

Gemstar word1[7:4]

Gemstar word1[3:0]

Gemstar word2[7:4]

Gemstar word2[3:0]

0 0 SDID

0 0 SDID

0 0

0 0 User data-words

0 0 User data-words

0 0 User data-words

User data-words

Table 87. Gemstar_1× Data, Full-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6 Gemstar word1[7:0] 0 0 User data-words
7 Gemstar word2[7:0] 0 0 User data-words
8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200
9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200
10

EP

EP

CS[8]

EP EF 0

EP 0 0 0 0 0 1 0 0 Data count

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

line[3:0]

0 0 SDID

Rev. A | Page 67 of 112

ADV7180

Table 88. NTSC CCAP Data, Half-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6

7

8

9

10

EP

EP

EP

EP

EP

EP

CS[8]

Table 89. NTSC CCAP Data, Full-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6 CCAP word1[7:0] 0 0 User data-words
7 CCAP word2[7:0] 0 0 User data-words
8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200
9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200
10

EP

EP

CS[8]

EP EF 0 1 0 1 1 0 0 SDID

EP 0 0 0 0 0 1 0 0 Data count

EP 0 0

EP 0 0

EP 0 0

EP 0 0

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

EP EF 0 1 0 1 1 0 0 SDID

EP 0 0 0 0 0 1 0 0 Data count

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

CCAP word1[7:4]

CCAP word1[3:0]

CCAP word2[7:4]

CCAP word2[3:0]

0 0

0 0 User data-words

0 0 User data-words

0 0 User data-words

User data-words

Rev. A | Page 68 of 112

ADV7180

Table 90. PAL CCAP Data, Half-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6

7

8

9

10

EP

EP

EP

EP

EP

EP

CS[8]

Table 91. PAL CCAP Data, Full-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description

0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4

5

6 CCAP word1[7:0] 0 0 User data-words
7 CCAP word2[7:0] 0 0 User data-words
8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200
9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200
10

EP

EP

CS[8]

NTSC CCAP Data

Half-byte output mode is selected by setting CDECAD to 0, and
the full-byte mode is enabled by setting CDECAD to 1. See the
GDECAD, Gemstar Decode Ancillary Data Format, Address
0x4C [0]
and

section. The data packet formats are shown in Tab le 8 8

Tabl e 89 . Only closed caption data can be embedded in the

output data stream.

NTSC closed caption data is sliced on Line 21d of even and odd
fields. The corresponding enable bit has to be set high. See the
GDECAD, Gemstar Decode Ancillary Data Format, Address
0x4C [0] section and the GDECOL[15:0], Gemstar Decoding
Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0] section.

PAL CCAP Data

Half-byte output mode is selected by setting CDECAD to 0, and
full-byte output mode is selected by setting CDECAD to 1. See
the GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C [0] section. Tab l e 9 0 and Tab l e 9 1 list the bytes of
the data packet.

Only closed caption data can be embedded in the output data
stream. PAL closed caption data is sliced from Line 22 and
Line 335. The corresponding enable bits must be set.

EP EF 0 1 0 1 0 0 0 SDID

EP 0 0 0 0 0 1 0 0 Data count

EP 0 0

EP 0 0

EP 0 0

EP 0 0

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

EP EF 0 1 0 1 0 0 0 SDID

EP 0 0 0 0 0 1 0 0 Data count

CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

CCAP word1[7:4]

CCAP word1[3:0]

CCAP word2[7:4]

CCAP word2[3:0]

0 0

0 0 User data-words

0 0 User data-words

0 0 User data-words

User data-words

See the GDECEL[15:0], Gemstar Decoding Even Lines,
Address 0x48 [7:0], Address 0x49 [7:0] section and the
GDECOL[15:0], Gemstar Decoding Odd Lines, Address 0x4A
[7:0], Address 0x4B [7:0] section.

GDECEL[15:0], Gemstar Decoding Even Lines,
Address 0x48 [7:0], Address 0x49 [7:0]

The 16 bits of GDECEL[15:0] are interpreted as a collection of
16 individual line decode enable signals. Each bit refers to a line
of video in an even field. Setting the bit enables the decoder
block trying to find Gemstar or closed caption-compatible data
on that particular line. Setting the bit to 0 prevents the decoder
from trying to retrieve data. See Tabl e 92 and Ta ble 9 3.

To retrieve closed caption data services on NTSC (Line 284),
GDECEL[11] must be set.

To retrieve closed caption data services on PAL (Line 335),
GDECEL[14] must be set.

The default value of GDECEL[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the even field. The user should only
enable Gemstar slicing on lines where VBI data is expected.

Rev. A | Page 69 of 112

ADV7180

Table 92. NTSC Line Enable Bits and Corresponding
Line Numbering

Line Number

line[3:0]

0 10 GDECOL[0] Gemstar
1 11 GDECOL[1] Gemstar
2 12 GDECOL[2] Gemstar
3 13 GDECOL[3] Gemstar
4 14 GDECOL[4] Gemstar
5 15 GDECOL[5] Gemstar
6 16 GDECOL[6] Gemstar
7 17 GDECOL[7] Gemstar
8 18 GDECOL[8] Gemstar
9 19 GDECOL[9] Gemstar
10 20 GDECOL[10] Gemstar
11 21 GDECOL[11]

12 22 GDECOL[12] Gemstar
13 23 GDECOL[13] Gemstar
14 24 GDECOL[14] Gemstar
15 25 GDECOL[15] Gemstar
0 273 (10) GDECEL[0] Gemstar
1 274 (11) GDECEL[1] Gemstar
2 275 (12) GDECEL[2] Gemstar
3 276 (13) GDECEL[3] Gemstar
4 277 (14) GDECEL[4] Gemstar
5 278 (15) GDECEL[5] Gemstar
6 279 (16) GDECEL[6] Gemstar
7 280 (17) GDECEL[7] Gemstar
8 281 (18) GDECEL[8] Gemstar
9 282 (19) GDECEL[9] Gemstar
10 283 (20) GDECEL[10] Gemstar
11 284 (21) GDECEL[11]

12 285 (22) GDECEL[12] Gemstar
13 286 (23) GDECEL[13] Gemstar
14 287 (24) GDECEL[14] Gemstar
15 288 (25) GDECEL[15] Gemstar

(ITU-R BT.470)

Enable Bit Comment

Gemstar or
closed caption

Gemstar or
closed caption

GDECOL[15:0], Gemstar Decoding Odd Lines,
Address 0x4A [7:0], Address 0x4B [7:0]

The 16 bits of GDECOL[15:0] form a collection of 16 individual
line decode enable signals. See Ta ble 9 2 and Ta b l e 93 .

To retrieve closed caption data services on NTSC (Line 21),
GDECOL[11] must be set.

To retrieve closed caption data services on PAL (Line 22),
GDECOL[14] must be set.

The default value of GDECOL[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the odd field. The user should only
enable Gemstar slicing on lines where VBI data is expected.

Rev. A | Page 70 of 112

GDECAD, Gemstar Decode Ancillary Data Format,
Address 0x4C [0]

The decoded data from Gemstar-compatible transmissions or
closed caption-compatible transmission is inserted into the
horizontal blanking period of the respective line of video. A
potential problem can arise if the retrieved data bytes have a
value of 0x00 or 0xFF. In an ITU-R BT.656-compatible data
stream, these values are reserved and used only to form a fixed
preamble. The GDECAD bit allows the data to be inserted into
the horizontal blanking period in two ways:

•

Insert all data straight into the data stream, even the

reserved values of 0x00 and 0xFF, if they occur. This may
violate output data format specification ITU-R BT.1364.

Split all data into nibbles and insert the half-bytes over

•

double the number of cycles in a 4-bit format.

0 (default)—The data is split into half-bytes and inserted.

1—The data is output straight into the data stream in 8-bit format.

Table 93. PAL Line Enable Bits and Line Numbering

Line Number

line[3:0]

12 8 GDECOL[0] Not valid
13 9 GDECOL[1] Not valid
14 10 GDECOL[2] Not valid
15 11 GDECOL[3] Not valid
0 12 GDECOL[4] Not valid
1 13 GDECOL[5] Not valid
2 14 GDECOL[6] Not valid
3 15 GDECOL[7] Not valid
4 16 GDECOL[8] Not valid
5 17 GDECOL[9] Not valid
6 18 GDECOL[10] Not valid
7 19 GDECOL[11] Not valid
8 20 GDECOL[12] Not valid
9 21 GDECOL[13] Not valid
10 22 GDECOL[14] Closed caption
11 23 GDECOL[15] Not valid
12 321 (8) GDECEL[0] Not valid
13 322 (9) GDECEL[1] Not valid
14 323 (10) GDECEL[2] Not valid
15 324 (11) GDECEL[3] Not valid
0 325 (12) GDECEL[4] Not valid
1 326 (13) GDECEL[5] Not valid
2 327 (14) GDECEL[6] Not valid
3 328 (15) GDECEL[7] Not valid
4 329 (16) GDECEL[8] Not valid
5 330 (17) GDECEL[9] Not valid
6 331 (18) GDECEL[10] Not valid
7 332 (19) GDECEL[11] Not valid
8 333 (20) GDECEL[12] Not valid
9 334 (21) GDECEL[13] Not valid
10 335 (22) GDECEL[14] Closed caption
11 336 (23) GDECEL[15] Not valid

(ITU-R BT.470)

Enable Bit Comment

ADV7180

Letterbox Detection

Incoming video signals may conform to different aspect ratios
(16:9 wide screen or 4:3 standard). For certain transmissions in
the wide-screen format, a digital sequence (WSS) is transmitted
with the video signal. If a WSS sequence is provided, the aspect
ratio of the video can be derived from the digitally decoded bits
that WSS contains.

In the absence of a WSS sequence, letterbox detection can be
used to find wide-screen signals. The detection algorithm
examines the active video content of lines at the start and end of
a field. If black lines are detected, this may indicate that the
currently shown picture is in wide-screen format.

The active video content (luminance magnitude) over a line of
video is summed together. At the end of a line, this accumulated
value is compared with a threshold, and a decision is made as to
whether or not a particular line is black. The threshold value
needed may depend on the type of input signal; some control is
provided via LB_TH[4:0].

Detection at the Start of a Field

The ADV7180 expects a section of at least six consecutive black
lines of video at the top of a field. Once those lines are detected,
Register LB_LCT[7:0] reports the number of black lines that
were actually found. By default, the ADV7180 starts looking for
those black lines in sync with the beginning of active video, for
example, immediately after the last VBI video line. LB_SL[3:0]
allows the user to set the start of letterbox detection from the
beginning of a frame on a line-by-line basis. The detection
window closes in the middle of the field.

Detection at the End of a Field

The ADV7180 expects at least six continuous lines of black video
at the bottom of a field before reporting the number of lines
actually found via the LB_LCB[7:0] value. The activity window
for letterbox detection (end of field) starts in the middle of an
active field. Its end is programmable via LB_EL[3:0].

Detection at the Midrange

Some transmissions of wide-screen video include subtitles
within the lower black box. If the ADV7180 finds at least two
black lines followed by some more nonblack video, for example,
the subtitle followed by the remainder of the bottom black
block, it reports a midcount via LB_LCM[7:0]. If no subtitles are
found, LB_LCM[7:0] reports the same number as LB_LCB[7:0].

There is a 2-field delay in reporting any line count parameter.

There is no letterbox detected bit. Read the LB_LCT[7:0] and
LB_LCB[7:0] register values to determine whether or not the
letterbox-type video is present in software.

LB_LCT[7:0], Letterbox Line Count Top, Address 0x9B
[7:0]; LB_LCM[7:0], Letterbox Line Count Mid,
Address 0x9C [7:0]; LB_LCB[7:0], Letterbox Line Count
Bottom, Address 0x9D [7:0]

Table 94. LB_LCx Access Information

Signal Name Address

LB_LCT[7:0] 0x9B
LB_LCM[7:0] 0x9C
LB_LCB[7:0] 0x9D

LB_TH[4:0], Letterbox Threshold Control,
Address 0xDC [4:0]

Table 95. LB_TH Function

LB_TH[4:0] Description

01100 (default) Default threshold for detection of black lines.
01101 to 10000

00000 to 01011

Increase threshold (need larger active video
content before identifying nonblack lines).

Decrease threshold (even small noise levels
can cause the detection of nonblack lines).

LB_SL[3:0], Letterbox Start Line, Address 0xDD [7:4]

The LB_SL[3:0] bits are set at 0100 by default. For an NTSC
signal, this window is from Line 23 to Line 286.

By changing the bits to 0101, the detection window starts on
Line 24 and ends on Line 287.

LB_EL[3:0], Letterbox End Line, Address 0xDD [3:0]

The LB_EL[3:0] bits are set at 1101 by default. This means that the
letterbox detection window ends with the last active video line.
For an NTSC signal, this window is from Line 262 to Line 525.

By changing the bits to 1100, the detection window starts on
Line 261 and ends on Line 254.

Rev. A | Page 71 of 112

ADV7180

PIXEL PORT CONFIGURATION

The ADV7180 has a very flexible pixel port that can be
configured in a variety of formats to accommodate downstream
ICs.

Tabl e 96 , Table 9 7, and Tab l e 98 summarize the various
functions that the ADV7180 pins can have in different modes of
operation.

The ordering of components, for example, Cr vs. Cb for
Channels A, B, and C can be changed. Refer to the SWPC, Swap
Pixel Cr/Cb, Address 0x27 [7] section. Ta ble 96 indicates the
default positions for the Cr/Cb components.

OF_SEL[3:0], Output Format Selection, Address 0x03 [5:2]

The modes in which the ADV7180 pixel port can be configured
are under the control of OF_SEL[3:0]. See

The default LLC frequency output on the LLC1 pin is approxi­mately 27 MHz. For modes that operate with a nominal data rate
of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin
stays at the higher rate of 27 MHz. For information on outputting
the nominal 13.5 MHz clock on the LLC1 pin, see the section
LLC_PAD_SEL[2:0], LLC1 Output Selection,
Address 0x8F [6:4].

Tabl e 98 for details.

SWPC, Swap Pixel Cr/Cb, Address 0x27 [7]

This bit allows Cr and Cb samples to be swapped.

When SWPC is 0 (default), no swapping is allowed.

When SWPC is 1, the Cr and Cb values can be swapped.

LLC_PAD_SEL[2:0], LLC1 Output Selection,
Address 0x8F [6:4]

The following I2C write allows the user to select between LLC1
(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).

The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See the OF_SEL[3:0], Output Format
Selection, Address 0x03 [5:2] section for additional information.
The LLC2 signal and data on the data bus are synchronized.
By default, the rising edge of LLC1/LLC2 is aligned with the
Y data; the falling edge occurs when the data bus holds C data.
The polarity of the clock, and therefore the Y/C assignments to
the clock edges, can be altered by using the polarity LLC pin.

When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC1 pin (default).

When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC2 pin.

Table 96. ADV7180 LQFP-64 P15 to P0 Output/Input Pin Mapping

Data Port Pins P[15:0]

Format and Mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Video Out, 8-Bit, 4:2:2 YCrCb[7:0]OUT
Video Out, 16-Bit, 4:2:2 Y[7:0]OUT CrCb[7:0]OUT

Table 97. ADV7180 LFCSP-40 P7 to P0 Output/Input Pin Mapping

Data Port Pins P[7:0]
Format and Mode 7 6 5 4 3 2 1 0

Video Out, 8-Bit, 4:2:2 YCrCb[7:0]OUT

Table 98. ADV7180 Standard Definition Pixel Port Modes

ADV7180 LQFP-64 P[15: 0] ADV7180 LFCSP-40
OF_SEL[3:0] Format P[15:8] P[7: 0] P[7: 0]

0000 to 0001 Reserved Reserved, do not use
0010 16-bit @ LLC2 4:2:2 Y[7:0] CrCb[7:0] Not valid
0011 (Default) 8-bit @ LLC1 4:2:2 (default) YCrCb[7:0] Three-state YCrCb[7:0]
0100 to 1111 Reserved Reserved, do not use

Rev. A | Page 72 of 112

ADV7180

GPO CONTROL

The ADV7180 LQFP-64 has four general-purpose outputs
(GPO). These outputs allow the user to control other devices in
a system via the I

2

C port of the ADV7180 LQFP-64.

The ADV7180 LFCSP-40 does not have GPO pins.

GPO_Enable, General Purpose Output Enable,
Address 0x59[4]

When GPO_Enable is set to 0, all four GPO pins are three-stated.

When GPO_Enable is set to 1, all four GPO pins are in a driven
state. The polarity output from each GPO is controlled by
GPO[3:0].

GPO[3:0], General Purpose Outputs, Address 0x59 [3:0]

Individual control of the four GPO ports is achieved using
GPO[3:0].

GPO_Enable must be set to 1 for the GPO pins to become
active.

GPO[0]

When GPO[0] is set to 0, a Logic Level 0 is output from the
GPO0 pin [Pin 13]

When GPO[0] is set to 1, a Logic Level 1 is output from the
GPO0 pin.

GPO[1]

When GPO[1] is set to 0, a Logic Level 0 is output from the
GPO1 pin [Pin 12].

When GPO[1] is set to 1, a Logic Level 1 is output from the
GPO1 pin.

GPO[2]

When GPO[2] is set to 0, a Logic Level 0 is output from the
GPO2 pin [Pin 56].

When GPO[2] is set to 1, a Logic Level 1 is output from the
GPO2 pin.

GPO[3]

When GPO[3] is set to 0, a Logic Level 0 is output from the
GPO3 pin [Pin 55].

When GPO[3] is set to 1, a Logic Level 1 is output from the
GPO3 pin.

Table 99. General-Purpose Output Truth Table

GPO_Enable GPO[3:0] GPO3 GPO2 GPO1 GPO0

0 XXXX Z Z Z Z
1 0000 0 0 0 0
1 0001 0 0 0 1
1 0010 0 0 1 0
1 0011 0 0 1 1
1 0100 0 1 0 0
1 0101 0 1 0 1
1 0110 0 1 1 0
1 0111 0 1 1 1
1 1000 1 0 0 0
1 1001 1 0 0 1
1 1010 1 0 1 0
1 1011 1 0 1 1
1 1100 1 1 0 0
1 1101 1 1 0 1
1 1110 1 1 1 0
1 1111 1 1 1 1

Rev. A | Page 73 of 112

ADV7180

MPU PORT DESCRIPTION

The ADV7180 supports a 2-wire (I2C-compatible) serial inter­face. Two inputs, serial data (SDA) and serial clock (SCLK),
carry information between the ADV7180 and the system I

2

C
master controller. Each slave device is recognized by a unique
address. The ADV7180 I

2

C port allows the user to set up and
configure the decoder and to read back captured VBI data. The
ADV7180 has four possible slave addresses for both read and
write operations, depending on the logic level of the ALSB pin.
The four unique addresses are shown in Tab le 1 0 0. The ADV7180
ALSB pin controls Bit 1 of the slave address. By altering the ALSB,
it is possible to control two ADV7180s in an application without
having the conflict of using the same slave address. The LSB (Bit 0)
sets either a read or write operation. Logic 1 corresponds to a
read operation; Logic 0 corresponds to a write operation.

Table 100. I2C Address for ADV7180

ALSB

R/W

Slave Address

0 0 0x40
0 1 0x41
1 0 0x42
1 1 0x43

To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establishing
a start condition, which is defined by a high-to-low transition
on SDA while SCLK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/

W

bit).

The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse; this is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCLK lines for the start
condition and the correct transmitted address. The R/

W

bit

determines the direction of the data. Logic 0 on the LSB of the

first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.

The ADV7180 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
address plus the R/

W

bit. The device has 249 subaddresses to
enable access to the internal registers. It therefore interprets the
first byte as the device address and the second byte as the
starting subaddress. The subaddresses auto-increment, allowing
data to be written to or read from the starting subaddress. A
data transfer is always terminated by a stop condition. The user
can also access any unique subaddress register on a one-by-one
basis without updating all the registers.

Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLK high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7180 does
not issue an acknowledge and returns to the idle condition.

In auto-increment mode, if the user exceeds the highest
subaddress, the following action is taken:

•

In read mode, the highest subaddress register contents

continue to be output until the master device issues a no
acknowledge. This indicates the end of a read. A no
acknowledge condition is when the SDA line is not pulled
low on the ninth pulse.

•

In write mode, the data for the invalid byte is not loaded

into any subaddress register. A no acknowledge is issued by
the ADV7180, and the part returns to the idle condition.

SDATA

SCLOCK

S P

1–7 1–789 89 1–789

START ADDR ACK ACK DATA ACK STOPSUBADDRESS

R/W

Figure 48. Bus Data Transfer

05700-044

WRITE

SEQUENCE

READ

SEQUENCE

SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S)

S

LSB = 1LSB = 0

SLAVE ADDR SLAVE ADDRA(S) SUB ADDR A(S) S A(S) DATA A(M)

S

S = START BIT
P=STOPBIT

A(S) = ACKNOWL EDGE BY S LAVE
A(M) = ACKNOWLEDGE BY MASTER

Figure 49. Read and Write Sequence

Rev. A | Page 74 of 112

A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOW LEDGE BY MASTER

DATA A(S) P

DATA A(M) P

05700-045

ADV7180

REGISTER ACCESS

The MPU can write to or read from all of the ADV7180
registers except the subaddress register, which is write only. The
subaddress register determines which register the next read or
write operation accesses. All communications with the part
through the bus start with an access to the subaddress register.
Then a read/write operation is performed from or to the target
address, which increments to the next address until a stop
command on the bus is performed.

REGISTER PROGRAMMING

The following sections describe the configuration for each
register. The communication register is an 8-bit, write-only
register. After the part has been accessed over the bus and a
read/write operation is selected, the subaddress is set up. The
subaddress register determines to or from which register the
operation takes place. Table 101 lists the various operations
under the control of the subaddress register for the control port.

SUB_USR_EN, Address 0x0E [5]

This bit splits the register map at Register 0x40.

USER MAP

COMMON I2C SPACE

ADDRESS 0x00  0x3F

ADDRESS 0x0E BIT 5 = 0b

USER SUB MA P

ADDRESS 0x0E BIT 5 = 1b

Register Select (SR7 to SR0)

These bits are set up to point to the required starting address.

2

I C SEQUENCER

An I2C sequencer is used when a parameter exceeds eight bits

2

and is therefore distributed over two or more I

C registers, for

example, HSB [11:0].

When such a parameter is changed using two or more I

2

C write
operations, the parameter may hold an invalid value for the
time between the first I

2

C being completed and the last I2C
being completed. In other words, the top bits of the parameter
may hold the new value while the remaining bits of the parameter
still hold the previous value.

To avoid this problem, the I

2

C sequencer holds the updated bits
of the parameter in local memory, and all bits of the parameter
are updated together once the last register write operation has
completed.

The correct operation of the I

2

C sequencer relies on the

following:

•

All I

2

C registers for the parameter in question must be
written to in order of ascending addresses. For example, for
HSB[10:0], write to Address 0x34 first, followed by 0x35,
and so on.

•

No other I

2

C can take place between the two (or more) I2C
writes for the sequence. For example, for HSB[10:0], write
to Address 0x34 first, immediately followed by 0x35, and
so on.

2

CSPACE

I

ADDRESS 0x40  0xFF

NORMAL REG ISTER SPACE

Figure 50. Register Access—User Map and User Sub Map

I2C SPACE

ADDRESS 0x40  0x9C

INTERRUPT AND V DP REGI STER SPACE

05700-050

Rev. A | Page 75 of 112

ADV7180

I2C REGISTER MAPS

Table 101. Main Register Map Details

Address Reset

Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value (Hex)

0 00 Input Control RW VID_SEL[3] VID_SEL[2] VID_SEL[1] VID_SEL[0] INSEL[3] INSEL[2] INSEL[1] INSEL[0] 00000000 00

1 01 Video Selection RW ENHSPLL BETACAM ENVSPROC 11001000 C8

3 03 Output Control RW VBI_EN TOD OF_SEL[3] OF_SEL[2] OF_SEL[1] OF_SEL[0] SD_DUP_AV 00001100 0C

4 04 Extended Output Cont rol RW BT.656-4 TIM_OE BL_C_VBI EN_SFL_PIN RANGE 01xx0101 45

5 05 Reserved

6 06 Reserved

7 07 Autodetect Enable RW AD_SEC525_EN AD_SECAM_EN AD_N443_EN AD_P60_EN AD_PALN_EN AD_PALM_EN AD_NTSC_EN AD_PAL_EN 01111111 7F

8 08 Contrast RW CON[7] CON[6] CON[5] CON[4] CON[3] CON[2] CON[1] CON[0] 10000000 80

9 09 Reserved

10 0A Brightness RW BRI[7] BRI[6] BRI[5] BRI[4] BRI[3] BRI[2] BRI[1] BRI[0] 00000000 00

11 0B Hue RW HUE[7] HUE[6] HUE[5] HUE[4] HUE[3] HUE[2] HUE[1] HUE[0] 00000000 00

12 0C Default Value Y RW DEF_Y[5] DEF_Y[4] DEF_Y[3] DEF_Y[2] DEF_Y[1] DEF_Y[0]

13 0D Default Value C RW DEF_C[7] DEF_C[6] DEF_C[5] DEF_C[4] DEF_C[3] DEF_C[2] DEF_C[1] DEF_C[0] 01111100 7C

14 0E ADI Control 1 SUB_USR_EN 00000000 00

15 0F Power Management RW RESET PWRDWN PDBP 00000000 00

16 10 Status 1 R COL_KILL AD_RESULT[2] AD_RESULT[1] AD_RESULT[0] FOLLOW_PW FSC_LOCK LOST_LOCK IN_LOCK --- ---

17 11 IDENT R IDENT[7] IDENT[6] IDENT[5] IDENT[4] IDENT[3] IDENT[2] IDENT[1] IDENT[0] 00011011 1B

18 12 Status 2 R FSC NSTD LL NSTD MV AGC D ET MV PS DET MVCS T3 MVCS DET --- ---

19 13 Stat us 3 R PAL_SW_LOCK INTERLACED STD FLD LE N FREE_RUN_ACT CVBS SD_OP_50Hz GEMD INST_HL OCK --- -- -

20 14 Analog Clamp Control RW CCLEN 00010010 12

21 15 Digital Clamp Control RW DCT[1] DCT[0] 0000xxxx 00

22 16 Reserved

23 17 Shaping Filter Control 1 RW CSFM[2] CSFM[1] CSFM[0] YSFM[4] YSFM[3] YSFM[2] YSFM[1] YSFM[0] 00000001 01

24 18 Shaping Filter Control 2 RW WYSFMOVR WYSFM[4] WYSFM[3] WYSFM[2] WYSFM[1] WYSFM[0] 10010011 93

25 19 Comb Filter Control RW NSFSEL[1] NSFSEL[0] PSFSEL[1] PSFSEL[0] 11110001 F1

29 1D ADI Control 2 RW TRI_LLC EN28XTAL 01000xxx 40

39 27 Pixel Delay Control RW SWPC AUTO_PDC_EN CTA[2] CTA[1] CTA[0] LTA[1] LTA[0] 01011000 58

43 2B Misc Gain Control RW CKE PW_UPD 11100001 E1

44 2C AGC Mode Control RW LAGC[2] LAGC[1] LAGC[0] CAGC[1] CAGC[0] 10101110 AE

45 2D Chroma Gain C ontrol 1 W CAGT[1] CAGT[0] CMG[11] CMG[10] CMG[ 9] CMG[ 8] 11110100 F4

46 2E Chroma Gain C ontrol 2 W CMG[7] CMG[6] CMG[5] CMG[4] CMG[3] CMG[2] CMG[1] CMG[0] 00000000 00

47 2F Luma Gain Cont rol 1 W LAGT[1] LAGT[0] LMG[11] LMG[10] LMG[9] LMG[8] 1111xxxx F0

48 30 Luma G ain Control 2 W LMG.7 LMG[ 6] LMG[5] LMG[4] LMG[3] LMG[2] LMG[1] LMG[0] xxxxxxxx 00

49 31 VSYNC Field Control 1 RW NEWAVMODE HVSTIM 00010010 12

50 32 VSYNC Field Control 2 RW VSBHO VSBHE 01000001 41

51 33 VSYNC Field Control 3 RW VSEHO VSEHE 10000100 84

52 34 HSYNC Position Control 1 RW HSB[10] HSB[9] HSB[8] HSE[10] HSE[9] HSE[8] 00000000 00

53 35 HSYNC Position Control 2 RW HSB.7 HSB[6] HSB[5] HSB[4] HSB[3] HSB[2] HSB[1] HSB[0] 00000010 02

54 36 HSYNC Position Control 3 RW HSE.7 HSE[6] HSE[5] HSE[4] HSE[3] HSE[2] HSE[1] HSE[0] 00000000 00

55 37 Polarity RW PHS PVS PF PCLK 00000001 01

56 38 NTSC Comb Control RW CTAPSN[1] CTAPSN[0] CCMN[2] CCMN[1] CCMN[0] YCMN[2] YCMN[1] YCMN[0] 10000000 80

57 39 PAL Comb Control RW CTAPSP[1] CTAPSP[0] CCMP[2] CCMP[1] CCMP[0] YCMP[2] YCMP[1] YCMP[0] 11000000 C0

58 3A ADC Control RW MUX_0_PD MUX_1_PD MUX_2_PD

61 3D Manual Window Control RW CKILLTHR[2] CKILLTHR[1] CKILLTHR[0] 01110010 B2

65 41 Resample Control RW SFL_INV 00000001 01

72 48 Gemstar Control 1 RW GDECEL[15] GDECEL[14] GDECEL[13] GDECEL[12] GDECEL[11] GDECEL[10] GDECEL[9] GDECEL[8] 00000000 00

73 49 Gemstar Control 2 RW GDECEL[7] GDECEL[6] GDECEL[5] GDECEL[4] GDECEL[3] GDECEL[2] GDECEL[1] GDECEL[0] 00000000 00

74 4A Gemstar Control 3 RW GDECOL[15] GDECOL[14] GDECOL[13] GDECOL[12] GDECOL[11] GDECOL[10] GDECOL[9] GDECOL[8] 00000000 00

75 4B Gemstar Control 4 RW GDECOL[7] GDECOL[6] GDECOL[5] GDECOL[4] GDECOL[3] GDECOL[2] GDECOL[1] GDECOL[0] 00000000 00

76 4C Gemstar Control 5 RW GDECAD xxxx0000 00

77 4D CTI DNR Control 1 RW DNR_EN CTI_AB.1 CTI_AB.0 CTI_AB_EN CTI_EN 11101111 EF

78 4E CTI DNR Control 2 RW CTI_C_TH[7] CTI_C_TH[6] CTI_C_TH[5] CTI_C_TH[4] CTI_C_TH[3] CTI_C_TH[2] CTI_C_TH[1] CTI_C_TH[0] 00001000 08

80 50 CTI DNR Control 4 RW DNR_TH[7] DNR_TH[6] DNR_TH[5] DNR_TH[4] DNR_TH[3] DNR_TH[2] DNR_TH[1] DNR_TH[0] 00001000 08

81 51 Lock Count RW FSCLE SRLS COL[2] COL[1] COL[0] CIL[2] CIL[1] CIL[0] 00100100 24

88 58 VS/FIELD Pin Control1 RW ADC sampling control VS/FIELD 00000000 00

89 59 General-Purpose O/P2 RW GPO_Enable GPO[3] GPO[2] GPO[1] GPO[0] 00000000 00

143 8F Free-Run Line Length 1 W

144 90 VBI INFO R CCAPD

153 99 CCAP 1 R CCAP1[7] CCAP1[6] CCAP1[5] CCAP1[4] CCAP1[3] CCAP1[2] CCAP1[1] CCAP1[0] – –

LLC_PAD_
SEL_MAN

LLC_PAD_
SEL[1]

LLC_PAD_
SEL[0]

00000000 00

DEF_VAL_
AUTO_EN

Rev. A | Page 76 of 112

DEF_VAL_EN 00110110 36

MUX PDN
Override

00010000 10

ADV7180

Address Reset

Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value (Hex)

154 9A CCAP 2 R CCAP2[7] CCAP2[6] CCAP2[5] CCAP2[4] CCAP2[3] CCAP2[2] CCAP2[1] CCAP2[0] – –

155 9B Letterbox 1 R LB_LCT[7] LB_LCT[6] LB_LCT[5] LB_LCT[4] LB_LCT[3] LB_LCT[2] LB_LCT[1] LB_LCT[0] – –

156 9C Letterbox 2 R LB_LCM[7] LB_LCM[6] LB_LCM[5] LB_LCM[4] LB_LCM[3] LB_LCM[2] LB_LCM[1] LB_LCM[0] – –

157 9D Letterbox 3 R LB_LCB[7] LB_LCB[6] LB_LCB[5] LB_LCB[4] LB_LCB[3] LB_LCB[2] LB_LCB[1] LB_LCB[0] – –

178 B2 CRC W CRC_ENABLE 00011100 1C

195 C3 ADC Switch 1 RW MUX1[3] MUX1[2] MUX1[1] MUX1[0] MUX0[3] MUX0[2] MUX0[1] MUX0[0] xxxxxxxx 00

196 C4 ADC Switch 2 RW MAN_MUX_EN MUX2[3] MUX2[2] MUX2[1] MUX2[0] 0xxxxxxx 00

220 DC Letterbox Control 1 RW LB_TH[4] LB_TH[3] LB_TH[2] LB_TH[1] LB_TH[0] 10101100 AC

221 DD Letterbox Control 2 RW LB_SL[3] LB_SL.2 LB_SL[1] LB_SL[0] LB_EL[3] LB_EL[2] LB_EL[1] LB_EL[0] 01001100 4C

222 DE ST Noise Readback 1 R ST_NOISE_ VLD ST_NOISE[10] ST_NOISE[9] ST_NOISE[8] – –

223 DF ST Noise Readback 2 R ST_N OISE[7] ST_NOISE.6 ST_NOI SE[5] ST_NOIS E[4] ST_NOISE[3] ST_NOISE[2] ST_NOISE[1] ST_NOISE[0] – –

224 E0 Reserved

225 E1 SD Offset Cb RW SD_OFF_CB[7] SD_ OFF_CB[6] SD_OFF_CB[5] SD_OFF_CB[4] SD_OFF_CB[3] SD_OFF_CB[2] SD_OFF_CB[1] SD_OFF_CB[0] 10000000 80

226 E2 SD Offset Cr RW SD_OFF_CR[7] SD_OFF_CR[6] SD_OFF_CR[5] SD_OFF_CR[4] SD_OFF_CR[3] SD_OFF_CR[2] SD_OFF_CR[1] SD_OFF_CR[0] 10000000 80

227 E3 SD Saturation Cb RW SD_SAT_CB[7] SD_SAT_CB[6] SD_SAT_CB[5] SD_SAT_CB[4] SD_SAT_CB[3] SD_SAT_CB[2] SD_SAT_CB[1] SD_SAT_CB[0] 10000000 80

228 E4 SD Saturation Cr RW SD_SAT_CR[7] SD_SAT_CR[6] SD_S AT_CR[5] SD_SAT_CR[4] SD_SAT_CR[3] SD_SAT_CR[2] SD_SAT_CR[1] SD_SAT_CR[0] 10000000 80

229 E5 NTSC V Bit Begin RW NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG[4] NVBEG[3] NVBEG[2] NVBEG[1] NVBEG[0] 00100101 25

230 E6 NTSC V Bit End RW NVENDDELO NVENDDELE NVENDSIGN NVEND[4] NVEND[3] NVEND[2] NVEND[1] NVEND[0] 00000100 04

231 E7 NTSC F Bit Toggle RW NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG[4] NFTOG[3] NFTOG[2] NFTOG[1] NFTOG[0] 01100011 63

232 E8 PAL V Bit Begin RW PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG[4] PVBEG[3] PVBEG[2] PVBEG[1] PVBEG[0] 01100101 65

233 E9 PAL V Bit End RW PVENDDELO PVENDDELE PVENDSIGN PVEND[4] PVEND[3] PVEND[2] PVEND[1] PVEND[0] 00010100 14

234 EA PAL F Bit Toggle RW PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG[4] PFTOG[3] PFTOG[2] PFTOG[1] PFTOG[0] 01100011 63

235 EB Vblank Control 1 RW NVBIOLCM[1] NVBIOLCM[0] NVBIELCM[1] NVBIELCM[0] PVBIOLCM.1 PVBIOLCM.0 PVBIELCM.1 PVBIELCM.0 01010101 55

236 EC Vblank Control 2 RW NVBIOCCM[1] NVBIOCCM[0] NVBIECCM[1] NVBIECCM[0] PVBIOCCM.1 PVBIOCCM.0 PVBIECCM.1 PVBIECCM.0 01010101 55

243 F3 AFE_CONTROL 1 RW

AA_FILT_
MAN_OVR

244 F4 Drive Strength RW DR_STR[1] DR_STR[0] DR _STR_C[1] DR_STR_C[0] DR_STR_S[1] DR_STR_S[0] xx010101 15

248 F8 IF Comp Control RW IFFILTSEL[2] IFFILTSEL[1] IFFILTSEL[0] 00000000 00

249 F9 VS Mode Control RW

251 FB Peaking Control RW

PEAKING_
GAIN[7]

PEAKING_
GAIN[6]

PEAKING_
GAIN[5]

PEAKING_
GAIN[4]

VS_COAST_
MODE[1]

PEAKING_
GAIN[3]

252 FC Coring Threshold RW DNR_TH2[7] DNR_TH2[6] DNR_TH2[5] DNR_TH2[4] DNR_TH2[3] DNR_TH2[2] DNR_TH2[1] DNR_TH2[0] 00000100 04

1

This feature applies to the ADV7180BCPZ 40-lead only because VS or field are shared on a single pin (Pin 37).

2

This feature applies to the ADV7180BSTZ 64-lead only.

Table 102. Interrupt System Register Map Details

Address Reset

Dec Hex Register Name R/W 7 6 5 4 3 2 1 0 Value (Hex)

64 40 Interru pt

66 42 Interru pt

67 43 Interrupt Clear 1 W MV_PS_CS_

68 44 Interrupt

69 45 Raw

70 46 Interrupt

71 47 Interrupt Clear 2 W MPU_STIM_

72 48 Interrupt

73 49 Raw

74 4A Interrupt

75 4B Interrupt Clear 3 W PAL_SW_LK_

76 4C Interrupt

78 4E Interrupt

79 4F Interrupt Clear 4 W VDP_VITC_

Config. 1

Status 1

Mask 1

Status 1

Status 2

Mask 2

Status 2

Status 3

Mask 3

Status 4

RW INTRQ_DUR_

SEL[1]

R MV_PS_CS_Q SD_FR_

RW MV_PS_CS_

R MPU_STIM_I

NTRQ

R MPU_STIM_

INTRQ_Q

INTRQ_CLR

RW MPU_STIM_

INTRQ_MSKB

R SCM_LOCK SD_H_LOCK SD_V_LOCK SD_OP_50Hz – –

R PAL_SW_LK_

RW PAL_SW_LK_

R VDP_VITC_Q VDP_GS_

INTRQ_DUR_
SEL[0]

CLR

MSKB

EVEN_FIELD CCAPD – –

SD_FIELD_

SD_FIELD_

SD_FIELD_

CLR

1

MV_INTRQ_
SEL[1]

CHNG_Q

SD_FR_
CHNG_CLR

SD_FR_
CHNG_MSKB

CHNG_Q

CHNG_CLR

CHNG_MSKB

VDP_GS_

MV_INTRQ_
SEL[0]

SD_UNLOCK

SD_UNLOCK_

SD_UNLOCK_

CHNGD_Q

CHNGD_CLR

CHNGD_MSK
B

SCM_LOCK_
CHNG_Q

SCM_LOCK_
CHNG_CLR

SCM_LOCK_
CHNG_MSKB

VPS_PDC_
UTC_CHNG_
Q

VPS_PDC_
UTC_CHNG_
CLR

Rev. A | Page 77 of 112

AA_FILT_EN[2] AA_FILT_EN[1] AA_FILT_EN[0] 00000000 00

VS_COAST_
MODE[0]

PEAKING_
GAIN[2]

MPU_STIM_

GEMD_Q CCAPD_Q – –

GEMD_CLR CCAPD_CLR 0xx00000 00

GEMD_MSKB CCAPD_

SD_AD_
CHNG_Q

SD_AD_
CHNG_CLR

SD_AD_
CHNG_MSKB

VDP_CGMS_

VDP_CGMS_

INTRQ

SD_H_LOCK_
CHNG_Q

SD_H_LOCK_
CHNG_CLR

SD_H_LOCK_
CHNG_MSKB

WSS_
CHNGD_Q

WSS_CHNGD
_CLR

EXTEND_VS_
MIN_FREQ

PEAKING_
GAIN[1]

INTRQ_OP_
SEL[1]

_Q

CLR

MSKB

SD_V_LOCK_
CHNG_Q

SD_V_LOCK_
CHNG_CLR

SD_V_LOCK_
CHNG_MSKB

VDP_CCAPD_Q – –

VDP_CCAPD_

EXTEND_VS_
MAX_FREQ

PEAKING_
GAIN[0]

INTRQ_OP_SE
L[0]

SD_LOCK_Q – –

SD_LOCK_
CLR

SD_LOCK_
MSKB

MSKB

SD_OP_
CHNG_Q

SD_OP_
CHNG_CLR

SD_OP_
CHNG_MSKB

CLR

00000011 03

01000000 40

0001x000 10

x0000000 00

x0000000 00

0xx00000 00

– –

xx000000 00

xx000000 00

00x0x0x0 00

ADV7180

Address Reset

Dec Hex Register Name R/W 7 6 5 4 3 2 1 0 Value (Hex)

80 50 Interrupt

96 60 VDP_Config_1 RW WST_PKT_

97 61 VDP_Config_2 RW AUTO_

98 62 VDP_ADF_

99 63 VDP_ADF _

100 64 VDP_LINE_00E RW MAN_LINE_

101 65 VDP_LINE_00F RW VBI_DATA_

102 66 VDP_LINE_010 RW VBI_DATA_

103 67 VDP_LINE_011 RW VBI_DATA_

104 68 VDP_LINE_012 RW VBI_DATA_

105 69 VDP_LINE_013 RW VBI_DATA_

106 6A VDP_LINE_014 RW VBI_DATA_

107 6B VDP_LINE_015 RW VBI_DATA_

108 6C VDP_LINE_016 RW VBI_DATA_

109 6D VDP_LINE_017 RW VBI_DATA_

110 6E VDP_LINE_018 RW VBI_DATA_

111 6F VDP_LINE_019 RW VBI_DATA_

112 70 VDP_LINE_01A RW VBI_DATA_

113 71 VDP_LINE_01B RW VBI_DATA_

114 72 VDP_LINE_01C RW VBI_DATA_

115 73 VDP_LINE_01D RW VBI_DATA_

116 74 VDP_LINE_01E RW VBI_DATA_

117 75 VDP_LINE_01F RW VBI_DATA_

118 76 VDP_LINE_020 RW VBI_DATA_

119 77 VDP_LINE_021 RW VBI_DATA_

120 78 VDP_STATUS_

120 78 VDP_STATUS R TTXT_AVL VITC_AVL GS_DATA_

121 79 VDP_CCAP_

122 7A VDP_CCAP_

125 7D VDP_CGMS_

126 7E VDP_CGMS_

127 7F VDP_CGMS_

132 84 VDP_GS_VPS_

133 85 VDP_GS_VPS_

134 86 VDP_GS_VPS_

Mask 4

Config_1

Config_2

CLEAR

DATA_0

DATA_1

WSS_DATA_0

WSS_DATA_1

WSS_ DATA_2

PDC_UTC_0

PDC_UTC_1

PDC_UTC_2

RW VDP_VITC_

RW ADF_ENABLE ADF_MODE[1] ADF_MODE[0] ADF_DID[4] ADF_DID[3] ADF_DID[2] ADF_DID[1] ADF_DID[0] 00010101 15

RW DUPLICATE_

ADF

PGM

P6_N23[3]

P7_N24[3]

P8_N25[3]

P9[3]

P10[3]

P11[3]

P12_N10[3]

P13_N11[3]

P14_N12[3]

P15_N13[3]

P16_N14[3]

P17_N15[3]

P18_N16[3]

P19_N17[3]

P20_N18[3]

P21_N19[3]

P22_N20[3]

P23_N21[3]

P24_N22[3]

W VITC_CLEAR GS_PDC_

R CCAP_

BYTE_1[7]

R CCAP_

BYTE_2[7]

R CGMS_

R CGMS_

CRC[1]

R CGMS_

WSS[7]

R GS_VPS_

PDC_UTC_
BYTE_0[7]

R GS_VPS_

PDC_UTC_
BYTE_1[7]

R GS_VPS_

PDC_UTC_
BYTE_2[7]

MSKB

ADF_SDID[5] ADF_SDID[4] ADF_SDID[3] ADF_SDID[2] ADF_SDID[1] ADF_SDID[0] 0x101010 2A

VBI_DATA_

VBI_DATA_
P6_N23[2]

VBI_DATA_
P7_N24[2]

VBI_DATA_
P8_N25[2]

VBI_DATA_
P9[2]

VBI_DATA_
P10[2]

VBI_DATA_
P11[2]

VBI_DATA_
P12_N10[2]

VBI_DATA_
P13_N11[2]

VBI_DATA_
P14_N12[2]

VBI_DATA_
P15_N13[2]

VBI_DATA_
P16_N14[2]

VBI_DATA_
P17_N15[2]

VBI_DATA_
P18_N16[2]

VBI_DATA_
P19_N17[2]

VBI_DATA_
P20_N18[2]

VBI_DATA_
P21_N19[2]

VBI_DATA_
P22_N20[2]

VBI_DATA_
P23_N21[2]

VBI_DATA_
P24_N22[2]

CCAP_
BYTE_1[6]

CCAP_
BYTE_2[6]

CGMS_
CRC[0]

CGMS_
WSS[6]

GS_VPS_
PDC_UTC_
BYTE_0[6]

GS_VPS_
PDC_UTC_
BYTE_1[6]

GS_VPS_
PDC_UTC_
BYTE_2[6]

VDP_GS_

VBI_DATA_
P6_N23[1]

VBI_DATA_
P7_N24[1]

VBI_DATA_
P8_N25[1]

VBI_DATA_
P9[1]

VBI_DATA_
P10.1

VBI_DATA_
P11[1]

VBI_DATA_
P12_N10[1]

VBI_DATA_
P13_N11[1]

VBI_DATA_
P14_N12[1]

VBI_DATA_
P15_N13[1]

VBI_DATA_
P16_N14[1]

VBI_DATA_
P17_N15[1]

VBI_DATA_
P18_N16[1]

VBI_DATA_
P19_N17[1]

VBI_DATA_
P20_N18[1]

VBI_DATA_
P21_N19[1]

VBI_DATA_
P22_N20[1]

VBI_DATA_
P23_N21[1]

VBI_DATA_
P24_N22[1]

TYPE

CCAP_
BYTE_1[5]

CCAP_
BYTE_2[5]

CGMS_
WSS[13]

CGMS_
WSS[5]

GS_VPS_
PDC_UTC_
BYTE_0[5]

GS_VPS_
PDC_UTC_
BYTE_1[5]

GS_VPS_
PDC_UTC_
BYTE_2[5]

VPS_PDC_
UTC_CHNG_
MSKB

DETECT_GS_
TYPE

VBI_DATA_
P6_N23[0]

VBI_DATA_
P7_N24[0]

VBI_DATA_
P8_N25[0]

VBI_DATA_
P9[0]

VBI_DATA_
P10[0]

VBI_DATA_
P11[0]

VBI_DATA_
P12_N10[0]

VBI_DATA_
P13_N11[0]

VBI_DATA_
P14_N12[0]

VBI_DATA_
P15_N13[0]

VBI_DATA_
P16_N14[0]

VBI_DATA_
P17_N15[0]

VBI_DATA_
P18_N16[0]

VBI_DATA_
P19_N17[0]

VBI_DATA_
P20_N18[0]

VBI_DATA_
P21_N19[0]

VBI_DATA_
P22_N20[0]

VBI_DATA_
P23_N21[0]

VBI_DATA_
P24_N22[0]

VPS_UTC_
CLEAR

GS_PDC_
VPS_UTC_
AVL

CCAP_
BYTE_1[4]

CCAP_
BYTE_2[4]

CGMS_
WSS[12]

CGMS_
WSS[4]

GS_VPS_
PDC_UTC_
BYTE_0[4]

GS_VPS_
PDC_UTC_
BYTE_1[4]

GS_VPS_
PDC_UTC_
BYTE_2[4]

VDP_CGMS_

DECODE_
DISABLE

0001xx00 10

P318[3]

VBI_DATA_
P319_N286[3]

VBI_DATA_
P320_N287[3]

VBI_DATA_
P321_N288[3]

VBI_DATA_
P322[3]

VBI_DATA_
P323[3]

VBI_DATA_
P324_N272[3]

VBI_DATA_
P325_N273[3]

VBI_DATA_
P326_N274[3]

VBI_DATA_
P327_N275[3]

VBI_DATA_
P328_N276[3]

VBI_DATA_
P329_N277[3]

VBI_DATA_
P330_N278[3]

VBI_DATA_
P331_N279[3]

VBI_DATA_
P332_N280[3]

VBI_DATA_
P333_N281[3]

VBI_DATA_
P334_N282[3]

VBI_DATA_
P335_N283[3]

VBI_DATA_
P336_N284[3]

VBI_DATA_
P337_N285[3]

CGMS_WSS_

CGMS_WSS_

CCAP_
BYTE_1[3]

CCAP_
BYTE_2[3]

CRC[5]

CGMS_
WSS[11]

CGMS_
WSS[3]

GS_VPS_
PDC_UTC_
BYTE_0[3]

GS_VPS_
PDC_UTC_
BYTE_1[3]

GS_VPS_
PDC_UTC_
BYTE_2[3]

WSS_CHNGD_
MSKB

VDP_TTXT_
TYPE_MAN_
ENABLE

VBI_DATA_
P318[2]

VBI_DATA_
P319_N286[2]

VBI_DATA_
P320_N287[2]

VBI_DATA_
P321_N288[2]

VBI_DATA_
P322[2]

VBI_DATA_
P323[2]

VBI_DATA_
P324_N272[2]

VBI_DATA_
P325_N273[2]

VBI_DATA_
P326_N274[2]

VBI_DATA_
P327_N275[2]

VBI_DATA_
P328_N276[2]

VBI_DATA_
P329_N277[2]

VBI_DATA_
P330_N278[2]

VBI_DATA_
P331_N279[2]

VBI_DATA_
P332_N280[2]

VBI_DATA_
P333_N281[2]

VBI_DATA_
P334_N282[2]

VBI_DATA_
P335_N283[2]

VBI_DATA_
P336_N284[2]

VBI_DATA_
P337_N285[2]

CLEAR

AVL

CCAP_
BYTE_1[2]

CCAP_
BYTE_2[2]

CGMS_
CRC[4]

CGMS_
WSS[10]

CGMS_
WSS[2]

GS_VPS_
PDC_UTC_
BYTE_0[2]

GS_VPS_
PDC_UTC_
BYTE_1[2]

GS_VPS_
PDC_UTC_
BYTE_2[2]

VDP_CCAPD_

VDP_TTXT_
TYPE_MAN[1]

VBI_DATA_
P318[1]

VBI_DATA_
P319_N286[1]

VBI_DATA_
P320_N287[1]

VBI_DATA_
P321_N288[1]

VBI_DATA_
P322[1]

VBI_DATA_
P323[1]

VBI_DATA_
P324_N272[1]

VBI_DATA_
P325_N273[1]

VBI_DATA_
P326_N274[1]

VBI_DATA_
P327_N275[1]

VBI_DATA_
P328_N276[1]

VBI_DATA_
P329_N277[1]

VBI_DATA_
P330_N278[1]

VBI_DATA_
P331_N279[1]

VBI_DATA_
P332_N280[1]

VBI_DATA_
P333_N281[1]

VBI_DATA_
P334_N282[1]

VBI_DATA_P
335_N283[1]

VBI_DATA_
P336_N284[1]

VBI_DATA_
P337_N285[1]

CC_CLEAR 00000000 00

CC_EVEN_
FIELD

CCAP_
BYTE_1[1]

CCAP_
BYTE_2[1]

CGMS_
CRC[3]

CGMS_
WSS[9]

CGMS_
WSS[1]

GS_VPS_
PDC_UTC_
BYTE_0[1]

GS_VPS_
PDC_UTC_
BYTE_1[1]

GS_VPS_
PDC_UTC_
BYTE_2[1]

MSKB

VDP_TTXT_
TYPE_MAN[0]

VBI_DATA_
P318[0]

VBI_DATA_
P319_N286[0]

VBI_DATA_
P320_N287[0]

VBI_DATA_
P321_N288[0]

VBI_DATA_
P322[0]

VBI_DATA_
P323[0]

VBI_DATA_
P324_N272[0]

VBI_DATA_
P325_N273[0]

VBI_DATA_
P326_N274[0]

VBI_DATA_
P327_N275[0]

VBI_DATA_
P328_N276[0]

VBI_DATA_
P329_N277[0]

VBI_DATA_
P330_N278[0]

VBI_DATA_
P331_N279[0]

VBI_DATA_
P332_N280[0]

VBI_DATA_
P333_N281[0]

VBI_DATA_
P334_N282[0]

VBI_DATA_
P335_N283[0]

VBI_DATA_
P336_N284[0]

VBI_DATA_
P337_N285[0]

CC_AVL – –

CCAP_
BYTE_1[0]

CCAP_
BYTE_2[0]

CGMS_
CRC[2]

CGMS_
WSS[8]

CGMS_
WSS[0]

GS_VPS_
PDC_UTC_
BYTE_0[0]

GS_VPS_
PDC_UTC_
BYTE_1[0]

GS_VPS_
PDC_UTC_
BYTE_2[0]

00x0x0x0 00

10001000 88

0xxx0000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

00000000 00

– –

– –

– –

– –

– –

– –

– –

– –

Rev. A | Page 78 of 112

ADV7180

Address Reset

Dec Hex Register Name R/W 7 6 5 4 3 2 1 0 Value (Hex)

135 87 VDP_GS_VPS_

136 88 VDP_VPS_

137 89 VDP_VPS_

138 8A VDP_VPS_

139 8B VDP_VPS_

140 8C VDP_VPS_

141 8D VDP_VPS_

142 8E VDP_VPS_

143 8F VDP_VPS_

144 90 VDP_VPS_

146 92 VDP_VITC_

147 93 VDP_VITC_

148 94 VDP_VITC_

149 95 VDP_VITC_

150 96 VDP_VITC_

151 97 VDP_VITC_

152 98 VDP_VITC_

153 99 VDP_VITC_

154 9A VDP_VITC_

155 9B VDP_VITC_

156 9C VDP_OUTPUT_

1

To access the registers listed in Table 102, SUB_USR_EN in Register Address 0x0E must be programmed to 1.

PDC_UTC_3

PDC_UTC_4

PDC_UTC_5

PDC_UTC_6

PDC_UTC_7

PDC_UTC_8

PDC_UTC_9

PDC_UTC_10

PDC_UTC_11

PDC_UTC_12

DATA_0

DATA_1

DATA_2

DATA_3

DATA_4

DATA_5

DATA_6

DATA_7

DATA_8

CALC_CRC

SEL

R GS_VPS_

PDC_UTC_
BYTE_3[7]

R VPS_

PDC_UTC_
BYTE_4[7]

R VPS_

PDC_UTC_
BYTE_5[7]

R VPS_

PDC_UTC_
BYTE_6[7]

R VPS_

PDC_UTC_
BYTE_7[7]

R VPS_

PDC_UTC_
BYTE_8[7]

R VPS_

PDC_UTC_
BYTE_9[7]

R VPS_

PDC_UTC_
BYTE_10[7]

R VPS_

PDC_UTC_
BYTE_11[7]

R VPS_

PDC_UTC_
BYTE_12[7]

R VITC_

DATA_0[7]

R VITC_

DATA_1[7]

R VITC_

DATA_2[7]

R VITC_

DATA_3[7]

R VITC_

DATA_4[7]

R VITC_

DATA_5[7]

R VITC_

DATA_6[7]

R VITC_

DATA_7[7]

R VITC_

DATA_8[7]

R VITC_CRC[7] VITC_CRC[6] VITC_CRC.5 VITC_CRC[4] VITC_CRC[3] VITC_CRC[2] VITC_CRC[1] VITC_CRC[0] – –

RW I2C_GS_

VPS_PDC_
UTC[1]

GS_VPS_
PDC_UTC_
BYTE_3.6

VPS_
PDC_UTC_
BYTE_4[6]

VPS_
PDC_UTC_
BYTE_5[6]

VPS_
PDC_UTC_
BYTE_6[6]

VPS_
PDC_UTC_
BYTE_7[6]

VPS_
PDC_UTC_
BYTE_8[6]

VPS_
PDC_UTC_
BYTE_9[6]

VPS_
PDC_UTC_
BYTE_10[6]

VPS_
PDC_UTC_
BYTE_11[6]

VPS_
PDC_UTC_
BYTE_12[6]

VITC_
DATA_0[6]

VITC_
DATA_1[6]

VITC_
DATA_2[6]

VITC_
DATA_3[6]

VITC_
DATA_4[6]

VITC_
DATA_5[6]

VITC_
DATA_6[6]

VITC_
DATA_7[6]

VITC_
DATA_8[6]

I2C_GS_
VPS_PDC_
UTC[0]

GS_VPS_
PDC_UTC_
BYTE_3.5

VPS_
PDC_UTC_
BYTE_4[5]

VPS_
PDC_UTC_
BYTE_5[5]

VPS_
PDC_UTC_
BYTE_6[5]

VPS_
PDC_UTC_
BYTE_7[5]

VPS_
PDC_UTC_
BYTE_8[5]

VPS_
PDC_UTC_
BYTE_9[5]

VPS_
PDC_UTC_
BYTE_10[5]

VPS_
PDC_UTC_
BYTE_11[5]

VPS_
PDC_UTC_
BYTE_12[5]

VITC_
DATA_0[5]

VITC_
DATA_1[5]

VITC_
DATA_2[5]

VITC_
DATA_3[5]

VITC_
DATA_4[5]

VITC_
DATA_5[5]

VITC_
DATA_6[5]

VITC_
DATA_7[5]

VITC_
DATA_8[5]

GS_VPS_
PDC_UTC_
CB_CHANGE

GS_VPS_
PDC_UTC_
BYTE_3.4

VPS_
PDC_UTC_
BYTE_4[4]

VPS_
PDC_UTC_
BYTE_5[4]

VPS_
PDC_UTC_
BYTE_6[4]

VPS_
PDC_UTC_
BYTE_7[4]

VPS_
PDC_UTC_
BYTE_8[4]

VPS_
PDC_UTC_
BYTE_9[4]

VPS_
PDC_UTC_
BYTE_10[4]

VPS_
PDC_UTC_
BYTE_11[4]

VPS_
PDC_UTC_
BYTE_12[4]

VITC_
DATA_0[4]

VITC_
DATA_1[4]

VITC_
DATA_2[4]

VITC_
DATA_3[4]

VITC_
DATA_4[4]

VITC_
DATA_5[4]

VITC_
DATA_6[4]

VITC_
DATA_7[4]

VITC_
DATA_8[4]

WSS_CGMS_
CB_CHANGE

GS_VPS_
PDC_UTC_
BYTE_3[3]

VPS_
PDC_UTC_
BYTE_4[3]

VPS_
PDC_UTC_
BYTE_5[3]

VPS_
PDC_UTC_
BYTE_6[3]

VPS_
PDC_UTC_
BYTE_7[3]

VPS_
PDC_UTC_
BYTE_8[3]

VPS_
PDC_UTC_
BYTE_9[3]

VPS_
PDC_UTC_
BYTE_10[3]

VPS_
PDC_UTC_
BYTE_11[3]

VPS_
PDC_UTC_
BYTE_12[3]

VITC_
DATA_0[3]

VITC_
DATA_1[3]

VITC_
DATA_2[3]

VITC_
DATA_3[3]

VITC_
DATA_4[3]

VITC_
DATA_5[3]

VITC_
DATA_6[3]

VITC_
DATA_7[3]

VITC_
DATA_8[3]

00110000 30

GS_VPS_
PDC_UTC_
BYTE_3[2]

VPS_
PDC_UTC_
BYTE_4[2]

VPS_
PDC_UTC_
BYTE_5[2]

VPS_
PDC_UTC_
BYTE_6[2]

VPS_
PDC_UTC_
BYTE_7[2]

VPS_
PDC_UTC_
BYTE_8[2]

VPS_
PDC_UTC_
BYTE_9[2]

VPS_
PDC_UTC_
BYTE_10[2]

VPS_
PDC_UTC_
BYTE_11[2]

VPS_
PDC_UTC_
BYTE_12[2]

VITC_
DATA_0[2]

VITC_
DATA_1[2]

VITC_
DATA_2[2]

VITC_
DATA_3[2]

VITC_
DATA_4[2]

VITC_
DATA_5[2]

VITC_
DATA_6[2]

VITC_
DATA_7[2]

VITC_
DATA_8[2]

GS_VPS_
PDC_UTC_
BYTE_3[1]

VPS_
PDC_UTC_
BYTE_4[1]

VPS_
PDC_UTC_
BYTE_5[1]

VPS_
PDC_UTC_
BYTE_6[1]

VPS_
PDC_UTC_
BYTE_7[1]

VPS_
PDC_UTC_
BYTE_8[1]

VPS_
PDC_UTC_
BYTE_9[1]

VPS_
PDC_UTC_
BYTE_10[1]

VPS_
PDC_UTC_
BYTE_11[1]

VPS_
PDC_UTC_
BYTE_12[1]

VITC_
DATA_0[1]

VITC_
DATA_1[1]

VITC_
DATA_2[1]

VITC_
DATA_3[1]

VITC_
DATA_4[1]

VITC_
DATA_5[1]

VITC_
DATA_6[1]

VITC_DATA_
7[1]

VITC_
DATA_8[1]

GS_VPS_
PDC_UTC_
BYTE_3[0]

VPS_
PDC_UTC_
BYTE_4[0]

VPS_
PDC_UTC_
BYTE_5[0]

VPS_
PDC_UTC_
BYTE_6[0]

VPS_
PDC_UTC_
BYTE_7[0]

VPS_
PDC_UTC_
BYTE_8[0]

VPS_
PDC_UTC_
BYTE_9[0]

VPS_
PDC_UTC_
BYTE_10[0]

VPS_
PDC_UTC_
BYTE_11[0]

VPS_
PDC_UTC_
BYTE_12[0]

VITC_
DATA_0[0]

VITC_
DATA_1[0]

VITC_
DATA_2[0]

VITC_
DATA_3[0]

VITC_
DATA_4[0]

VITC_
DATA_5[0]

VITC_
DATA_6[0]

VITC_
DATA_7[0]

VITC_
DATA_8[0]

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

– –

Rev. A | Page 79 of 112

ADV7180

Table 103. Register Map Descriptions (Normal Operation)

Subaddress Register Bit Description

0x00 Input Control

INSEL [3:0]. The INSEL
bits allow the user to
select an input channel
and the input format.

Refer to Tab le 9 and

Table 8 for full routing

details.

VID_SEL [3:0]. The
VID_SEL bits allow the
user to select the input
video standard.

0x01 Video Selection

Reserved. 0 0 0 Set to default

Reserved. 0 Set to default

Reserved. 1 Set to default

Bits (Shading Indicates Default

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 0 0 0 Composite Composite
0 0 0 1 Composite Reserved
0 0 1 0 Composite Reserved

0 0 1 1 Composite Composite
0 1 0 0 Composite Composite
0 1 0 1 Composite Reserved
0 1 1 0 S-Video S-Video

0 1 1 1 S-Video Reserved
1 0 0 0 S-Video Reserved
1 0 0 1 YPrPb YPrPb
1 0 1 0 YPrPb Reserved
1 0 1 1 Reserved Reserved
1 1 0 0 Reserved Reserved
1 1 0 1 Reserved Reserved
1 1 1 0 Reserved Reserved
1 1 1 1 Reserved Reserved
0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0 NTSC J
0 1 0 1 NTSC M
0 1 1 0 PAL 60
0 1 1 1 NTSC 4.43
1 0 0 0 PAL B/G/H/I/D
1 0 0 1

1 0 1 0 PAL M (without pedestal)
1 0 1 1 PAL M
1 1 0 0 PAL Combination N
1 1 0 1

1 1 1 0 SECAM
1 1 1 1 SECAM (with pedestal)

0 Disable vsync processor ENVSPROC.

0 Standard video input BETACAM.
1 Betacam input enable
0 Disable hsync processor ENHSPLL.

1 Enable hsync processor

State) Comments

Notes

Mandatory write required
for Y/C (S-video mode)
Reg 0x58 = 0x04; see
Reg 0x58 for bit description

Autodetect PAL B/G/H/I/D,
NTSC (without pedestal),
SECAM

Autodetect PAL B/G/H/I/D,
NTSC M (with pedestal),
SECAM

Autodetect PAL N, NTSC M
(without pedestal), SECAM

Autodetect PAL N, NTSC M
(with pedestal), SECAM

PAL N (B/G/H/I/D without
pedestal)

PAL Combination N
(with pedestal)

1 Enable vsync processor

Rev. A | Page 80 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x03 Output Control

0x04

0 Decode and output color

0 HS, VS, F three-stated

Reserved. x x
Reserved. 1
0 ITU-R BT.656-3 compatible

0x05 Reserved
0x06 Reserved

Extended Output
Control

SD_DUP_AV.
Duplicates the AV
codes from the luma
into the chroma path.

Reserved. 0 Set as default
OF_SEL [3:0]. Allows

the user to choose
from a set of output
formats.

TOD. Three-state
output drivers. This bit
allows the user to
three-state the output
drivers: P[19:0], HS, VS,
FIELD, and SFL.

VBI_EN. Allows VBI data
(Lines 1 to 21) to be
passed through with
only a minimum
amount of filtering
performed.

RANGE. Allows the user
to select the range of
output values. Can be
ITU-R BT.656 compliant,
or can fill the whole
accessible number
range.

EN_SFL_PIN.

BL_C_VBI. Blank
chroma during VBI. If
set, it enables data in
the VBI region to be
passed through the
decoder undistorted.

TIM_OE. Timing signals
output enable.

BT.656-4. Allows the
user to select an
output mode
compatible with
ITU-R BT.656-3/4.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0

1

0 0 0 0 Reserved
0 0 0 1 Reserved
0 0 1 0 16-bit @ LLC1 4:2:2
0 0 1 1

0 1 0 0 Not used
0 1 0 1 Not used
0 1 1 0 Not used
0 1 1 1 Not used
1 0 0 0 Not used
1 0 0 1 Not used
1 0 1 0 Not used
1 0 1 1 Not used
1 1 0 0 Not used
1 1 0 1 Not used
1 1 1 0 Not used
1 1 1 1 Not used
0 Output pins enabled

1 Drivers three-stated

0 All lines filtered and scaled
1

0 16 < Y < 235, 16 < C < 240 ITU-R BT.656

1 1 < Y < 254, 1 < C < 254 Extended range

0 SFL output is disabled
1

1 Blank Cr and Cb

1 HS, VS, F forced active

1 ITU-R BT.656-4 compatible

State) Comments

Notes

AV codes to suit 8-bit
interleaved data output

AV codes duplicated
(for 16-bit interfaces)

8-bit @ LLC1 4:2:2
ITU-R BT.656

Only active video region
filtered

SFL information output on
the SFL pin

Options apply to
ADV7180 LQFP-64 only

See also TIM_OE
and TRI_LLC

SFL output enables
encoder and decoder
to be connected directly

During VBI

Controlled by TOD

Rev. A | Page 81 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x07 Autodetect Enable

0x08 Contrast Register

0x09 Reserved Reserved. 1 0 0 0 0 0 0 0
0x0A Brightness Register

0x0B Hue Register

0x0C Default Value Y 0

0 Disable free-run mode

0 0 1 1 0 1

0x0D Default Value C 0 1 1 1 1 1 0 0

0x0E ADI Control Reserved. 0 0 0 0 0 Set as default
0 Access main register space

Reserved. 0 0 Set as default

AD_PAL_EN. PAL B/G/I/H
autodetect enable.

AD_NTSC_EN. NTSC
autodetect enable.

AD_PALM_EN. PAL M
autodetect enable.

AD_PALN_EN. PAL N
autodetect enable.

AD_P60_EN. PAL 60
autodetect enable.

AD_N443_EN.
NTSC 4.43 autodetect
enable.

AD_SECAM_EN. SECAM
autodetect enable.

AD_SEC525_EN.
SECAM 525 autodetect
enable.

CON[7:0]. Contrast
adjust. This is the user
control for contrast
adjustment.

BRI[7:0]. This register
controls the brightness
of the video signal.

HUE[7:0].
This register contains
the value for the color
hue adjustment.

DEF_VAL_EN. Default
value enable.

DEF_VAL_AUTO_EN.
Default value.

DEF_Y[5:0]. Default
value Y. This register
holds the Y default
value.

DEF_C[7:0]. Default
value C. The Cr and Cb
default values are
defined in this register.

SUB_USR_EN. Enables
user to access the
interrupt/VDP register
map.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 Disable

0 Disable

0 Disable

1 Enable
0 Disable

1 Enable
0 Disable

1 Enable
0 Disable

1 Enable
0 Disable

1 Enable
0 Disable

1 Enable
1 0 0 0 0 0 0 0 Luma gain = 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 Hue range = −90° to +90°

1

1

1

State) Comments

Notes

1 Enable

1 Enable

0x00 gain = 0,
0x80 gain = 1,
0xFF gain = 2

0x00 = 0IRE,
0x7F = +100IRE,
0x80 = –100IRE

Free-run mode dependent
on DEF_VAL_AUTO_EN

Force free-run mode on
and output blue screen

Enable automatic free-run
mode (blue screen)

Y[7:0] = {DEF_Y[5:0], 0, 0}

Cr[7:0] = DEF_C[7:4], 0, 0, 0, 0}
Cb[7:0] = DEF_C[3:0], 0, 0, 0, 0}

Access interrupt/VDP register
space

When lock is lost, free-run
mode can be enabled to
output stable timing, clock,
and a set color

Default Y value output in
free-run mode

Default Cb/Cr value output
in free-run mode; default
values give blue screen
output

See Figure 50

Rev. A | Page 82 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x0F

0

Reserved. 0 0 Set to default
0 System functional

Reserved. 0 Set to default
0 Normal operation

0x10 IN_LOCK. x 1 = in lock (now)
LOST_ LOCK. x 1 = lost lock (since last read)

FOLLOW_PW. x

0 0 0 NTSM M/J
0 0 1 NTSC 4.43
0 1 0 PAL M
0 1 1 PAL 60
1 0 0 PAL B/G/H/I/D
1 0 1 SECAM
1 1 0 PAL Combination N

COL_KILL. x 1 = color kill is active Color kill
0x11 IDENT (Read Only)

0x12 MVCS DET. x MV color striping detected 1 = detected
MVCS T3. x MV color striping type

MV PS DET. x MV pseudosync detected 1 = detected
MV AGC DET. x MV AGC pulses detected 1 = detected
LL NSTD. x Nonstandard line length 1 = detected
FSC NSTD. x FSC frequency nonstandard 1 = detected

0x13 INST_HLOCK. x

FREE_RUN_ACT. x 1 = free-run mode active Blue screen output

0x14

Power
Management

Status Register 1
(Read Only)

Status Register 2
(Read Only)

Status Register 3
(Read Only)

Analog Clamp
Control

Reserved. 0 0 Set to default

PDBP. Power-down
bit priority selects
between PWRDWN bit
or pin control.

PWRDWN. Power­down places the
decoder into a full
power-down mode.

RESET. Chip reset, loads
all I2C bits with default
values.

FSC_LOCK. x 1 = FSC lock (now)

AD_RESULT[2:0].
Autodetection result
reports the standard of
the input video.

IDENT[7:0]. Provides
identification on the
revision of the part.

Reserved. x x

GEMD. x 1 = Gemstar data detected

CVBS.

STD FLD LEN. x 1 = field length standard Correct field length found
INTERLACED. x 1 = interlaced video detected Field sequence found
PAL_SW_LOCK. x 1 = swinging burst detected

Reserved. 0 0 1 0 Set to default
CCLEN. Current clamp

enable allows the user
to switch off the
current sources in the
analog front.

Reserved.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

1

1 Powered down See PDBP, 0x0F Bit 2

1 Start reset sequence

1 1 1 SECAM 525

0 0 0 1 1 0 1 1 Power-up value = 0x1B

0 SD 60 Hz detected SD_OP_50Hz.
1 SD 50 Hz detected
0 Y/C signal detected
1 CVBS signal detected

0 Current sources switched off

0 0 0 Set to default

State) Comments

Notes

Chip power-down
controlled by pin

Bit has priority
(pin disregarded)

1 = peak white
AGC mode active

1 = horizontal lock
achieved

1 Current sources enabled

Executing reset takes
approx. 2 ms; this bit is
self-clearing

Provides information
about the internal status
of the decoder

Detected standard

0 = Type 2
1 = Type 3

Unfiltered

SD field rate detect

Result of CVBS and
Y/C autodetection

Reliable swinging burst
sequence

Rev. A | Page 83 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x15

0x17

0 0 0 1 0 SVHS 1

0 0 1 0 0 SVHS 3
0 0 1 0 1 SVHS 4
0 0 1 1 0 SVHS 5
0 0 1 1 1 SVHS 6
0 1 0 0 0 SVHS 7

0 1 0 1 0 SVHS 9
0 1 0 1 1 SVHS 10
0 1 1 0 0 SVHS 11
0 1 1 0 1 SVHS 12
0 1 1 1 0 SVHS 13
0 1 1 1 1 SVHS 14
1 0 0 0 0 SVHS 15
1 0 0 0 1 SVHS 16
1 0 0 1 0 SVHS 17
1 0 0 1 1 SVHS 18 (CCIR601)
1 0 1 0 0 PAL NN1
1 0 1 0 1 PAL NN2
1 0 1 1 0 PAL NN3
1 0 1 1 1 PAL WN1
1 1 0 0 0 PAL WN2
1 1 0 0 1 NTSC NN1
1 1 0 1 0 NTSC NN2
1 1 0 1 1 NTSC NN3
1 1 1 0 0 NTSC WN1
1 1 1 0 1 NTSC WN2
1 1 1 1 0 NTSC WN3
1 1 1 1 1 Reserved
0 0 0 Auto selection 15.0 MHz
0 0 1 Auto selection 2.17 MHz

0 1 0 SH1
0 1 1 SH2
1 0 0 SH3
1 0 1 SH4
1 1 0 SH5

Digital Clamp
Control 1

Shaping Filter
Control

Reserved. x x x x Set to default
Digital clamp freeze

(DCFE)

DCT[1:0]. Digital clamp
timing determines the
time constant of the
digital fine clamp
circuitry.

Reserved. 0 Set to default
YSFM[4:0]. Selects Y

shaping filter mode in
CVBS-only mode.

Allows the user to
select a wide range of
low-pass and notch
filters.

If either auto mode is
selected, the decoder
selects the optimum Y
filter depending on the
CVBS video source
quality (good vs. bad).

CSFM[2:0]. C shaping
filter mode allows
selection from a range
of low-pass chrominance
filters. If either auto
mode is selected, the
decoder selects the
optimum C filter
depending on the
CVBS video source
quality (good vs. bad).
Nonauto settings force
a C filter for all standards
and quality of CVBS
video.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 Digital clamp on
1 Digital clamp off
0 0 Slow (TC = 1 sec)
0 1 Medium (TC = 0.5 sec)
1 0 Fast (TC = 0.1 sec)
1 1 TC dependent on video

0 0 0 0 0

0 0 0 0 1

0 0 0 1 1 SVHS 2

0 1 0 0 1 SVHS 8

1 1 1 Wideband mode

State) Comments

Notes

Auto wide notch for poor
quality sources or wide­band filter with comb for
good quality input

Auto narrow notch for poor
quality sources or wideband
filter with comb for good
quality input

Decoder selects optimum
Y shaping filter depending
on CVBS quality

If one of these modes is
selected, the decoder does
not change filter modes;
depending on video
quality, a fixed filter
response (the one
selected) is used for good
and bad quality video

Automatically selects a
C filter based on video
standard and quality

Selects a C filter for all
video standards and for
good and bad video

Rev. A | Page 84 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x18 0 0 0 0 0 Reserved, do not use
0 0 0 0 1 Reserved, do not use

0 0 0 1 1 SVHS 2
0 0 1 0 0 SVHS 3
0 0 1 0 1 SVHS 4
0 0 1 1 0 SVHS 5
0 0 1 1 1 SVHS 6
0 1 0 0 0 SVHS 7
0 1 0 0 1 SVHS 8
0 1 0 1 0 SVHS 9
0 1 0 1 1 SVHS 10
0 1 1 0 0 SVHS 11
0 1 1 0 1 SVHS 12
0 1 1 1 0 SVHS 13
0 1 1 1 1 SVHS 14
1 0 0 0 0 SVHS 15
1 0 0 0 1 SVHS 16
1 0 0 1 0 SVHS 17
1 0 0 1 1 SVHS 18 (CCIR 601)
1 0 1 0 0 Reserved, Do not use
~ ~ ~ ~ ~ Reserved, Do not use

Shaping Filter
Control 2

WYSFM[4:0]. Wideband
Y shaping filter mode
allows the user to
select which Y shaping
filter is used for the Y
component of Y/C,
YPrPb, B/W input
signals. It is also used
when a good quality
input CVBS signal is
detected. For all other
inputs, the Y shaping
filter chosen is
controlled by
YSFM[4:0].

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 0 0 1 0 SVHS 1

1 1 1 1 1 Reserved, Do not use

State) Comments

Notes

Reserved. 0 0 Set to default
0 Autoselection of best filter

0x19 Comb Filter Control

0x1D ADI Control 2

WYSFMOVR. Enables
the use of automatic
WYSFM filter.

PSFSEL[1:0]. Controls
the signal bandwidth
that is fed to the comb
filters (PAL).

NSFSEL[1:0]. Controls
the signal bandwidth
that is fed to the comb
filters (NTSC).

Reserved.
Reserved. 0 0 0 x x x Set to default

TRI_LLC.

1

0 0 Narrow
0 1 Medium
1 0 Wide
1 1 Widest
0 0 Narrow
0 1 Medium
1 0 Medium
1 1 Wide
1 1 1 1 Set as default

0 Use 27 MHz crystal EN28XTAL.
1 Use 28 MHz crystal
0 LLC pin active
1

Manual select filter using
WYSFM[4:0]

LLC pin three-stated

Rev. A | Page 85 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x27 Pixel Delay Control 0 0 No delay

1 0 Luma 1 clock (37 ns) late

1 0 Luma 2 clock (74 ns) early

Reserved. 0 Set to 0

0 0 1 Chroma + 2 pixels (early)
0 1 0 Chroma + 1 pixel (early)
0 1 1 No delay
1 0 0 Chroma − 1 pixel (late)
1 0 1 Chroma − 2 pixels (late)
1 1 0 Chroma − 3 pixels (late)
1 1 1 Not valid setting
0

0 No swapping

0x2B 0 Update once per video line

Misc Gain Control

LTA[1:0]. Luma timing
adjust allows the user
to specify a timing
difference between
chroma and luma
samples.

CTA[2:0]. Chroma
timing adjust allows
a specified timing
difference between
the luma and chroma
samples.

AUTO_PDC_EN.
Automatically
programs the LTA/CTA
values so that luma
and chroma are
aligned at the output
for all modes of
operation.

SWPC. Allows the Cr
and Cb samples to be
swapped.

PW_UPD. Peak white
update determines the
rate of gain.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

1 1 Luma 1 clock (37 ns) early

0 0 0 Not valid setting

1

1

1 Update once per field

State) Comments

Notes

CVBS mode LTA[1:0] = 00b,
S-video mode LTA[1:0] = 01b,
YPrPb mode LTA[1:0] = 01b

CVBS mode CTA[2:0] = 011b,
S-Video mode CTA[2:0] = 101b,
YPrPb mode CTA[2:0] = 110b

Use values in LTA[1:0] and
CTA[2:0] for delaying
luma/chroma

LTA and CTA values
determined automatically

Swap the Cr and Cb O/P
samples

See Swap_CR_CB_WB,
Addr 0x89

Peak white must be
enabled; see LAGC[2:0]

Reserved. 1 0 0 0 0 Set to default
0 Color kill disabled

0x2C AGC Mode Control

CKE. Color kill enable
allows the color kill
function to be
switched on and off.

Reserved. 1 Set to default
CAGC[1:0]. Chroma

automatic gain control
selects the basic mode
of operation for the
AGC in the chroma path.

Reserved. 1 1 Set to 1
LAGC[2:0]. Luma

automatic gain control
selects the mode of
operation for the gain
control in the luma
path.

Reserved.

1 Color kill enabled

0 0 Manual fixed gain Use CMG[11:0]
0 1 Use luma gain for chroma
1 0 Automatic gain Based on color burst
1 1 Freeze chroma gain

0 0 0 Manual fixed gain Use LMG[11:0]
0 0 1 Reserved
0 1 0 Peak white algorithm on Blank level to sync tip
0 1 1 Reserved
1 0 0 Peak white algorithm off Blank level to sync tip
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Freeze gain
1 Set to 1

For SECAM color kill,
threshold is set at 8%;
see CKILLTHR[2:0]

Rev. A | Page 86 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x2D

0x2E

0x2F Luma Gain Control 1

0x30 Luma Gain Control 2

0x31 Reserved. 0 1 0 Set to default
0 Start of line relative to HSE HSE = Hsync end

0

0x32 VS/FIELD Control 2

0x33 VS/FIELD Control 3

Chroma Gain
Control 1

Chroma Gain
Control 2

VS/FIELD Control 1

CMG[11:8]/CG[11:8]. In
manual mode, the
chroma gain control can
be used to program a
desired manual chroma
gain. In auto mode, it can
be used to read back the
current gain value.

Reserved. 1 1 Set to 1
CAGT[1:0]. Chroma

automatic gain timing
allows adjustment of
the chroma AGC
tracking speed.

CMG[7:0]/CG[7:0].
Chroma manual gain
lower eight bits. See
CMG[11:8]/CG[11:8] for
description.

LMG[11:8]/LG[11:8]. In
manual mode, luma gain
control can be used to
program a desired
manual chroma gain. In
auto mode, it can be
used to read back the
actual gain value used.

Reserved. 1 1 Set to 1
LAGT[1:0]. Luma

automatic gain timing
allows adjustment of
the luma AGC tracking
speed.

LMG[7:0]/LG[7:0]. Luma
manual gain lower eight
bits. See LMG[11:8]/
LG[11:8] for description.

HVSTIM. Selects where
within a line of video
the VS signal is asserted.

NEWAVMODE. Sets the
EAV/SAV mode.

Reserved. 0 0 0 Set to default
Reserved. 0 0 0 0 0 1 Set to default
VSBHE. 0

1

VSBHO. 0

1

Reserved. 0 0 0 1 0 0 Set to default
VSEHE. 0

1

VSEHO.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 1 0 0

0 0 Slow (TC = 2 sec)
0 1 Medium (TC = 1 sec)
1 0 Fast (TC = 0.2 sec)
1 1 Adaptive

0 0 0 0 0 0 0 0

x x x x

0 0 Slow (TC = 2 sec)
0 1 Medium (TC = 1 sec)
1 0 Fast (TC = 0.2 sec)
1 1 Adaptive

x x x x x x x x

1 Start of line relative to HSB HSB = Hsync begin

1

0

1

Rev. A | Page 87 of 112

State) Comments

Notes

CAGC[1:0] settings decide
in which mode CMG[11:0]
operates

Has an effect only if
CAGC[1:0] is set to
autogain (10)

CMG[11:0] = 750d; gain is 1
in NTSC. CMG[11:0] = 741d;
gain is 1 in PAL

LAGC[1:0] settings decide
in which mode LMG[11:0]
operates

LMG[11:0] = 1600d;
gain is 1 in NTSC

LMG[11:0] = 1630d;
gain is 1 in PAL

EAV/SAV codes generated
to suit Analog Devices
encoders

Manual VS/FIELD position
controlled by the 0x32, 0x33,
and 0xE5 to 0xEA registers

VS goes high in the middle
of the line (even field)

VS changes state at the
start of the line (even field)

VS goes high in the middle
of the line (odd field)

VS changes state at the
start of the line (odd field)

VS goes low in the middle
of the line (even field)

VS changes state at the
start of the line (even field)

VS goes low in the middle
of the line (odd field)

VS changes state at the
start of the line odd field

Min value is 0 dec
(G = 1/1000)
Max value is 3750 dec
(Gain = 5)

Only has an effect if
LAGC[1:0] is set to auto
gain (001, 010, 011,or 100)

Minimum value
NTSC 2048 (G = 0.5)
PAL 2048 (G = 0.5)

Maximum value
NTSC 4095 (G = 2)
PAL 4095 (G = 2)

NEWAVMODE bit must be
set high

NEWAVMODE bit must be
set high

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x34 HS Position Control 1

0x35 HS Position Control 2

0x36 HS Position Control 3 H SE[7:0] Se e above. 0 0 0 0 0 0 0 0
0x37 Polarity

0x38 NTSC Comb Control

HSE[10:8]. HS end
allows positioning of
the HS output within
the video line.

Reserved. 0 Set to 0
HSB[10:8]. HS begin

allows positioning of
the HS output within
the video line.

Reserved. 0 Set to 0
HSB[7:0] See above,

using HSB[10:0] and
HSE[10:0], users can
program the position
and length of HS output
signal.

PCLK. Sets polarity of
LLC1.

Reserved. 0 0 Set to 0
PF. Sets the FIELD

polarity.

Reserved. 0 Set to 0
PVS. Sets the VS

polarity.

Reserved. 0 Set to 0
PHS. Sets HS polarity.

YCMN[2:0]. Luma
comb mode, NTSC.

CCMN[2:0]. Chroma
comb mode, NTSC.

CTAPSN[1:0]. Chroma
comb taps, NTSC.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 0 0

0 0 0

0 0 0 0 0 0 1 0

0 Invert polarity
1

0 Active high
1 Active low

0 Active high
1 Active low

0 Active high
1 Active low
0 0 0 Adaptive 3-line, 3-tap luma
1 0 0 Use low-pass notch
1 0 1 Fixed luma comb (2-line) Top lines of memory
1 1 0 Fixed luma comb (3-line) All lines of memory
1 1 1 Fixed luma comb (2-line) Bottom lines of memory
0 0 0

1 0 0 Disable chroma comb
1 0 1

1 1 0

1 1 1

0 0 Adapts three to two lines
0 1 Not used
1 0 Adapts five to three lines
1 1 Adapts five to four lines

Rev. A | Page 88 of 112

State) Comments

Notes

HS output ends HSE[10:0]
pixels after the falling edge
of hsync

HS output starts HSB[10:0]
pixels after the falling edge
of hsync

Normal polarity as per the
timing diagrams

3-line adaptive for
CTAPSN = 01

4-line adaptive for
CTAPSN = 10

5-line adaptive for
CTAPSN = 11

Fixed 2-line for
CTAPSN = 01

Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11

Fixed 3-line for
CTAPSN = 01

Fixed 4-line for
CTAPSN = 10
Fixed 5-line for
CTAPSN = 11

Fixed 2-line for
CTAPSN = 01

Fixed 3-line for
CTAPSN = 10

Fixed 4-line for
CTAPSN = 11

Using HSB and HSE the
user can program the
position and length of
the output hsync

Top lines of memory

All lines of memory

Bottom lines of memory

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x39 PAL Comb Control 0 0 0

1 0 0 Use low-pass notch
1 1 0 Fixed luma comb Top lines of memory
1 1 0 Fixed luma comb (5-line) All lines of memory

1 0 0 Disable chroma comb
Fixed 2-line for CTAPSN = 01 Top lines of memory
Fixed 3-line for CTAPSN = 10

Fixed 3-line for CTAPSN = 01 All lines of memory
Fixed 4-line for CTAPSN = 10

1 1 1 Fixed 2-line for CTAPSN = 01 Bottom lines of memory
Fixed 3-line for CTAPSN = 10
Fixed 4-line for CTAPSN = 11
0 0

0 1 Not used
1 0

0x3A ADC Control

YCMP[2:0]. Luma
comb mode, PAL.

CCMP[2:0]. Chroma
comb mode, PAL.

CTAPSP[1:0]. Chroma
comb taps, PAL.

MUX PDN override.
MUX power-down
override.

When INSEL[3:0] is
used, unused channels
are automatically
powered down.

PWRDWN_MUX_2.
Enables power-down
of MUX_2 and
associated channel
clamp and buffer.

1

PWRDWN_MUX_1.
Enables power-down
of MUX_1 and
associated channel
clamp and buffer.

1

PWRDWN_MUX_0.
Enables power-down
of MUX_0 and
associated channel
clamp and buffer.

1

Reserved.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

1 1 1 Fixed luma comb (3-line) Bottom lines of memory
0 0 0

1 0 1

1 1 0

1 1

0

1

0

0

0 0 0 1 Set as default

State) Comments

Notes

No control over power­down for muxes and
associated channel circuit

Allows power-down of
MUX_0/1/2 and associated
channel circuit

MUX PDN override =1

MUX PDN override =1

MUX PDN override =1

0

Adaptive 5-line, 3-tap luma
comb

3-line adaptive
for CTAPSN = 01

4-line adaptive
for CTAPSN = 10

5-line adaptive
for CTAPSN = 11

Fixed 4-line for CTAPSN = 11

Fixed 5-line for CTAPSN = 11

Adapts five to two lines
(two taps)

Adapts five to three lines
(three taps)

Adapts five to four lines
(four taps)

MUX_2 and associated
channel in normal operation

Power down MUX_2 and
associated channel operation

MUX_1 and associated
channel in normal operation

Power down MUX_1 and
associated channel operation

MUX_0 and associated
channel in normal operation

Power down MUX_0 and
associated channel operation

Rev. A | Page 89 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0x3D

0x41 Resample Control

0x48 Gemstar Control 1

0x49 Gemstar Control 2 GDECEL[7:0]. 0 0 0 0 0 0 0 0

0x4A Gemstar Control 3

0x4B Gemstar Control 4 GDECOL[7:0]. 0 0 0 0 0 0 0 0

0x4C Gemstar Control 5

0x4D CTI DNR Control 1

0x4E CTI DNR Control 2

0x50 CTI DNR Control 4

Manual Window
Control

Reserved. 0 0 1 0 Set to default
CKILLTHR[2:0].

Reserved. 1 Set to default
Reserved. 0 0 0 0 0 1 Set to default
SFL_INV. Controls the

behavior of the PAL
switch bit.

Reserved. 0 Set to default
GDECEL[15:8]. See the

Comments column.

GDECOL[15:8]. See the
Comments column.

GDECAD. Controls the
manner in which
decoded Gemstar data
is inserted into the
horizontal blanking
period.

Reserved. x x x x x x x Undefined

CTI_AB_EN. Enables
the mixing of the
transient improved
chroma with the
original signal.

CTI_AB[1:0]. Controls
the behavior of the
alpha-blend circuitry.

Reserved. 0 Set to default
DNR_EN. Enable or

bypass the DNR block.

Reserved. 1 1 Set to default
CTI_C_TH[7:0].

Specifies how big the
amplitude step must
be to be steepened by
the CTI block.

DNR_TH[7:0]. Specifies
the maximum edge
that is interpreted as
noise and is therefore
blanked.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 0 0 Kill at 0.5%
0 0 1 Kill at 1.5%
0 1 0 Kill at 2.5%
0 1 1 Kill at 4%
1 0 0 Kill at 8.5%
1 0 1 Kill at 16%
1 1 0 Kill at 32%
1 1 1 Reserved

0

1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 Split data into half-byte To avoid 00/FF code

1

0 Disable CTI CTI_EN. CTI enable.
1 Enable CTI
0 Disable CTI alpha blender

0 0 Sharpest mixing
0 1 Sharp mixing
1 0 Smooth

0 Bypass the DNR block
1 Enable the DNR block

0 0 0 0 1 0 0 0

0 0 0 0 1 0 0 0

State) Comments

Notes

CKE = 1 enables the color
kill function and must be
enabled for CKILLTHR[2:0]
to take effect

SFL compatible with
ADV7190/ADV7191/
ADV7194 encoders

SFL compatible with
ADV717x/ADV7173x
encoders

GDECEL[15:0]: sixteen
individual enable bits that
select the lines of video
(even field Line 10 to Line 25)
that the decoder checks for
Gemstar-compatible data

GDECOL[15:0]: sixteen
individual enable bits that
select the lines of video
(odd field Line 10 to Line 25)
that the decoder checks for
Gemstar-compatible data

Output in straight 8-bit
format

1 Enable CTI alpha blender

1 1 Smoothest

Set to 0x04 for AV input;
set to 0x0A for tuner input

LSB = Line 10
MSB = Line 25
Default = Do not check for
Gemstar-compatible data
on any lines [10 to 25] in
even fields

LSB = Line 10
MSB = Line 25
Default = Do not check for
Gemstar-compatible data
on any lines [10 to 25] in
odd fields

Rev. A | Page 90 of 112

ADV7180

Subaddress Register Bit Description

0x51 Lock Count

0x58

0x59

0x8F

0x99

0x9A

VSYNC/FIELD Pin
Control

Reserved. 0 Set to default
ADC Sampling Control.

Reserved. 0 0 0 0 0 Set to default
General-Purpose

Outputs

Free-Run Line
Length 1

CCAP1
(Read Only)

CCAP2
(Read Only)

CIL[2:0]. Count into
lock determines the
number of lines the
system must remain in
lock before showing a
locked status.

COL[2:0]. Count out of
lock determines the
number of lines the
system must remain
out-of-lock before
showing a lost-locked
status.

SRLS. Select raw lock
signal. Selects the
determination of the
lock status.

FSCLE. FSC lock enable.

VS/FIELD.
Vsync or field output.
ADV7180 LFCSP-40 only.

GPO[3:0].
ADV7180 LQFP-64 only.

Reserved.
Reserved. 0 0 0 0 Set to default
LLC_PAD_SEL[2:0].

Enables manual
selection of clock
for LLC1 pin.

Reserved. 0 Set to default
CCAP1[7:0] Closed

caption data register.
CCAP2[7:0] Closed

caption data register.

Bits (Shading Indicates Default

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 0 0 1 line of video
0 0 1 2 lines of video
0 1 0 5 lines of video
0 1 1 10 lines of video
1 0 0 100 lines of video
1 0 1 500 lines of video
1 1 0 1000 lines of video
1 1 1 100,000 lines of video
0 0 0 1 line of video
0 0 1 2 lines of video
0 1 0 5 lines of video
0 1 1 10 lines of video
1 0 0 100 lines of video
1 0 1 500 lines of video
1 1 0 1000 lines of video
1 1 1 100,000 lines of video
0 Over field with vertical info
1 Line-to-line evaluation

0

1

0 FIELD
1 VSYNC

0 CVBS/YPrPb modes only

1 Y/C mode only Mandatory write

0 Outputs 0 to GPO0, Pin 13
1 Outputs 1 to GPO0, Pin 13
0 Outputs 0 to GPO1, Pin 12
1 Outputs 1 to GPO1, Pin 12
0 Outputs 0 to GPO2, Pin 56
1 Outputs 1 to GPO2, Pin 56
0 Outputs 0 to GPO3, Pin 55
1 Outputs 1 to GPO3, Pin 55
0 GPO[3:0] three-stated GPO_Enable.
1 GPO[3:0] enabled
0 0 0

0 0 0

1 0 1

x x x x x x x x

x x x x x x x x

State) Comments

Notes

Lock status set only by
horizontal lock

Lock status set by
horizontal lock and
subcarrier lock

LLC1 (nominal 27 MHz)
selected out on LLC1 pin

LLC2 (nominal 13.5 MHz)
selected out on LLC1 pin

CCAP1[7] contains parity
bit for Byte 0

CCAP2[7] contains parity
bit for Byte 0

Pin 37 on LFCSP-40

GPO_Enable must be set to
1 for these bits to take
effect

For 16-bit 4:2:2 out,
OF_SEL[3:0] = 0010

Rev. A | Page 91 of 112

ADV7180

Subaddress Register Bit Description

0x9B

0x9C

0x9D

0xB2

0xC3 ADC SWITCH 1

0xC4 ADC Switch 2

0xDC Letterbox Control 1

0xDD Letterbox Control 2

Letterbox 1
(Read Only)

Letterbox 2
(Read Only)

Letterbox 3
(Read Only)

CRC Enable
(Write Only)

LB_LCT[7:0]. Letterbox
data register.

LB_LCM[7:0]. Letterbox
data register.

LB_LCB[7:0]. Letterbox
data register.

Reserved. 0 0 Set as default
CRC_ENABLE. Enable

CRC checksum
decoded from CGMS
packet to validate
CGMSD.

Reserved. 0 0 0 1 1 Set as default
MUX_0[3:0]. Manual

muxing control for
MUX0.

This setting controls
which input is routed
to the ADC for
processing.

Reserved. 0
MUX_1[3:0]. Manual

muxing control for
MUX1.

This setting controls
which input is routed
to the ADC for
processing.

Reserved.
MUX_2[3:0]. Manual

muxing control for
MUX2.

This setting controls
which input is routed
to the ADC for
processing.

Reserved. 0 0 0 0
MAN_MUX_EN. Enable

manual setting of the
input signal muxing.

LB_TH [4:0]. Sets the
threshold value that
determines if a line is
black.

Reserved. 1 0 1 Set as default
LB_EL[3:0]. Programs

the end line of the
activity window for LB
detection (end of field).

LB_SL[3:0]. Program
the start line of the
activity window for LB
detection (start of
field).

Bits (Shading Indicates Default

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

x x x x x x x x

x x x x x x x x

x x x x x x x x

0 Turn off CRC check
1

0 0 0 No connect No connect
0 0 1 AIN1 AIN1
0 1 0 AIN2 No connect
0 1 1 AIN3 No connect
1 0 0 AIN4 AIN2
1 0 1 AIN5 AIN3
1 1 0 AIN6 No connect
1 1 1 No connect No connect

0 0 0 No connect No connect
0 0 1 No connect No connect
0 1 0 No connect No connect
0 1 1 AIN3 No connect
1 0 0 AIN4 AIN2
1 0 1 AIN5 AIN3
1 1 0 AIN6 No connect
1 1 1 No connect No connect
0
0 0 0 No connect No connect
0 0 1 No connect No connect
0 1 0 AIN2 No connect
0 1 1 No connect No connect
1 0 0 No connect No connect
1 0 1 AIN5 AIN3
1 1 0 AIN6 No connect
1 1 1 No connect No connect

0 Disable
1 Enable

0 1 1 0 0

1 1 0 0

0 1 0 0

State) Comments

Notes

Reports the number of
black lines detected at the
top of active video

Reports the number of
black lines detected in the
bottom half of active video
if subtitles are detected

Reports the number of
black lines detected at the
bottom of active video

CGMSD goes high with
valid checksum

Default threshold for the
detection of black lines

LB detection ends with the
last line of active video on a
field, 1100b: 262/525

Letterbox detection aligned
with the start of active video,
0100b: 23/286 NTSC

This feature examines the
active video at the start
and end of each field; it
enables format detection
even if the video is not
accompanied by a CGMS
or WSS sequence

MAN_MUX_EN = 1

MAN_MUX_EN = 1

MAN_MUX_EN = 1

This bit must be set to 1 for
manual muxing

Rev. A | Page 92 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0xDE

0xDF

0xE0 Reserved. 0 0 0 1 0 1 0 0
0xE1 SD Offset Cb

0xE2 SD Offset Cr

0xE3 SD Saturation Cb

0xE4 SD Saturation Cr

0xE5 NTSC V Bit Begin

0xE6 NTSC V Bit End

ST_Noise Readback 1
(Read Only)

ST_Noise Readback 2
(Read Only)

ST NOISE[10:0]. Noise
measurement.

ST_NOISE[10:8]. x x x
ST_Noise_Valid. x

ST_NOISE[7:0]. x x x x x x x x

SD_OFF_CB [7:0].
Adjusts the hue by
selecting the offset for
the Cb channel.

SD_OFF_CR [7:0].
Adjusts the hue by
selecting the offset for
the Cr channel.

SD_SAT_CB [7:0].
Adjusts the saturation
by affecting gain on
the Cb channel.

SD_SAT_CR [7:0].
Adjusts the saturation
by affecting gain on
the Cr channel.

NVBEG[4:0]. Number of
lines after l
to set V high.

NVBEGSIGN.

NVBEGDELE. Delay
V bit going high by one
line relative to NVBEG
(even field).

NVBEGDELO. Delay
V bit going high by one
line relative to NVBEG
(odd field).

NVEND[4:0]. Number of
lines after l
to set V low.

NVENDSIGN.

NVENDDELE. Delay
V bit going low by one
line relative to NVEND
(even field).

NVENDDELO. Delay
V bit going low by one
line relative to NVEND
(odd field).

COUNT

COUNT

rollover

rollover

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

1 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 Chroma gain = 0 dB

1 0 0 0 0 0 0 0 Chroma gain = 0 dB

0 0 1 0 1 NTSC default (ITU-R BT.656)

0

1

0 No delay
1 Additional delay by one line

0 No delay
1 Additional delay by one line

0

1

0 No delay
1 Additional delay by one line

0 No delay
1 Additional delay by one line

State) Comments

Notes

When = 1, ST_Noise[10:0] is
valid

Set to low when manual
programming

Not suitable for user
programming

0 0 1 0 0 NTSC default (ITU-R BT.656)

Set to low when manual
programming

Not suitable for user
programming

Rev. A | Page 93 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0xE7 NTSC F Bit Toggle

NFTOG[4:0]. Number of
lines after l

COUNT

rollover

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

to toggle F signal.
NFTOGSIGN.

0

1

NFTOGDELE. Delay
F transition by one line
relative to NFTOG

0 No delay
1 Additional delay by one line

(even field).
NFTOGDELO. Delay

F transition by one line
relative to NFTOG

0 No delay
1 Additional delay by one line

(odd field).

0xE8 PAL V Bit Begin

PVBEG[4:0]. Number of
lines after l

COUNT

rollover

0 0 1 0 1 PAL default (ITU-R BT.656)

to set V high.
PVBEGSIGN.

0

1

PVBEGDELE. Delay V bit
going high by one line
relative to PVBEG (even

0 No delay
1 Additional delay by one line

field).
PVBEGDELO. Delay V bit

going high by one line
relative to PVBEG (odd

0 No delay
1 Additional delay by one line

field).

0xE9 PAL V Bit End

PVEND[4:0]. Number of
lines after l

COUNT

rollover

1 0 1 0 0 PAL default (ITU-R BT.656)

to set V low.
PVENDSIGN.

0

1

PVENDDELE. Delay V bit
going low by one line
relative to PVEND (even

0 No delay
1 Additional delay by one line

field).
PVENDDELO. Delay V bit

going low by one line
relative to PVEND (odd

0 No delay
1 Additional delay by one line

field).

0xEA PAL F Bit Toggle

0

PFTOG[4:0]. Number of
lines after l
to toggle F signal.

COUNT

rollover

PFTOGSIGN.

0 No delay

PFTOGDELE. Delay
F transition by one line
relative to PFTOG

1

1 Additional delay by one line

(even field).

0 No delay

PFTOGDELO. Delay
F transition by one line
relative to PFTOG

1 Additional delay by one line

(odd field).

State) Comments

Notes

0 0 0 1 1 NTSC default

Set to low when manual
programming

Not suitable for user
programming

Set to low when manual
programming

Not suitable for user
programming

Set to low when manual
programming

Not suitable for user
programming

0 0 0 1 1 PAL default (ITU-R BT.656)

Set to low when manual
programming

Not suitable for user
programming

Rev. A | Page 94 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0xEB V Blank Control 1

0xEC V Blank Control 2 0 0

0 1

1 0

0 0

0 1

1 0

0 0

0 1

1 0

0 0

0 1

1 0

PVBIELCM[1:0]. PAL VBI
even field line control.

PVBIOLCM[1:0]. PAL VBI
odd field line control.

NVBIELCM[1:0]. NTSC VBI
even field line control.

PVBIOLCM[1:0]. NTSC VBI
odd field line control.

PVBIECCM[1:0]. PAL VBI
even field color control.

PVBIOCCM[1:0]. PAL VBI
odd field color control.

NVBIECCM[1:0]. NTSC VBI
even field color control.

NVBIOCCM[1:0]. NTSC VBI
odd field color control.

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

0 0

0 1

1 0 VBI ends one line later (Line 22)
1 1

1 1

1 1

1 1

1 1

State) Comments

Notes

VBI ends one line earlier
(Line 335)

ITU-R BT.470 compliant
(Line 336)

VBI ends one line later
(Line 337)

VBI ends two lines later
(Line 338)

VBI ends one line earlier
(Line 22)

ITU-R BT.470 compliant
(Line 23)

VBI ends one line later
(Line 24)

VBI ends two lines later
(Line 25)

VBI ends one line earlier
(Line 282)

ITU-R BT.470-compliant
(Line 283)

VBI ends one line later
(Line 284)

VBI ends two lines later
(Line 285)

VBI ends one line earlier
(Line 20)

ITU-R BT.470-compliant
(Line 21)

VBI ends two lines later
(Line 23)

Color output beginning
Line 335

ITU-R BT.470-compliant color
output beginning Line 336

Color output beginning
Line 337

Color output beginning
Line 338

Color output beginning
Line 22

ITU-R BT.470-compliant color
output beginning Line 23

Color output beginning
Line 24

Color output beginning
Line 25

Color output beginning
Line 282

ITU-R BT.470-compliant color
output beginning Line 283

VBI ends one line later
(Line 284)

Color output beginning
Line 285

Color output beginning
Line 20

ITU-R BT.470 compliant color
output beginning
Line 21

Color output beginning
Line 22

Color output beginning
Line 23

Controls position of first
active (comb filtered) line
after VBI on even field in PAL

Controls position of first
active (comb filtered) line
after VBI on odd field in PAL

Controls position of first
active (comb filtered) line
after VBI on even field in NTSC

Controls position of first
active (comb filtered) line
after VBI on odd field in NTSC

Controls the position of first
line that outputs color after
VBI on even field in PAL

Controls the position of first
line that outputs color after
VBI on odd field in PAL

Controls the position of first
line that outputs color after
VBI on even field in NTSC

Controls the position of first
line which outputs color after
VBI on odd field in NTSC

Rev. A | Page 95 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0xF3 AFE Control 1

1 Antialiasing Filter 1 enabled

0 Antialiasing Filter 2 disabled

1 Antialiasing Filter 2 enabled

0 Antialiasing Filter 3 disabled

1

0 Override disabled

Reserved. 0 0 0 0

0xF4 Drive Strength

0xF8 IF Comp Control

AA_FILT_EN[2:0].
Antialiasing filter enable.

AA_FILT_MAN_OVR.
Antialiasing filter
override.

DR_STR_S[1:0]. Selects
the drive strength for
the sync output signals.

DR_STR_C[1:0]. Selects
the drive strength for
the clock output signal.

DR_STR[1:0]. Selects the
drive strength for the
data output signals.
Can be increased or
decreased for EMC or
crosstalk reasons.

Reserved. x x
IFFILTSEL[2:0]. IF filter

selection for PAL and
NTSC.

Reserved. 0 0 0 0 0

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0 Antialiasing Filter 1 disabled

1 Override enabled

0 0 Low drive strength (1×)
0 1

1 0

1 1 High drive strength (4×)
0 0 Low drive strength (1×)
0 1

1 0

1 1 High drive strength (4×)
0 0 Low drive strength (1×)
0 1

1 0

1 1 High drive strength (4×)

0 0 0 Bypass mode 0 dB

0 0 1 −3 dB −2 dB
0 1 0 −6 dB +3.5 dB
0 1 1 −10 dB +5 dB
1 0 0 Reserved

1 0 1 −2 dB +2 dB
1 1 0 −5 dB +3 dB
1 1 1 −7 dB +5 dB

State) Comments

Notes

AA_FILT_MAN_OVR must
be enabled to change
settings defined by
INSEL[3:0]

Antialiasing Filter 3
enabled

Medium-low drive
strength (2×)

Medium-high drive
strength (3×)

Medium-low drive
strength (2×)

Medium-high drive
strength (3×)

Medium-low drive
strength (2×)

Medium-high drive
strength (3×)

2 MHz 5 MHz

3 MHz 6 MHz

NTSC filters

PAL filters

Rev. A | Page 96 of 112

ADV7180

Bits (Shading Indicates Default

Subaddress Register Bit Description

0xF9 VS Mode Control

VS_COAST_MODE[1:0].

Reserved. 0 0 0 0

0xFB Peaking Control PEAKING_GAIN[7:0]. 0 1 0 0 0 0 0 0

0xFC Coring Threshold 2 DNR_TH2[7:0]. 0 0 0 0 0 1 0 0

7 6 5 4 3 2 1 0 LQFP-64 LFCSP-40

0

1

0

1

0 0 Autocoast mode
0 1 50 Hz coast mode
1 0 60 Hz coast mode
1 1 Reserved

State) Comments

Notes

Limits maximum vsync
frequency to 66.25 Hz
(475 lines/frame)

Limits maximum vsync
frequency to 70.09 Hz
(449 lines/frame)

Limits minimum vsync
frequency to 42.75 Hz
(731 lines/frame)

Limits minimum vsync
frequency to 39.51 Hz
(791 lines/frame)

Increases/decreases the
gain for high frequency
portions of the video signal.

Specifies the maximum
edge that is interpreted as
noise and therefore blanked.

EXTEND_VS_MAX_FREQ.

EXTEND_VS_MIN_FREQ.

This value sets up the
output coast frequency

Rev. A | Page 97 of 112

ADV7180

Table 104. Register Map Descriptions (Interrupt Operation)

(Shading Indicates

Bit

User Sub Map

Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes

0x40 Interrupt Configuration 1

0x42 Interrupt Status 1

0x43 Interrupt Clear 1

0x44 Interrupt Mask 1

(Read Only)

(Write Only)

(Read/Write)

INTRQ_OP_SEL[1:0]. Interrupt drive
level select.

set mode.

Reserved x Not used
MV_INTRQ_SEL[1:0]. Macrovision

interrupt select.

INTRQ_DUR_SEL[1:0]. Interrupt
duration select.

Reserved. x
Reserved. x
Reserved. x

Reserved. x

Reserved. 0 Not used
Reserved. 0 Not used
Reserved. 0 Not used

Reserved.

.

.

Reserved. 0 Not used
Reserved. 0 Not used
Reserved. 0 Not used

.

.

Reserved.

Default State)

0 0 Open drain
01 Drive low when active
10 Drive high when active
11 Reserved
0 Manual interrupt mode disabled MPU_STIM_INTRQ. Manual interrupt
1 Manual interrupt mode enabled

00 Reserved
0 1 Pseudo sync only
10 Color stripe only
11 Pseudo sync or color stripe
0 0 3 XTAL periods
01 15 XTAL periods
10 63 XTAL periods
1 1 Active until cleared
0 No change SD_LOCK_Q.
1 SD input has caused the decoder to go

0 No change SD_UNLOCK_Q.
1 SD input has caused the decoder to go

0 No Change SD_FR_CHNG_Q.
1 Denotes a change in the free-run status
0 No Change MV_PS_CS_Q.
1 Pseudo sync/color striping detected. See

0 Do not clear SD_LOCK_CLR.
1 Clears SD_LOCK_Q bit
0 Do not clear SD_UNLOCK_CLR.
1 Clears SD_UNLOCK_Q bit

0 Do not clear SD_FR_CHNG_CLR.
1 Clears SD_FR_CHNG_Q bit
0 Do not clear MV_PS_CS_CLR.
1 Clears MV_PS_CS_Q bit
x Not used
0 Masks SD_LOCK_Q bit SD_LOCK_MSK
1 Unmasks SD_LOCK_Q bit
0 Masks SD_UNLOCK_Q bit SD_UNLOCK_MSK
1 Unmasks SD_UNLOCK_Q bit

0 Masks SD_FR_CHNG_Q bit SD_FR_CHNG_MSK
1 Unmasks SD_FR_CHNG_Q bit
0 Masks MV_PS_CS_Q bit MV_PS_CS_MSK
1 Unmasks MV_PS_CS_Q bit
x Not used

These bits can be cleared
or masked in Registers

from an unlocked state to a locked state

from a locked state to an unlocked state

Reg. 0x40 MV_INTRQ_SEL[1:0] for
selection

0x43 and 0x44,
respectively

Rev. A | Page 98 of 112

ADV7180

(Shading Indicates

Bit

User Sub Map

Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes

0x45 Raw Status 2

0x46 Interrupt Status 2

0x47 Interrupt Clear 2

0x48 Interrupt Mask 2

0x49 Raw Status 3

(Read Only)

(Read Only)

(Write Only)

(Read/Write)

(Read Only)

CCAPD.

Reserved. xxx

Reserved. xx
MPU_STIM_INTRQ.

CCAPD_Q.

GEMD_Q.

Reserved. xx
SD_FIELD_CHNGD_Q.

Reserved. x Not used
Reserved. x Not used
MPU_STIM_INTRQ_Q.

Reserved. 0 0

Reserved. x Not used
Reserved. x Not used
MPU_STIM_INTRQ_CLR.

.

.

Reserved. 0 0 Not used

.

Reserved. 0 0 Not used
MPU_STIM_INTRQ_MSK

frame rate at output.

Reserved. x Not used

Reserved. x Not used
Reserved. x Not used
Reserved. x Not used

.

Default State)

0 No CCAPD data detected—

1 CCAPD data detected—VBI System 2

0 Current SD field is odd numbered EVEN_FIELD.
1 Current SD field is even numbered

0 MPU_STIM_INT = 0
1 MPU_STIM_INT = 1
0 Closed captioning not detected in the

1 Closed captioning data detected in the

0 Gemstar data not detected in the input

1 Gemstar data detected in the input

0 SD signal has not changed field from

1 SD signal has changed Field from odd to

0 Manual interrupt not set
1 Manual interrupt set
0 Do not clear—VBI System 2 CCAPD_CLR.
1 Clears CCAPD_Q bit – VBI System 2
0 Do not clear GEMD_CLR.
1 Clears GEMD_Q bit

0 Do not clear SD_FIELD_CHNGD_CLR.
1 Clears SD_FIELD_CHNGD_Q bit

0 Do not clear
1 Clears MPU_STIM_INTRQ_Q bit
0 Masks CCAPD_Q bit—VBI System 2 CCAPD_MSK
1 Unmasks CCAPD_Q bit—

0 Masks GEMD_Q bit—VBI System 2 GEMD_MSK
1 Unmasks GEMD_Q bit—VBI System 2

0 Masks SD_FIELD_CHNGD_Q bit SD_FIELD_CHNGD_MSK
1 Unmasks SD_FIELD_CHNGD_Q bit

0 Masks MPU_STIM_INTRQ_Q bit
1 Unmasks MPU_STIM_INTRQ_Q bit
0 SD 60 Hz signal output SD_OP_50Hz. SD 60 Hz/50 Hz
1 SD 50 Hz signal output
0 SD vertical sync lock not established SD_V_LOCK.
1 SD vertical sync lock established
0 SD horizontal sync lock not established SD_H_LOCK.
1 SD horizontal sync lock established

0 SECAM lock not established SCM_LOCK.
1 SECAM lock established

VBI System 2

input video signal—VBI System 2

video input signal—VBI System 2

video signal—VBI System 2

video signal—VBI System 2

odd to even or vice versa

even or vice versa

VBI System 2

These bits are status bits
only; they cannot be
cleared or masked;
Register 0x46 is used for
this purpose

These bits can be cleared
or masked by Registers
0x47 and 0x48,
respectively

Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer

Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer

Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS, and
WSS data is using the
Mode 1 data slicer.

These bits are status bits
only; they cannot be
cleared or masked;
Register 0x4A is used for
this purpose

Rev. A | Page 99 of 112

ADV7180

(Shading Indicates

Bit

User Sub Map

Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes

0x4A Interrupt Status 3

0x4B Interrupt Clear 3

0x4C Interrupt Mask 3

(Read Only)

(Write only)

(Read/Write)

SD_OP_CHNG_Q. SD 60 Hz/50 Hz
frame rate at output.

SD_AD_CHNG_Q. SD autodetect
changed.

PAL_SW_LK_CHNG_Q.

Reserved. x Not used
Reserved. x Not used

Reserved. x Not used
Reserved. x Not used

.

.

.

.

.

.

Reserved. x Not used
Reserved. x Not used

Default State)

0 No change in SD signal standard

1 A change in SD signal standard is

0 No change in SD vsync lock status SD_V_LOCK_CHNG_Q.
1 SD vsync lock status has changed
0 No change in SD hsync lock status SD_H_LOCK_CHNG_Q.
1 SD hsync lock status has changed
0 No change in AD_RESULT[2:0] bits in

1 AD_RESULT[2:0] bits in Status Register 1

0 No change in SECAM lock status SCM_LOCK_CHNG_Q. SECAM lock.
1 SECAM lock status has changed
0 No change in PAL swinging burst

1 PAL swinging burst lock status has

0 Do not clear SD_OP_CHNG_CLR.
1 Clears SD_OP_CHNG_Q bit
0 Do not clear SD_V_LOCK_CHNG_CLR.
1 Clears SD_V_LOCK_CHNG_Q bit
0 Do not clear SD_H_LOCK_CHNG_CLR.
1 Clears SD_H_LOCK_CHNG_Q bit
0 Do not clear SD_AD_CHNG_CLR.
1 Clears SD_AD_CHNG_Q bit
0 Do not clear SCM_LOCK_CHNG_CLR.
1 Clears SCM_LOCK_CHNG_Q bit
0 Do not clear PAL_SW_LK_CHNG_CLR.
1 Clears PAL_SW_LK_CHNG_Q bit

0 Masks SD_OP_CHNG_Q bit SD_OP_CHNG_MSK
1 Unmasks SD_OP_CHNG_Q bit
0 Masks SD_V_LOCK_CHNG_Q bit SD_V_LOCK_CHNG_ MSK
1 Unmasks SD_V_LOCK_CHNG_Q bit
0 Masks SD_H_LOCK_CHNG_Q bit SD_H_LOCK_CHNG_ MSK
1 Unmasks SD_H_LOCK_CHNG_Q bit
0 Masks SD_AD_CHNG_Q bit SD_AD_CHNG_ MSK
1 Unmasks SD_AD_CHNG_Q bit
0 Masks SCM_LOCK_CHNG_Q bit SCM_LOCK_CHNG_ MSK
1 Unmasks SCM_LOCK_CHNG_Q bit
0 Masks PAL_SW_LK_CHNG_Q bit PAL_SW_LK_CHNG_ MSK
1 Unmasks PAL_SW_LK_CHNG_Q bit

detected at the output

detected at the output

Status Register 1

have changed

lock status

changed

These bits can be cleared
and masked by Registers
0x4B and 0x4C,
respectively

Rev. A | Page 100 of 112