ANALOG DEVICES ADV7180 Service Manual

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10-Bit, 4× Oversampling

FEATURES

Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling

for Y/C mode, and 2× oversampling for YPrPb (per channel)
Three video input channels with on-chip antialiasing filter
CVBS (composite), Y/C (S-video), and YPrPb (component)

video input support
5-line adaptive comb filters and CTI/DNR video

enhancement
Adaptive Digital Line Length Tracking (ADLLT™),

signal processing, and enhanced FIFO management give

mini-TBC functionality
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
NTSC/PAL/SECAM autodetection
8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, FIELD

1.0 V analog input signal range
Four general-purpose outputs (GPO)

2

Full feature VBI data slicer with teletext support (WST)
Power-down mode and ultralow sleep mode current
2-wire serial MPU interface (I

2

C® compatible)

1.8 V analog, 1.8 V PLL, 1.8 V digital, 3.3 V I/O supply

−40°C to +85°C temperature grade
Two package types:

40-lead, 6 mm × 6 mm, Pb-free LFCSP

64-lead, 10 mm × 10 mm, Pb-free LQFP

GENERAL DESCRIPTION

The ADV7180 automatically detects and converts standard
analog baseband television signals compatible with worldwide
NTSC, PAL, and SECAM standards into 4:2:2 component video
data compatible with the 8-bit ITU-R BT.656 interface standard.

The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devices, Inc., digital video encoders, such as the
ADV7179. External HS, VS, and FIELD signals provide timing
references for LCD controllers and other video ASICs, if
required

The accurate 10-bit analog-to-digital conversion provides
professional quality video performance for consumer applications
with true 8-bit data resolution. Three analog video input channels
accept standard composite, S-video, or component video
signals, supporting a wide range of consumer video sources.

1

The ADV7180 LFCSP-40 uses one pin to output VS or FIELD.

2

ADV7180 LQFP-64 only.

1

SDTV Video Decoder

ADV7180

APPLICATIONS

Digital camcorders and PDAs
Low-cost SDTV PIP decoder for digital TVs
Multichannel DVRs for video security
AV receivers and video transcoding
PCI-/USB-based video capture and TV tuner cards
Personal media players and recorders
Smartphone/multimedia handsets
In-car/automotive infotainment units
Rearview camera/vehicle safety systems

FUNCTIONAL BLOCK DIAGRAM

XTAL1

XTAL

ANALOG

VIDEO

INPUTS

AIN1

A

2

IN

A

3

IN

1

A

4

IN

1

AIN5

AIN6

1

ONLY AVAILABLE ON 64-LEAD PACKAGE.

2

40-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD.

1

MUX BLOCK

ADV7180

AGC and clamp-restore circuitry allow an input video signal
peak-to-peak range up to 1.0 V. Alternatively, these can be
bypassed for manual settings.

The line-locked clock output allows the output data rate, timing
signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length
variation. Output control signals allow glueless interface
connections in many applications. The ADV7180 is programmed
via a 2-wire, serial, bidirectional port (I

The ADV7180 is fabricated in a 1.8 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. A chip-scale, 40-lead, Pb-free
LFCSP package option makes the decoder ideal for space­constrained portable applications. A 64-lead LQFP package is
also available (pin compatible with ADV7181B).

CLOCK PROCESSI NG BLOCK

10-BIT, 86MHz

AA

FILTER

AA

FILTER

AA

FILTER

REFERENCE

PLL ADLLT PROCESSING

DIGITAL

ADC

SHA A/D

PROCESSING

BLOCK

2D COMB

VBI SLICER

COLOR

DEMOD

2

C/CONTROL

I

SCLK SDATA ALSB RESET PWRDWN

Figure 1.

2

C compatible).

LLC

1

8-BIT/16

-BIT

PIXEL DATA

P7 TO P0

FIFOOUTPUT BLOCK

VS

HS

2

FIELD

1

GPO

SFL

INTRQ

05700-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADV7180

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 3

Introduction ...................................................................................... 4

Analog Front End......................................................................... 4

Standard Definition Processor ................................................... 4

Comparison with the ADV7181B.............................................. 5

Functional Block Diagrams............................................................. 6

Specifications..................................................................................... 7

Electrical Characteristics............................................................. 7

Video Specifications..................................................................... 8

Timing Specifications .................................................................. 9

Analog Specifications................................................................... 9

Thermal Specifications ................................................................ 9

Timing Diagrams........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions .........................12

40-Lead LFCSP ...........................................................................12

64-Lead LQFP............................................................................. 13

Analog Front End........................................................................... 15

Input Configuration................................................................... 16

INSEL[3:0], Input Selection, Address 0x00 [3:0] ...................16

Analog Input Muxing ................................................................ 17

Antialiasing Filters ..................................................................... 18

Global Control Registers ............................................................... 19

Power-Saving Modes .................................................................. 19

Reset Control .............................................................................. 19

Global Pin Control..................................................................... 19

Global Status Register .................................................................... 21

Identification............................................................................... 21

Status 1 .........................................................................................21

Autodetection Result.................................................................. 21

Status 2 .........................................................................................21

Status 3 .........................................................................................21

Video Processor .............................................................................. 22

SD Luma Path ............................................................................. 22

SD Chroma Path ......................................................................... 22

Sync Processing .......................................................................... 23

VBI Data Recovery..................................................................... 23

General Setup.............................................................................. 23

Color Controls............................................................................ 25

Clamp Operation........................................................................ 27

Luma Filter .................................................................................. 28

Chroma Filter.............................................................................. 31

Gain Operation........................................................................... 32

Chroma Transient Improvement (CTI) .................................. 36

Digital Noise Reduction (DNR) and Luma Peaking Filter... 37

Comb Filters................................................................................ 38

IF Filter Compensation ............................................................. 40

AV Code Insertion and Controls ............................................. 41

Synchronization Output Signals............................................... 43

Sync Processing .......................................................................... 50

VBI Data Decode ....................................................................... 50

2

I

C Readback Registers .............................................................. 59

Pixel Port Configuration ............................................................... 72

GPO Control................................................................................... 73

MPU Port Description................................................................... 74

Register Access............................................................................ 75

Register Programming............................................................... 75

2

I

C Sequencer.............................................................................. 75

2

I

C Register Maps........................................................................... 76

2

I

C Programming Examples........................................................ 106

ADV7180 LQFP-64 .................................................................. 106

ADV7180 LFCSP-40................................................................ 107

PCB Layout Recommendations.................................................. 108

Analog Interface Inputs........................................................... 108

Power Supply Decoupling .......................................................108

PLL ............................................................................................. 108

VREFN and VREFP................................................................. 108

Digital Outputs (Both Data and Clocks) .............................. 108

Digital Inputs ............................................................................ 108

Typical C i r c uit Conne c tion ......................................................... 109

Outline Dimensions .....................................................................111

Ordering Guide ........................................................................ 111

Rev. A | Page 2 of 112

ADV7180

REVISION HISTORY

11/06—Rev. 0 to Rev. A

Changes to Table 10 and Table 11 .................................................16

Changes to Table 30 ........................................................................28

Changes to Gain Operation Section .............................................33

Changes to Table 43 ........................................................................35

Changes to Table 97 ........................................................................72

Changes to Table 99 ........................................................................73

Changes to Table 103 ......................................................................80

Changes to Figure 54 ....................................................................110

1/06—Revision 0: Initial Version

Rev. A | Page 3 of 112

ADV7180

INTRODUCTION

The ADV7180 is a versatile one-chip multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-video, and
component video into a digital ITU-R BT.656 format.

The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devides digital video encoders, such as the ADV7179.
External HS, VS, and FIELD signals provide timing references
for LCD controllers and other video ASICs that do not support
the ITU-R BT.656 interface standard.

ANALOG FRONT END

The ADV7180 analog front end comprises a single high speed,
10-bit, analog-to-digital converter (ADC) that digitizes the
analog video signal before applying it to the standard definition
processor. The analog front end employs differential channels
to the ADC to ensure high performance in mixed-signal
applications.

The front end also includes a 3-channel input mux that enables
multiple composite video signals to be applied to the ADV7180.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see
is performed downstream by digital fine clamping within
the ADV7180.

Tabl e 1 shows the three ADC clocking rates, which are determined
by the video input format to be processed—that is, INSEL[3:0].
These clock rates ensure 4× oversampling per channel for CVBS
mode and 2× oversampling per channel for Y/C and YPrPb modes.

Table 1. ADC Clock Rates

Input Format ADC Clock Rate

CVBS 57.27 MHz 4×
Y/C (S-Video)
YPrPb 86 MHz 2×

1

Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins.

2

Refer to INSEL[3:0] in Table 103 for the mandatory write for Y/C (S-video) mode.

Figure 24). Fine clamping of the video signal

Oversampling

1

Rate per Channel

2

86 MHz 2×

STANDARD DEFINITION PROCESSOR

The ADV7180 is capable of decoding a large selection of
baseband video signals in composite, S-video, and component
formats. The video standards supported by the video processor
include PA L B/D/I / G /H, PAL 6 0 , PAL M, PA L N, PAL Nc,
NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The
ADV7180 can automatically detect the video standard and
process it accordingly.

The ADV7180 has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the
video standard and signal quality without requiring user
intervention. Video user controls such as brightness, contrast,
saturation, and hue are also available with the ADV7180.

The ADV7180 implements a patented Adaptive Digital Line
Length Tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7180 to track and decode poor quality video sources such
as VCRs and noisy sources from tuner outputs, VCD players,
and camcorders. The ADV7180 contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.

The video processor can process a variety of VBI data services,
such as closed captioning (CCAP), wide-screen signaling
(WSS), copy generation management system (CGMS), EDTV,
Gemstar® 1×/2×, and extended data service (XDS). Teletext data
slicing for world standard teletext (WST), along with program
delivery control (PDC) and video programming service (VPS),
are provided. Data is transmitted via the 8-bit video output port
as ancillary data packets (ANC). The ADV7180 is fully
Macrovision certified; detection circuitry enables Type I,
Type II, and Type III protection levels to be identified and
reported to the user. The decoder is also fully robust to all
Macrovision signal inputs.

Rev. A | Page 4 of 112

ADV7180

COMPARISON WITH THE ADV7181B

In comparison with the ADV7181B, the ADV7180 LQFP-64 has
the following additional features:

• Improved VCR and weak tuner locking capabilities

• Three on-chip antialiasing filters

• Four general-purpose outputs (GPOs)

• 1.8 V analog supply voltage

• 40-lead LFCSP option

• Automatic power-down of unused channels when using

INSEL[3:0]

Pin Compatibility with the ADV7181B

The ADV7180 LQFP-64 is pin compatible with the ADV7181B.

A complete ADV7181B-to-ADV7180 change over document is
available on request that specifies software changes required to
make the transition. Contact Analog Devices local field
engineers for more information.

Please note that the ADV7180 has a different ADC reference
decoupling circuit (shown in

0.1µF

Figure 2. ADV7180 ADC Reference Decoupling Circuit

Figure 2) than the ADV7181B.

0.1µF

0.1µF

VREFN

VREFP

05700-002

Rev. A | Page 5 of 112

ADV7180

ANA

A

FUNCTIONAL BLOCK DIAGRAMS

CLOCK PROCESSING BL OCK

PLL ADLLT PROCESSING

10-BIT, 86MHz

AA

AA

AA

ADC

SHA A/D

REFERENCE

DIGITAL

PROCESSING

BLOCK

2D COMB

VBI SLICER

COLOR
DEMOD

2

I

C/CONTROL

SCLK S DATA ALSB RESET PWRDWN

FIFOOUTPUT BLOCK

LLC

16-BIT
PIXEL DATA

P15 TO P0

HS

VS

FIELD

GPO0 TO GPO3

SFL

INTRQ

05700-003

LOG

VIDEO

INPUTS

XTAL1

XTAL

AIN1

A

IN

A

IN

A

IN

A

IN

A

IN

MUX BLOCK

FILTER

FILTER

FILTER

2

3

4

5

6

Figure 3. Functional Block Diagram (64-Lead LQFP)

CLOCK PROCESSI NG BLOCK

PLL ADLLT PROCESSING

10-BIT, 86MHz

AA

AA

AA

ADC

SHA A/D

DIGITAL

PROCESSING

BLOCK

2D COMB

VBI SLICER

COLOR

DEMOD

FIFOOUTPUT BLO CK

LLC

8-BIT
PIXEL DATA

P7 TO P0

HS

VS/FIELD

SFL

NALOG

VIDEO

INPUTS

XTAL1

XTAL

AIN1

AIN2

AIN3

MUX BLOCK

FILTER

FILTER

FILTER

REFERENCE

2

I

C/CONTROL

SCLK SDATA ALSB RESET PWRDWN

Figure 4. Functional Block Diagram (40-Lead LFCSP)

Rev. A | Page 6 of 112

INTRQ

05700-004

ADV7180

SPECIFICATIONS

Temperature range: T

ELECTRICAL CHARACTERISTICS

At A
range, unless otherwise noted.

Table 2.

Parameter Symbol Test Conditions Min Typ Max Unit

STATIC PERFORMANCE

DIGITAL INPUTS

DIGITAL OUTPUTS

POWER REQUIREMENTS

1

2

= 1.71 V to 1.89 V, D

VDD

Resolution (Each ADC) N 10 Bits
Integral Nonlinearity INL BSL in CVBS mode 2 LSB
Differential Nonlinearity DNL CVBS mode −0.6/+0.6 LSB

Input High Voltage V
Input Low Voltage V

Crystal Inputs V

Crystal Inputs V
Input Current I
Input Capacitance C

Output High Voltage V
Output Low Voltage V
High Impedance Leakage Current I
Output Capacitance C

Digital Power Supply D
Digital I/O Power Supply D
PLL Power Supply P
Analog Power Supply A
Digital Supply Current I
Digital I/O Supply Current I
PLL Supply Current I
Analog Supply Current I
Y/C input 59 mA
YPrPb input 77 mA
Power-Down Current I
I
I
I
Total Power Dissipation in Power-Down Mode2 15 μW
Power-Up Time t

Guaranteed by characterization.
ADV7180 clocked.

MIN

to T

1

is −40°C to +85°C. The min/max specifications are guaranteed over this range.

MAX

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

IH

IL

IH

IL

IN

IN

OH

OL

LEAK

OUT

= 1.65 V to 2.0 V, specified at operating temperature

VDD

2 V

0.8 V

1.2 V

0.4 V
–10 +10 μA
10 pF

I

= 0.4 mA 2.4 V

SOURCE

I

= 3.2 mA 0.4 V

SINK

10 μA
20 pF

VDD

VDDIO

VDD

VDD

DVDD

DVDDIO

PVDD

AVDD

DVDD

DVDDIO

PVDD

AVDD

PWRUP

1.65 1.8 2 V

3.0 3.3 3.6 V

1.65 1.8 2.0 V

1.71 1.8 1.89 V
77 mA
3 mA
12 mA
CVBS input 33 mA

6 μA

0.1 μA
1 μA
1 μA

20 ms

Rev. A | Page 7 of 112

ADV7180

VIDEO SPECIFICATIONS

Guaranteed by characterization. At A
specified at operating temperature range, unless otherwise noted.

Table 3.

Parameter Symbol Test Conditions Min Typ Max Unit

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulate 5-step [NTSC] 0.6 Degrees
Differential Gain DG CVBS input, modulate 5-step [NTSC] 0.5 %
Luma Nonlinearity LNL CVBS input, 5-step [NTSC] 2.0 %

NOISE SPECIFICATIONS

SNR Unweighted Luma ramp 57.1 dB
Luma flat field 58 dB
Analog Front-End Crosstalk 60 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range –5 +5 %
Vertical Lock Range 40 70 Hz
FSC Subcarrier Lock Range ±1.3 kHz
Color Lock-In Time 60 Lines
Sync Depth Range 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Autodetection Switch Speed 100 Lines
Chroma Lima Gain Delay CVBS 2.9 ns
Y/C 5.6 ns
YPrPb −3.0 ns

LUMA SPECIFICATIONS

Luma Brightness Accuracy CVBS, 1 V input 1 %
Luma Contrast Accuracy CVBS, 1 V input 1 %

= 1.71 V to 1.89 V, D

VDD

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V,

VDD

Rev. A | Page 8 of 112

ADV7180

TIMING SPECIFICATIONS

Guaranteed by characterization. At A
specified at operating temperature range, unless otherwise noted.

Table 4.

Parameter Symbol Test Conditions Min Typ Max Unit

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency 28.6363 MHz
Frequency Stability ±50 ppm

I2C PORT

SCLK Frequency 400 kHz
SCLK Minimum Pulse Width High t
SCLK Minimum Pulse Width Low t
Hold Time (Start Condition) t
Setup Time (Start Condition) t
SDA Setup Time t
SCLK and SDA Rise Times t
SCLK and SDA Fall Times t
Setup Time for Stop Condition t

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC1 Mark Space Ratio t9:t

DATA AND CONTROL OUTPUTS

Data Output Transitional Time t

Data Output Transitional Time t

= 1.71 V to 1.89 V, D

VDD

1

2

3

4

5

6

7

8

10

11

12

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V,

VDD

0.6 μs

1.3 μs

0.6 μs

0.6 μs
100 ns
300 ns
300 ns

0.6 μs

45:55 55:45 % duty cycle

Negative clock edge to start of valid data
(t

= t10 – t11)

ACCESS

End of valid data to negative clock edge

= t9 + t12)

(t

HOLD

3.6 ns

2.4 ns

ANALOG SPECIFICATIONS

Guaranteed by characterization. At A
specified at operating temperature range, unless otherwise noted.

Table 5.

Parameter Test Conditions Min Typ Max Unit

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF
Input Impedance Clamps switched off 10 MΩ
Large-Clamp Source Current 0.4 mA
Large-Clamp Sink Current 0.4 mA
Fine Clamp Source Current 10 μA
Fine Clamp Sink Current 10 μA

= 1.71 V to 1.89 V, D

VDD

= 1.65 V to 2.0 V, D

VDD

= 3.0 V to 3.6 V, P

VDDIO

= 1.65 V to 2.0 V,

VDD

THERMAL SPECIFICATIONS

Table 6.

Parameter Symbol Test Conditions Min Typ Max Unit

THERMAL CHARACTERISTICS

Junction-to-Ambient Thermal

Resistance (Still Air)
Junction-to-Case Thermal Resistance θ

Junction-to-Ambient Thermal

Resistance (Still Air)
Junction-to-Case Thermal Resistance θ

θ

JA

4-layer PCB with solid ground plane,
40-lead LFCSP

JC

4-layer PCB with solid ground plane,
40-lead LFCSP

θ

JA

4-layer PCB with solid ground plane,
64-lead LQFP

JC

4-layer PCB with solid ground plane,
64-lead LQFP

30 °C/W

3 °C/W

47 °C/W

11.1 °C/W

Rev. A | Page 9 of 112

ADV7180

S

TIMING DIAGRAMS

t

t

1

t

7

5

Figure 5. I

2

C Timing

DATA

SCLK

t

3

t

6

t

2

OUTPUT LLC

OUTPUTS P0–P15, VS,

HS, FIE LD,

SFL

t

9

t

12

Figure 6. Pixel Port and Control Output Timing

t

t

11

t

3

t

4

10

t

8

05700-005

05700-006

Rev. A | Page 10 of 112

ADV7180

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

A

to AGND 2.2 V

VDD

D

to DGND 2.2 V

VDD

P

to AGND 2.2 V

VDD

D

to DGND 4 V

VDDIO

D

to A
P
D
D
A
A

VDDIO

VDD

VDDIO

VDDIO

VDD

VDD

to D

to P

to D

to P
to D

VDD

VDD

VDD

VDD

VDD

VDD

Digital Inputs Voltage DGND − 0.3 V to D
Digital Output Voltage DGND − 0.3 V to D
Analog Inputs to AGND AGND − 0.3 V to A
Maximum Junction Temperature

(T

max)

J

−0.3 V to +2 V

−0.3 V to +0.9 V
–0.3 V to +2 V

−0.3 V to +2 V

−0.3 V to +0.3 V

−0.3 V to +0.9 V

125°C

VDDIO

VDDIO

+ 0.3 V

VDD

+ 0.3 V
+ 0.3 V

Storage Temperature Range −65°C to +150°C
Infrared Reflow Soldering (20 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

ESD CAUTION

Rev. A | Page 11 of 112

ADV7180

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

40-LEAD LFCSP

B

SDATA34SCLK35DGND36DVDD37VS/FIELD38INTRQ

ALS

RESET

32

31

33

30

AIN3

29

AIN2

28

AGND

27

AVD D

26

VREFN

25

VREFP

24

AGND

23

AIN1

22

TEST_0

21

AGND

15

17P016P118

19

20

N

ND

DW

ELPF

DG

PVDD

R

PW

05700-007

DVDDIO

SFL

DGND

DVDDIO

P7
P6
P5
P4
P3
P2

ND

DG

39HS40

PIN 1

1

INDICATOR

2
3
4
5
6
7
8
9

10

ADV7180

LFCSP

TOP VIEW

(Not to Scale)

11

12

13

14

LLC

XTAL

DVDD

XTAL1

Figure 7. 40-Lead LFCSP Pin Configuration

Table 8. Pin Function Descriptions for the ADV7180 LFCSP-40

Pin No. Mnemonic Type Function

3, 15, 35, 40 DGND G Ground for Digital Supply.
21, 24, 28 AGND G Ground for Analog Supply.
1, 4 DVDDIO P Digital I/O Supply Voltage (3.3 V).
14, 36 DVDD P Digital Supply Voltage (1.8 V ).
27 AVDD P Analog Supply Voltage (1.8 V).
20 PVDD P PLL Supply Voltage (1.8 V).
23, 29, 30 AIN1 to AIN3 I Analog Video Input Channels.
5 to 10, 16, 17 P7 to P2, P1, P0 O Video Pixel Output Port.
39 HS O Horizontal Synchronization Output Signal.
38

INTRQ

O

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see

Table 104).
37 VS/FIELD O Vertical Synchronization Output Signal/Field Synchronization Output Signal.
33 SDATA I/O I2C Port Serial Data Input/Output Pin.
34 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
32 ALSB I

Selects the I

2

C Address for the ADV7180. For ALSB set to Logic 0, the address selected for a

write is 0xTBC; for ALSB set to logic high, the address selected is 0xTBC.

31

RESET

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.

11 LLC O

Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz, but varies up or
down according to video line length.

13 XTAL I

Input Pin for the 28.6363 MHz Crystal. Can be overdriven by an external 1.8 V, 28.6363 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

12 XTAL1 O

This pin should be connected to the 28.6363 MHz crystal, or not connected if an external

1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.

18

PWRDWN

19 ELPF I

I A logic low on this pin places the ADV7180 into power-down mode.

The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 53.

2 SFL O

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital video

encoder.
26 VREFN O Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
25 VREFP O Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
22 TEST_0 I This pin must be tied to DGND.

Rev. A | Page 12 of 112

ADV7180

64-LEAD LQFP

6

FIELD62P1261P1360P1459P1558DVDD57DGND56GPO255GPO354SCLK53SDATA52ALSB51RESET50NC49A

64VS63

1

INTRQ

HS

DGND

DVDDIO

P11
P10

P9
P8

SFL

DGND

DVDDIO

GPO1
GPO0

P7
P6
P5

NC = NO CONNECT

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

PIN 1

17P418P319P220

21

LLC

ADV7180

TOP VIEW

(Not to Scale)

22

23

XTAL

XTAL1

LQFP

24

25P126P027NC28NC29

DVDD

DGND

PWRDWN

Figure 8. 64-Lead LQFP Pin Configuration

IN

48

AIN5

47

AIN4

46

AIN3

45

NC

44

NC

43

AGND

42

NC

41

NC

40

AVDD

39

VREFN

38

VREFP

37

AGND

36

AIN2

35

AIN1

34

TEST_0

33

NC

30

31

32

ELPF

PVDD

AGND

05700-008

Table 9. Pin Function Description for the ADV7180 LQFP-64

Pin No. Mnemonic Type Function

3, 10, 24, 57 DGND G Digital Ground.
32, 37, 43 AGND G Analog Ground.
4, 11 DVDDIO P Digital I/O Supply Voltage (3.3 V).
23, 58 DVDD P Digital Supply Voltage (1.8 V).
40 AVDD P Analog Supply Voltage (1.8 V).
31 PVDD P PLL Supply Voltage (1.8 V).
38 VREFP O Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
39 VREFN O Internal Voltage Reference Output. See Figure 54 for recommended output circuitry.
35, 36, 46 to 49 AIN1 to AIN6 I Analog Video Input Channels.

27, 28, 33, 41, 42,
44, 45, 50

5 to 8, 14 to 19,
25, 26, 59 to 62

NC

P11 to P8,
P7 to P2, P1,

O

No Connect Pins. These pins are not connected internally.

Video Pixel Output Port. See Table 96 for output configuration for 8-bit and 16-bit modes.

P0, P15 to P12

2 HS O Horizontal Synchronization Output Signal.
64 VS O Vertical Synchronization Output Signal.
63 FIELD O Field Synchronization Output Signal.
1

INTRQ

O

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).

53 SDATA I/O I2C Port Serial Data Input/Output Pin.
54 SCLK I I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
52 ALSB I

29

PWRDWN

I A logic low on this pin places the ADV7180 in power-down mode.

30 ELPF I

This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address
selected for a write is 0x40; for ALSB set to logic high, the address selected is 0x42.

The recommended external loop filter must be connected to the ELPF pin, as shown in
Figure 54.

51

RESET

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.

Rev. A | Page 13 of 113

ADV7180

Pin No. Mnemonic Type Function

9 SFL O

20 LLC O

21 XTAL1 O

22 XTAL I

12, 13, 55, 56 GPO0 to GPO3 O

34 TEST_0 I This pin must be tied to DGND.

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.

This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz, but varies up or down according to video line length.

This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an
external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal
mode, the crystal must be a fundamental crystal.

This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external

1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a
fundamental crystal.

General-Purpose Outputs. These pins can be configured via I
devices.

2

C to allow control of external

Rev. A | Page 14 of 113

ADV7180

ANALOG FRONT END

2

IN

A

A

IN

IN

IN

IN

IN

A

A

A

A

5

6

3

4

1

3

2

1

IN

IN

IN

A

A

A

MAN_MUX_EN

AIN2
AIN1
AIN4
AIN3
AIN6
AIN5

AIN4
AIN3
AIN6
AIN5

AIN6
AIN5

MUX_0[3:0]

MUX_1[3:0]

MUX_2[3:0]

Figure 9. Internal Pin Connections LQFP-64

MAN_MUX_EN

ADC

05700-009

AIN1
AIN2
AIN3

AIN2
AIN3

AIN3

MUX_0[3:0]

MUX_1[3:0]

MUX_2[3:0]

ADC

05700-010

Figure 10. Internal Pin Connections LFCSP-40

Rev. A | Page 15 of 112

ADV7180

INPUT CONFIGURATION

There are two key steps for configuring the ADV7180 to
correctly decode the input video.

1. Use INSEL[3:0] to configure routing and format decoding

(CVBS, Y/C, or YPrPb). For the ADV7180 LQFP-64, see
Tabl e 10 . For ADV7180 LFCSP-40, see Ta ble 11 .

2. If the input requirements are not met using the INSEL[3:0]

options, the analog input muxing section must be
configured manually to correctly route the video from the
analog input pins to the ADC. The standard definition
processor block, which decodes the digital data, should be
configured to process either CVBS, Y/C, or YPrPb format.
This is performed by INSEL[3:0] selection.

CONNECT ANA LOG V IDEO

SIGNAL S TO ADV7180.

SET INSE L[3:0] TO CONFIG URE

VIDEO FORMAT. USE PREDEFI NED

FORMAT/ROUTING.

NO

YES

LQFP-64 LFCSP-40

CONFIGUR E ADC INPUTS US ING

MANUAL MUXI NG CONTROL BI TS:

REFER TO

TABLE 10

REFER T O

TABLE 11

Figure 11. Signal Routing Options

MUX_0[3:0], MUX_1[3:0] , MUX_2[ 3:0].

SEE TABL E 12.

INSEL[3:0], INPUT SELECTION, ADDRESS 0x00
[3:0]

The INSEL bits allow the user to select the input format. They
also configure the standard definition processor core to process
composite (CVBS), S-video (Y/C), or component (YPrPb)
format.

INSEL[3:0] has predefined analog input routing schemes that
do not require manual mux programming (see
Tabl e 11 ). This allows the user to route the various video signal
types to the decoder and select them using INSEL[3:0] only.
The added benefit is that if, for example, CVBS input is selected,
the remaining channels are powered down.

Table 1 0 and

05700-011

Table 10. ADV7180 LQFP-64 INSEL[3:0]

INSEL[3:0] Video Format Analog Input

0000 Composite
0001 Composite
0010 Composite
0011 Composite
0100 Composite
0101 Composite
0110 Y/C (S-video)

0111 Y/C (S-video)

1000 Y/C (S-video)

1001 YPrPb

1010 YPrPb

CVBS → AIN1
CVBS → A

IN

CVBS → AIN3
CVBS → A

IN

CVBS → AIN5
CVBS → AIN6
Y → AIN1

4

C → A

IN

Y → AIN2
C → AIN5
Y → AIN3
C → AIN6
Y → AIN1
Pb → AIN4
Pr → AIN5
Y → AIN2
Pr → AIN6
Pb → AIN3

2

4

1011 to 1111 Not used Not used

Table 11. ADV7180 LFCSP-40 INSEL[3:0]

INSEL[3:0] Video Format Analog Input

0000 Composite

CVBS → AIN1
0001 to 0010 Not used Not used
0011 Composite
0100 Composite

CVBS → AIN2

CVBS → AIN3
0101 Not used Not used
0110 Y/C (S-video)

Y → AIN1

C → AIN2
0111 to 1000 Not used Not used
1001 YPrPb

Y → AIN1

Pr → A

IN

Pb → A

3

2

IN

1010 to 1111 Not used Not used

Rev. A | Page 16 of 112

ADV7180

ANALOG INPUT MUXING

The ADV7180 has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder.
of the input muxing provided in the ADV7180.

A maximum of six CVBS inputs can be connected to and
decoded by the ADV7180BSTZ (64-lead LQFP) and a
maximum of three for ADV7180BCPZ (40-lead LFCSP). As
shown in the
section, these analog input pins lie in close proximity to one
another. This calls for a careful design of the PCB layout; for
example, ground shielding between all signals should be routed
through tracks that are physically close together. It is strongly
recommended to connect any unused analog input pins to
AGND to act as a shield.

Figure 9 and Figure 10 outline the overall structure

Pin Configurations and Function Description

MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4 [7]

To configure the ADV7180 analog muxing section, the user
must select the analog input A

1 to AIN3 (ADV7180BCPZ) that is to be processed by the

A

IN

1 to AIN6 (ADV7180BSTZ) or

IN

ADC. MAN_MUX_EN must be set to 1 to enable the following
muxing blocks:

• MUX_0[3:0], ADC Mux Configuration, Address 0xC3 [3:0]

• MUX_1[3:0], ADC Mux Configuration, Address 0xC3 [7:4]

• MUX_2[3:0], ADC Mux Configuration, Address 0xC4 [3:0]

The three mux sections are controlled by the signal buses
SW_0/1/2[3:0].

Tabl e 12 explains the control words used.

The input signal that contains the timing information (HS and
VS) must be processed by MUX_0. For example, in a Y/C input
configuration, MUX0 should be connected to the Y channel
and MUX1 to the C channel. When one or more muxes are not
used to process video, such as CVBS input, the idle mux and
associated channel clamps and buffers should be powered down
(see the description of Register 0x3A in

Tabl e 1 0 3).

Table 12. Manual Mux Settings for the ADC (MAN_MUX_EN Must be Set to 1)

ADC Connected to ADC Connected to ADC Connected to
MUX_0[3:0] LQFP-64 LFCSP-40 MUX_1[3:0] LQFP-64 LFCSP-40 MUX_2[3:0] LQFP-64 LFCSP-40

000 No connect No connect 000 No connect No connect 000 No connect No connect
001 AIN1 AIN1 001 No connect No connect 001 No connect No connect
010 AIN2 No connect 010 No connect No connect 010 AIN2 No connect
011 AIN3 No connect 011 AIN3 No connect 011 No connect No connect
100 AIN4 AIN2 100 AIN4 AIN2 100 No connect No connect
101 AIN5 AIN3 101 AIN5 AIN3 101 AIN5 AIN3
110 AIN6 No connect 110 AIN6 No connect 110 AIN6 No connect
111 No connect No connect 111 No connect No connect 111 No connect No connect

Note the following:

• CVBS can only be processed by MUX_0.

• Y/C can only be processed by MUX_0 and MUX_1, respectively.

• YPrPb can only be processed by MUX_0, MUX_1, and MUX_2, respectively.

Rev. A | Page 17 of 112

ADV7180

A

A

A

–

–12–

–

–24–28–

–

–

–

–

–

ANTIALIASING FILTERS

The ADV7180 has optional on-chip antialiasing filters on each
of the three channels that are multiplexed to the ADC (see
Figure 12). The filters are designed for standard definition video
up to 10 MHz bandwidth.

Figure 13 and Figure 14 show the

filter magnitude and phase characteristics.

The antialiasing filters are enabled by default and the selection
of INSEL[3:0] determines which filters are powered up at any
given time. For example, if CVBS mode is selected, the filter
circuits for the remaining input channels are powered down to
conserve power. However, the antialiasing filters can be disabled
or bypassed using the AA_FILT_MAN_OVR control.

10-BIT, 86MHz

AIN1

A

A

IN

IN

IN

AA

MUX BLOCK

FILTER 1

AA

FILTER 2

AA

FILTER 3

2

IN

3

IN

1

4

1

5

1

6

1

ONLY AVAIL ABLE IN 64-LE AD PACKAGE

ADC

SHA A/D

05700-012

Figure 12. Antialias Filter Configuration

AA_FILT_MAN_OVR, Antialiasing Filter Override,
Address 0xF3 [3]

This feature allows the user to override the antialiasing filters
on/off settings, which are automatically selected by INSEL[3:0].

AA_FILT_EN, Antialiasing Filter Enable, Address 0xF3 [2:0]

These bits allow the user to enable or disable the antialiasing
filters on each of the three input channels multiplexed to the
ADC. When disabled, the analog signal bypasses the AA filter
and is routed directly to the ADC.

AA_FILT_EN, Address 0xF3 [0]

When AA_FILT_EN[0] is 0, AA Filter 1 is bypassed.

When AA_FILT_EN[0] is 1, AA Filter 1 is enabled.

AA_FILT_EN, Address 0xF3 [1]

When AA_FILT_EN[1] is 0, AA Filter 2 is bypassed.

When AA_FILT_EN[1] is 1, AA Filter 2 is enabled.

AA_FILT_EN, Address 0xF3 [2]

When AA_FILT_EN[2] is 0, AA Filter 3 is bypassed.

When AA_FILT_EN[2] is 1, AA Filter 3 is enabled.

0

–4

–8

16

20

32

36

1k

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 13. Antialiasing Filter Magnitude Response

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

100

–110

120

130

140

150

1k

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 14. Antialiasing Filter Phase Response

100M

100M

05700-013

05700-014

Rev. A | Page 18 of 112

ADV7180

GLOBAL CONTROL REGISTERS

Register control bits listed in this section affect the whole chip.

POWER-SAVING MODES

Power-Down

PDBP, Address 0x0F [2]

The digital supply of the ADV7180 can be shut down by using
the (

PWRDWN

controls whether the I
priority. The default is to give the pin (

) pin or via I2C (PWRDWN, see below). PDBP

2

C control or the pin has the higher

PWRDWN

) priority.

This allows the user to have the ADV7180 powered down by
default at power-up without the need for an I

2

C write.

When PDBD is 0 (default), the digital supply power is controlled
by the

PWRDWN

pin (the PWRDWN bit is disregarded).

When PDBD is 1, the PWRDWN bit, 0x0F[5], has priority
(the pin is disregarded).

PWRDWN, Address 0x0F [5]

When PDBP is set to 1, setting the PWRDWN bit switches the
ADV7180 to a chip-wide power-down mode. The power-down
stops the clock from entering the digital section of the chip,
thereby freezing its operation. No I

2

C bits are lost during
power-down. The PWRDWN bit also affects the analog blocks
and switches them into low current modes. The I

2

C interface is

unaffected and remains operational in power-down mode.

The ADV7180 leaves the power-down state if the PWRDWN bit is
set to 0 (via I

2

C) or if the ADV7180 is reset using the

RESET

pin.

PDBP must be set to 1 for the PWRDWN bit to power down
the ADV7180.

When PWRDWN is 0 (default), the chip is operational.
When PWRDWN is 1, the ADV7180 is in a chip-wide
power-down mode.

RESET CONTROL

RESET, Chip Reset, Address 0x0F [7]

Setting this bit, which is equivalent to controlling the
pin on the ADV7180, issues a full chip reset. All I
are reset to their default/power-up values. Note that some
register bits do not have a reset value specified. They keep their
last written value. Those bits are marked as having a reset value
of x in the register tables (

Table 103 and Ta b le 1 04 ). After the
reset sequence, the part immediately starts to acquire the
incoming video signal.

RESET

2

C registers

After setting the RESET bit (or initiating a reset via the
the part returns to the default for its primary mode of operation.

2

All I

C bits are loaded with their default values, making this bit

self-clearing.

Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I
performed.

2

C master controller receives a no acknowledge condition

The I
on the ninth clock cycle when chip reset is implemented. See
the

MPU Port Description section.

When RESET is 0 (default), operation is normal.

When RESET is 1, the reset sequence starts.

GLOBAL PIN CONTROL

Three-State Output Drivers

TOD, Address 0x03 [6]

This bit allows the user to three-state the output drivers of the
ADV7180.

Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the
ADV7180 LFCSP-40), HS, VS, FIELD (VS/FIELD pin for the
ADV7180 LFCSP-40), and SFL pins are three-stated.

The timing pins (HS, VS, FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the

Three-State LLC Driver and the Timing Signals Output

Enable

sections.

Individual drive strength controls are provided via the
DR_STR_XX bits.

When TOD is 0 (default), the output drivers are enabled.

When TOD is 1, the output drivers are three-stated.

Three-State LLC Driver

TRI_LLC, Address 0x1D [7]

This bit allows the output drivers for the LLC pin of the
ADV7180 to be three-stated. For more information on three­state control, refer to the
Timing Signals Output Enable sections.

Individual drive strength controls are provided via the
DR_STR_XX bits.

When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).

When TRI_LLC is 1, the LLC pin drivers are three-stated.

Three-State Output Drivers and the

RESET

pin),

2

C writes are

Rev. A | Page 19 of 112

ADV7180

Timing Signals Output Enable

TIM_OE, Address 0x04 [3]

The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD into the active state (that is, driving state) even if the
TOD bit is set. If TIM_OE is set to low, the HS, VS, and FIELD
pins are three-stated depending on the TOD bit. This
functionality is beneficial if the decoder is to be used as a
timing generator only. This may be the case if only the timing
signals are to be extracted from an incoming signal, or if the
part is in free-run mode, where a separate chip can output a
company logo, for example.

For more information on three-state control, refer to the
Three-State Output Drivers section and the Three-State LLC
Driver

section.

Individual drive strength controls are provided via the
DR_STR_XX bits.

When TIM_OE is 0 (default), HS, VS, and FIELD are three­stated according to the TOD bit.

When TIM_OE is 1, HS, VS, and FIELD are forced active all the
time.

Drive Strength Selection (Data)

DR_STR[1:0], Address 0xF4 [5:4]

For EMC and crosstalk reasons, it may be desirable to
strengthen or weaken the drive strength of the output drivers.
The DR_STR[1:0] bits affect the P[15:0] output drivers.

For more information on three-state control, refer to the
Strength Selection (Clock)
(Sync)

sections.

Table 13. DR_STR Function

DR_STR[1:0] Description

00 Low drive strength (1×)
01 (default) Medium-low drive strength (2×)
10 Medium-high drive strength (3×)
11 High drive strength (4×)

and the Drive Strength Selection

Drive

Drive Strength Selection (Clock)

DR_STR_C[1:0], Address 0xF4 [3:2]

The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the
Strength Selection (Data)

Drive Strength Selection (Sync) and the Drive

sections.

Table 14. DR_STR_C Function

DR_STR_C[1:0] Description

00 Low drive strength (1×)
01 (default) Medium-low drive strength (2×)
10 Medium-high drive strength (3×)
11 High drive strength (4×)

Drive Strength Selection (Sync)

DR_STR_S[1:0], Address 0xF4 [1:0]

The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and FIELD are
driven. For more information, refer to the
Selection (Data)

Table 15. DR_STR_S Function

DR_STR_S[1:0] Description

00 Low drive strength (1×)
01 (default) Medium-low drive strength (2×)
10 Medium-high drive strength (3×)
11 High drive strength (4×)

section.

Drive Strength

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN, Address 0x04 [1]

The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as Genlock) from the ADV7180 core
to an encoder in a decoder/encoder back-to-back arrangement.

When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.

When EN_SFL_PIN is 1, the subcarrier frequency lock
information is presented on the SFL pin.

Polarity LLC Pin

PCLK, Address 0x37 [0]

The polarity of the clock that leaves the ADV7180 via the LLC
pin can be inverted using the PCLK bit.

Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.

When PCLK is 0, the LLC output polarity is inverted.

When PCLK is 1 (default), the LLC output polarity is normal
(see the

Timing Specifications section).

Rev. A | Page 20 of 112

ADV7180

GLOBAL STATUS REGISTER

Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV7180. The other three registers contain
status bits from the ADV7180.

IDENTIFICATION

IDENT[7:0], Address 0x11 [7:0]

The register identification of the revision of the ADV7180. An
identification value of 0x18 indicates the ADV7180.

STATUS 1

STATUS_1[7:0], Address 0x10 [7:0]

This read-only register provides information about the internal
status of the ADV7180.

See the
and the

CIL[2:0], Count Into Lock, Address 0x51 [2:0] section

COL[2:0], Count Out of Lock, Address 0x51 [5:3]

section for details on timing.

Depending on the setting of the FSCLE bit, the Status Register 0
and Status Register 1 are based solely on horizontal timing infor­mation or on the horizontal timing and lock status of the color
subcarrier. See the

FSCLE, FSC Lock Enable, Address 0x51 [7]

section.

AUTODETECTION RESULT

AD_RESULT[2:0], Address 0x10 [6:4]

The AD_RESULT[2:0] bits report back on the findings from the
ADV7180 autodetection block. Consult the
section for more information on enabling the autodetection
block and the

Autodetection of SD Modes section for more

information on how to configure it.

Table 16. AD_RESULT Function

AD_RESULT[2:0] Description

000 NTSM M/J
001 NTSC 4.43
010 PAL M
011 PAL 60
100 PAL B/G/H/I/D
101 SECAM
110 PAL Combination N
111 SECAM 525

General Setup

Table 17. Status_1 Function

STATUS_1
[7:0]

0 IN_LOCK In lock (now)
1 LOST_LOCK

2 FSC_LOCK FSC locked (now)
3 FOLLOW_PW

4 AD_RESULT[0] Result of autodetection
5 AD_RESULT[1] Result of autodetection
6 AD_RESULT[2] Result of autodetection
7 COL_KILL Color kill active

Bit Name Description

Lost lock (since last read of this
register)

AGC follows peak white
algorithm

STATUS 2

STATUS_2[7:0], Address 0x12 [7:0]

Table 18. STATUS_2 Function

STATUS_2
[7:0]

0 MVCS DET Detected Macrovision color striping
1 MVCS T3

2 MV PS DET

3 MV AGC DET Detected Macrovision AGC pulses
4 LL NSTD Line length is nonstandard
5 FSC NSTD FSC frequency is nonstandard
6 Reserved

7 Reserved

Bit Name Description

Macrovision color striping
protection; conforms to Type 3 if
high, Type 2 if low

Detected Macrovision pseudo
sync pulses

STATUS 3

STATUS_3[7:0], Address 0x13 [7:0]

Table 19. STATUS_3 Function

STATUS_3
[7:0]

0 INST_HLOCK

1 GEMD Gemstar detect
2 SD_OP_50Hz

3 Reserved for future use
4 FREE_RUN_ACT

5 STD FLD LEN

6 INTERLACED

7 PAL_SW_LOCK

Bit Name Description

Horizontal lock indicator
(instantaneous)

Flags whether 50 Hz or 60 Hz is
present at output

ADV7180 outputs a blue screen
(see the
Value Enable, Address 0x0C [0]
section)

Field length is correct for
currently selected video standard

Interlaced video detected (field
sequence found)

Reliable sequence of swinging
bursts detected

DEF_VAL_EN, Default

Rev. A | Page 21 of 112

ADV7180

VIDEO PROCESSOR

STANDARD DEFINITION PROCESSOR

DIGITIZE D CVBS

DIGITIZED Y (YC)

DIGITIZE D CVBS

DIGITIZED C (YC)

MACROVISIO N

DETECTIO N

LUMA

DIGITAL

FINE

CLAMP

CHROMA

DIGITAL

FINE

CLAMP

RECOVERY

CHROMA

DEMOD

F

SC

RECOVERY

VBI DATA

FILTER

EXTRACT

CHROMA

FILTER

AUTODETECTION

LUMA

SYNC

STANDARD

PREDICTOR

Figure 15. Block Diagram of the Video Processor

Figure 15 shows a block diagram of the ADV7180 video processor.
The ADV7180 can handle standard definition video in CVBS,
Y/C, and YPrPb formats. It can be divided into a luminance and
chrominance path. If the input video is of a composite type
(CVBS), both processing paths are fed with the CVBS input.

SD LUMA PATH

The input signal is processed by the following blocks:

• Luma Digital Fine Clamp.

This block uses a high precision algorithm to clamp the
video signal.

• Luma Filter.

This block contains a luma decimation filter (YAA) with a
fixed response and some shaping filters (YSH) that have
selectable responses.

• Luma Gain Control.

The automatic gain control (AGC) can operate on a variety
of different modes, including gain based on the depth of
the horizontal sync pulse, peak white mode, and fixed
manual gain.

• Luma Resample.

To correct for line-length errors as well as dynamic line­length changes, the data is digitally resampled.

• Luma 2D Comb.

The two-dimensional comb filter provides Y/C separation.

• AV Code Insertion.

At this point, the decoded luma (Y) signal is merged with
the retrieved chroma values. AV codes can be inserted
(as per ITU-R BT.656).

LUMA

GAIN

CONTRO L

LINE

LENGTH

CHROMA

GAIN

CONTRO L

SLLC

CONTROL

LUMA

RESAMPLE

RESAMPLE

CONTROL

CHROMA

RESAMPLE

LUMA

2D COMB

CHROMA
2D COMB

AV

CODE

INSERTION

VIDEO DAT A
OUTPUT

MEASUREMENT
BLOCK ( I

VIDEO DAT A
PROCESSING
BLOCK

SD CHROMA PATH

The input signal is processed by the following blocks:

• Chroma Digital Fine Clamp.

This block uses a high precision algorithm to clamp the
video signal.

• Chroma Demodulation.

This block employs a color subcarrier (F
regenerate the color subcarrier for any modulated chroma
scheme. The demodulation block then performs an AM
demodulation for PAL and NTSC, and an FM demodulation
for SECAM.

• Chroma Filter.

This block contains a chroma decimation filter (CAA) with
a fixed response and some shaping filters (CSH) that have
selectable responses.

• Chroma Gain Control.

Automatic gain control (AGC) can operate on several
different modes, including gain based on the color subcarrier
amplitude, gain based on the depth of the horizontal sync
pulse on the luma channel, or fixed manual gain.

• Chroma Resample.

The chroma data is digitally resampled to keep it perfectly
aligned with the luma data. The resampling is done to
correct for static and dynamic line-length errors of the
incoming video signal.

• Chroma 2D Comb.

The 2D, 5-line, superadaptive comb filter provides high
quality Y/C separation in case the input signal is CVBS.

) recovery unit to

SC

2

C)

05700-015

Rev. A | Page 22 of 112

ADV7180

• AV Code Insertion.

At this point, the demodulated chroma (Cr and Cb) signal
is merged with the retrieved luma values. AV codes can be
inserted (as per ITU-R BT.656).

SYNC PROCESSING

The ADV7180 extracts syncs embedded in the analog input
video signal. There is currently no support for external HS/VS
inputs. The sync extraction is optimized to support imperfect
video sources, such as videocassette recorders with head
switches. The actual algorithm used employs a coarse detection
based on a threshold crossing, followed by a more detailed
detection using an adaptive interpolation algorithm. The raw
sync information is sent to a line-length measurement and
prediction block. The output of this is then used to drive the
digital resampling section to ensure that the ADV7180 outputs
720 active pixels per line.

The sync processing on the ADV7180 also includes the
following specialized postprocessing blocks that filter and
condition the raw sync information retrieved from the digitized
analog video:

• VSYNC Processor.

This block provides extra filtering of the detected VSYNCs
to improve vertical lock.

• HSYNC Processor.

The HSYNC processor is designed to filter incoming
HSYNCs that have been corrupted by noise, providing
much improved performance for video signals with a
stable time base but poor SNR.

VBI DATA RECOVERY

The ADV7180 can retrieve the following information from the
input video:

• Wide-screen signaling (WSS)

• Copy generation management system (CGMS)

• Closed captioning (CCAP)

• Macrovision protection presence

• EDTV data

• Gemstar-compatible data slicing

• Te l e te x t

• VITC/VPS

The ADV7180 is also capable of automatically detecting the
incoming video standard with respect to

• Color subcarrier frequency

• Field rate

• Line rate

The ADV7180 can configure itself to support PAL B/G/H/I/D,
PAL M/N, PAL Combination N, NTSC M, NTSC J, SECAM
50 Hz/60 Hz, NTSC 4.43, and PAL 60.

Rev. A | Page 23 of 112

GENERAL SETUP

Video Standard Selection

The VID_SEL[3:0] register allows the user to force the digital
core into a specific video standard. Under normal circumstances,
this is not necessary. The VID_SEL[3:0] bits default to an auto­detection mode that supports PAL, NTSC, SECAM, and variants
thereof. The following section provides more information on
the autodetection system.

Autodetection of SD Modes

To guide the autodetect system of the ADV7180, individual
enable bits are provided for each of the supported video standards.
Setting the relevant bit to 0 inhibits the standard from being
detected automatically. Instead, the system picks the closest of
the remaining enabled standards. The results of the autodetection
block can be read back via the status registers. See the
Status Register

section for more information.

VID_SEL[3:0], Address 0x00 [7:4]

Table 20. VID_SEL Function

VID_SEL[3:0] Description

0000 (default)

0001

0010

0011

0100 NTSC J (1)
0101 NTSC M (1)
0110 PAL 60
0111 NTSC 4.43 (1)
1000 PAL B/G/H/I/D
1001 PAL N = PAL B/G/H/I/D (with pedestal)
1010 PAL M (without pedestal)
1011 PAL M
1100 PAL Combination N
1101 PAL Combination N (with pedestal)
1110 SECAM
1111 SECAM (with pedestal)

Autodetect (PAL B/G/H/I/D) <–> NTSC J
(no pedestal), SECAM

Autodetect (PAL B/G/H/I/D) <–> NTSC M
(pedestal), SECAM

Autodetect (PAL N) (pedestal) <–> NTSC J
(no pedestal), SECAM

Autodetect (PAL N) (pedestal) <–> NTSC M
(pedestal), SECAM

AD_SEC525_EN, Enable Autodetection of SECAM 525
Line Video, Address 0x07 [7]

Setting AD_SEC525_EN to 0 (default) disables the
autodetection of a 525-line system with a SECAM-style, FM­modulated color component.

Setting AD_SEC525_EN to 1 enables the detection of a
SECAM-style, FM-modulated color component.

Global

ADV7180

K

AD_SECAM_EN, Enable Autodetection of SECAM,
Address 0x07 [6]

Setting AD_SECAM_EN to 0 (default) disables the
autodetection of SECAM.

Setting AD_SECAM_EN to 1 enables the detection of SECAM.

AD_N443_EN, Enable Autodetection of NTSC 4.43,
Address 0x07 [5]

Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.

Setting AD_N443_EN to 1 (default) enables the detection of
NTSC style systems with a 4.43 MHz color subcarrier.

AD_P60_EN, Enable Autodetection of PAL 60,
Address 0x07 [4]

Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.

Setting AD_P60_EN to 1 (default) enables the detection of PAL
systems with a 60 Hz field rate.

AD_PALN_EN, Enable Autodetection of PAL N,
Address 0x07 [3]

Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.

Setting AD_PALN_EN to 1 enables the detection of the PAL N
standard.

AD_PALM_EN, Enable Autodetection of PAL M,
Address 0x07 [2]

Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.

Setting AD_PALM_EN to 1 enables the detection of PAL M.

AD_NTSC_EN, Enable Autodetection of NTSC,
Address 0x07 [1]

Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.

Setting AD_NTSC_EN to 1 enables the detection of standard
NTSC.

SIGNAL

0

COUNTER INTO LOCK

COUNTER OUT O F LOCK

1

TIME_WIN

FREE_RUN

F

LOCK

SC

SELECT THE RAW LOC
SRLS

1

0

AD_PAL_EN, Enable Autodetection of PAL,
Address 0x07 [0]

Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.

Setting AD_PAL_EN to 1 enables the detection of standard PAL.

SFL_INV, Subcarrier Frequency Lock Inversion

This bit controls the behavior of the PAL switch bit in the SFL
(Genlock Telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems.

First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.

Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(Genlock Telegram) bit directly, whereas the later ones invert
the bit prior to using it. The reason for this is that the inversion
compensated for the one-line delay of an SFL (Genlock
Telegram) transmission.

As a result, ADV717x encoders need the PAL switch bit in the
SFL (GenLock Telegram) to be 1 for NTSC to work. Also,
ADV7190/ADV7191/ADV7194 encoders need the PAL switch
bit in the SFL to be 0 to work in NTSC. If the state of the PAL
switch bit is wrong, a 180° phase shift occurs.

In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.

SFL_INV, Subcarrier Frequency Lock Inversion,
Address 0x41 [6]

Setting SFL_INV to 0 (default) makes the part SFL-compatible
with ADV7190/ADV7191/ADV7194 encoders.

Setting SFL_INV to 1 makes the part SFL-compatible with
ADV717x and ADV7173x encoders.

Lock Related Controls

Lock information is presented to the user through Bits[1:0] of
the Status Register 1. See the
section.

Figure 16 outlines the signal flow and the controls

STATUS_1[7:0], Address 0x10 [7:0]

available to influence the way the lock status information is
generated.

FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]

STATUS_1 [0]

MEMORY

STATUS_1 [1]

TAKE F

LOCK INTO ACCOUNT

SC

FSCLE

Figure 16. Lock Related Signal Path

Rev. A | Page 24 of 112

05700-016

ADV7180

SRLS, Select Raw Lock Signal, Address 0x51 [6]

Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status Register 1).
Refer to

Figure 16.

• The TIME_WIN signal is based on a line-to-line evaluation

of the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.

• The FREE_RUN signal evaluates the properties of the

incoming video over several fields, taking vertical
synchronization information into account.

Setting SRLS to 0 (default) selects the FREE_RUN signal.

Setting SRLS to 1 selects the TIME_WIN signal.

FSCLE, FSC Lock Enable, Address 0x51 [7]

The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in Status
Register 1. This bit must be set to 0 when operating the
ADV7180 in YPrPb component mode in order to generate a
reliable HLOCK status bit.

When FSCLE is set to 0 (default), only the overall lock status is
dependent on horizontal sync lock.

When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and F

lock.

SC

CIL[2:0], Count Into Lock, Address 0x51 [2:0]

CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state and reports this via Status 0 [1:0]. The bit
counts the value in lines of video.

Table 21. CIL Function

CIL[2:0] Number of Video Lines

000 1
001 2
010 5
011 10
100 (default) 100
101 500
110 1000
111 100,000

COL[2:0], Count Out of Lock, Address 0x51 [5:3]

COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into the unlocked state and reports this via Status 0 [1:0]. It counts
the value in lines of video.

Table 22. COL Function

COL[2:0] Number of Video Lines

000 1
001 2
010 5
011 10
100 (default) 100
101 500
110 1000
111 100,000

COLOR CONTROLS

These registers allow the user to control picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture clamping,
although both controls affect the dc level of the signal.

CON[7:0], Contrast Adjust, Address 0x08 [7:0]

This register allows the user to control contrast adjustment of
the picture.

Table 23. CON Function

CON[7:0] Description

0x80 (default) Gain on luma channel = 1
0x00 Gain on luma channel = 0
0xFF Gain on luma channel = 2

SD_SAT_Cb[7:0], SD Saturation Cb Channel,
Address 0xE3 [7:0]

This register allows the user to control the gain of the Cb
channel only, which in turn adjusts the saturation of the picture.

Table 24. SD_SAT_Cb Function

SD_SAT_Cb[7:0] Description

0x80 (default) Gain on Cb channel = 0 dB
0x00 Gain on Cb channel = −42 dB
0xFF Gain on Cb channel = +6 dB

Rev. A | Page 25 of 112

ADV7180

SD_SAT_Cr[7:0], SD Saturation Cr Channel,
Address 0xE4 [7:0]

This register allows the user to control the gain of the Cr
channel only, which in turn adjusts the saturation of the picture.

Table 25. SD_SAT_Cr Function

SD_SAT_Cr[7:0] Description

0x80 (default) Gain on Cr channel = 0 dB
0x00 Gain on Cr channel = −42 dB
0xFF Gain on Cr channel = +6 dB

SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1 [7:0]

This register allows the user to select an offset for the Cb
channel only and to adjust the hue of the picture. There is a
functional overlap with the HUE[7:0] register.

Table 26. SD_OFF_Cb Function

SD_OFF_Cb[7:0] Description

0x80 (default) 0 offset applied to the Cb channel
0x00 −312 mV offset applied to the Cb channel
0xFF +312 mV offset applied to the Cb channel

SD_OFF_Cr [7:0], SD Offset Cr Channel, Address 0xE2 [7:0]

This register allows the user to select an offset for the Cr channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.

Table 27. SD_OFF_Cr Function

SD_OFF_Cr[7:0] Description

0x80 (default) 0 offset applied to the Cr channel
0x00 −312 mV offset applied to the Cr channel
0xFF +312 mV offset applied to the Cr channel

BRI[7:0], Brightness Adjust, Address 0x0A [7:0]

This register controls the brightness of the video signal. It
allows the user to adjust the brightness of the picture.

Table 28. BRI Function

BRI[7:0] Description

0x00 (default) Offset of the luma channel = 0IRE
0x7F Offset of the luma channel = +100IRE
0x80 Offset of the luma channel = –100IRE

HUE[7:0], Hue Adjust, Address 0x0B [7:0]

This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.

HUE[7:0] has a range of ±90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.

The hue adjustment value is fed into the AM color demodula­tion block. Therefore, it only applies to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM and
does not work on component video inputs (YPrPb).

Table 29. HUE Function

HUE[7:0] Description (Adjust Hue of the Picture)
0x00 (default) Phase of the chroma signal = 0°
0x7F Phase of the chroma signal = −90°
0x80 Phase of the chroma signal = +90°

DEF_Y[5:0], Default Value Y, Address 0x0C [7:2]

When the ADV7180 loses lock on the incoming video signal or
when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:

• If DEF_VAL_AUTO_EN bit is set to high and the ADV7180

has lost lock to the input video signal, this is the intended
mode of operation (automatic mode).

• The DEF_VAL_EN bit is set, regardless of the lock status of

the video decoder. This is a forced mode that may be
useful during configuration.

The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.

For DEF_Y[5:0], 0x0D (blue) is the default value for Y.

Register 0x0C has a default value of 0x36.

DEF_C[7:0], Default Value C, Address 0x0D [7:0]

The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the four MSBs of Cr and Cb values to be output if

• The DEF_VAL_AUTO_EN bit is set to high and the

ADV7180 cannot lock to the input video (automatic mode).

• DEF_VAL_EN bit is set to high (forced output).

The data that is finally output from the ADV7180 for the
chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =
{DEF_C[3:0], 0, 0, 0, 0}.

For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.

DEF_VAL_EN, Default Value Enable, Address 0x0C [0]

This bit forces the use of the default values for Y, Cr, and Cb.
Refer to the descriptions in the
Address 0x0C [7:2]
0x0D [7:0]

sections for additional information. In this mode,

and DEF_C[7:0], Default Value C, Address

DEF_Y[5:0], Default Value Y,

the decoder also outputs a stable 27 MHz clock, HS, and VS.

Setting DEF_VAL_EN to 0 (default) outputs a colored screen
determined by user-programmable Y, Cr, and Cb values when
the decoder free-runs. Free-run mode is turned on and off by
the DEF_VAL_AUTO_EN bit.

Setting DEF_VAL_EN to 1 forces a colored screen output
determined by user-programmable Y, Cr, and Cb values. This
overrides picture data even if the decoder is locked.

Rev. A | Page 26 of 112

ADV7180

DEF_VAL_AUTO_EN, Default Value Automatic Enable,
Address 0x0C [1]

This bit enables the automatic use of the default values for Y, Cr,
and Cb when the ADV7180 cannot lock to the video signal.

Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If
the decoder is unlocked, it outputs noise.

Setting DEF_VAL_EN to 1 (default) enables free-run mode and
a colored screen set by user-programmable Y, Cr, and Cb values
is displayed when the decoder loses lock.

CLAMP OPERATION

The input video is ac-coupled into the ADV7180. Therefore, its
dc value needs to be restored. This process is referred to as
clamping the video. This section explains the general process of
clamping on the ADV7180 and shows the different ways in
which a user can configure its behavior.

The ADV7180 uses a combination of current sources and a
digital processing block for clamping, as shown in
The analog processing channel shown is replicated three times
inside the IC. While only one single channel is needed for a
CVBS signal, two independent channels are needed for Y/C
(S-VHS) type signals, and three independent channels are
needed to allow component signals (YPrPb) to be processed.

The clamping can be divided into two sections:

• Clamping before the ADC (analog domain): current

sources.

• Clamping after the ADC (digital domain): digital

processing block.

The ADC can digitize an input signal only if it resides within
the ADC 1.0 V input voltage range. An input signal with a dc
level that is too large or too small is clipped at the top or bottom
of the ADC range.

The primary task of the analog clamping circuits is to ensure that
the video signal stays within the valid ADC input window so that
the analog-to-digital conversion can take place. It is not necessary
to clamp the input signal with a very high accuracy in the analog
domain as long as the video signal fits within the ADC range.

Figure 17.

After digitization, the digital fine clamp block corrects for any
remaining variations in dc level. Because the dc level of an input
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations may occur. Further­more, dynamic changes in the dc level almost certainly lead to
visually objectionable artifacts, and must therefore be prohibited.

The clamping scheme has to complete two tasks. It must acquire
a newly connected video signal with a completely unknown dc
level, and it must maintain the dc level during normal operation.

To acquire an unknown video signal quickly, the large current
clamps should be activated. It is assumed that the amplitude of
the video signal at this point is of a nominal value. Control of
the coarse and fine current clamp parameters is performed
automatically by the decoder.

Standard definition video signals may have excessive noise on
them. In particular, CVBS signals transmitted by terrestrial
broadcast and demodulated using a tuner usually show very
large levels of noise (>100 mV). A voltage clamp would be
unsuitable for this type of video signal. Instead, the ADV7180
employs a set of four current sources that can cause coarse
(>0.5 mA) and fine (<0.1 mA) currents to flow into and away
from the high impedance node that carries the video signal
(see

Figure 17).

2

The following sections describe the I

C signals that can be used

to influence the behavior of the clamping block.

CCLEN, Current Clamp Enable, Address 0x14 [4]

The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This may be
useful if the incoming analog video signal is clamped externally.

When CCLEN is 0, the current sources are switched off.

When CCLEN is 1 (default), the current sources are enabled.

COARSE CURRENT SOURCESFINE CURRENT SOURCES

ANALOG

VIDEO

INPUT

ADC

Figure 17. Clamping Overview

Rev. A | Page 27 of 112

DATA
PRE-

PROCESSOR

(DPP)

CLAMP CONT ROL

VIDEO PRO CESSOR

WITH DIGITAL

FINE CL AMP

05700-017

ADV7180

DCT[1:0], Digital Clamp Timing, Address 0x15 [6:5]

The clamp timing register determines the time constant of the
digital fine clamp circuitry. It is important to note that the
digital fine clamp reacts very quickly because it is supposed to
immediately correct any residual dc level error for the active
line. The time constant from the digital fine clamp must be
much quicker than the one from the analog blocks.

By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.

Table 30. DCT Function

DCT[1:0] Description

00 (default) Slow (TC = 1 sec)
01 Medium (TC = 0.5 sec)
10 Fast (TC = 0.1 sec)
11

Determined by ADV7180, depending on the
input video parameters

DCFE, Digital Clamp Freeze Enable, Address 0x15 [4]

This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who would like to do their
own clamping. Users should disable the current sources for
analog clamping via the appropriate register bits, wait until the
digital clamp loop settles, and then freeze it via the DCFE bit.

When DCFE to 0 (default), the digital clamp is operational.

When DCFE is 1, the digital clamp loop is frozen.

LUMA FILTER

Data from the digital fine clamp block is processed by three sets
of filters. Note that the data format at this point is CVBS for
CVBS input or luma only for Y/C and YPrPb input formats.

• Luma Antialias Filter (YAA).

The ADV7180 receives video at a rate of 27 MHz. (In the case
of 4× oversampled video, the ADC samples at 57.27 MHz,
and the first decimation is performed inside the DPP filters.
Therefore, the data rate into the ADV7180 is always 27 MHz.)
The ITU-R BT.601 recommends a sampling frequency of

13.5 MHz. The luma antialias filter decimates the oversampled
video using a high quality linear phase, low-pass filter that
preserves the luma signal while at the same time attenuating
out-of-band components. The luma antialias filter (YAA)
has a fixed response.

• Luma Shaping Filters (YSH).

The shaping filter block is a programmable low-pass filter
with a wide variety of responses. It can be used to
selectively reduce the luma video signal bandwidth
(needed prior to scaling, for example). For some video
sources that contain high frequency noise, reducing the
bandwidth of the luma signal improves visual picture
quality. A follow-on video compression stage may work
more efficiently if the video is low-pass filtered.

The ADV7180 has two responses for the shaping filter:
one that is used for good quality composite, component,
and S-VHS type sources, and a second for nonstandard
CVBS signals.

The YSH filter responses also include a set of notches for
PAL and NTSC. However, using the comb filters for Y/C
separation is recommended.

• Digital Resampling Filter.

This block allows dynamic resampling of the video signal
to alter parameters such as the time base of a line of video.
Fundamentally, the resampler is a set of low-pass filters.
The actual response is chosen by the system with no
requirement for user intervention.

Figure 19 through Figure 22 show the overall response of all
filters together. Unless otherwise noted, the filters are set into a
typical wideband mode.

Y Shaping Filter

For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. Y/C separation must aim for best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
Y/C separation can be achieved by using the internal comb
filters of the ADV7180. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of
the video line rate) and the color subcarrier (F

). For good

SC

quality CVBS signals, this relationship is known; the comb filter
algorithms can be used to separate luma and chroma with high
accuracy.

In the case of nonstandard video signals, the frequency
relationship may be disturbed and the comb filters may not be
able to remove all crosstalk artifacts in the best fashion without
the assistance of the shaping filter block.

Rev. A | Page 28 of 112

ADV7180

An automatic mode is provided that allows the ADV7180 to
evaluate the quality of the incoming video signal and select the
filter responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.

The luma shaping filter has three control registers:

• YSFM[4:0] allows the user to manually select a shaping

filter mode (applied to all video signals) or to enable an
automatic selection (depending on video quality and video
standard).

• WYSFMOVR allows the user to manually override the

WYSFM decision.

• WYSFM[4:0] allows the user to select a different shaping

filter mode for good quality composite (CVBS), component
(YPrPb), and S-VHS (Y/C) input signals.

In automatic mode, the system preserves the maximum
possible bandwidth for good CVBS sources (because they can
be successfully combed) as well as for luma components of
YPrPb and Y/C sources (because they need not be combed).
For poor quality signals, the system selects from a set of
proprietary shaping filter responses that complements comb
filter operation in order to reduce visual artifacts.

The decisions of the control logic are shown in

Figure 18.

YSFM[4:0], Y Shaping Filter Mode, Address 0x17 [4:0]

The Y shaping filter mode bits allow the user to select from a
wide range of low-pass and notch filters. When switched in
automatic mode, the filter selection is based on other register
selections, such as detected video standard, as well as properties
extracted from the incoming video itself, such as quality and
time base stability. The automatic selection always selects the
widest possible bandwidth for the video input encountered.

• If the YSFM settings specify a filter (that is, YSFM is set to

values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.

• In automatic selection mode, the notch filters are only used

for bad quality video signals. For all other video signals,
wideband filters are used.

WYSFMOVR, Wideband Y Shaping Filter Override,
Address 0x18 [7]

Setting the WYSFMOVR bit enables the use of the
WYSFM[4:0] settings for good quality video signals. For more
information, refer to the general discussion of the luma shaping
filters in the
in

Figure 18.

Y Shaping Filter section and the flowchart shown

When WYSFMOVR is 0, the shaping filter for good quality
video signals is selected automatically.

Setting WYSFMOVR to 1 (default) enables manual override via
WYSFM[4:0].

SET YSFM

YSFM IN AUTO MODE?

00000 OR 00001

WYSFMOVR

SELECT AUTOMATIC

WIDEBAND FILTER

USE YSFM SELECTED

FILTER REGARDLESS O F

VIDEO QUAL ITY

05700-018

VIDEO

BAD GOOD

AUTO SELECT LUMA
SHAPING FILTER TO

COMPLEME NT COMB

QUALITY

1 0

SELECT WIDEBAND

FILTER AS PER

WYSFM[ 4:0]

Figure 18. YSFM and WYSFM Control Flowchart

YES NO

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ADV7180

A

Table 31. YSFM Function

YSFM[4:0] Description

0'0000

Automatic selection including a wide-notch
response (PAL/NTSC/SECAM)

0'0001
(default)

Automatic selection including a narrow-notch

response (PAL/NTSC/SECAM)
0'0010 SVHS 1
0'0011 SVHS 2
0'0100 SVHS 3
0'0101 SVHS 4
0'0110 SVHS 5
0'0111 SVHS 6
0'1000 SVHS 7
0'1001 SVHS 8
0'1010 SVHS 9
0'1011 SVHS 10
0'1100 SVHS 11
0'1101 SVHS 12
0'1110 SVHS 13
0'1111 SVHS 14
1'0000 SVHS 15
1'0001 SVHS 16
1'0010 SVHS 17
1'0011 SVHS 18 (CCIR 601)
1'0100 PAL NN1
1'0101 PAL NN2
1'0110 PAL NN3
1'0111 PAL WN1
1'1000 PAL WN2
1'1001 NTSC NN1
1'1010 NTSC NN2
1'1011 NTSC NN3
1'1100 NTSC WN1
1'1101 NTSC WN2
1'1110 NTSC WN3
1'1111 Reserved

WYSFM[4:0], Wideband Y Shaping Filter Mode,
Address 0x18 [4:0]

The WYSFM[4:0] bits allow the user to manually select a
shaping filter for good quality video signals, for example, CVBS
with stable time base, luma component of YPrPb, and luma
component of Y/C. The WYSFM bits are only active if the
WYSFMOVR bit is set to 1. See the general discussion of the
shaping filter settings in the

Y Shaping Filter section.

Table 32. WYSFM Function

WYSFM[4:0] Description

0'0000 Do not use
0'0001 Do not use
0'0010 SVHS 1
0'0011 SVHS 2
0'0100 SVHS 3
0'0101 SVHS 4
0'0110 SVHS 5
0'0111 SVHS 6
0'1000 SVHS 7
0'1001 SVHS 8
0'1010 SVHS 9
0'1011 SVHS 10
0'1100 SVHS 11
0'1101 SVHS 12
0'1110 SVHS 13
0'1111 SVHS 14
1'0000 SVHS 15
1'0001 SVHS 16
1'0010 SVHS 17
1'0011 (default) SVHS 18 (CCIR 601)
1'0100 to 1’1111 Do not use

The filter plots in
S-VHS 18 (widest) shaping filter settings.

Figure 19 show the S-VHS 1 (narrowest) to

Figure 21 shows the
PAL notch filter responses. The NTSC-compatible notches are
shown in

Figure 22.

COMBINED Y

0

–10

–20

–30

–40

AMPLITUDE ( dB)

–50

–60

–70

0186421

Figure 19. Y S-VHS Combined Responses

NTIALIAS, S-VHS LOW-PASS FILTERS,

Y RESAMPLE

FREQUENCY (MHz)

02

05700-019

Rev. A | Page 30 of 112