Analog Devices ADV7177 8 c Datasheet

Integrated Digital CCIR-601

FEATURES

ITU-R BT601/656 YCrCb to PAL/NTSC video encoder
High quality, 9-bit video DACs
Integral nonlinearity <1 LSB at 9 bits
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz crystal/clock required (±2 oversampling)
75 dB video SNR
32-bit direct digital synthesizer for color subcarrier
Multistandard video output support:

Composite (CVBS)
Component S-video (Y/C)
Component YUV or RGB

Video input data port supports:

CCIR-656 4:2:2 8-bit parallel input format
4:2:2 16-bit parallel input format

Full video output drive or low signal drive capability

34.7 mA max into 37.5 Ω (doubly terminated 75 R)
5 mA min with external buffers

Programmable simultaneous composite and S-VHS

(VHS) Y/C or RGB (SCART)/YUV video outputs
Programmable luma filters (low-pass/notch/extended)
Programmable VBI (vertical blanking interval)
Programmable subcarrier frequency and phase
Programmable luma delay
Individual on/off control of each DAC
CCIR and square pixel operation

FUNCTIONAL BLOCK DIAGRAM

V

AA

to PAL/NTSC Video Encoder

ADV7177/ADV7178

Color-signal control/burst-signal control
Interlaced/noninterlaced operation
Complete on-chip video timing generator
OSD support (ADV7177 only)
Programmable multimode master/slave operation
Macrovision AntiTaping Rev. 7.01 (ADV7178 only)
Closed captioning support
On-board voltage reference

2

2-wire serial MPU interface (I

C®-compatible)
Single-supply 5 V or 3 V operation
Small 44-lead MQFP package
Synchronous 27 MHz/13.5 MHz clock output

APPLICATIONS

MPEG-1 and MPEG-2 video, DVD, digital satellite,

cable systems (set-top boxes/IRDs), digital TVs,
CD video/karaoke, video games, PC video/multimedia

1

This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216,

4,819,098 and other intellectual property rights. The Macrovision anticopy
process is licensed for noncommercial home use only, which is its sole
intended use in the device. Please contact sales office for latest Macrovision
version available. ITU-R and CCIR are used interchangeably in this document
(ITU-R has replaced CCIR recommendations).

1

ADV7177

ONLY

OSD_EN

OSD_0
OSD_1
OSD_2

COLOR

DATA
P7–P0

P15–P8

HSYNC

FIELD/VSYNC

BLANK

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

4:2:2 TO

POLATOR

CLOCK CLOCK CLOCK/2 RESET

4:4:4

INTER-

VIDEO TIMING

8

YCrCb

8

MATRIX

8

GENERATOR

ADV7177/ADV7178

8

8

TO

YUV

8

8

ADD

SYNC

ADD

BURST

ADD

BURST

INTER-

POLATOR

8

INTER-

POLATOR

8

INTER-

POLATOR

I2C MPU PORT

SCLOCK SDATA ALSB GND

Y

LOW-PASS

FILTER

8 9

8

U

LOW-PASS

FILTER

V

LOW-PASS

FILTER

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

9

DDS BLOCK

DAC A
(PIN 31)

DAC B
(PIN 27)

DAC C
(PIN 26)

V

REF

R

SET

COMP

YUV TO

RBG

MATRIX

98

SIN/COS

9

9-BIT

DAC

9

9-BIT

DAC

9

9-BIT

MULTIPLEXER

DAC

99

VOLTAGE

REFERENCE

CIRCUIT

www.analog.com

00228-001

ADV7177/ADV7178

TABLE OF CONTENTS

General Description......................................................................... 4

Specifications..................................................................................... 5

5 V Specifications ......................................................................... 5

3.3 V Specifications ...................................................................... 6

5 V Dynamic Specifications........................................................ 7

3.3 V Dynamic Specifications..................................................... 8

5 V Timing Specifications........................................................... 9

3.3 V Timing Specifications...................................................... 10

Absolute Maximum Ratings.......................................................... 12

Stress Ratings .............................................................................. 12

Package Thermal Performance................................................. 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Typical Performance Characteristics........................................... 14

Theory of Operation ...................................................................... 16

Data Path Description ...............................................................16

Pixel Timing Description .......................................................... 16

Video Timing Description ........................................................ 17

Timing and Control ................................................................... 18

Power-On Reset .......................................................................... 25

MPU Port Description...............................................................25

Registers........................................................................................... 27

Register Access............................................................................ 27

Register Programming............................................................... 27

Mode Register 0 MR0 (MR07–MR00).................................... 27

MR0 Bit Description.................................................................. 27

Mode Register 1 MR1 (MR17–MR10).................................... 28

MR1 Bit Description.................................................................. 28

Subcarrier Frequency Register 3–0.......................................... 28

Subcarrier Phase Register (FP7–FP0)...................................... 29

Timing Register 0 (TR07–TR00) ............................................. 29

TR0 Bit Description ...................................................................29

Closed Captioning Even Field Data Register 1–0 (CED15–

.......................................................................................... 29

CED0)

Closed Captioning Odd Field Data Register 1–0 (CCD15–

.......................................................................................... 29

CCD0)

Timing Register 1 (TR17–TR10) ............................................. 30

TR1 Bit Description ................................................................... 30

Mode Register 2 MR2 (MR27–MR20).................................... 30

MR2 Bit Description.................................................................. 31

NTSC Pedestal Registers 3–0 PCE15–0, PCO15–0............... 31

Mode Register 3 MR3 (MR37–MR30).................................... 31

MR3 Bit Description.................................................................. 31

OSD Register 0–11..................................................................... 32

Board Design and Layout Considerations .................................. 33

Ground Planes ............................................................................ 33

Power Planes ............................................................................... 33

Supply Decoupling ..................................................................... 33

Digital Signal Interconnect....................................................... 33

Analog Signal Interconnect ...................................................... 33

Closed Captioning.......................................................................... 35

Waveform Illustrations.................................................................. 36

NTSC Waveforms With Pedestal............................................. 36

NTSC Waveforms Without Pedestal ....................................... 37

PAL Waveforms.......................................................................... 38

UV Waveforms........................................................................... 39

Register Values................................................................................ 40

NTSC (FSC = 3.5795454 MHZ) ............................................... 40

PAL B, D, G, H, I (FSC = 4.43361875 MHZ).......................... 40

PAL M (FSC = 3.57561149 MHZ)............................................ 40

Optional Output Filter................................................................... 41

Optional DAC Buffering ............................................................... 42

Outline Dimensions ....................................................................... 43

Ordering Guide .......................................................................... 43

Rev. C | Page 2 of 44

ADV7177/ADV7178

REVISION HISTORY

3/05—Rev. B to Rev. C

Updated Format.................................................................. Universal

Changes to Figure 6.........................................................................13

Changes to Subcarrier Frequency Register 3–0 Section ............28

Changes to Register Values Section..............................................40

Updated Outline Dimensions........................................................43

Changes to Ordering Guide...........................................................43

3/02—Rev. A to Rev. B

Changed Figures 7–13 into TPC section .....................................10

Edits to Figures 20 and 21..............................................................21

Rev. C | Page 3 of 44

ADV7177/ADV7178

GENERAL DESCRIPTION

The ADV7177/AD7178 are integrated digital video encoders
that convert digital CCIR-601 4:2:2 8- or 16-component video
data into a standard analog baseband television signal
compatible with worldwide standards. The 4:2:2 YUV video
data is interpolated to 2× the pixel rate. The color-difference
components (UV) are quadrature modulated using a subcarrier
frequency generated by an on-chip, 32-bit digital synthesizer
(also running at 2× the pixel rate). The 2× pixel rate sampling
allows for better signal-to-noise ratio. A 32-bit DDS with a 9-bit
look-up table produces a superior subcarrier in terms of both
frequency and phase. In addition to the composite output
signal, there is the facility to output S-video (Y/C video), YUV
or RGB video.

Each analog output is capable of driving the full video-level
(34.7 mA) signal into an unbuffered, doubly terminated 75 Ω
load. With external buffering, the user has the additional option
to scale back the DAC output current to 5 mA min, thereby
significantly reducing the power dissipation of the device.

The ADV7177/ADV7178 also support both PAL and NTSC
square pixel operation.

The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate)

These timing signals can be adjusted to change pulse width and
position while the parts are in master mode. The encoder
requires a single, 2× pixel rate (27 MHz) clock for standard
operation. Alternatively, the encoder requires a 24.5454 MHz
clock for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.

The ADV7177/ADV7178 modes are set up over a 2-wire serial
bidirectional port (I

Functionally, the ADV7178 and the ADV7177 are the same
except that the ADV7178 can output the Macrovision anticopy
algorithm, and OSD is only supported on the ADV7177.

The ADV7177/ADV7178 are packaged in a 44-lead, thermally
enhanced MQFP package.

HSYNC, VSYNC

2

C-compatible) with two slave addresses.

, and FIELD timing signals.

Rev. C | Page 4 of 44

ADV7177/ADV7178

SPECIFICATIONS

5 V SPECIFICATIONS

VAA = 5 V ± 5%,1 V

Table 1.

Parameter Conditions1 Min Typ Max Unit

STATIC PERFORMANCE3

Resolution (Each DAC) 9 Bits
Accuracy (Each DAC)

Integral Nonlinearity ±1.0 LSB
Differential Nonlinearity Guaranteed monotonic ±1.0 LSB

DIGITAL INPUTS3

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, I
Input Capacitance, C

DIGITAL OUTPUTS

Output High Voltage, VOH I
Output Low Voltage, VOL I
Three-State Leakage Current 10 µA
Three-State Output Capacitance 10 pF

ANALOG OUTPUTS

Output Current6 R
Output Current
DAC-to-DAC Matching 0.6 5 %
Output Compliance, V
Output Impedance, R
Output Capacitance, C

VOLTAGE REFERENCE

Reference Range, V

POWER REQUIREMENTS

V

AA

Low Power Mode

I

(max)

DAC

I

(min)9 25 mA

DAC

10

I

CCT

Power-Supply Rejection Ratio COMP = 0.1 µF 0.01 0.5 %/%

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

2

Temperature range T

3

Guaranteed by characterization.

4

All digital input pins except pins

5

Excluding all digital input pins except pins

6

Full drive into 75 Ω load.

7

Minimum drive current (used with buffered/scaled output load).

8

Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.

9

I

is the total current (min corresponds to 5 mA output per DAC, max corresponds to 18.5 mA output per DAC) to drive all three DACs. Turning off individual DACs

DAC

reduces I

10

I

CCT

correspondingly.

DAC

(circuit current) is the continuous current required to drive the device.

= 1.235 V, R

REF

= 300 Ω. All specifications T

SET

MIN

to T

INH

INL

4

VIN = 0.4 V or 2.4 V ±1 µA

IN

5

IN

IN

3

3

7

OC

OUT

OUT

3

REF

3, 8

2 V

0.8 V

VIN = 0.4 V or 2.4 V ± 50 µA
10 pF

= 400 µA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

= 300 Ω, RL = 75 Ω 16.5 17.35 18.5 mA

SET

5 mA

0 1.4 V
15 kΩ
I

= 0 mA 30 pF

OUT

I

= 20 µA 1.112 1.235 1.359 V

VREFOUT

4.75 5.0 5.25 V

9

62 mA

100 150 mA

to T

MIN

: 0°C to 70°C.

MAX

RESET

, OSD0, and CLOCK.

RESET

, OSD0, and CLOCK.

2

, unless otherwise noted.

MAX

Rev. C | Page 5 of 44

ADV7177/ADV7178

3.3 V SPECIFICATIONS

VAA = 3.0 V to 3.6 V1, V

Table 2.

Parameter Conditions

STATIC PERFORMANCE3

Resolution (Each DAC) 9 Bits
Accuracy (Each DAC)

Integral Nonlinearity ±0.5 LSB
Differential Nonlinearity Guaranteed monotonic ±0.5 LSB

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, I

IN

IN

Input Capacitance, CIN 10 pF

DIGITAL OUTPUTS

Output High Voltage, VOH I
Output Low Voltage, VOL I
Three-State Leakage Current
Three-State Output Capacitance3 10 pF

ANALOG OUTPUTS

Output Current

6, 7

Output Current8 5 mA
DAC-to-DAC Matching 2.0 %
Output Compliance, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C

POWER REQUIREMENTS

VAA 3.0 3.3 3.6 V
Normal Power Mode

I

(max)10 R

DAC

I

DAC

I

CCT

3

(min)

15 mA

9

45 mA

Low Power Mode

I

DAC

I

DAC

I

CCT

3

(max)

60 mA

3

(min)

25 mA

11

Power-Supply Rejection Ratio COMP = 0.1 µF 0.01 0.5 %/%

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.

2

Temperature range T

3

Guaranteed by characterization.

4

All digital input pins except pins

5

Excluding all digital input pins except pins

6

Full drive into 75 Ω load.

7

DACs can output 35 mA typically at 3.3 V (R

8

Minimum drive current (used with buffered/scaled output load).

9

Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.

10

I

is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all three DACs. Turning off individual DACs

DAC

reduces IDAC correspondingly.

11

I

(circuit current) is the continuous current required to drive the device.

CCT

= 1.235 V, R

REF

2 V

INH

0.8 V

INL

, 4

3

, 5

3

3

10 µA

3

15 kΩ

OUT

I

OUT

3, 9

= 300 Ω. All specifications T

SET

1

Min Typ Max Unit

MIN

to T

VIN = 0.4 V or 2.4 V ±1 µA
VIN = 0.4 V or 2.4 V ±50 µA

= 400 µA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

R

= 300 Ω, RL = 75 Ω

SET

= 0 mA 30 pF

OUT

16.5 17.35 18.5 mA

= 300 Ω, RL = 150 Ω 113 116 mA

SET

45 mA

to T

MIN

: 0°C to 70°C.

MAX

RESET

, OSD0, and CLOCK.

RESET

, OSD0, and CLOCK.

= 150 Ω and RL = 75 Ω), optimum performance obtained at 18 mA DAC current (R

SET

2

, unless otherwise noted.

MAX

= 300 Ω and RL = 150 Ω).

SET

Rev. C | Page 6 of 44

ADV7177/ADV7178

5 V DYNAMIC SPECIFICATIONS

VAA = 4.75 V to 5.25 V,1 V

Table 3.

Parameter Conditions

FILTER CHARACTERISTICS

Luma Bandwidth3 (Low-Pass Filter) NTSC Mode

Stop-Band Cutoff >54 dB Attenuation 7.0 MHz
Pass-Band Cutoff, F

Chroma Bandwidth NTSC Mode

Stop-Band Cutoff >40 dB Attenuation 3.2 MHz
Pass-Band Cutoff, F

Luma Bandwidth3 (Low-Pass Filter) PAL Mode

Stop-Band Cutoff >50 dB Attenuation 7.4 MHz
Pass-Band Cutoff, F

Chroma Bandwidth PAL Mode

Stop-Band Cutoff >40 dB Attenuation 4.0 MHz

Pass-Band Cutoff F
Differential Gain4 Lower Power Mode 2.0 %
Differential Phase

4

Lower Power Mode 1.5 Degrees

SNR4 (Pedestal) RMS 75 dB rms
Peak Periodic 70 dB p-p
SNR4 (Ramp) RMS 57 dB rms
Peak Periodic 56 dB p-p
Hue Accuracy4 1.2 Degrees
Color Saturation Accuracy4 1.4 %
Chroma Nonlinear Gain4 Referenced to 40 IRE 1.0 ± %
Chroma Nonlinear Phase
PAL 0.6 ± Degrees
Chroma/Luma Intermod
Referenced to 700 mV (PAL) 0.2 ± %
Chroma/Luma Gain Inequality
Chroma/Luma Delay Inequality
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

2

Temperature range T

3

These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see . Table 10

4

Guaranteed by characterization.

4

4

to T

MIN

= 1.235 V, R

REF

>3 dB Attenuation 4.2 MHz

3 dB

>3 dB Attenuation 2.0 MHz

3 dB

>3 dB Attenuation 5.0 MHz

3 dB

>3 dB Attenuation 2.4 MHz

3 dB

4

NTSC 0.4 ± Degrees

4

Referenced to 714 mV (NTSC) 0.2 ± %

4

0.6 ± %

4

2.0 ns

4

1.2 ± %
64 dB
62 dB

: 0°C to 70°C.

MAX

= 300 Ω. All specifications T

SET

1

MIN

to T

,2 unless otherwise noted.

MAX

Min Typ Max Unit

Rev. C | Page 7 of 44

ADV7177/ADV7178

3.3 V DYNAMIC SPECIFICATIONS

VAA = 3.0 V to 3.6 V,1 V

Table 4.

Parameter Conditions

FILTER CHARACTERISTICS

Luma Bandwidth3 (Low-Pass Filter) NTSC mode

Stop-Band Cutoff >54 dB attenuation 7.0 MHz
Pass-Band Cutoff, F

Chroma Bandwidth NTSC mode

Stop-Band Cutoff >40 dB attenuation 3.2 MHz
Pass-Band Cutoff, F

Luma Bandwidth3 (Low-Pass Filter) PAL mode

Stop-Band Cutoff >50 dB attenuation 7.4 MHz
Pass-Band Cutoff, F

Chroma Bandwidth PAL mode

Stop-Band Cutoff >40 dB attenuation 4.0 MHz

Pass-Band Cutoff, F
Differential Gain4 Normal power mode 1.0 %
Differential Phase4 Normal power mode 1.0 Degrees
SNR4 (Pedestal) RMS 70 dB rms
Peak periodic 64 dB p-p
SNR4 (Ramp) RMS 56 dB rms
Peak periodic 54 dB p-p
Hue Accuracy4 1.2 Degrees
Color Saturation Accuracy4 1.4 %
Luminance Nonlinearity4 1.4 ± %
Chroma AM Noise4 NTSC 64 dB
Chroma PM Noise4 NTSC 62 dB
Chroma AM Noise4 PAL 64 dB
Chroma PM Noise4 PAL 62 dB

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.

2

Temperature range T

3

These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see . Table 7

4

Guaranteed by characterization.

to T

MIN

= 1.235 V, R

REF

>3 dB attenuation 4.2 MHz

3 dB

>3 dB attenuation 2.0 MHz

3 dB

>3 dB attenuation 5.0 MHz

3 dB

>3 dB attenuation 2.4 MHz

3 dB

: 0°C to 70°C.

MAX

= 300 Ω. All specifications T

SET

to T

MIN

,2 unless otherwise noted.

MAX

1

Min Typ Max Unit

Rev. C | Page 8 of 44

ADV7177/ADV7178

5 V TIMING SPECIFICATIONS

VAA = 4.75 V to 5.25 V,1 V

Table 5.

Parameter Conditions

MPU PORT

3, 4

SCLOCK Frequency 0 100 kHz
SCLOCK High Pulse Width, t1 4.0 µs
SCLOCK Low Pulse Width, t2 4.7 µs
Hold Time (Start Condition), t
Setup Time (Start Condition), t4 Relevant for repeated start condition 4.7 µs
Data Setup Time, t5 250 ns
SDATA, SCLOCK Rise Time, t6 1 µs
SDATA, SCLOCK Fall Time, t7 300 ns
Setup Time (Stop Condition), t

ANALOG OUTPUTS

3, 5

Analog Output Delay 5 ns
DAC Analog Output Skew 0 ns

CLOCK CONTROL AND PIXEL PORT

f

27 MHz

CLOCK

Clock High Time, t
Clock Low Time, t

9

10

Data Setup Time, t11 3.5 ns
Data Hold Time, t12 4 ns
Control Setup Time, t11 4 ns
Control Hold Time, t12 3 ns
Digital Output Access Time, t13 24 ns
Digital Output Hold Time, t14 4 ns
Pipeline Delay, t

RESET CONTROL

15

3, 4

RESET Low Time

INTERNAL CLOCK CONTROL

Clock/2 Rise Time, t
Clock/2 Fall Time, t17 7 ns

OSD TIMING4

OSD Setup Time, t

18

OSD Hold Time, t19 2 ns

1

The max/min specifications are guaranteed over this range.

2

Temperature range T

3

TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Analog output load ≤ 10 pF.

4

Guaranteed by characterization.

5

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

6

Pixel port consists of the following:

Pixel inputs: P15–P0
Pixel controls:
Clock input: CLOCK

HSYNC

to T

MIN

, FIELD/

= 1.235 V, R

REF

= 300 Ω. All specifications T

SET

MIN

to T

,2 unless otherwise noted.

MAX

Min Typ Max Unit

3

8

After this period, the first clock is generated 4.0 µs

4.7 µs

3, 4, 6

8 ns
8 ns

37 Clock Cycles

6 ns

16

7 ns

6 ns

: 0°C to 70°C.

MAX

VSYNC, BLANK

Rev. C | Page 9 of 44

ADV7177/ADV7178

3.3 V TIMING SPECIFICATIONS

VAA = 3.0 V–3.6 V,1 V

Table 6.

Parameter Conditions Min Typ Max Unit

MPU PORT

3, 4

SCLOCK Frequency 0 100 kHz
SCLOCK High Pulse Width, t
SCLOCK Low Pulse Width, t2 4.7 µs
Hold Time (Start Condition), t3 After this period the first clock is generated 4.0 µs
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t6 1 µs
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

ANALOG OUTPUTS

Analog Output Delay 7 ns
DAC Analog Output Skew 0 ns

CLOCK CONTROL AND PIXEL PORT

f

27 MHz

CLOCK

Clock High Time, t
Clock Low Time, t10 8 ns
Data Setup Time, t11 3.5 ns
Data Hold Time, t
Control Setup Time, t11 4 ns
Control Hold Time, t12 3 ns
Digital Output Access Time, t13 24 ns
Digital Output Hold Time, t
Pipeline Delay, t15 37 Clock cycles

RESET CONTROL

RESET Low Time

INTERNAL CLOCK CONTROL

Clock/2 Rise Time, t
Clock/2 Fall Time, t

OSD TIMING4

OSD Setup Time, t18 10 ns
OSD Hold Time, t19 2 ns

1

The max/min specifications are guaranteed over this range.

2

Temperature range T

3

TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Analog output load ≤ 10 pF.

4

Guaranteed by characterization.

5

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

6

Pixel port consists of the following:

Pixel inputs: P15–P0
Pixel controls:
Clock input: CLOCK

HSYNC

3, 5

3, 4

MIN

, FIELD/

= 1.235 V, R

REF

5

9

12

16

17

to T

MAX

VSYNC, BLANK

1

4

7

8

3, 4, 6

14

: 0°C to 70°C.

= 300 Ω. All specifications T

SET

4.0 µs

Repeated for start condition 4.7 µs
250 ns

300 ns

4.7 µs

8 ns

4 ns

4 ns

6 ns

10 ns
10 ns

MIN

to T

,2 unless otherwise noted.

MAX

Rev. C | Page 10 of 44

ADV7177/ADV7178

S

K

C

C

ONTROL

I/PS

SDATA

CLOC

FIELD/VSYNC,

CLOCK

HSYNC,

BLANK

t

3

t

t

6

1

t

2

Figure 2. MPU Port Timing Diagram

t

t

9

10

t

5

t

7

t

12

t

3

t

4

t

00228-002

8

ONTROL

O/PS

CLOCK

CLOCK/2

CLOCK

CLOCK/2

PIXEL INPUT

DATA

HSYNC,

FIELD/VSYNC,

BLANK

Cb Y Cr Y Cb Y

t

11

t

13

t

14

Figure 3. Pixel and Control Data Timing Diagram

t

16

t

16

t

17

t

17

Figure 4. Internal Timing Diagram

00228-003

00228-004

CLOCK

OSD_EN

OSD0–2

t

18

t

19

00228-005

Figure 5. OSD Timing Diagram

Rev. C | Page 11 of 44

ADV7177/ADV7178

ABSOLUTE MAXIMUM RATINGS

STRESS RATINGS

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 7.

Parameter Rating

VAA to GND 7 V
Voltage on Any Digital Input Pin GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) –65°C to +150°C
Junction Temperature (TJ) 150°C
Lead Temperature

(Soldering, 10 sec)

Analog Outputs to GND

1

Analog output short circuit to any power supply or common can be of an

indefinite duration.

1

260°C
GND – 0.5 V to V

AA

PACKAGE THERMAL PERFORMANCE

The 44-lead MQFP package used for this device has a junction­to-ambient thermal resistance (θ
of 53.2°C/W. The junction-to-case thermal resistance (θ

18.8°C/W. Care must be taken when operating the part in
certain conditions to prevent overheating. Table 8 lists the
conditions to use when using the part.

Table 8. Allowable Operating Conditions

Condition 5 V 3 V

3 DACs on, double 75 R
3 DACs on, low power
3 DACs on, buffered

1

2

3

2 DACs on, double 75 R No Yes
2 DACs on, low power Yes Yes
2 DACs on, buffered Yes Yes

1

DAC on, double 75 R refers to a condition where the DACs are terminated

into a double 75 R load and low power mode is disabled.

2

DAC on, low power refers to a condition where the DACs are terminated in

a double 75 R load and low power mode is enabled.

3

DAC on, buffered refers to a condition where the DAC current is reduced to

5 mA and external buffers are used to drive the video loads.

) in still air on a 4-layer PCB

JA

JC

No Yes
Yes Yes
Yes Yes

) is

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 12 of 44

ADV7177/ADV7178

C

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLOCK43CLOCK42GND41P440P339P238P137P036OSD_235OSD_134OSD_0

44

V

LOCK/2

P10
P11
P12

OSD_EN

1

AA

P5
P6
P7
P8
P9

PIN 1

2
3
4
5
6
7
8

9
10
11

AD7177/ADV7178

(Not to Scale)

12

13

14

15

P14

P13

P15

HSYNC

MQFP

TOP VIEW

16

17

BLANK

18

19

20

V

GND

ALSB

33

R

SET

32

V

REF

31

DAC A

30

V

AA

29

GND

28

V

AA

27

DAC B

26

DAC C

25

COMP

24

SDATA

23

SCLOCK

21

22

AA

GND

RESET

FIELD/VSYNC

00228-006

Figure 6. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic I/O Function

1, 20, 28, 30 VAA P Power Supply.
2 CLOCK/2 O

Synchronous Clock Output Signal. Can be either 27 MHz or 13.5 MHz; this can be controlled by MR32
and MR33 in Mode Register 3.

3 to 10,
12 to 14,
37 to 41

P5 to P12,
P13 to 14,
P0 to P4

I

8-Bit, 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port (P15–P0). P0 represents the
LSB.

11 OSD_EN I Enables OSD input data on the video outputs.
15

HSYNC

I/O

HSYNC (Modes 1 and 2) Control Signal. This pin can be configured to output (master mode) or accept
(slave mode) Sync signals.

16

17

FIELD/
VSYNC

BLANK

I/O

Dual Function Field (Mode 1) and

VSYNC (Mode 2) Control Signal. This pin can be configured to

output (master mode) or accept (slave mode) these control signals.

I/O Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.
18 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.
19, 21, 29, 42 GND G Ground Pin.
22

RESET

I

The input resets the on-chip timing generator and sets the ADV7177/ADV7178 into default mode. This

is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2× composite and S VHS out.
23 SCLOCK I MPU Port Serial Interface Clock Input.
24 SDATA I/O MPU Port Serial Data Input/Output.
25 COMP O Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA.
26 DAC C O DAC C Analog Output.
27 DAC B O DAC B Analog Output.
31 DAC A O DAC A Analog Output.
32 V
33 R

I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

REF

I

SET

A 300 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video

signals.
34–36

OSD_0 to

I On Screen Display Inputs.

OSD_2

43

CLOCK

44 CLOCK I

O Crystal Oscillator Output (to crystal). Leave unconnected if no crystal is used.

Crystal Oscillator Input. If no crystal is used, this pin can be driven by an external TTL clock source; it

requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC)

or 29.5 MHz (PAL) can be used for square pixel operation.

Rev. C | Page 13 of 44

ADV7177/ADV7178

TYPICAL PERFORMANCE CHARACTERISTICS

0

0

–10

TYPE A

–20

–30

–40

AMPLITUDE (dB)

–50

–60

024681012

FREQUENCY (MHz)

TYPE B

Figure 7. NTSC Low-Pass Filter

0

–10

–20

–30

–40

AMPLITUDE (dB)

00228-007

AMPLITUDE (dB)

AMPLITUDE (dB)

–10

–20

–30

–40

–50

–60

–10

–20

–30

–40

FREQUENCY (MHz)

120246810

00228-010

Figure 10. PAL Notch Filter

0

AMPLITUDE (dB)

–50

–60

–10

–20

–30

–40

–50

–60

–50

AMPLITUDE (dB)

–60

FREQUENCY (MHz)

Figure 11. NTSC/PAL Extended Mode Filter

0

–10

–20

–30

–40

–50

–60

FREQUENCY (MHz)

Figure 12. NTSC UV Fil ter

FREQUENCY (MHz)

120426810

00228-008

Figure 8. NTSC Notch Filter

0

TYPE A

TYPE B

FREQUENCY (MHz)

120246810

00228-009

Figure 9. PAL Low-Pass Filter

120426810

120246810

00228-011

00228-012

Rev. C | Page 14 of 44