Analog Devices ADV7176, ADV7175 Datasheet

Integrated Digital CCIR-601

a

FEATURES
CCIR-601 YCrCb to PAL/NTSC Video Encoder
Single 27 MHz Clock Required (32 Oversampling)
Pixel Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
SMPTE 170M NTSC Compatible Composite Video Output
CCIR624/CCIR601 PAL Compatible Composite Video Output
SCART/PeriTV Support
YUV Output Mode
Simultaneous Composite and S-VHS Y/C or RGB YUV

Video Outputs
Programmable Luma Filters (Low-Pass/Notch)
Square Pixel Support (Slave Mode)
Allows Subcarrier Phase Locking with External Video

Source
10-Bit DAC Resolution for Encoded Video Channels
8-Bit DAC Resolution for RGB Output
YUV Interpolation for Accurate Subcarrier Construction
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Master/Slave Operation Supported
Master Mode Timing Programmability
Macrovision Antitaping Facility Rev 6.1/7.x (ADV7175 Only)*

FUNCTIONAL BLOCK DIAGRAM

YCrCb to PAL/NTSC Video Encoder

ADV7175/ADV7176

Close Captioning Support
Teletext Support (Passthrough Mode)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I
+5 V CMOS Monolithic Construction
44-Pin PQFP Thermally Enhanced Package

APPLICATIONS
MPEG-1 and MPEG-2 Video
DVD
Digital Satellite/Cable Systems (Set Top Boxes/IRDs)
Video Games
CD Video/Karaoke
Professional Studio Quality
PC Video/Multimedia

GENERAL DESCRIPTION

The ADV7175/ADV7176 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 component video data into a
standard analog baseband television signal compatible with world
wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In
addition to the composite output signal, there is the facility to out­put S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or
RGB format is simultaneously available at the analog outputs with
the composite video signal. Each analog output generates a
standard video-level signal into a doubly terminated 75 Ω load.

2

C Compatible)

(Continued on page 6)

V

RESET

COLOR

DATA
P7–P0

P15–P8

HSYNC

FIELD/VSYNC

BLANK

AA

YUV TO

RBG

MATRIX

ADD

SYNC

ADD

BURST

ADD

BURST

8

8

88

INTER-

POLATOR

INTER-

POLATOR

INTER-

POLATOR

4:2:2 TO

4:4:4

INTER-

POLATOR

VIDEO TIMING

GENERATOR

8

8

8

CLOCK

YCrCb

TO

YUV

MATRIX

8

8 10

2

I

C MPU PORT

SCLOCK SDATA ALSB

8

8

8

8

LOW-PASS

FILTER

8

LOW-PASS

FILTER

8

LOW-PASS

FILTER

REAL-TIME

CONTROL

CIRCUIT

SCRESET/RTC

Y

U

V

10

10

10

SIN/COS

DDS BLOCK

10

M
U

10

10-BIT

L

DAC

T

I

10

P

10-BIT

L

DAC

E

10

X

10-BIT

E

DAC

R

10

10-BIT

DAC

ADV7175/ADV7176

VOLTAGE

REFERENCE

CIRCUIT

GND

GREEN/
LUMA/
Y

RED/
CHROMA/
V

BLUE/
COMPOSITE/
U

COMPOSITE

V

REF

R

SET

COMP

*This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 a nd other intellectual property rights. The Macrovision anticopy process is

licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

© Analog Devices, Inc., 1996

(VAA = +5 V1, V
T

ADV7175/ADV7176–SPECIFICA TIONS

Model ADV7175/ADV7176
Parameter Conditions

1

MIN

to T

MAX

= 1.235 V R

REF

2

unless otherwise noted)

= 150 V. All specifications

SET

Min Typ Max Units

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±1 LSB

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

VIN = 0.4 V or 2.4 V ±1 µA

2V

0.8 V

10 pF

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

I
I

= 400 µA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

Floating-State Leakage Current 10 µA
Floating-State Output Capacitance 10 pF

ANALOG OUTPUTS

Output Current
Output Current

3
4

33 34.7 37 mA

8mA
Full-Scale DAC Output 182.5 IRE
LSB Size 33.9 µA
DAC-to-DAC Matching 25%
Output Compliance, V
Output Impedance, R

OC

OUT

Output Capacitance, C

OUT

I

= 0 mA 30 pF

OUT

0 +1.4 V

15 kΩ

VOLTAGE REFERENCE

Voltage Reference Range, V

POWER REQUIREMENTS

V

AA

6

I

DAC

7

I

CCT

5

REF

I

VREFOUT

= 20 µA 1.112 1.235 1.359 V

5V

140 155 mA

110 150 mA
Power Supply Rejection Ratio COMP = 0.1 µF 0.02 0.5 %/%

DYNAMIC PERFORMANCE

8

Luma Bandwidth9 (Low-Pass Filter) NTSC Mode

Stopband Cutoff >50 dB Attenuation 7.5 MHz
Pass Band Cutoff <0.06 dB Attenuation 2.3 MHz

Chroma Bandwidth NTSC Mode

Stopband Cutoff <40 dB Attenuation 3.6 MHz
Pass Band Cutoff >0.1 dB Attenuation 1.0 MHz

Luma Bandwidth

9

(Low-Pass Filter) PAL MODE
Stopband Cutoff >50 dB Attenuation 8.0 MHz
Pass Band Cutoff <0.06 dB Attenuation 3.4 MHz

Chroma Bandwidth PAL MODE

Stopband Cutoff <40 dB Attenuation 4.0 MHz
Pass Band Cutoff >0.1 dB Attenuation 1.3 MHz
Differential Gain 0.8 %
Differential Phase 0.8 Degree
Differential Gain Lower Power Mode 7 %
Differential Phase Lower Power Mode 2 Degree
SNR RMS 60 dB rms
SNR Peak Periodic 56 dB p-p
Hue Accuracy 1.0 Degree
Color Saturation Accuracy 1.0 %

NOTES

1

± 5% for all versions.

2

Temperature range T

3

Full drive into 37.5 Ω load.

4

Minimum drive with buffered/scaled output load.

5

Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 100°C.

6

I

is the total current to drive all four DACs. Turning off one DAC reduces I

DAC

7

I

(Circuit Currrent) is the continuous currrent required to drive the device.

CCT

8

Guaranteed by characterization.

9

These specifications are for the low-pass filter only. For the other internal filters please see Figure 3.

Specifications subject to change without notice.

MIN

to T

: 0°C to 70°C.

MAX

correspondingly.

DAC

–2–

REV. A

ADV7175/ADV7176

AC CHARACTERISTICS

Parameter Min Typ Max Units Condition

Chroma Nonlinear Gain 0.6 ±% Referenced to 40 IRE
Chroma Nonlinear Phase 1 ±° NTSC
Chroma Nonlinear Phase 1.7 ±° PAL
Chroma/Luma Intermod 0.2 ±% Referenced to 714 mV (NTSC)
Chroma/Luma Intermod 0.4 ±% Referenced to 700 mV (PAL)
Chroma/Luma Gain Ineq 0.6 ±%
Chroma/Luma Delay Ineq 1 ns
Luminance Nonlinearity 0.8 ±%
Chroma AM Noise 60 dB
Chroma PM Noise 59 dB

1

TIMING–SPECIFICATIONS

2

(VAA = +5 V3, V

= 1.235 V R

REF

= 150 V. All specifications T

SET

MIN

4

to T

unless otherwise noted)

MAX

Parameter Min Typ Max Units Condition

MPU PORT

1

SCLOCK Frequency 0 100 kHz
SCLOCK High Pulse Width, t
SCLOCK Low Pulse Width, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

ANALOG OUTPUTS

1, 5

1

2

3

4

6

7

8

4.0 µs

4.7 µs

4.0 µs After this period the first clock pulse is generated

4.7 µs Relevant for repeated start condition.
250 ns

1 µs
300 ns

4.7 µs

Analog Output Delay 5 ns
DAC Analog Output Skew 0 ns

CLOCK CONTROL
AND PIXEL PORT

F

CLOCK

Clock High Time t
Clock Low Time t
Data Setup Time t
Data Hold Time t
Control Setup Time t
Control Hold Time t
Digital Output Access Time t
Digital Output Hold Time t
Pipeline Delay t

NOTES

1

Guaranteed by characterization.

2

TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog Output Load ≤ 3 pF.

3

±5% for all versions.

4

Temperature range (T

5

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

6

Pixel Port consists of the following inputs:
Pixel Inputs: P15–P0
Pixel Controls: HSYNC, FIELD/VSYNC, BLANK
Clock Input: CLOCK

Specifications subject to change without notice.

15

MIN

6

9

10

11

12

to T

11

12

); 0°C to +70°C.

MAX

24.52 27 29.5 MHz
8ns
8ns

3.5 ns
1ns
4ns
2ns

13

14

6ns

24 ns

37 Clock Cycles

REV. A

–3–

ADV7175/ADV7176

WARNING!

ESD SENSITIVE DEVICE

CONTROL

SDATA

SCLOCK

I/PS

CLOCK

HSYNC,

FIELD/VSYNC,

BLANK

t

t

3

t

6

t

1

5

t

2

t

7

Figure 1. MPU Port Timing Diagram

t

t

9

10

t

12

t

3

t

4

t

8

CONTROL

O/PS

PIXEL INPUT

DATA

HSYNC,

FIELD/VSYNC,

BLANK

Cb Y Cr Y Cb Y

Figure 2. Pixel and Control Data Timing Diagram

ABSOLUTE MAXIMUM RATINGS

1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Input Pin . GND – 0.5 V to V
Storage Temperature (T
Junction Temperature (T

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C

Analog Outputs to GND

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.

) . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . +150°C

J

2

. . . . . . . . . . . . . GND –0.5 to V

+ 0.5 V

AA

AA

t

11

t

13

t

14

ORDERING GUIDE

Temperature Package

Model Range Option

ADV7175KS 0°C to +70°C S-44
ADV7176KS 0°C to +70°C S-44

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7175/ADV7176 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

ADV7175/ADV7176

PIN DESCRIPTION

Mnemonic Input/Output Function

P15-P0 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or

16-Bit YCrCb Pixel Port (P15–P0). P0 represents the LSB.

CLOCK I TTL Clock Input. Requires a stable 27 MHz reference Clock for proper operation.

Alternatively a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel
operation.

HSYNC I/O HSYNC (Modes 1 & 2) Control Signal. This pin may be configured to output (Mas-

ter Mode) or accept (Slave Mode) Sync signals.

FIELD/VSYNC I/O Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may

be configured to output (Master Mode) or accept (Slave Mode) these control signals.

BLANK I/O Video Blanking Control Signal. The pixel inputs are ignored when this is logic level

“0.” This signal is optional.

SCRESET/RTC I This pin can be configured as an input by setting MR22 and MR21 of Mode

Register 2. It can be configured as a subcarrier reset pin, in which case a high to low
transition on this pin will reset the subcarrier to field 0. Alternatively it may be con­figured as a Real Time Control (RTC) input.

V

REF

R

SET

COMP O Compensation Pin. Connect a 0.1 µF capacitor from COMP to V
COMPOSITE O PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286 mV) for

RED/CHROMA/V O RED/S-VHS C/V Analog Output.
GREEN/LUMA/Y O GREEN/S-VHS Y/Y Analog Output.
BLUE/COMPOSITE/U O BLUE/Composite/U Analog Output.
SCLOCK I MPU Port Serial Interface Clock Input.
SDATA I/O MPU Port Serial Data Input/Output.
ALSB I TTL Address Input. This signal set up the LSB of the MPU address.
RESET I The input resets the on chip timing generator and sets the ADV7175/ADV7176 into

V

AA

GND G Ground Pin.

I/O Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
I A 150 Ω resistor connected from this pin to GND is used to control full-scale ampli-

tudes of the video signals.

.

AA

NTSC and 1300 mV for PAL.

default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 ×
composite & S VHS out.

P +5 V Supply.

REV. A

PIN CONFIGURATION

CLOCK

GND

P3

P4

42

4344 36

1

V

AA

PIN 1
IDENTIFIER

2

P5

3

P6

4

P7

5

P8

6

P9

7

P10

8

P11

9

P12

10

GND

11

V

AA

12 13 14 15 16 17 18 192021 22

P13

40

ADV7175/ADV7176

(Not to Scale)

P14

P15

FIELD/

HSYNC

P2

P1

39 3841

PQFP

TOP VIEW

VSYNC

BLANK

–5–

P0

ALSB

AA

V

GND

GND

AA

V

35 3437

SCRESET/

GND

RTC

SET

R

RESET

33

V

32

COMPOSITE

31
30
29

GND

28

V

27

GREEN/LUMA/Y

26

RED/CHROMA/V

25

COMP

24

SDATA

23

SCLOCK

REF

BLUE/COMPOSITE/U
V

AA

AA

ADV7175/ADV7176

(Continued from page 1)

The ADV7175/ADV7176 also supports both a PAL and NTSC
square pixel mode in slave mode.

The video encoder accepts an 8-bit parallel pixel data stream in
CCIR-656 format or a 16-bit parallel data stream. This 4:2:2
data stream is interpolated into 4:4:4 component video (YUV).
The YUV video is interpolated to two times the pixel rate. The
color-difference components (UV) are quadrature modulated
using a subcarrier frequency generated by an on-chip synthesizer
(also running at two times the pixel rate). The two times pixel
rate sampling allows more accurate generation of the subcarrier
because frequency and phase errors are reduced by the higher
sampling rate. The ADV7175/ADV7176 also offers the option to
output the YUV information directly.

The luminance and chrominance components are digitally com­bined and the resulting composite signal is output via a 10-bit
DAC. Three additional 10-/8-bit DACs are provided to output
S-VHS Y/C Video (10 bits), YUV or RGB Video (8 bits).

The output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts (and
can generate)

HSYNC, VSYNC & FIELD timing signals. These
timing signals can be adjusted to change pulse width and posi­tion while the part is in the master mode. The encoder requires a
single two times pixel rate (27 MHz) clock for standard operation.
Alternatively the encoder requires 24.54 MHz clock for NTSC
or 29.5 MHz clock for PAL square pixel mode operation. All in­ternal clocks are generated on-chip. The ADV7175/ADV7176
modes are set up over a two wire serial bidirectional port (I

2

C

Compatible) with two slave addresses.
Additionally, the ADV7175/ADV7176 allows a subcarrier phase

lock with an external video source and has a color bar generator
on-board.

Functionally the ADV7175 and ADV7176 are the same with
the exception that the ADV7175 can output the Macrovision
(Revision 6.1/7.x) anticopy algorithm.

The ADV7175/ADV7176 is fabricated in a +5 V CMOS pro­cess. Its monolithic CMOS construction ensures greater func­tionality with low power dissipation.

The ADV7175/ADV7176 is packaged in a 44-pin thermally en­hanced PQFP package (patent pending).

The ADV7175/ADV7176 is protected by U.S. Patent Numbers
5,343,196 and 5,442,355 and other intellectual property rights.

DATA PATH DESCRIPTION

For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a

13.5 MHz data rate. The pixel data is de-multiplexed to form
three data paths. Y has a range of 16 to 235, Cr and Cb have a
range of 128 ± 112. The ADV7175/ADV7176 supports PAL
(B, D, G, H, I, N, M) and NTSC (with and without Pedestal)
standards. The appropriate SYNC, BLANK and burst levels are
added to the YCrCb data. Macrovision antitaping (ADV7175
only) and close-captioning levels are also added to Y and the
resultant data is interpolated to a rate of 27 MHz. The interpo­lated data is filtered and scaled by three digital FIR filters.

The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi­nance signal. The luma (Y) signal can be delayed 1-3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.

The YCrCb data is also used to generate RGB data with appro­priate SYNC and BLANK levels. The RGB data is in sychro­nization with the composite video output. Alternatively analog
YUV data can be generated instead of RGB.

The four 10-bit DACs can be used to output:

1. 10-bit composite video + 8-bit RGB video.

2. 10-bit composite video + 8-bit YUV video.

3. Two 10-bit composite video signals
+ 10-bit LUMA & CHROMA (Y/C) signals.

Alternatively, each DAC can be individually powered off if not
required.

All possible video outputs are illustrated in Appendix 3, 4 and 5.

INTERNAL FILTER RESPONSE

The Y filter supports several different frequency responses in­cluding two 4.5/5.0 MHz low-pass and PAL/NTSC subcarrier
notch responses. The U and V filters have a 0.6/1 0.3 MHz
low-pass response.

These filter characteristics are illustrated in Figures 3 to 11.

FILTER SELECTION

MR04 MR03
NTSC 0 0 2.3 0.026 7.5
PAL 0 0 3.4 0.098 8.0
NTSC 0 1 1.0 0.085 3.57
PAL 0 1 1.4 0.107 4.43
NTSC/PAL 1 0 4.0 0.150 8.0
NTSC 1 1 2.3 0.054 7.5
PAL 1 1 3.4 0.106 8.0

PASSBAND

CUT OFF (MHz)

PASSBAND

RIPPLE (dB)

Figure 3. Y Filter Specifications

FILTER SELECTION

NTSC 1.0 0.085 3.6
PAL 1.3 0.04 4.0

PASSBAND

CUT OFF (MHz)

PASSBAND

RIPPLE (dB)

CUT OFF (MHz)

Figure 4. UV Filter Specifications

–6–

STOPBAND

STOPBAND

CUT OFF (MHz)

STOPBAND

ATTENUATION (dB)

>

40 0.3 2.05

>

40 0.02 2.45

STOPBAND

ATTENUATION (dB)

>

50 4.2

>

51.3 5.0

>

27.6 2.1

>

29.3 2.7

>

40 5.65

>

54 4.2

>

50.3 5.0

ATTENUATION @

1.3MHz (dB)

F

3dB

F

3dB

REV. A

ADV7175/ADV7176

FREQUENCY – MHz

0

–120

–100

–80

–20

–40

–60

02468 1210

AMPLITUDE – dB

TYPE A

TYPE B

FREQUENCY – MHz

0

–120

–100

–80

–20

–40

–60

02468 1210

AMPLITUDE – dB

0

–20

–40

–60

AMPLITUDE – dB

–80

–100

–120

02468 1210

TYPE A

FREQUENCY – MHz

Figure 5. NTSC Low-Pass Filter

0

–20

–40

–60

TYPE B

Figure 7. PAL Low-Pass Filter

AMPLITUDE – dB

–80

–100

–120

02468 1210

Figure 6. NTSC Notch Filter

FREQUENCY – MHz

0

–20

–40

–60

AMPLITUDE – dB

–80

–100

–120

02468 1210

FREQUENCY – MHz

Figure 8. PAL Notch Filter

REV. A

Figure 9. NTSC/PAL Extended Mode Filter

–7–

ADV7175/ADV7176

FREQUENCY – MHz

02468 1210

AMPLITUDE – dB

–10

–40

–20

0

–80

–60

–100

–50

–30

–90

–70

0

–10

–20

–30

–40

–50

–60

AMPLITUDE – dB

–70

–80

–90

–100

02468 1210

FREQUENCY – MHz

Figure 10. NTSC UV Filter

COLOR BAR GENERATION

The ADV7175/ADV7176 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”

SQUARE PIXEL MODE

The ADV7175/ADV7176 can be used to operate in square
pixel mode. For NTSC operation an input clock of 24.54MHz
is required. Alternatively, for PAL operation, an input clock of

29.5 MHz is required. The internal filters scale accordingly for
square pixel mode operation.

COLOR SIGNAL CONTROL

The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.

BURST SIGNAL CONTROL

The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.

NTSC PEDESTAL CONTROL

The pedestal information on both odd and even fields can be
controlled on a line by line basis using the NTSC Pedestal
Control Registers. This allows the pedestals to be controlled
during the vertical blanking interval (Lines 10 to 25).

SUBCARRIER RESET

Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used in subcarrier reset mode. The subcarrier will reset to field
0 at the start of the following field when a high to low transition
occurs on this input pin.

REAL TIME CONTROL

Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used to lock an external video source. The real time control
mode allows the ADV7175/ADV7176 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs out a digi­tal datastream in the RTC format (such as a Phillips SAA7110
video decoder), the part will automatically change to the com­pensated subcarrier frequency on a line by line basis. This
digital datastream is 67 bits wide and the subcarrier is con­tained in bits 0 to 21. Each bit is 2 clock cycles long.

Figure 11. PAL UV Filter

CLOCK

COMPOSITE

VIDEO

e.g. VCR

OR CABLE

VIDEO

DECODER

(e.g.SAA7110)

MPEG

DECODER

M
U
X

SCRESET/RTC

P7–P0

BLUE/COMPOSITE/U

HSYNC

FIELD/VSYNC

GREEN/LUMA/Y

RED/CHROMA/V

COMPOSITE

ADV7175/ADV7176

Figure 12. RTC Connections

PIXEL TIMING DESCRIPTION

The ADV7175/ADV7176 can operate in either 8-bit or 16-bit
YCrCb Mode.

8-Bit YCrCb Mode

This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on
a rising clock edge.

16-Bit YCrCb Mode

This mode accepts Y inputs through the P7-P0 pixel inputs and
multiplexed CrCb inputs through the P15-P8 pixel inputs. The
data is loaded on every second rising clock edge of CLOCK.
The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.

VIDEO TIMING DESCRIPTION

The ADV7175/ADV7176 is intended to interface to off the shelf
MPEG1 and MPEG2 Decoders. As a consequence the
ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing gen­erator. The ADV7175/ADV7176 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.

The ADV7175/ADV7176 calculates the width and placement
of analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.

(Continued on page 15)

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REV. A

ADV7175/ADV7176

Mode 0 (CCIR-656): Slave Option.

(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before

and after each line during active picture and retrace. Mode 0 is illustrated in Figure 13. The
(if not used) pins should be tied high in this mode.

ANALOG

VIDEO

HSYNC, FIELD/VSYNC and BLANK

INPUT PIXELS

NTSC SYSTEM

PAL SYSTEM

EAV CODE

FF0000X

CrC

Y

b

4 PIXELS

4 PIXELS

END OF ACTIVE

VIDEO LINE

8

10801

0

Y

0

FF00FFABABA

B

ANCILLARY DATA

(HANC)

268 PIXELS

280 PIXELS

801

0

SAV CODE

8

10FF0

0

0

XYC

Y

0

b

0

4 PIXELS

4 PIXELS

START OF ACTIVE

VIDEO LINE

CrC

C

C

Y

r

b

1440 PIXELS

1440 PIXELS

C

Y

b

r

Figure 13. Timing Mode 0 (Slave Mode)

Mode 0 (CCIR-656): Master Option.

(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7175/ADV7176 generates H, V and F signals required for the SAV (start active video) and EAV (end active video) time

codes in the CCIR656 standard. The H bit is output on the
output on the FIELD/

VSYNC pin. Mode 0 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL). The H, V and F transitions

HSYNC pin, the V bit is output on the BLANK pin and the F bit is

relative to the video waveform are illustrated in Figure 16.

DISPLAY

522 523 524 525 1 2 3 4

H

VERTICAL BLANK

67

5

8

10 11 20 21 22

9

DISPLAY

REV. A

V

F

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

H

V

F

ODD FIELD

ODD FIELDEVEN FIELD

VERTICAL BLANK

EVEN FIELD

Figure 14. Timing Mode 0 (NTSC Master Mode)

–9–

283

284

DISPLAY

285

ADV7175/ADV7176

DISPLAY

622 623 624 625 1 2 3 4

H

V

F

DISPLAY

309 310 311 312 314 315 316 317

H

V

F

ODD FIELD EVEN FIELD

ODD FIELDEVEN FIELD

313

Figure 15. Timing Mode 0 (PAL Master Mode)

VERTICAL BLANK

5

VERTICAL BLANK

67

318

319 320 334

DISPLAY

22 23

21

DISPLAY

335 336

ANALOG

VIDEO

H

F

V

Figure 16. Timing Mode 0 Data Transitions (Master Mode)

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REV. A

ADV7175/ADV7176

Mode 1: Slave Option. HSYNC, BLANK, FIELD.
(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode the ADV7175/ADV7176 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when

HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled
the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 17 (NTSC)
and Figure 18 (PAL).

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

284

DISPLAY

285

DISPLAY

522 523 524 525

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

ODD FIELD EVEN FIELD

VERTICAL BLANK

678

5

VERTICAL BLANK

9

10 11

20 21 22

283

Figure 17. Timing Mode 1 (NTSC)

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

DISPLAY

622 623 624 625 1 2 3 4

ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD EVEN FIELD

VERTICAL BLANK

VERTICAL BLANK

Figure 18. Timing Mode 1 (PAL)

5

317

67

318 319

320

DISPLAY

21 22 23

DISPLAY

334 335 336

REV. A

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