CMOS, 330 MHz
V
FEATURES
330 MSPS throughput rate
Triple 8-bit DACs
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal Reference (1.235 V)
Single-supply +5 V/+3.3 V operation
48-lead LQFP and LFCSP packages
Low power dissipation (30 mW minimum @ 3 V)
Low power standby mode (6 mW typical @ 3 V)
Industrial temperature range (−40°C to +85°C)
Pb-free (lead-free) packages
Qualified for automotive applications
APPLICATIONS
Digital video systems
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
Automotive infotainment units
Triple 8-Bit High Speed Video DAC
ADV7125
FUNCTIONAL BLOCK DIAGRAM
AA
BLANK
SYNC
R7 TO R0
G7 TO G0
B7 TO B0
PSAVE
CLOCK
8
REGISTER
8
REGISTER
8
REGISTER
POWER-DOWN
DATA
DATA
DATA
MODE
8
8
8
R
COMPGND
SET
Figure 1.
DAC
DAC
DAC
BLANK AND
SYNC LOGI C
VOLTAGE
REFERENCE
CIRCUIT
ADV7125
IOR
IOR
IOG
IOG
IOB
IOB
V
REF
03097-001
GENERAL DESCRIPTION
The ADV7125 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three high
speed, 8-bit video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.
The ADV7125 has three separate 8-bit-wide input ports. A
single +5 V/+3.3 V power supply and clock are all that are
required to make the part functional. The ADV7125 has
additional video control signals, composite
SYNC
as well as a power save mode.
ADV is a registered trademark of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
and
BLANK
,
The ADV7125 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7125 is available in
48-lead LQFP and 48-lead LFCSP packages.
PRODUCT HIGHLIGHTS
1. 330 MSPS (3.3 V only) throughput.
2. Guaranteed monotonic to eight bits.
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2011 Analog Devices, Inc. All rights reserved.
ADV7125
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Electrical Characteristics...................................................... 3
3.3 V Electrical Characteristics................................................... 4
5 V Timing Specifications ........................................................... 5
3.3 V Timing Specifications........................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 10
Circuit Description and Operation.............................................. 11
Digital Inputs .............................................................................. 11
Clock Input.................................................................................. 11
Video Synchronization and Control........................................ 12
Reference Input........................................................................... 12
DACs............................................................................................ 12
Analog Outputs .......................................................................... 12
Gray Scale Operation................................................................. 13
Video Output Buffers................................................................. 13
PCB Layout Considerations...................................................... 13
Digital Signal Interconnect ....................................................... 13
Analog Signal Interconnect....................................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Automotive Products................................................................. 16
REVISION HISTORY
2/11—Rev. B to Rev. C
Change to Table 6 ............................................................................. 8
7/10—Rev. A to Rev. B
Change to Features Section............................................................. 1
Changes to Clock Frequency Parameter, Table 4 ......................... 6
Changes to Figure 2.......................................................................... 6
Changes to Figure 4 and Figure 5................................................. 11
Changes to Table 7.......................................................................... 12
Changes to Endnotes to Ordering Guide .................................... 15
Added Automotive Products Section .......................................... 15
3/09—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features Section, Applications Section, and General
Description Section .......................................................................... 1
Changes to Figure 3 and Table 6......................................................8
Deleted Ground Planes Section, Power Planes Section, and
Supply Decoupling Section ........................................................... 11
Changes to Figure 5........................................................................ 11
Changes to Table 7, Analog Outputs Section, Figure 6, and
Figure 7 ............................................................................................ 12
Changes to Video Output Buffers Section, PCB Layout
Considerations Section, and Figure 9.......................................... 13
Changes to Analog Signal Interconnect Section and
Figure 10 .......................................................................................... 14
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide.......................................................... 16
10/02—Revision 0: Initial Version
Rev. C | Page 2 of 16
ADV7125
SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VAA = 5 V ± 5%, V
Table 1.
Parameter Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits
Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB
Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2 V
Input Low Voltage, V
Input Current, I
PSAVE Pull-Up Current
Input Capacitance, CIN
ANALOG OUTPUTS
Output Current 2.0 26.5 mA
2.0 18.5 mA
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C
Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V
Gain Error2 −5.0 +5.0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, V
POWER DISSIPATION
Digital Supply Current3 3.4 9 mA f
10.5 15 mA f
18 25 mA f
Analog Supply Current 67 72 mA R
8 mA R
Standby Supply Current4 2.1 5.0 mA
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range T
2
Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = V
3
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4
These maximum/minimum specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.
= 1.235 V, R
REF
0.8 V
IL
−1 +1 μA VIN = 0.0 V or V
IN
= 560 Ω, CL = 10 pF. All specifications T
SET
20 μA
MIN
to T
,1 unless otherwise noted, T
MAX
10 pF
Green DAC, SYNC
RGB DAC, SYNC
100 kΩ
OUT
10 pF I
OUT
= 0 mA
OUT
1.12 1.235 1.35 V
REF
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 530 Ω
SET
= 4933 Ω
SET
= low, digital, and control inputs at VDD
PSAVE
to T
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
MIN
MAX
× K × (0xFFH) × 4 and K = 7.9896.
REF/RSET
DD
= high
= low
J MAX
= 110°C.
Rev. C | Page 3 of 16
ADV7125
3.3 V ELECTRICAL CHARACTERISTICS
VAA = 3.0 V to 3.6 V, V
Table 2.
Parameter2 Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits R
Integral Nonlinearity (BSL) −1 ±0.5 +1 LSB R
Differential Nonlinearity −1 ±0.25 +1 LSB R
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current
Input Capacitance, C
ANALOG OUTPUTS
Output Current 2.0 26.5 mA
2.0 18.5 mA
DAC-to-DAC Matching 1.0 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C
Offset Error 0 0 % FSR Tested with DAC output = 0 V
Gain Error3 0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE, EXTERNAL
Reference Range, V
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, V
POWER DISSIPATION
Digital Supply Current4 2.2 5.0 mA f
6.5 12.0 mA f
11 15 mA f
16 mA f
Analog Supply Current 67 72 mA R
8 mA R
Standby Supply Current 2.1 5.0 mA
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range T
2
These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.
3
Gain error = ((Measured (FSC)/Ideal (FSC) −1) × 100), where Ideal = V
4
Digital supply is measured with continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
= 1.235 V, R
REF
10 pF
IN
= 560 Ω, CL = 10 pF. All specifications T
SET
20 μA
MIN
to T
SET
SET
SET
MAX
= 680 Ω
= 680 Ω
= 680 Ω
Green DAC, SYNC
RGB DAC, SYNC
70 kΩ
OUT
10 pF
OUT
1.12 1.235 1.35 V
REF
1.235 V
REF
to T
MIN
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
MAX
× K × (0xFFH) × 4 and K = 7.9896.
REF/RSET
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 330 MHz
CLK
= 560 Ω
SET
= 4933 Ω
SET
= low, digital, and control inputs at VDD
PSAVE
,1 unless otherwise noted, T
= high
= low
J MAX
= 110°C.
Rev. C | Page 4 of 16
ADV7125
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 V
Table 3.
Parameter3 Symbol Min Typ Max Unit Conditions
ANALOG OUTPUTS
Analog Output Delay t6 5.5 ns
Analog Output Rise/Fall Time4 t7 1.0 ns
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t
CLOCK CONTROL
CLOCK Frequency7 f
0.5 140 MHz 140 MHz grade
0.5 240 MHz 240 MHz grade
Data and Control Setup6 t1 0.5 ns
Data and Control Hold6 t2 1.5 ns
CLOCK Period t3 4.17 ns
CLOCK Pulse Width High6 t4 1.875 ns f
CLOCK Pulse Width Low6 t5 1.875 ns f
CLOCK Pulse Width High6 t4 2.85 ns f
CLOCK Pulse Width Low6 t5 2.85 ns f
CLOCK Pulse Width High t4 8.0 ns f
CLOCK Pulse Width Low t5 8.0 ns f
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time
1
The maximum and minimum specifications are guaranteed over this range.
2
Temperature range T
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
CLK
= 1.235 V, R
REF
6
to T
MIN
= 560 Ω, CL = 10 pF. All specifications T
SET
1 2 ns
9
0.5 50 MHz 50 MHz grade
CLK
t
10
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
MAX
2 10
MIN
to T
,2 unless otherwise noted, T
MAX
ns
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 110°C.
J MAX
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
Rev. C | Page 5 of 16
ADV7125
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 V
Table 4.
Parameter3 Symbol Min Typ Max Unit Conditions
ANALOG OUTPUTS
Analog Output Delay, t6 7.5 ns
Analog Output Rise/Fall Time4 t
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t9 1 2 ns
CLOCK CONTROL
CLOCK Frequency7 f
140 MHz 140 MHz grade
240 MHz 240 MHz grade
330 MHz 330 MHz grade
Data and Control Setup6 t1 0.2 ns
Data and Control Hold6 t2 1.5 ns
CLOCK Period t3 3 ns
CLOCK Pulse Width High6 t4 1.4 ns f
CLOCK Pulse Width Low6 t5 1.4 ns f
CLOCK Pulse Width High6 t4 1.875 ns f
CLOCK Pulse Width Low6 t5 1.875 ns f
CLOCK Pulse Width High6 t4 2.85 ns f
CLOCK Pulse Width Low6 t5 2.85 ns f
CLOCK Pulse Width High t4 8.0 ns f
CLOCK Pulse Width Low t5 8.0 ns f
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time
1
These maximum and minimum specifications are guaranteed over this range.
2
Temperature range: T
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
CLK
6
to T
MIN
= 1.235 V, R
REF
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
MAX
= 560 Ω, CL = 10 pF. All specifications T
SET
1.0 ns
7
50 MHz 50 MHz grade
CLK
t
10
4 10
MIN
to T
,2 unless otherwise noted, T
MAX
ns
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 110°C.
J MAX
= 330 MHz
= 330 MHz
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
t
3
t
4
t
5
CLOCK
(R7 TO R0, G7 TO G0, B7 TO B0,
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. OUTPUT DELAY (
OF FULL -SCALE TRANSITION.
2. OUTPUT RISE/FALL TIM E (
3. TRANSITION TIME (
FINAL OUTPUT VALUE.
DIGITAL INPUTS
SYNC, BLANK)
ANALOG OUTPUTS
t
) MEASURED FRO M THE 50% POI NT OF T HE RISING EDGE OF CL OCK TO T HE 50% POINT
6
t
t
) MEASURED FRO M THE 50% POI NT OF F ULL-SCALE TRANSITI ON TO W ITHIN 2% O F THE
8
t
1
) MEASURED BETW EEN THE 10% AND 90% POI NTS OF F ULL-SCAL E TRANSITION.
7
t
2
t
6
t
8
t
7
03097-002
Figure 2. Timing Diagram
Rev. C | Page 6 of 16
ADV7125
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VAA to GND 7 V
Voltage on Any Digital Pin GND − 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) −40°C to +85°C
Storage Temperature (TS) −65°C to +150°C
Junction Temperature (TJ) 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase Soldering (1 Minute) 220°C
I
to GND1 0 V to VAA
OUT
1
Analog output short circuit to any power supply or common GND can be of
an indefinite duration.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 7 of 16
ADV7125
K
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
R7R6R5R4R3R2R1R0GND
4847464544434241403938
GND
1
GND
2
G0
3
G1
4
G2
5
6
G3
G4
7
G5
8
G6
9
G7
10
11
BLAN
12
SYNC
NOTES
1. THE LF CSP_VQ HAS AN EXP OSED PADDLE T HAT MUST BE
CONNECT ED TO GND.
PIN 1
INDICATOR
ADV7125
TOP VIEW
(Not to Scale)
13141516171819
AA
B0B1B2B3B4B5B6
V
GND
GND
2021222324
SET
GND
PSAVE
R
37
V
36
REF
35
COMP
IOR
34
IOR
33
IOG
32
IOG
31
30
V
AA
29
V
AA
28
IOB
27
IOB
26
GND
25
GND
03097-003
B7
CLOCK
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number Mnemonic Description
1, 2, 14, 15, 25,
GND Ground. All GND pins must be connected.
26, 39, 40
3 to 10, 16 to
23, 41 to 48
11
G0 to G7,
B0 to B7,
R0 to R7
Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog
BLANK
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of
CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be
connected to either the regular printed circuit board (PCB) power or ground plane.
outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of
12
CLOCK. While BLANK
Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a
SYNC
is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored.
40 IRE current source. This is internally connected to the IOG analog output. SYNC
any other control or data input; therefore, it should only be asserted during the blanking interval.
SYNC
is latched on the rising edge of CLOCK. If sync information is not required on the green channel,
the SYNC
input should be tied to Logic 0.
13, 29, 30 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected.
24 CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7, SYNC
and BLANK
pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK
should be driven by a dedicated TTL buffer.
33, 31, 27
, IOG, IOB Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
IOR
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω
load. If the complementary outputs are not required, these outputs should be tied to ground.
34, 32, 28 IOR, IOG, IOB
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly
driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output
loads whether or not they are all being used.
35 COMP
36 V
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
REF
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic
capacitor must be connected between COMP and V
.
AA
does not override
,
Rev. C | Page 8 of 16
ADV7125
Pin Number Mnemonic Description
37 R
R
The relationship between R
IOR, IOB (mA) = 7989.6 × V
38
49 (EPAD) EP (EPAD) The LFCSP_VQ has an exposed paddle that must be connected to GND.
SET
A resistor (R
) connected between this pin and GND controls the magnitude of the full-scale video
SET
signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The
relationship between R
and the full-scale output current on IOG (assuming I
SET
is connected to IOG)
SYNC
is given by:
(Ω) = 11,445 × V
SET
IOG (mA) = 11,444.8 × V
The equation for IOG is the same as that for IOR and IOB when SYNC
(V)/IOG (mA)
REF
and the full-scale output current on IOR, IOG, and IOB is given by:
SET
(V)/R
REF
(Ω) (SYNC being asserted)
SET
(V)/R
REF
(Ω)
SET
is not being used, that is, SYNC
tied permanently low.
Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is
PSAVE
active.
Rev. C | Page 9 of 16
ADV7125
TERMINOLOGY
Blanking Level
SYNC
The level separating the
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that shuts off the picture
tube, resulting in the blackest possible picture.
Color Video (RGB)
This refers to the technique of combining the three primary
colors of red, green, and blue to produce color pictures within
the usual spectrum. In RGB monitors, three DACs are required,
one for each color.
Sync Signal (
The position of the composite video signal that synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels.
SYNC
)
portion from the video portion
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Level
The peak level of the
Video Signal
The portion of the composite video signal that varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion that can be
visually observed.
SYNC
signal.
Rev. C | Page 10 of 16
ADV7125
2. V
3
CIRCUIT DESCRIPTION AND OPERATION
The ADV7125 contains three 8-bit DACs, with three input
channels, each containing an 8-bit register. Also integrated
on board the part is a reference amplifier. The CRT control
functions,
BLANK
and
SYNC
, are integrated on board the
ADV7125.
DIGITAL INPUTS
There are 24 bits of pixel data (color information), R0 to R7,
G0 to G7, and B0 to B7, latched into the device on the rising
edge of each clock cycle. This data is presented to the three 8-bit
DACs and then converted to three analog (RGB) output waveforms (see Figure 4).
CLOCK
DIGITAL INPUTS
(R7 TO R0, G7 TO G0,
B7 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG,
IOB, IOB)
Figure 4. Video Data Input/Output
The ADV7125 has two additional control signals that are latched
to the analog video outputs in a similar fashion.
SYNC
are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.
The
BLANK
and
SYNC
functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK
and
SYNC
digital inputs.
Figure 5 shows the analog output, RGB video waveform of the
ADV7125. The influence of
SYNC
video waveform is illustrated.
RED AND BLUE
mA V
18.67 0.7
DATA
BLANK
and
GREEN
mA V
26.0 0.975
BLANK
and
on the analog
03097-004
Tabl e 7 details the resultant effect on the analog outputs of
BLANK
and
SYNC
.
All these digital inputs are specified to accept TTL logic levels.
CLOCK INPUT
The CLOCK input of the ADV7125 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, is determined by the
on-screen resolution, according to the following equation:
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh
Rate)/(Retrace Factor)
where:
Horiz Res is the number of pixels per line.
Ver t Res is the number of lines per frame.
Refresh Rate is the horizontal scan rate. This is the rate at which
the screen must be refreshed, typically 60 Hz for a noninterlaced
system, or 30 Hz for an interlaced system.
Retrace Factor is the total blank time factor. This takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
Therefore, for a graphics system with a 1024 × 1024 resolution,
a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8,
Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz. All video
data and control inputs are latched into the ADV7125 on the
rising edge of CLOCK, as previously described in the Digital
Inputs section. It is recommended that the CLOCK input to the
ADV7125 be driven by a TTL buffer (for example, the 74F244).
WHITE LEVEL
00
NOTES
1. OUTPUTS CO NNECTED TO A DOUBLY TE RMINAT ED 75Ω LOAD.
= 1.235V, R
REF
. RS-343 LEVELS AND TOL ERANCES ASSUMED O N ALL LEVELS.
7.2 0.271
00
= 530Ω.
SET
Figure 5. Typical RGB Video Output Waveform
Rev. C | Page 11 of 16
BLANK LEVEL
SYNC LEVEL
03097-005
ADV7125
Table 7. Typical Video Output Truth Table (R
Video Output Level IOG (mA)
IOG
White Level 26.0 0 18.67 0 1 1 0xFFH
Video Video + 7.2 18.67 − Video Video 18.67 − Video 1 1 Data
Video to BLANK
Video 18.67 − Video Video 18.67 − Video 0 1 Data
Black Level 7.2 18.67 0 18.67 1 1 0x00H
Black to BLANK
BLANK Level
SYNC Level
0 18.67 0 18.67 0 1 0x00H
7.2 18.67 0 18.67 1 0 0xXXH (don’t care)
0 18.67 0 18.67 0 0 0xXXH (don’t care)
VIDEO SYNCHRONIZATION AND CONTROL
The ADV7125 has a single composite sync (
control. Many graphics processors and CRT controllers have the
ability to generate horizontal sync (HSYNC), vertical sync
(VSYNC), and composite
SYNC
.
In a graphics system that does not automatically generate a
composite
SYNC
signal, the inclusion of some additional logic
circuitry enables the generation of a composite
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7125, the
SYNC
to logic low.
REFERENCE INPUT
The ADV7125 contains an on-board voltage reference. The V
pin should be connected as shown in Figure 10.
A resistance, R
determines the amplitude of the output video level according to
Equation 1 and Equation 2 for the ADV7125.
IOG (mA) = 11,444.8 × V
IOR, IOB (mA) = 7989.6 × V
Equation 1 applies to the ADV7125 only, when
SYNC
used. If
Equation 1 is similar to Equation 2.
Using a variable value of R
the analog output video levels. Use of a fixed 560 R
yields the analog output levels quoted in the Specifications section.
These values typically correspond to the RS-343A video waveform values, as shown in Figure 5.
, connected between the R
SET
REF
(V)/R
(Ω) (1)
SET
(V)/R
REF
SET
is not being encoded onto the green channel,
allows for accurate adjustment of
SET
= 530 Ω, R
SET
(mA)
SYNC
SYNC
) input
IOR/IOB (mA)
signal.
input should be tied
REF
pin and GND,
SET
(Ω) (2)
SYNC
is being
resistor
SET
= 37.5 Ω)
LOAD
/
(mA)
IOR
IOB
SYNC
BLANK
DAC Input Data
low glitch. The on-board operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.
ANALOG OUTPUTS
The ADV7125 has three analog outputs, corresponding to the
red, green, and blue video signals.
The red, green, and blue analog outputs of the ADV7125 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 load, such
as a doubly terminated 75 coaxial cable. Figure 6 shows the
required configuration for each of the three RGB outputs
connected into a doubly terminated 75 load. This arrangement
develops RS-343A video output voltage levels across a 75
monitor.
A suggested method of driving RS-170 video levels into a 75
monitor is shown in Figure 7. The output current levels of the
DACs remain unchanged, but the source termination resistance,
Z
, on each of the three DACs is increased from 75 to 150 .
S
IOR, IOG, IOB
DACs
= 75Ω
Z
S
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE T IMES
FOR RED, GREEN, AND BLUE DACs
Figure 6. Analog Output Termination for RS-343A
IOR, IOG, IOB
DACs
= 150Ω
Z
S
(SOURCE
TERMINATION)
= 75Ω
Z
0
(CABLE)
= 75Ω
Z
0
(CABLE)
= 75Ω
Z
L
(MONITOR)
= 75Ω
Z
L
(MONITOR)
03097-006
DACS
The ADV7125 contains three matched 8-bit DACs. The DACs
are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = 1) or GND (bit = 0)
by a sophisticated decoding scheme. Because all this circuitry
is on one monolithic device, matching between the three DACs
is optimized. As well as matching, the use of identical current
sources in a monolithic design guarantees monotonicity and
Rev. C | Page 12 of 16
TERMINATION REPEATED THREE T IMES
FOR RED, GREEN, AND BLUE DACs
Figure 7. Analog Output Termination for RS-170
03097-007
More detailed information regarding load terminations for
various output configurations, including RS-343A and RS-170,
is available in the AN-205 Application Note, Video Formats and
Required Load Terminations, available from Analog Devices at
www.analog.com.
ADV7125
Figure 5 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 load of
Figure 6. As well as the gray scale levels (black level to white
level), Figure 5 also shows the contributions of
BLANK
for the ADV7125. These control inputs add appro-
SYNC
and
priately weighted currents to the analog outputs, producing
the specific output level requirements for video applications.
details how the Tabl e 7
SYNC
and
BLANK
inputs modify the
output levels.
GRAY SCALE OPERATION
The ADV7125 can be used for standalone, gray scale (monochrome) or composite video applications (that is, only one channel
used for video information). Any one of the three channels, red,
green, or blue, can be used to input the digital video data. The
two unused video data channels should be tied to Logic 0. The
unused analog outputs should be terminated with the same load
as that for the used channel, that is, if the red channel is used
and IOR is terminated with a doubly terminated 75 load
(37.5 ), IOB and IOG should be terminated with 37.5
resistors (see Figure 8).
37.5Ω
37.5Ω
DOUBLY
TERMINATED
75Ω LOAD
03097-008
VIDEO
OUTPUT
Figure 8. Input and Output Connections for Standalone Gray Scale or
R0
R7
ADV7125
G0
G7
B0
B7
IOR
IOG
IOB
GND
Composite Video
VIDEO OUTPUT BUFFERS
The ADV7125 is specified to drive transmission line loads. The
analog output configuration to drive such loads is described in the
Analog Outputs section and illustrated in Figure 9. However,
in some applications, it may be required to drive long transmission line cable lengths. Cable lengths greater than 10 meters can
attenuate and distort high frequency analog output pulses. The
inclusion of output buffers compensates for some cable distortion.
Buffers with large full power bandwidths and gains between
two and four are required. These buffers also need to be able
to supply sufficient current over the complete output voltage
swing. Analog Devices produces a range of suitable op amps for
such applications. These include the AD843, AD844, AD847,
and AD848 series of monolithic op amps. In very high frequency
applications (80 MHz), the AD8061 is recommended. More
information on line driver buffering circuits is given in the
relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
Z
2
IOR, IOG, IOB
DACs
= 75Ω
Z
S
(SOURCE
TERMINATION)
Z
1
+V
0.1µF
S
4
2
AD848
3
Figure 9. AD848 As an Output Buffer
7
0.1µF
6
–V
S
GAIN (G) = 1 +
75Ω
Z
= 75Ω
0
(CABLE)
Z
Z
ZL = 75Ω
(MONITOR)
1
2
PCB LAYOUT CONSIDERATIONS
The ADV7125 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7125, it is imperative
that great care be given to the PCB layout. Figure 10 shows a
recommended connection diagram for the ADV7125.
The layout should be optimized for lowest noise on the
ADV7125 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of V
and GND pins
AA
to minimize inductive ringing.
It is recommended to use a 4-layer printed circuit board with a
single ground plane. The ground and power planes should
separate the signal trace layer and the solder side layer. Noise
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 10). Optimum
performance is achieved by using 0.1 F and 0.01 F ceramic
capacitors. Individually decouple each V
pin to ground by
AA
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance. It is important to note that while the ADV7125
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) provides EMI
suppression between the switching power supply and the main
PCB. Alternatively, consideration can be given to using a 3terminal voltage regulator.
DIGITAL SIGNAL INTERCONNECT
Isolate the digital signal lines to the ADV7125 as much as
possible from the analog outputs and other analog circuitry.
Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the
ADV7125 should be avoided to minimize noise pickup.
Connect any active pull-up termination resistors for the digital
inputs to the regular PCB power plane (V
analog power plane.
) and not to the
CC
03097-009
Rev. C | Page 13 of 16
ADV7125
G
ANALOG SIGNAL INTERCONNECT
Place the ADV7125 as close as possible to the output connectors,
thus minimizing noise pickup and reflections due to impedance
mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high
frequency power supply rejection.
POWER SUPPLY DECOUPLIN
(0.1µF AND 0.01µF CA PACITOR
FOR EACH V
0.1µF
COMP V
35
R7 TO R0
3TO 10
G7 TO G0
B7 TO B0
VIDEO
DATA
INPUTS
V
AA
41 TO 48
16 TO 23
ADV7125
SYNC
12
BLANK
11
CLOCK
24
PSAVE
38
GND
13, 29,
30
AA
36
V
REF
AD1580
R
37
SET
IOR
IOG
IOB
IOR
IOG
IOB
1, 2, 14, 15,
25, 26, 39, 40
34
32
28
33
31
27
R
SET
530Ω
75Ω 75Ω
COMPLEMENTARY
OUTPUTS
Figure 10. Typical Connection Diagram
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 (doubly
terminated 75 configuration). This termination resistance
should be as close as possible to the ADV7125 to minimize
reflections.
Additional information on PCB design is available in the
AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI, which is available from
Analog Devices at www.analog.com.
GROUP
)
AA
0.1µF
1
2
75Ω
0.01µF
V
AA
V
AA
1kΩ
1µF
COAXIAL CABLE
75Ω
BNC
CONNECTORS
75Ω
75Ω
75Ω
MONITOR (CRT)
03097-010
Rev. C | Page 14 of 16
ADV7125
OUTLINE DIMENSIONS
9.20
48
1
12
13
0.50
BSC
0.60 MAX
37
9.00 SQ
8.80
PIN 1
TOP VIEW
(PINS DO WN)
0.30
0.23
0.18
37
24
0.27
0.22
0.17
36
7.20
7.00 SQ
6.80
25
051706-A
PIN 1
48
INDICAT OR
1
1.45
1.40
1.35
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
0.75
0.60
0.45
0.20
0.09
7°
3.5°
0°
0.08
COPLANARIT Y
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
1.60
MAX
VIEW A
LEAD PITCH
Figure 11. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
7.00
BSC SQ
PIN 1
INDICATO R
0.60 MAX
36
1.00
0.85
0.80
12° MAX
SEATING
PLANE
TOP
VIEW
0.80 MAX
0.65 TYP
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
6.75
BSC SQ
0.20 REF
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
(BOTTOM VIEW)
25
24
EXPOSED
PAD
13
5.50
REF
FOR PROPER CO NNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRI PTIONS
SECTION O F THIS DAT A SHEET.
5.25
5.10 SQ
4.95
12
0.25 MIN
080108-A
Figure 12. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
Rev. C | Page 15 of 16
ADV7125
ORDERING GUIDE
1, 2, 3
Model
ADV7125KSTZ50 −40°C to +85°C 48-Lead LQFP 50 MHz ST-48
ADV7125KSTZ50-REEL −40°C to +85°C 48-Lead LQFP 50 MHz ST-48
ADV7125KSTZ140 −40°C to +85°C 48-Lead LQFP 140 MHz ST-48
ADV7125JSTZ240 0°C to +70°C 48-Lead LQFP 240 MHz ST-48
ADV7125JSTZ330 0°C to +70°C 48-Lead LQFP 330 MHz ST-48
ADV7125WBSTZ170 −40°C to +85°C 48-Lead LQFP 170 MHz ST-48
ADV7125WBSTZ170-RL −40°C to +85°C 48-Lead LQFP 170 MHz ST-48
ADV7125BCPZ170 −40°C to +85°C 48-Lead LFCSP_VQ 170 MHz CP-48-1
ADV7125BCPZ170-RL −40°C to +85°C 48-Lead LFCSP_VQ 170 MHz CP-48-1
ADV7125WBCPZ170 −40°C to +85°C 48-Lead LFCSP_VQ 170 MHz CP-48-1
ADV7125WBCPZ170-RL
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
3
ADV7125JSTZ330 is available in a 3.3 V option only.
AUTOMOTIVE PRODUCTS
The ADV7125W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Temperature Range Package Description Speed Option Package Option
−40°C to +85°C 48-Lead LFCSP_VQ 170 MHz CP-48-1
©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03097-0-2/11(C)
Rev. C | Page 16 of 16
Loading...