ANALOG DEVICES ADV7125 Service Manual

CMOS, 330 MHz

V

FEATURES

330 MSPS throughput rate
Triple 8-bit DACs
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal Reference (1.235 V)
Single-supply +5 V/+3.3 V operation
48-lead LQFP and LFCSP packages
Low power dissipation (30 mW minimum @ 3 V)
Low power standby mode (6 mW typical @ 3 V)
Industrial temperature range (−40°C to +85°C)
Pb-free (lead-free) packages
Qualified for automotive applications

APPLICATIONS

Digital video systems
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
Automotive infotainment units

Triple 8-Bit High Speed Video DAC

ADV7125

FUNCTIONAL BLOCK DIAGRAM

AA

BLANK

SYNC

R7 TO R0

G7 TO G0

B7 TO B0

PSAVE

CLOCK

8

REGISTER

8

REGISTER

8

REGISTER

POWER-DOWN

DATA

DATA

DATA

MODE

8

8

8

R

COMPGND

SET

Figure 1.

DAC

DAC

DAC

BLANK AND

SYNC LOGI C

VOLTAGE

REFERENCE

CIRCUIT

ADV7125

IOR

IOR

IOG

IOG

IOB

IOB

V

REF

03097-001

GENERAL DESCRIPTION

The ADV7125 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three high
speed, 8-bit video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.

The ADV7125 has three separate 8-bit-wide input ports. A
single +5 V/+3.3 V power supply and clock are all that are
required to make the part functional. The ADV7125 has
additional video control signals, composite

SYNC

as well as a power save mode.

ADV is a registered trademark of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

and

BLANK

,

The ADV7125 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7125 is available in
48-lead LQFP and 48-lead LFCSP packages.

PRODUCT HIGHLIGHTS

1. 330 MSPS (3.3 V only) throughput.

2. Guaranteed monotonic to eight bits.

3. Compatible with a wide variety of high resolution color

graphics systems, including RS-343A and RS-170.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2011 Analog Devices, Inc. All rights reserved.

ADV7125

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

5 V Electrical Characteristics...................................................... 3

3.3 V Electrical Characteristics................................................... 4

5 V Timing Specifications ........................................................... 5

3.3 V Timing Specifications........................................................ 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Terminology .................................................................................... 10

Circuit Description and Operation.............................................. 11

Digital Inputs .............................................................................. 11

Clock Input.................................................................................. 11

Video Synchronization and Control........................................ 12

Reference Input........................................................................... 12

DACs............................................................................................ 12

Analog Outputs .......................................................................... 12

Gray Scale Operation................................................................. 13

Video Output Buffers................................................................. 13

PCB Layout Considerations...................................................... 13

Digital Signal Interconnect ....................................................... 13

Analog Signal Interconnect....................................................... 14

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 16

Automotive Products................................................................. 16

REVISION HISTORY

2/11—Rev. B to Rev. C

Change to Table 6 ............................................................................. 8

7/10—Rev. A to Rev. B

Change to Features Section............................................................. 1

Changes to Clock Frequency Parameter, Table 4 ......................... 6

Changes to Figure 2.......................................................................... 6

Changes to Figure 4 and Figure 5................................................. 11

Changes to Table 7.......................................................................... 12

Changes to Endnotes to Ordering Guide .................................... 15

Added Automotive Products Section .......................................... 15

3/09—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Features Section, Applications Section, and General

Description Section .......................................................................... 1

Changes to Figure 3 and Table 6......................................................8

Deleted Ground Planes Section, Power Planes Section, and

Supply Decoupling Section ........................................................... 11

Changes to Figure 5........................................................................ 11

Changes to Table 7, Analog Outputs Section, Figure 6, and

Figure 7 ............................................................................................ 12

Changes to Video Output Buffers Section, PCB Layout

Considerations Section, and Figure 9.......................................... 13

Changes to Analog Signal Interconnect Section and

Figure 10 .......................................................................................... 14

Updated Outline Dimensions....................................................... 15

Changes to Ordering Guide.......................................................... 16

10/02—Revision 0: Initial Version

Rev. C | Page 2 of 16

ADV7125

SPECIFICATIONS

5 V ELECTRICAL CHARACTERISTICS

VAA = 5 V ± 5%, V

Table 1.

Parameter Min Typ Max Unit Test Conditions1

STATIC PERFORMANCE

Resolution (Each DAC) 8 Bits
Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB
Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic

DIGITAL AND CONTROL INPUTS

Input High Voltage, VIH 2 V
Input Low Voltage, V
Input Current, I
PSAVE Pull-Up Current

Input Capacitance, CIN

ANALOG OUTPUTS

Output Current 2.0 26.5 mA

2.0 18.5 mA
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C
Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V
Gain Error2 −5.0 +5.0 % FSR FSR = 18.62 mA

VOLTAGE REFERENCE, EXTERNAL AND

INTERNAL
Reference Range, V

POWER DISSIPATION

Digital Supply Current3 3.4 9 mA f

10.5 15 mA f
18 25 mA f
Analog Supply Current 67 72 mA R
8 mA R
Standby Supply Current4 2.1 5.0 mA

Power Supply Rejection Ratio 0.1 0.5 %/%

1

Temperature range T

2

Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = V

3

Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.

4

These maximum/minimum specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.

= 1.235 V, R

REF

0.8 V

IL

−1 +1 μA VIN = 0.0 V or V

IN

= 560 Ω, CL = 10 pF. All specifications T

SET

20 μA

MIN

to T

,1 unless otherwise noted, T

MAX

10 pF

Green DAC, SYNC
RGB DAC, SYNC

100 kΩ

OUT

10 pF I

OUT

= 0 mA

OUT

1.12 1.235 1.35 V

REF

= 50 MHz

CLK

= 140 MHz

CLK

= 240 MHz

CLK

= 530 Ω

SET

= 4933 Ω

SET

= low, digital, and control inputs at VDD

PSAVE

to T

: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.

MIN

MAX

× K × (0xFFH) × 4 and K = 7.9896.

REF/RSET

DD

= high

= low

J MAX

= 110°C.

Rev. C | Page 3 of 16

ADV7125

3.3 V ELECTRICAL CHARACTERISTICS

VAA = 3.0 V to 3.6 V, V

Table 2.

Parameter2 Min Typ Max Unit Test Conditions1

STATIC PERFORMANCE

Resolution (Each DAC) 8 Bits R
Integral Nonlinearity (BSL) −1 ±0.5 +1 LSB R
Differential Nonlinearity −1 ±0.25 +1 LSB R

DIGITAL AND CONTROL INPUTS

Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current
Input Capacitance, C

ANALOG OUTPUTS

Output Current 2.0 26.5 mA

2.0 18.5 mA
DAC-to-DAC Matching 1.0 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C
Offset Error 0 0 % FSR Tested with DAC output = 0 V
Gain Error3 0 % FSR FSR = 18.62 mA

VOLTAGE REFERENCE, EXTERNAL

Reference Range, V

VOLTAGE REFERENCE, INTERNAL

Voltage Reference, V

POWER DISSIPATION

Digital Supply Current4 2.2 5.0 mA f

6.5 12.0 mA f
11 15 mA f
16 mA f
Analog Supply Current 67 72 mA R
8 mA R
Standby Supply Current 2.1 5.0 mA

Power Supply Rejection Ratio 0.1 0.5 %/%

1

Temperature range T

2

These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.

3

Gain error = ((Measured (FSC)/Ideal (FSC) −1) × 100), where Ideal = V

4

Digital supply is measured with continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.

= 1.235 V, R

REF

10 pF

IN

= 560 Ω, CL = 10 pF. All specifications T

SET

20 μA

MIN

to T

SET

SET

SET

MAX

= 680 Ω
= 680 Ω
= 680 Ω

Green DAC, SYNC
RGB DAC, SYNC

70 kΩ

OUT

10 pF

OUT

1.12 1.235 1.35 V

REF

1.235 V

REF

to T

MIN

: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.

MAX

× K × (0xFFH) × 4 and K = 7.9896.

REF/RSET

= 50 MHz

CLK

= 140 MHz

CLK

= 240 MHz

CLK

= 330 MHz

CLK

= 560 Ω

SET

= 4933 Ω

SET

= low, digital, and control inputs at VDD

PSAVE

,1 unless otherwise noted, T

= high

= low

J MAX

= 110°C.

Rev. C | Page 4 of 16

ADV7125

5 V TIMING SPECIFICATIONS

VAA = 5 V ± 5%,1 V

Table 3.

Parameter3 Symbol Min Typ Max Unit Conditions

ANALOG OUTPUTS

Analog Output Delay t6 5.5 ns
Analog Output Rise/Fall Time4 t7 1.0 ns
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t

CLOCK CONTROL

CLOCK Frequency7 f

0.5 140 MHz 140 MHz grade

0.5 240 MHz 240 MHz grade
Data and Control Setup6 t1 0.5 ns
Data and Control Hold6 t2 1.5 ns
CLOCK Period t3 4.17 ns
CLOCK Pulse Width High6 t4 1.875 ns f
CLOCK Pulse Width Low6 t5 1.875 ns f
CLOCK Pulse Width High6 t4 2.85 ns f
CLOCK Pulse Width Low6 t5 2.85 ns f
CLOCK Pulse Width High t4 8.0 ns f
CLOCK Pulse Width Low t5 8.0 ns f
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time

1

The maximum and minimum specifications are guaranteed over this range.

2

Temperature range T

3

Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.

4

Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.

5

Measured from 50% point of full-scale transition to 2% of final value.

6

Guaranteed by characterization.

7

f

maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.

CLK

= 1.235 V, R

REF

6

to T

MIN

= 560 Ω, CL = 10 pF. All specifications T

SET

1 2 ns

9

0.5 50 MHz 50 MHz grade

CLK

t

10

: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.

MAX

2 10

MIN

to T

,2 unless otherwise noted, T

MAX

ns

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

= 110°C.

J MAX

= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz

Rev. C | Page 5 of 16