Datasheet ADV7125 Datasheet (Analog Devices)

CMOS, 330 MHz

R7–R0

GND

R

SET

IOR

IOR

COMP

ADV7125

V

REF

VOLTA G E

REFERENCE

CIRCUIT

G7–G0

B7–B0

IOG

IOG

IOB

IOB

PSAVE

POWER-DOWN

MODE

BLANK

SYNC

CLOCK

V

AA

DAC

8

DATA

REGISTER

8

DAC

8

DATA

REGISTER

8

DAC

8

DATA

REGISTER

BLANK AND

SYNC LOGIC

8

a

FEATURES
330 MSPS Throughput Rate
Triple 8-Bit DACs
RS-343A/RS-170 Compatible Output
Complementary Outputs
DAC Output Current Range 2 to 26 mA
TTL Compatible Inputs
Internal Reference (1.23 V)
Single-Supply 5 V/3.3 V Operation
48-Lead LQFP Package
Low Power Dissipation (30 mW Min @ 3 V)
Low Power Standby Mode (6 mW Typ @ 3 V)
Industrial Temperature Range (–40°C to +85°C)

APPLICATIONS
Digital Video Systems
High Resolution Color Graphics
Digital Radio Modulation
Image Processing
Instrumentation
Video Signal Reconstruction

Triple 8-Bit High Speed Video DAC

ADV7125

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The ADV®7125 is a triple high speed, digital-to-analog converter
on a single monolithic chip. It consists of three high speed, 8-bit
video DACs with complementary outputs, a standard TTL input
interface, and a high impedance, analog output current source.

The ADV7125 has three separate 8-bit-wide input ports. A single
5 V/3.3 V power supply and clock are all that are required to make
the part functional. The ADV7125 has additional video control
signals, composite SYNC and BLANK, as well as a power-
save mode.

The ADV7125 is fabricated in a 5 V CMOS process. Its mono­lithic CMOS construction ensures greater functionality with
lower power dissipation. The ADV7125 is available in a 48-lead
LQFP package.

ADV is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. 330 MSPS (3.3 V only) throughput

2. Guaranteed monotonic to eight bits

3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADV7125–SPECIFICATIONS

(VAA = 5 V ± 5%, V

5 V ELECTRICAL CHARACTERISTICS

1

, unless otherwise noted, T

T

MAX

Parameter Min Typ Max Unit Test Conditions

= 1.235 V, R

REF

= 560 ⍀, CL = 10 pF. All specifications T

SET

= 110ⴗC.)

J MAX

1

STATIC PERFORMANCE

Resolution (Each DAC) 8 Bits
Integral Nonlinearity (BSL) –1 ± 0.4 +1 LSB
Differential Nonlinearity –1 ± 0.25 +1 LSB Guaranteed Monotonic

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IL

IN

IH

2V

0.8 V

–1 +1 µAV

= 0.0 V or V

IN

DD

PSAVE Pull-Up Current 20 µA
Input Capacitance, C

IN

10 pF

ANALOG OUTPUTS

Output Current 2.0 26.5 mA Green DAC, Sync = High
Output Current 2.0 18.5 mA R/G/B DAC, Sync = Low
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, V
Output Impedance, R

OUT

Output Capacitance, C
Offset Error –0.025 +0.025 % FSR Tested with DAC Output = 0 V
Gain Error

2

OC

OUT

0 1.4 V

100 kΩ
10 pF I

OUT

= 0 mA

–5.0 +5.0 % FSR FSR = 18.62 mA

VOLTAGE REFERENCE (Ext. and Int.)

Reference Range, V

POWER DISSIPATION

Digital Supply Current
Digital Supply Current
Digital Supply Current

REF

3

3

3

Analog Supply Current 67 72 mA R
Analog Supply Current 8 mA R
Standby Supply Current

4

1.12 1.235 1.35 V

3.4 9 mA f

10.5 15 mA f
18 25 mA f

2.1 5.0 mA PSAVE = Low, Digital, and Control

= 50 MHz

CLK

= 140 MHz

CLK

= 240 MHz

CLK

= 530 Ω

SET

= 4933 Ω

SET

Inputs at V

DD

Power Supply Rejection Ratio 0.1 0.5 %/%

NOTES

1

Temperature range T

2

Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V

3

Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and VDD.

4

These max/min specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.

Specifications subject to change without notice.

MIN

to T

: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.

MAX

× K × (FFH) × 4 and K = 7.9896.

REF/RSET

MIN

to

REV. 0–2–

ADV7125

(VAA = 3.0 V to 3.6 V, V

3.3 V ELECTRICAL CHARACTERISTICS

1

T

MIN

2

to T

, unless otherwise noted, T

MAX

Parameter Min Typ Max Unit Test Conditions

= 1.235 V, R

REF

= 560 ⍀, CL = 10 pF. All specifications

SET

= 110ⴗC.)

J MAX

2

STATIC PERFORMANCE

Resolution (Each DAC) 8 Bits R
Integral Nonlinearity (BSL) –1 ± 0.5 +1 LSB R
Differential Nonlinearity –1 ± 0.25 +1 LSB R

= 680 Ω

SET

= 680 Ω

SET

= 680 Ω

SET

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IL

IN

IH

2.0 V

0.8 V

–1 +1 µAV

= 0.0 V or V

IN

DD

PSAVE Pull-Up Current 20 µA
Input Capacitance, C

IN

10 pF

ANALOG OUTPUTS

Output Current 2.0 26.5 mA Green DAC, Sync = High
Output Current 2.0 18.5 mA R/G/B DAC, Sync = Low
DAC-to-DAC Matching 1.0 %
Output Compliance Range, V
Output Impedance, R

OUT

Output Capacitance, C
Offset Error 0 0 % FSR Tested with DAC Output = 0 V
Gain Error

3

OC

OUT

0 1.4 V

70 kΩ
10 pF

0% FSR FSR = 18.62 mA

VOLTAGE REFERENCE (Ext.)

Reference Range, V

REF

1.12 1.235 1.35 V

VOLTAGE REFERENCE (Int.)

Reference Range, V

POWER DISSIPATION

Digital Supply Current
Digital Supply Current
Digital Supply Current
Digital Supply Current

REF

4

4

4

4

Analog Supply Current 67 72 mA R
Analog Supply Current 8 mA R

1.235 V

2.2 5.0 mA f

6.5 12.0 mA f
11 15 mA f
16 mA f

= 50 MHz

CLK

= 140 MHz

CLK

= 240 MHz

CLK

= 330 MHz

CLK

= 560 Ω

SET

= 4933 Ω

SET

Standby Supply Current 2.1 5.0 mA PSAVE = Low, Digital, and Control

Inputs at V

DD

Power Supply Rejection Ratio 0.1 0.5 %/%

NOTES

1

These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.

2

Temperature range T

3

Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V

4

Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and VDD.

Specifications subject to change without notice.

MIN

to T

: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.

MAX

× K × (FFH) × 4 and K = 7.9896.

REF/RSET

REV. 0

–3–

ADV7125

5 V TIMING SPECIFICATIONS

(VAA = 5 V ± 5%2, V

1

unless otherwise noted, T

= 1.235 V, R

REF

J MAX

= 560 ⍀, CL = 10 pF. All specifications T

SET

= 110ⴗC.)

Parameter Min Typ Max Unit Condition

ANALOG OUTPUTS

Analog Output Delay, t
Analog Output Rise/Fall Time, t
Analog Output Transition Time, t
Analog Output Skew, t

CLOCK CONTROL

7

f

CLK

7

f

CLK

7

f

CLK

Data and Control Setup, t
Data and Control Hold, t
Clock Period, t

3

Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Pipeline Delay, t
PSAVE Up Time, t

NOTES

1

Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.

2

These maximum and minimum specifications are guaranteed over this range.

3

Temperature range T

4

Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.

5

Measured from 50% point of full-scale transition to 2% of final value.

6

Guaranteed by characterization.

7

f

max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.

CLK

Specifications subject to change without notice.

MIN

PD

6

6

9

4

7

5

8

0.5 50 MHz 50 MHz Grade

0.5 140 MHz 140 MHz Grade

6

1

6

2

6

4

6

5

6

4

6

5

4

5

6

6

10

to T

: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.

MAX

0.5 240 MHz 240 MHz Grade

0.5 ns

1.5 ns

4.17 ns

1.875 ns f

1.875 ns f

2.85 ns f

2.85 ns f

8.0 ns f

8.0 ns f

1.0 1.0 1.0 Clock Cycles

5.5 ns

1.0 ns
15 ns
12ns

210ns

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz

MIN

to T

MAX

3

,

REV. 0–4–

ADV7125

3.3 V TIMING SPECIFICATIONS

(VAA = 3.0 V to 3.6 V2, V

1

3

to T

, unless otherwise noted, T

MAX

= 1.235 V, R

REF

= 560 ⍀, CL = 10 pF. All specifications T

SET

= 110ⴗC.)

J MAX

Parameter Min Typ Max Unit Condition

ANALOG OUTPUTS

Analog Output Delay, t
Analog Output Rise/Fall Time, t
Analog Output Transition Time, t
Analog Output Skew, t

CLOCK CONTROL

7

f

CLK

7

f

CLK

7

f

CLK

7

f

CLK

Data and Control Setup, t
Data and Control Hold, t
Clock Period, t

3

Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Pipeline Delay, t
PSAVE Up Time, t

NOTES

1

Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for 3.3 V supplies.

2

These maximum and minimum specifications are guaranteed over this range.

3

Temperature range: T

4

Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.

5

Measured from 50% point of full-scale transition to 2% of final value.

6

Guaranteed by characterization.

7

f

max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.

CLK

Specifications subject to change without notice.

PD

MIN

6

10

to T

6

6

9

2

4

6

5

4

6

5

4

6

5

4

5

6

MAX

4

7

5

8

6
1
6

6

6

6

0.2 ns

1.5 ns
3ns

1.4 ns f

1.4 ns f

1.875 ns f

1.875 ns f

2.85 ns f

2.85 ns f

8.0 ns f

8.0 ns f

1.0 1.0 1.0 Clock Cycles

: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.

7.5 ns

1.0 ns
15 ns
12ns

50 MHz 50 MHz Grade
140 MHz 140 MHz Grade
240 MHz 240 MHz Grade
330 MHz 330 MHz Grade

410ns

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

CLK_MAX

= 330 MHz
= 330 MHz
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz

MIN

REV. 0

CLOCK

DIGITAL INPUTS

(R7–R0, G7–G0, B7–B0,

SYNC, BLANK)

ANALOG OUTPUTS

(IOR, IOR, IOG, IOG, IOB, IOB)

NOTES

1. OUTPUT DELAY (
OF FULL-SCALE TRANSITION.

2. OUTPUT RISE/FALL TIME (

3. TRANSITION TIME (
FINAL OUTPUT VALUE.

t

) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT

6

t

8

t

3

t

t

4

5

t

2

DATA

t

1

t

) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.

7

) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE

t

8

t

6

t

7

Figure 1. Timing Diagram

–5–

ADV7125

ABSOLUTE MAXIMUM RATINGS

1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on any Digital Pin . . . . . GND – 0.5 V to V

Ambient Operating Temperature (T
Storage Temperature (T
Junction Temperature (T

) . . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . . . 150°C

J

) . . . . . –40°C to +85°C

A

+ 0.5 V

AA

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Analog output short circuit to any power supply or common can be of an indefinite
duration.

Vapor Phase Soldering (1 Minute) . . . . . . . . . . . . . . . . 220°C

to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

I

OUT

AA

ORDERING GUIDE

Speed Options

Package 50 MHz

1

140 MHz

1

240 MHz

2

330 MHz

Plastic LQFP (ST-48) ADV7125KST50 ADV7125KST140 ADV7125JST240 ADV7125JST330

NOTES

1

Specified for –40°C to +85°C operation.

2

Specified for 0°C to +70°C operation.

3

Available in 3.3 V version only.

PIN CONFIGURATION

2, 3

SET

GND

GND

B6

R

PSAVE

B7

CLOCK

36

35

34

33

32

31

30

29

28

27

26

25

V

REF

COMP

IOR

IOR

IOG

IOG

V

AA

V

AA

IOB

IOB

GND

GND

GND

GND

BLANK

SYNC

R3

R6R5R7

PIN 1
IDENTIFIER

AA

V

GND

R4

ADV7125

TOP VIEW

(Not to Scale)

B0B1B2B3B5

GND

48 4 7 46 45 44 39 38 3743 42 41 40

1

2

3

G0

4

G1

5

G2

6

G3

7

G4

8

G5

9

G6

10

G7

11

12

13 14 15 16 17 18 19 20 21 22 23 24

R2

R0

R1

B4

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7125 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–6–

ADV7125

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Function

1, 2, 14, 15, 25, GND Ground. All GND pins must be connected.
26, 39, 40

3–10, G0–G7, Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge
16–23, B0–B7, of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should
41–48 R0–R7 be connected to either the regular PCB power or ground plane.

11 BLANK Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the

analog outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the
rising edge of CLOCK. While BLANK is a logical zero, the R0–R7, G0–G7, and B0–B7 pixel
inputs are ignored.

12 SYNC Composite Sync Control Input (TTL Compatible). A logical zero on the SYNC input switches

off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does
not override any other control or data input; therefore, it should only be asserted during the
blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not
required on the green channel, the SYNC input should be tied to logical zero.

13, 29, 30 V

24 CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,

27, 31, 33 IOR, IOG, IOB Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These

28, 32, 34 IOR, IOG, IOB Red, Green, and Blue Current Outputs. These high impedance current sources are capable of

35 COMP Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF

36 V

37 R

38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this

AA

REF

SET

Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected.

SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video
system. CLOCK should be driven by a dedicated TTL buffer.

RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly
terminated 75 Ω load. If the complementary outputs are not required, these outputs should be
tied to ground.

directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have
similar output loads whether or not they are all being used.

ceramic capacitor must be connected between COMP and V

Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)

A resistor (R
video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current. The relationship between R
is connected to IOG) is given by:

The relationship between R

The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used,
i.e., SYNC tied permanently low.

pin is active.

) connected between this pin and GND controls the magnitude of the full-scale

SET

and the full-scale output current on IOG (assuming I

SET

RVVIOG mA

Ω

=×

11 445,/

()

SET REF

IOG mA V V R SYNC being asserted

()

IOR IOB mA V V R

,,./

and the full-scale output current on IOR, IOG, and IOB is given by:

SET

=×

11 444 8,. / Ω

=×

()

() ( )

() ()( )

REF SET

7 989 6 Ω

() ()

REF SET

AA

.

SYNC

REV. 0

–7–

ADV7125

TERMINOLOGY
Blanking Level

The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that will shut off the picture
tube, resulting in the blackest possible picture.

Color Video (RGB)

This usually refers to the technique of combining the three
primary colors of red, green, and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.

Sync Signal (SYNC)

The position of the composite video signal that synchronizes the
scanning process.

Grayscale

The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels.

Raster Scan

The most basic method of sweeping a CRT one line at a time to
generate and display images.

Reference Black Level

The maximum negative polarity amplitude of the video signal.

Reference White Level

The maximum positive polarity amplitude of the video signal.

Sync Level

The peak level of the SYNC signal.

Video Signal

The portion of the composite video signal that varies in grayscale
levels between reference white and reference black. Also referred
to as the picture signal, this is the portion that may be visually
observed.

REV. 0–8–

ADV7125

CIRCUIT DESCRIPTION AND OPERATION

The ADV7125 contains three 8-bit DACs, with three input
channels, each containing an 8-bit register. Also integrated on
board the part is a reference amplifier. CRT control functions
BLANK and SYNC are integrated on board the ADV7125.

Digital Inputs

Twenty-four bits of pixel data (color information) R0–R7, G0–G7,
and B0–B7 are latched into the device on the rising edge of
each clock cycle. This data is presented to the three 8-bit DACs
and then converted to three analog (RGB) output waveforms
(See Figure 2).

CLOCK

DIGITAL INPUTS

(R7–R0, G7–G0, B7–B0,

SYNC, BLANK)

ANALOG OUTPUTS

(IOR, IOR, IOB
IOR, IOG, IOB)

DATA

Figure 2. Video Data Input/Output

The ADV7125 has two additional control signals that are latched
to the analog video outputs in a similar fashion. BLANK and
SYNC are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.

The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV7125. The influence of
SYNC and BLANK on the analog video waveform is illustrated.

Table I details the resultant effect on the analog outputs of
BLANK and SYNC.

All these digital inputs are specified to accept TTL logic levels.

Clock Input

The CLOCK input of the ADV7125 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, will be determined by
the on-screen resolution, according to the following equation:

Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/(Retrace Factor)

Horiz Res = Number of Pixels/Line

Vert Res = Number of Lines/Frame

Refresh Rate = Horizontal Scan Rate. This is the rate at which

the screen must be refreshed, typically 60 Hz for a noninterlaced
system or 30 Hz for an interlaced system.

Retrace Factor = Total Blank Time Factor. This takes into account
that the display is blanked for a certain fraction of the total
duration of each frame (e.g., 0.8).

RED, BLUE GREEN

mA V mA V

18.62 0.7 26.67 1.000

100 IRE

008.62 0.3

43 IRE

00

NOTES

1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75⍀ LOAD.
= 1.235V, R

2. V

REF

3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

SET

= 530⍀.

WHITE LEVEL

BLANK LEVEL

SYNC LEVEL

Figure 3. RGB Video Output Waveform

Table I. Video Output Truth Table (R

= 530 Ω, R

SET

LOAD

= 37.5 Ω)

Description IOG (mA) IOG (mA) IOR/IOB IOR/IOB SYNC BLANK DAC Input Data

WHITE LEVEL 26.67 0 18.62 0 1 1 FFH
VIDEO Video + 8.05 18.62 – Video Video 18.62 – Video 1 1 Data
VIDEO to BLANK Video 18.62 – Video Video 18.62 – Video 0 1 Data
BLACK LEVEL 8.05 18.62 0 18.62 1 1 00H
BLACK to BLANK 0 18.62 0 18.62 0 1 00H

BLANK LEVEL 8.05 18.62 0 18.62 1 0 xxH
SYNC LEVEL 0 18.62 0 18.62 0 0 xxH

REV. 0

–9–

ADV7125

Therefore, if we have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate, and a retrace
factor of 0.8, then:

Dot Rate =××1024 1024 60 0 8/.

= 78 6. MHz

The required CLOCK frequency is thus 78.6 MHz.

All video data and control inputs are latched into the ADV7125
on the rising edge of CLOCK, as previously described in the
Digital Inputs section. It is recommended that the CLOCK
input to the ADV7125 be driven by a TTL buffer (e.g., 74F244).

Video Synchronization and Control

The ADV7125 has a single composite sync (SYNC) input con­trol. Many graphics processors and CRT controllers have the
ability to generate horizontal sync (HSYNC), vertical sync
(VSYNC), and composite SYNC.

In a graphics system that does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry enables the generation of a composite SYNC signal.

The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7125, the SYNC input should be tied
to logic low.

Reference Input

The ADV7125 contains an on-board voltage reference. The
V

pin is normally terminated to VAA through a 0.1 µF capaci-

REF

tor. Alternatively, the part could, if required, be overdriven by
an external 1.23 V reference (AD1580).

A resistance, R

connected between the R

SET,

pin and GND

SET

determines the amplitude of the output video level according to
Equations 1 and 2 for the ADV7125:

IOG mA V V R

*

=×

11 444 8,. / Ω

()

IOR IOB mA V V R

,,./

*Applies to the ADV7125 only when SYNC is being used. If SYNC is not being

encoded onto the green channel, Equation 1 will be similar to Equation 2.

=×

()

7 989 6 Ω

Using a variable value of R
the analog output video levels. Use of a fixed 560 Ω R

() ()

REF SET

() ()

REF SET

allows for accurate adjustment of

SET

SET

(1)

(2)

resistor
yields the analog output levels quoted in the specification page.
These values typically correspond to the RS-343A video wave­form values as shown in Figure 3.

DACs

The ADV7125 contains three matched 8-bit DACs. The DACs
are designed using an advanced, high speed, segmented archi­tecture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = “1”) or GND (bit = “0”)
by a sophisticated decoding scheme. As all this circuitry is on
one monolithic device, matching between the three DACs is
optimized. As well as matching, the use of identical current sources
in a monolithic design guarantees monotonicity and low glitch.
The on-board operational amplifier stabilizes the full-scale
output current against temperature and power supply variations.

Analog Outputs

The ADV7125 has three analog outputs, corresponding to the
red, green, and blue video signals.

The red, green, and blue analog outputs of the ADV7125 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 Ω load,
such as a doubly terminated 75 Ω coaxial cable. Figure 4a
shows the required configuration for each of the three RGB
outputs connected into a doubly terminated 75 Ω load. This
arrangement develops RS-343A video output voltage levels
across a 75 Ω monitor.

A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 4b. The output current levels of the
DACs remain unchanged, but the source termination resistance,
Z

, on each of the three DACs is increased from 75 Ω to 150 Ω.

S

IOR, IOG, IOB

DACs

Z

= 75⍀

S

(SOURCE

TERMINATION)



TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs

Z

= 75⍀

O

(CABLE)

Z

= 75⍀

L

(MONITOR)

Figure 4a. Analog Output Termination for RS-343A

IOR, IOG, IOB

DACs

= 150⍀

Z

S

(SOURCE

TERMINATION)



TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs

= 75⍀

Z

O

(CABLE)

= 75⍀

Z

L

(MONITOR)

Figure 4b. Analog Output Termination for RS-170

More detailed information regarding load terminations for various
output configurations, including RS-343A and RS-170, is avail­able in an application note entitled, Video Formats and Required
Load Terminations available from Analog Devices,
(www.analog.com/library/applicationNotes/video/AN205.pdf).

Figure 3 shows the video waveforms associated with the three RGB
outputs driving the doubly terminated 75 Ω load of Figure 4a. As
well as the gray scale levels (black level to white level), the diagram
also shows the contributions of SYNC and BLANK for the
ADV7125. These control inputs add appropriately weighted cur­rents to the analog outputs, producing the specific output level
requirements for video applications. Table I details how the SYNC
and BLANK inputs modify the output levels.

Grayscale Operation

The ADV7125 can be used for standalone, grayscale (mono­chrome) or composite video applications (i.e., only one channel
used for video information). Any one of the three channels, red,
green, or blue, can be used to input the digital video data. The
two unused video data channels should be tied to logical zero.
The unused analog outputs should be terminated with the same
load as that for the used channel. In other words, if the red

REV. 0–10–

ADV7125

channel is used and IOR is terminated with a doubly terminated
75 Ω load (37.5 Ω), IOB and IOG should be terminated with

37.5 Ω resistors (See Figure 5).

37.5⍀

37.5⍀

DOUBLY
TERMINATED
75⍀ LOAD

VIDEO
INPUT

R0
R7

G7

B0
B7

G0

ADV7125

IOR

IOG

IOB

GND

Figure 5. Input and Output Connections for
Standalone Grayscale or Composite Video

Video Output Buffers

The ADV7125 is specified to drive transmission line loads, as
are most monitors rated. The analog output configurations to
drive such loads are described in the Analog Outputs section
and are illustrated in Figure 6. However, in some applications,
it may be required to drive long transmission line cable lengths.
Cable lengths greater than 10 meters can attenuate and distort
high frequency analog output pulses. The inclusion of output
buffers will compensate for some cable distortion. Buffers with
large full power bandwidths and gains between two and four will
be required. These buffers will also need to be able to supply
sufficient current over the complete output voltage swing. Analog
Devices produces a range of suitable op amps for such applica­tions. These include the AD84x series of monolithic op amps.
In very high frequency applications (80 MHz), the AD8061 is
recommended. More information on line driver buffering
circuits is given in the relevant op amp data sheets.

Use of buffer amplifiers also allows implementation of other video
standards besides RS-343A and RS-170. Altering the gain com­ponents of the buffer circuit will result in any desired video level.

Z

2

IOR, IOG, IOB

DACs

= 75⍀

Z

S

(SOURCE

TERMINATION)

+V

AD848

–V

S

Z

1

0.1␮F

S

75⍀

0.1␮F

ZO = 75⍀

(CABLE)

GAIN (G) = 1 +

Z

= 75⍀

L

(MONITOR)

Z

1

Z

2

Figure 6. AD848 As an Output Buffer

PC Board Layout Considerations

The ADV7125 is optimally designed for lowest noise performance,
both radiated and conducted noise. To complement the excel­lent noise performance of the ADV7125, it is imperative that
great care be given to the PC board layout. Figure 7 shows a
recommended connection diagram for the ADV7125.

The layout should be optimized for lowest noise on the ADV7125
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V

and GND pins should by minimized to

AA

minimize inductive ringing.

Ground Planes

The ADV7125 and associated analog circuitry should have a
separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
plane at a single point through a ferrite bead, as illustrated in
Figure 7. This bead should be located as close as possible
(within three inches) to the ADV7125.

The analog ground plane should encompass all ADV7125
ground pins, voltage reference circuitry, power supply bypass
circuitry, the analog output traces, and any output amplifiers.

The regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV7125.

Power Planes

The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV7125 (V

) and all

AA

associated analog circuitry. This power plane should be con­nected to the regular PCB power plane (V

) at a single point

CC

through a ferrite bead, as illustrated in Figure 6. This bead
should be located within three inches of the ADV7125.

The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7125 power pins, voltage reference circuitry,
and any output amplifiers.

The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.

Supply Decoupling

Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 7).

Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of V

should be individually

AA

decoupled to ground. This should be done by placing the capaci­tors as close as possible to the device with the capacitor leads as
short as possible, thus minimizing lead inductance.

It is important to note that while the ADV7125 contains circuitry
to reject power supply noise, this rejection decreases with fre­quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three-terminal voltage regulator.

Digital Signal Interconnect

The digital signal lines to the ADV7125 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines should not overlay the analog
power plane.

Due to the high clock rates used, long clock lines to the ADV7125
should be avoided to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (V

CC

) and

not the analog power plane.

REV. 0

–11–

ADV7125

Analog Signal Interconnect

The ADV7125 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.

The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high fre­quency power supply rejection.

POWER SUPPLY DECOUPLING (0.1␮F AND 0.01␮F
CAPACITOR FOR EACH V

0.1␮F

ANALOG GROUND PLANE

0.1␮F

R

SET

530⍀

75⍀

75⍀

COMPLEMENTARY
OUTPUTS

5V (V

VIDEO

DATA

INPUTS

V

R

V

REF

SET

IOR

IOG

IOB

13, 29,
30

AA

0.1␮F

)

AA

41–48

3–10

16–23

COMP

R7–R0

G7–G0

B7–B0

ADV7125

SYNC

BLANK

CLOCK

PSAVE

GND

IOR

IOG

IOB

1, 2, 14, 15,
25, 26, 39, 40

For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω (doubly termi-
nated 75 Ω configuration). This termination resistance should
be as close as possible to the ADV7125 to minimize reflections.

Additional information on PCB design is available in an application
note entitled Design and Layout of a Video Graphics System for
Reduced EMI. This application note is available from Analog
Devices, publication no. E1309–15–10/89 (www.analog.com/
library/applicationNotes/designTech/AN333.pdf).

GROUP)

AA

0.01␮F

5V (VAA)

COAXIAL CABLE

75⍀

V

AA

10␮F

75⍀

BNC

CONNECTORS

L1

(FERRITE BEAD)

MONITOR

(CRT)

75⍀

75⍀

75⍀

V

CC

33␮F

C03097–0–10/02(0)

1.45

1.40

1.35

0.15

0.05

Figure 7. Typical Connection Diagram

48-Lead Plastic Quad Flatpack [LQFP]

SEATING

PLANE

ROTATED 90ⴗ CCW

VIEW A

0.08 MAX
COPLANARITY

OUTLINE DIMENSIONS

1.4 mm Thick
(ST-48)

Dimensions shown in millimeters

1.60 MAX

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7ⴗ

3.5ⴗ
0ⴗ

COMPLIANT TO JEDEC STANDARDS MS-026BBC

PIN 1

INDICATOR

VIEW A

1

12

0.50
BSC

48

13

9.00 BSC

TOP VIEW

(PINS DOWN)

37

24

36

25

0.27

0.22

0.17

7.00
BSC

PRINTED IN U.S.A.

–12–

REV. 0