Analog Devices ADV7125 Datasheet
CMOS, 330 MHz
R7–R0
GND
R
SET
IOR
IOR
COMP
ADV7125
V
REF
VOLTA G E
REFERENCE
CIRCUIT
G7–G0
B7–B0
IOG
IOG
IOB
IOB
PSAVE
POWER-DOWN
MODE
BLANK
SYNC
CLOCK
V
AA
DAC
8
DATA
REGISTER
8
DAC
8
DATA
REGISTER
8
DAC
8
DATA
REGISTER
BLANK AND
SYNC LOGIC
8
a
FEATURES
330 MSPS Throughput Rate
Triple 8-Bit DACs
RS-343A/RS-170 Compatible Output
Complementary Outputs
DAC Output Current Range 2 to 26 mA
TTL Compatible Inputs
Internal Reference (1.23 V)
Single-Supply 5 V/3.3 V Operation
48-Lead LQFP Package
Low Power Dissipation (30 mW Min @ 3 V)
Low Power Standby Mode (6 mW Typ @ 3 V)
Industrial Temperature Range (–40°C to +85°C)
APPLICATIONS
Digital Video Systems
High Resolution Color Graphics
Digital Radio Modulation
Image Processing
Instrumentation
Video Signal Reconstruction
Triple 8-Bit High Speed Video DAC
ADV7125
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADV®7125 is a triple high speed, digital-to-analog converter
on a single monolithic chip. It consists of three high speed, 8-bit
video DACs with complementary outputs, a standard TTL input
interface, and a high impedance, analog output current source.
The ADV7125 has three separate 8-bit-wide input ports. A single
5 V/3.3 V power supply and clock are all that are required to make
the part functional. The ADV7125 has additional video control
signals, composite SYNC and BLANK, as well as a power-
save mode.
The ADV7125 is fabricated in a 5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with
lower power dissipation. The ADV7125 is available in a 48-lead
LQFP package.
ADV is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. 330 MSPS (3.3 V only) throughput
2. Guaranteed monotonic to eight bits
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
ADV7125–SPECIFICATIONS
(VAA = 5 V ± 5%, V
5 V ELECTRICAL CHARACTERISTICS
1
, unless otherwise noted, T
T
MAX
Parameter Min Typ Max Unit Test Conditions
= 1.235 V, R
REF
= 560 ⍀, CL = 10 pF. All specifications T
SET
= 110ⴗC.)
J MAX
1
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits
Integral Nonlinearity (BSL) –1 ± 0.4 +1 LSB
Differential Nonlinearity –1 ± 0.25 +1 LSB Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
IL
IN
IH
2V
0.8 V
–1 +1 µAV
= 0.0 V or V
IN
DD
PSAVE Pull-Up Current 20 µA
Input Capacitance, C
IN
10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, Sync = High
Output Current 2.0 18.5 mA R/G/B DAC, Sync = Low
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, V
Output Impedance, R
OUT
Output Capacitance, C
Offset Error –0.025 +0.025 % FSR Tested with DAC Output = 0 V
Gain Error
2
OC
OUT
0 1.4 V
100 kΩ
10 pF I
OUT
= 0 mA
–5.0 +5.0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE (Ext. and Int.)
Reference Range, V
POWER DISSIPATION
Digital Supply Current
Digital Supply Current
Digital Supply Current
REF
3
3
3
Analog Supply Current 67 72 mA R
Analog Supply Current 8 mA R
Standby Supply Current
4
1.12 1.235 1.35 V
3.4 9 mA f
10.5 15 mA f
18 25 mA f
2.1 5.0 mA PSAVE = Low, Digital, and Control
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 530 Ω
SET
= 4933 Ω
SET
Inputs at V
DD
Power Supply Rejection Ratio 0.1 0.5 %/%
NOTES
1
Temperature range T
2
Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V
3
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4
These max/min specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.
Specifications subject to change without notice.
MIN
to T
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
MAX
× K × (FFH) × 4 and K = 7.9896.
REF/RSET
MIN
to
REV. 0–2–
ADV7125
(VAA = 3.0 V to 3.6 V, V
3.3 V ELECTRICAL CHARACTERISTICS
1
T
MIN
2
to T
, unless otherwise noted, T
MAX
Parameter Min Typ Max Unit Test Conditions
= 1.235 V, R
REF
= 560 ⍀, CL = 10 pF. All specifications
SET
= 110ⴗC.)
J MAX
2
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits R
Integral Nonlinearity (BSL) –1 ± 0.5 +1 LSB R
Differential Nonlinearity –1 ± 0.25 +1 LSB R
= 680 Ω
SET
= 680 Ω
SET
= 680 Ω
SET
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
IL
IN
IH
2.0 V
0.8 V
–1 +1 µAV
= 0.0 V or V
IN
DD
PSAVE Pull-Up Current 20 µA
Input Capacitance, C
IN
10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, Sync = High
Output Current 2.0 18.5 mA R/G/B DAC, Sync = Low
DAC-to-DAC Matching 1.0 %
Output Compliance Range, V
Output Impedance, R
OUT
Output Capacitance, C
Offset Error 0 0 % FSR Tested with DAC Output = 0 V
Gain Error
3
OC
OUT
0 1.4 V
70 kΩ
10 pF
0% FSR FSR = 18.62 mA
VOLTAGE REFERENCE (Ext.)
Reference Range, V
REF
1.12 1.235 1.35 V
VOLTAGE REFERENCE (Int.)
Reference Range, V
POWER DISSIPATION
Digital Supply Current
Digital Supply Current
Digital Supply Current
Digital Supply Current
REF
4
4
4
4
Analog Supply Current 67 72 mA R
Analog Supply Current 8 mA R
1.235 V
2.2 5.0 mA f
6.5 12.0 mA f
11 15 mA f
16 mA f
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 330 MHz
CLK
= 560 Ω
SET
= 4933 Ω
SET
Standby Supply Current 2.1 5.0 mA PSAVE = Low, Digital, and Control
Inputs at V
DD
Power Supply Rejection Ratio 0.1 0.5 %/%
NOTES
1
These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.
2
Temperature range T
3
Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V
4
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
Specifications subject to change without notice.
MIN
to T
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
MAX
× K × (FFH) × 4 and K = 7.9896.
REF/RSET
REV. 0
–3–
ADV7125
5 V TIMING SPECIFICATIONS
(VAA = 5 V ± 5%2, V
1
unless otherwise noted, T
= 1.235 V, R
REF
J MAX
= 560 ⍀, CL = 10 pF. All specifications T
SET
= 110ⴗC.)
Parameter Min Typ Max Unit Condition
ANALOG OUTPUTS
Analog Output Delay, t
Analog Output Rise/Fall Time, t
Analog Output Transition Time, t
Analog Output Skew, t
CLOCK CONTROL
7
f
CLK
7
f
CLK
7
f
CLK
Data and Control Setup, t
Data and Control Hold, t
Clock Period, t
3
Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Clock Pulsewidth High, t
Clock Pulsewidth Low, t
Pipeline Delay, t
PSAVE Up Time, t
NOTES
1
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range T
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
CLK
Specifications subject to change without notice.
MIN
PD
6
6
9
4
7
5
8
0.5 50 MHz 50 MHz Grade
0.5 140 MHz 140 MHz Grade
6
1
6
2
6
4
6
5
6
4
6
5
4
5
6
6
10
to T
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
MAX
0.5 240 MHz 240 MHz Grade
0.5 ns
1.5 ns
4.17 ns
1.875 ns f
1.875 ns f
2.85 ns f
2.85 ns f
8.0 ns f
8.0 ns f
1.0 1.0 1.0 Clock Cycles
5.5 ns
1.0 ns
15 ns
12ns
210ns
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
MIN
to T
MAX
3
,
REV. 0–4–
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