Analog Devices ADV611 Datasheet

Closed Circuit TV Digital

a

FEATURES
Programmable “Quality Box”
Industrial Temperature Range (ADV612)
Hardware Frame Rate Reduction
100% Bitstream Compatible with the ADV601 and

ADV601LC
Precise Compressed Bit Rate Control
Field Independent Compression
8-Bit Video Interface Supports CCIR-656 and Multi-

plexed Philips Formats
General Purpose 16- or 32-Bit Host Interface with

512 Deep 32-Bit FIFO

PERFORMANCE
Real-Time Compression or Decompression of CCIR-601

to Video:

720 ⴛ 288 @ 50 Fields/Sec — PAL

720 ⴛ 243 @ 60 Fields/Sec — NTSC
Compression Ratios from Visually Loss-Less to 7500:1
Visually Loss-Less Compression At 4:1 on Natural

Images (Typical)

APPLICATIONS
CCTV Cameras and Systems
Time-Lapse Video Tape Recorders
Time-Lapse Video Disk Recorders
Wireless CCTV Cameras
Fiber CCTV Systems

GENERAL DESCRIPTION

The ADV611/ADV612 are low cost, single chip, dedicated func­tion, all-digital-CMOS-VLSI devices capable of supporting
visually loss-less to 7500:1 real-time compression and decom­pression of CCIR-601 digital video at very high image quality

Video Codec

ADV611/ADV612

levels. The chips integrate glueless video and host interfaces
with on-chip SRAM to permit low part count, system level
implementations suitable for a broad range of applications.
The ADV611/ADV612 are 100% bitstream compatible with
the ADV601. The ADV611/ADV612 comes in a 120-lead
LQFP package.

The ADV611/ADV612 are video encoders/decoders optimized
for closed circuit TV (CCTV) applications. With the ADV611/
ADV612, you can define a portion of each video field to be at a
higher quality level relative to the rest of the field. This “quality
box” feature significantly increases compression of less impor­tant background details, while retaining the image’s overall
context. Additionally, the unique subband coding architecture
of the ADV611/ADV612 offer many application-specific
advantages. A review of the General Theory of Operation and
Applying the ADV611/ADV612 sections will help you get the
most use out of the ADV611/ADV612 in any given application.

The ADV611/ADV612 accept component digital video through
the Video Interface and outputs a compressed bitstream though the
Host Interface in Encode Mode. While in Decode Mode, the
ADV611/ADV612 accept compressed bitstream through the Host
Interface and outputs component digital video through the Video
Interface. The host accesses all of the ADV611/ADV612’s control
and status registers using the Host Interface. Figure 2 summarizes
the basic function of the part.

(continued on page 2)

ANALOG

VIDEO

SIGNAL

OR

IMAGE

SENSOR

SIGNAL

ADV7185

DECODER

DIGITIZER

ADV611/

ADV612

ADSP-21xx

Figure 1. Typical Application

SERIAL
OR PARALLEL
BITSTREAM FOR
TRANSMISSION
OR STORAGE

QUALITY BOX CONTROLS
FROM REMOTE SITE

FUNCTIONAL BLOCK DIAGRAM

LOCATION, SIZE AND CONTRAST CONTROL

ADV611/

ADV612

COMPONENT

VIDEO I/O

8

DIGITAL

VIDEO

I/O PORT

QUALITY

BOX

CONTROL

INTERPOLATOR

256K 3 16-BIT DRAM

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ON-CHIP

TRANSFORM

BUFFER

WAVELET

FILTERS,

DECIMATOR &

DRAM

MANAGER

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

SUBBAND STATISTICS

QUANTIZER
& ENTROPY

CODING

BIN WIDTH CONTROL

HOST

I/O PORT

& FIFO

16/32

HOST

ADV611/ADV612

TABLE OF CONTENTS

This data sheet gives an overview of the ADV611/ADV612’s
functionality and provides details on designing the part into a
system. The text of the data sheet is written for an audience with
a general knowledge of designing digital video systems. Where
appropriate, additional sources of reference material are noted
throughout the data sheet.

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

COMPARING THE ADV6xx FAMILY VIDEO CODECS . . . . . 3

INTERNAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . 4

GENERAL THEORY OF OPERATION . . . . . . . . . . . . . . . . . . 4

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

THE WAVELET KERNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

THE PROGRAMMABLE QUANTIZER . . . . . . . . . . . . . . . . . 8

THE RUN LENGTH CODER AND HUFFMAN CODER . . . . . 9

Encoding vs. Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PROGRAMMER’S MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ADV611/ADV612 REGISTER DESCRIPTIONS . . . . . . . . . . 11

VIDEO AREA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . 18

Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Video Formats–CCIR-656 . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DRAM Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Compressed Data-Stream Definition . . . . . . . . . . . . . . . . . . . 24

APPLYING THE ADV611/ADV612 . . . . . . . . . . . . . . . . . . . . 30

Using the ADV611/ADV612 in Computer Applications . . . . . . 30

Using the ADV611/ADV612 in Stand-Alone Applications . . . . 31

Connecting the ADV611/ADV612 to Popular Video

Decoders and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

GETTING THE MOST OUT OF ADV611/ADV612 . . . . . . . 32

How Much Compression Can Be Expected . . . . . . . . . . . . . . 32

Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Software Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Field Rate Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Edge Enhancement and Detection . . . . . . . . . . . . . . . . . . . . . 32

Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

ADV611/ADV612 SPECIFICATIONS . . . . . . . . . . . . . . . . . . 33

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Clock Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

CCIR-656 Video Format Timing . . . . . . . . . . . . . . . . . . . . . . 35

Multiplexed Philips Video Timing . . . . . . . . . . . . . . . . . . . . . 37

Host Interface (Indirect Address, Indirect Register Data,

and Interrupt Mask/Status) Register Timing . . . . . . . . . . . 40

Host Interface (Compressed Data) Register Timing . . . . . . . 42

ADV611/ADV612 LQFP PINOUTS . . . . . . . . . . . . . . . . . . . . 44

ADV611/ADV612 PIN CONFIGURATION . . . . . . . . . . . . . . 45

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

46

Table I. ADV611/ADV612 Field Rates and Sizes

GENERAL DESCRIPTION

VIDEO INTERFACE

DIGITAL VIDEO IN

(ENCODE)

DIGITAL VIDEO
OUT (DECODE)

(Continued from page 1)

ADV611/

ADV612

VIDEO CODEC
CCTV DIGITAL

HOST INTERFACE

COMPRESSED
VIDEO OUT
(ENCODE)

STATUS AND CONTROL

COMPRESSED VIDEO
IN (DECODE)

Figure 2. Functional Block Diagram

The ADV611/ADV612 adheres to international standard
CCIR-601 for studio quality digital video. The codec also sup­ports a range of field sizes and rates providing high performance
in computer, PAL, NTSC, or still image environments. The
ADV611/ADV612 is designed only for real-time interlaced
video; full frames of video are formed and processed as two
independent fields of data. The ADV611/ADV612 supports the
field rates and sizes in Table I. Note that the maximum active
field size is 720 by 288. The maximum pixel rate is 13.50 MHz.

The ADV611/ADV612 has a generic 16-/32-bit host interface
that includes a 512-position, 32-bit wide FIFO for compressed
video. With additional external hardware, the ADV611/ADV612’s
host interface is suitable (when interfaced to other devices) for
moving compressed video over PCI, ISA, SCSI, SONET, 10 Base
T, ARCnet, HDSL, ADSL and a broad range of digital inter­faces. For a full description of the Host Interface, see the Host
Interface section.

The compressed data rate is determined by the input data rate
and the selected compression ratio. The ADV611/ADV612 can
achieve a near constant compressed bit rate by using the current
field statistics in the off-chip bin width calculator on the exter­nal DSP or Host. The process of calculating bin widths on a
DSP or Host can be “adaptive,” optimizing the compressed bit
rate in real time. This feature provides a near constant bit rate
out of the host interface in spite of scene changes or other types
of source material changes that would otherwise create bit rate
burst conditions. For more information on the quantizer, see
the Programmable Quantizer section.

The ADV611/ADV612 typically yields visually loss-less com­pression on natural images at a 4:1 compression ratio. For more
information on compression ratios, see the Getting the Most
Out of the ADV611/ADV612 section. Desired image quality
levels can vary widely in different applications, so it is advisable
to evaluate image quality of known source material at different
compression ratios to find the best compression range for the
application. The subband coding architecture of the ADV611/
ADV612 provides a number of options to stretch compression
performance. These options are outlined in the Applying the
ADV611/ADV612 section.

Active Active Total Total
Standard Region Region Region Region Field Rate Pixel Rate
Name Horizontal Vertical

1

Horizontal Vertical (Hz) (MHz)

2

CCIR-601/525 720 243 858 262.5 59.94 13.50
CCIR-601/625 720 288 864 312.5 50.00 13.50

NOTES

1

The maximum active field size is 720 by 288.

2

The maximum pixel rate is 13.5 MHz.

–2–

REV. 0

ADV611/ADV612

Original Video Image Image after compression/decompression shown

with different box size and position

PROGRAMMABLE

QUALITY BOX

VARIABLE CONTRAST

BACKGROUND

Figure 3.

The ADV611/ADV612 are real-time compression integrated
circuits designed for remote video surveillance or closed circuit
television (CCTV) applications. The most important feature of
these two devices is the “Quality Box.” With this feature the
user can define a box of any size and location within each field
of video that will be compressed at full contrast while the re­mainder outside the box, or background of the image, is com­pressed at a lower level of contrast. The background contrast
level is controlled by the user. The lower the contrast level, the
more the image will be compressed. The objective in a given

Table II. Differences Between the ADV601, ADV601LC, ADV611 and ADV612

application is to adjust the background contrast to a level that
ensures both a recognizable and useful background as well as
the highest possible compression. Figure 3 shows how this qual­ity box appears in final video.

The ADV611/ADV612 is housed in a plastic LQFP package
suitable for cost-sensitive commercial applications.

COMPARING THE ADV6xx FAMILY VIDEO CODECS

The ADV6xx video codecs support a range of interface, pack­age, and compression features. Table II compares these codecs:

ADV601 ADV601LC ADV611 ADV612

Bits per Component 10 8 8 8
DSP Serial Port Yes No No No
Package 160 PQFP 120 LQFP 120 LQFP 120 LQFP
Pin Assignments Unique Unique 98% Similar to ADV601LC 98% Similar to ADV601LC

Temperature Range 0°C to +70°C0°C to +70°C0°C to +70°C –25°C to +85°C

θ

JA

θ

JC

31°C/W 35°C/W 35°C/W 35°C/W

7.5°C/W 5°C/W 5°C/W 5°C/W

Field Rate Reduction Software Software Hardware Hardware
Stall Mode No No Yes Yes
Field Truncation No No Yes Yes
Field Size Register No No Yes Yes
Field Bit Polarity Control No No Yes Yes
Evaluation Board VideoLab VideoPipe CCTVPIPE CCTVPIPE
Target Applications Professional Consumer CCTV Industrial CCTV

REV. 0

–3–

ADV611/ADV612

INTERNAL ARCHITECTURE

The ADV611/ADV612 is composed of eight blocks. Three of
these blocks are interface blocks and five are processing blocks.
The interface blocks are the Digital Video I/O Port, the Host
I/O Port and the external DRAM manager. The processing
blocks are the Wavelet Kernel, the On-Chip Transform Buffer,
the Programmable Quantizer, the Run Length Coder and the
Huffman Coder.

Digital Video I/O Port

Provides a real-time uncompressed video interface to support a
broad range of component digital video formats, including “D1.”

Host I/O Port and FIFO

Carries control, status, and compressed video to and from the
host processor. A 512 position by 32-bit FIFO buffers the com­pressed video stream between the host and the Huffman Coder.

Hardware Field Rate Reduction

In CCTV applications it is often desirable to reduce the field
rate to achieve the highest possible compression. The ADV611/
ADV612 have special hardware to permit this function. It is
possible to set a register on the ADV611/ADV612 during en­code mode that will automatically reduce the field rate. This is a
5-bit register that allows up to 31 fields to be “skipped.”

Stall Mode

It is possible to stall or halt the ADV611/ADV612 at any time
during Encode Mode. This allows the user to feed uncompressed
video data to these parts and to stop indefinitely between fields
or even between pixels. This feature is useful when compressing
video that is not coming into the ADV611/ADV612 at sustained

rates. Stall Mode is enabled by asserting the Stall pin at

V

CLK

any time during encode. Stall mode is enabled on the next clock
cycle after the pin is asserted.

Field Size Reporting

The ADV611/ADV612 have a read-only register that allows the
user to read the field size of the most recently compressed field.
This feature is useful in the feedback loop of a precise bit rate
controller. The data is valid after LCODE (unless an entire
compressed field resides in the internal FIFO).

DRAM Manager

Performs all tasks related to writing, reading and refreshing the
external DRAM. The external host buffer DRAM is used for
reordering and buffering quantizer input and output values.

Wavelet Kernel (Filters, Decimator, and Interpolator)

Gathers statistics on a per-field basis and includes a block of
filters, interpolators and decimators. The kernel calculates for­ward and backward bi-orthogonal, two-dimensional, separable
wavelet transforms on horizontal scanned video data. This block
uses the internal transform buffer when performing wavelet
transforms calculated on an entire image’s data and so elimi­nates any need for extremely fast external memories in an
ADV611/ADV612-based design.

On-Chip Transform Buffer

Provides an internal set of SRAM for use by the wavelet trans­form kernel. Its function is to provide enough delay line storage
to support calculation of separable two dimensional wavelet
transforms for horizontally scanned images.

Programmable Quantizer

Quantizes wavelet coefficients. Quantize controls are calculated
by the external DSP or host processor during encode operations
and de-quantize controls are extracted from the compressed
bitstream during decode. Each quantizer Bin Width is com­puted by the BW calculator software to maintain a constant
compressed bit rate or constant quality bit rate. A Bin Width is
a per-block parameter the quantizer uses when determining the
number of bits to allocate to each block (subband).

Quality Box

The quality box is defined using the Video Area Registers that
are described in the Registers Descriptions section. The back­ground contrast is controlled using Background Contrast Regis­ters that are defined later in this document. It is possible to
control both parameters on a per-field basis during Encode
Mode. This enables the quality box to either move slowly across
the image or to instantaneously jump from one location to the
next.

Run Length Coder

Performs run length coding on zero data and models nonzero
data, encoding or decoding for more efficient Huffman coding.
This data coding is optimized across the subbands and varies
depending on the block being coded.

Huffman Coder

Performs Huffman coder and decoder functions on quantized
run-length coded coefficient values. The Huffman coder/de­coder uses three ROM-coded Huffman tables that provide ex­cellent performance for wavelet transformed video.

Field Truncation

It is possible to set a hard upper limit to the field size of each
field during Encode Mode. The Huffman Coder is able to de­tect if the field size exceeds a preset threshold and then causes
the remaining Mallat block data to be zeroed out, therefore,
truncating the field’s data. The bitstream is truncated in such a
way that all end-of-field markers are inserted. This means that
the compressed bitstream can still be decompressed by any
hardware or software ADV6xx decoder. The only penalty is the
loss of Mallat blocks which, depending on how many are lost,
will degrade the image quality of the truncated field.

GENERAL THEORY OF OPERATION

The ADV611/ADV612 processor’s compression algorithm is
based on the bi-orthogonal (7, 9) wavelet transform, and imple­ments field independent subband coding. Subband coders trans­form two-dimensional spatial video data into spatial frequency
filtered subbands. The quantization and entropy encoding pro­cesses provide the ADV611/ADV612’s data compression.

The wavelet theory, on which the ADV611/ADV612 is based, is
a new mathematical apparatus first explicitly introduced by
Morlet and Grossman in their works on geophysics during the
mid 80s. This theory became very popular in theoretical physics
and applied math. The late 80s and 90s have seen a dramatic
growth in wavelet applications such as signal and image process­ing. For more on wavelet theory by Morlet and Grossman, see

Decomposition of Hardy Functions into Square Integrable Wavelets
of Constant Shape (journal citation listed in References section).

–4–

REV. 0

ADV611/ADV612

ENCODE

PATH

DECODE

PATH

WAVELET

KERNEL

FILTER BANK

ADAPTIVE

QUANTIZER

RUN LENGTH

CODER &

HUFFMAN

CODER

COMPRESSED

DATA

Figure 4. Encode and Decode Paths

References

For more information on the terms, techniques and underlying
principles referred to in this data sheet, you may find the follow­ing reference texts useful. A reference text for general digital
video principles is:

Jack, K., Video Demystified: A Handbook for the Digital Engineer
(High Text Publications, 1993) ISBN 1-878707-09-4

Three reference texts for wavelet transform background infor­mation are:

Vetterli, M., Kovacevic, J., Wavelets And Subband Coding
(Prentice Hall, 1995) ISBN 0-13-097080-8

Benedetto, J., Frazier, M., Wavelets: Mathematics And Applica-
tions (CRC Press, 1994) ISBN 0-8493-8271-8

Grossman, A., Morlet, J., Decomposition of Hardy Functions into
Square Integrable Wavelets of Constant Shape, Siam. J. Math.
Anal., Vol. 15, No. 4, pp 723-736, 1984

THE WAVELET KERNEL

This block contains a set of filters and decimators that work on
the image in both horizontal and vertical directions. Figure 8
illustrates the filter tree structure. The filters apply carefully
chosen wavelet basis functions that better correlate to the broad­band nature of images than the sinusoidal waves used in Dis­crete Cosine Transform (DCT) compression schemes (JPEG,
MPEG, and H261).

An advantage of wavelet-based compression is that the entire
image can be filtered without being broken into sub-blocks as
required in DCT compression schemes. This full image filtering
eliminates the block artifacts seen in DCT compression and
offers more graceful image degradation at high compression
ratios. The availability of full image subband data also makes

image processing, scaling, and a number of other system fea­tures possible with little or no computational overhead.

The resultant filtered image is made up of components of the
original image as is shown in Figure 5 (a modified Mallat Tree).
Note that Figure 5 shows how a component of video would be
filtered, but in multiple component video, luminance and color
components are filtered separately. In Figure 6 and Figure 7 an
actual image and the Mallat Tree (luminance only) equivalent is
shown. It is important to note that while the image has been
filtered or transformed into the frequency domain, no compres­sion has occurred. With the image in its filtered state, it is now
ready for processing in the second block, the quantizer.

Understanding the structure and function of the wavelet filters
and resultant product is the key to obtaining the highest perfor­mance from the ADV611/ADV612. Consider the following
points:

• The data in all blocks (except N) for all components are high
pass filtered. Therefore, the mean pixel value in those blocks
is typically zero and a histogram of the pixel values in these
blocks will contain a single “hump” (Laplacian distribution).

• The data in most blocks is more likely to contain zeros or
strings of zeros than unfiltered image data.

• The human visual system is less sensitive to higher frequency
blocks than low ones.

• Attenuation of the selected blocks in luminance or color com­ponents results in control over sharpness, brightness, contrast
and saturation.

• High quality filtered/decimated images can be extracted/created
without computational overhead.

Through leverage of these key points, the ADV611/ADV612
not only compresses video, but offers a host of application
features. Please see the Applying the ADV611/ADV612 section
for details on getting the most out of the ADV611/ADV612’s
subband coding architecture in different applications.

REV. 0

NML

BLOCK A IS HIGH PASS IN X AND DECIMATED BY TWO.
BLOCK B IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.

BLOCK C IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK D IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.

BLOCK E IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK F IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 32.
BLOCK G IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.

I

K

HJ

G

F

C

E

BD

Figure 5. Modified Mallat Diagram (Block Letters Correspond to Those in Filter Tree)

A

BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK I IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 128.
BLOCK J IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.

BLOCK K IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK L IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
BLOCK M IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK N IS LOW PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.

–5–

ADV611/ADV612

Figure 6. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts)

Figure 7. Modified Mallat Diagram of Image

–6–

REV. 0

ADV611/ADV612

LUMINANCE AND

COLOR

COMPONENTS (EACH

SEPARATELY)

HIGH

PASS IN

X2

BLOCK

A

HIGH

PASS IN

Y

Y

BLOCKBBLOCKCBLOCK

LOW

PASS IN

X

2

X

X2

HIGH

PASS IN

X

X2 X2

LOW

PASS IN

Y

Y

2

PASS IN

LOW

PASS IN

X

HIGH

PASS IN

Y

Y

D

HIGH

Y

Y

2

2

BLOCK

#

LOW

PASS IN

Y

Y

2

HIGH

PASS IN

X

X2 X2

LOW

PASS IN

Y

Y

2

INDICATES
CORRESPONDING
BLOCK LETTER ON
MALLAT DIAGRAM

LOW

PASS IN

X

HIGH

PASS IN

Y

Y

LOW

PASS IN

Y

Y

2

X2

INDICATES DECIMATE BY TWO IN X

Y2

INDICATES DECIMATE BY TWO IN Y

STAGE 1

STAGE 2

STAGE 3

2

BLOCKEBLOCKFBLOCK

G

HIGH

PASS IN

Y

Y

2

BLOCKHBLOCKIBLOCK

Figure 8. Wavelet Filter Tree Structure

HIGH

PASS IN

X

X2 X2

LOW

PASS IN

Y

Y

2

LOW

PASS IN

X

2

2

LOW

PASS IN

Y

Y

HIGH

PASS IN

X

X2 X2

LOW

PASS IN

Y

Y

L

HIGH

PASS IN

Y

Y

J

HIGH

PASS IN

Y

Y

BLOCKKBLOCK

STAGE 4

2

LOW

PASS IN

X

STAGE 5

HIGH

PASS IN

Y

Y

2

BLOCK

M

LOW

PASS IN

Y

Y

2

2

BLOCK

N

REV. 0

–7–

ADV611/ADV612

THE PROGRAMMABLE QUANTIZER

This block quantizes the filtered image based on the response
profile of the human visual system. In general, the human eye
cannot resolve high frequencies in images to the same level of
accuracy as lower frequencies. Through intelligent “quantiza­tion” of information contained within the filtered image, the
ADV611/ADV612 achieves compression without compromising
the visual quality of the image. Figure 9 shows the encode and
decode data formats used by the quantizer.

Figure 10 shows how a typical quantization pattern applies over
Mallat block data. The high frequency blocks receive much
larger quantization (appear darker) than the low frequency
blocks (appear lighter). Looking at this figure, one sees some key
point concerning quantization: (1) quantization relates directly
to frequency in Mallat block data and (2) levels of quantization
range widely from high to low frequency block. (Note that the
fill is based on a log formula.) The relation between actual
ADV611/ADV612 bin width factors and the Mallat block fill
pattern in Figure 10 appears in Table III.

Y COMPONENT

393633

24

30

2127

18

15

6

12

QUANTIZER - ENCODE MODE

WAVELET

DATA

15.0 BIN

NUMBER

9.7

UNSIGNED

6.10

1/BW

1/BW

QUANTIZER - DECODE MODE

SIGNED SIGNED

UNSIGNED

8.8 BW

BW

15.17 DATA

0.5

23.8

DE-QUANTIZED

WAVELET DATA

TRNCSIGNED SIGNED

SAT

Figure 9. Programmable Quantizer Data Flow

0

15.0 BIN
NUMBER

9.7
WAVELET
DATA

403734

31

413835

32

25

2228

191613

26

2329

201714

39

Cb COMPONENT

7

1

410

Cr COMPONENT

8

2

511

LOW

QUANTIZATION OF MALLAT BLOCKS

Figure 10. Typical Quantization of Mallat Data Blocks (Graphed)

–8–

HIGH

REV. 0

ADV611/ADV612

Table III. Typical Quantization of Mallat Data Block Data

1

Mallat Bin Width Reciprocal Bin
Blocks Factors Width Factors

39 0x007F 0x0810
40 0x009A 0x06a6
41 0x009A 0x06a6
36 0x00BE 0x0564
33 0x00BE 0x0564
30 0x00E4 0x047e
34 0x00E6 0x0474
35 0x00E6 0x0474
37 0x00E6 0x0474
38 0x00E6 0x0474
31 0x0114 0x03b6
32 0x0114 0x03b6
27 0x0281 0x0199
24 0x0281 0x0199
21 0x0301 0x0155
25 0x0306 0x0153
26 0x0306 0x0153
28 0x0306 0x0153
29 0x0306 0x0153
22 0x03A1 0x011a
23 0x03A1 0x011a

5 0x0A16 0x0066
18 0x0A16 0x0066
12 0x0C1A 0x0055
20 0x0C2E 0x0054
19 0x0C2E 0x0054
17 0x0C2E 0x0054
16 0x0C2E 0x0054
14 0x0E9D 0x0046
13 0x0E9D 0x0046

6 0x1DDC 0x0022

9 0x1DDC 0x0022

3 0x23D5 0x001d
11 0x2410 0x001c
10 0x2410 0x001c

8 0x2410 0x001c

7 0x2410 0x001c

5 0x2B46 0x0018

4 0x2B46 0x0018

0 0xA417 0x0006

2 0xC62B 0x0005

1 0xC62B 0x0005

NOTE

1

The Mallat block numbers, Bin Width factors, and Reciprocal Bin Width
factors in Table III correspond to the shading per-cent fill) of Mallat blocks in
Figure 10.

THE RUN LENGTH CODER AND HUFFMAN CODER

This block contains two types of entropy coders that achieve
mathematically loss-less compression: run-length and Huffman.
The run-length coder looks for long strings of zeros and replaces
them with short hand symbols. Table IV illustrates an example
of how compression is possible.

The Huffman coder is a digital compressor/decompressor that
can be used for compressing any type of digital data. Essentially,
an ideal Huffman coder creates a table of the most commonly
occurring code sequences (typically zero and small values near
zero) and then replaces those codes with some shorthand. The
ADV611/ADV612 employs three fixed Huffman tables; it does
not create tables.

The filters and the quantizer increase the number of zeros and
strings of zeros, which improves the performance of the entropy
coders. The higher the selected compression ratio, the more
zeros and small value sequences the quantizer needs to generate.
The transformed image in Figure 7 shows that the filter bank
concentrates zeros and small values in the higher frequency
blocks.

Encoding vs. Decoding

The decoding of compressed video follows the exact path as
encoding but in reverse order. There is no need to calculate bin
widths during decode because the bin width is stored in the
compressed image during encode.

PROGRAMMER’S MODEL

A host device configures the ADV611/ADV612 using the Host
I/O Port. The host reads from status registers and writes to
control registers through the Host I/O Port.

Table V. Register Description Conventions

Register Name

Register Type (Indirect or Direct, Read or Write) and Address
Register Functional Description Text
Bit [#] or Bit or Bit Field Name and Usage Description
Bit Range
[High:Low]

0 Action or Indication When Bit Is Cleared (Equals 0)
1 Action or Indication When Bit Is Set (Equals 1)

REV. 0

Table IV. Uncompressed Versus Compressed Data Using Run-Length Coding

0000000000000000000000000000000000000000000000000000000000000000000(uncompressed)

57 Zeros (Compressed)

–9–

ADV611/ADV612

REGISTER

ADDRESS

0x0

0x4

0x8

0xC

INDIRECT (INTERNALLY INDEXED) REGISTERS
{ACCESS THESE REGISTERS THROUGH THE

INDIRECT REGISTER ADDRESS AND
INDIRECT REGISTER DATA REGISTERS}

*NOTE:
YOU MUST WRITE 0X0880 TO THE MODE
CONTROL REGISTER ON CHIP RESET TO
SELECT THE CORRECT PIXEL MODE

BYTE 3 BYTE 2 BYTE 1

DIRECT (EXTERNALLY ACCESSIBLE) REGISTERS

RESERVED

RESERVED

RESET

BYTE 0

INDIRECT REGISTER ADDRESS

INDIRECT REGISTER DATA

COMPRESSED DATA

INTERRUPT MASK / STATUS RESERVED

0x0

RESERVED0x1 0x88

0x2 0x000

0x3 0x3FF

0x4 0x000

0x5 0x3FF

0x6

0x7 – 0x7F

0x8

0x9

0x80 – 0xA9

0xAA

MODE CONTROL*

FIFO CONTROL

HSTART

HEND

VSTART

VEND

RESERVED

RESERVED

COMPRESSED FIELD SIZE LIMIT

MODE CONTROL REGISTER 2

SUM OF SQUARES [0 – 41]

SUM OF LUMA

VALUE

UNDEF

UNDEF

UNDEF

0x00

0x0980

UNDEF

UNDEF

0xFFFF

0x7

UNDEF

UNDEF

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0x100

0x101

0x152

0x153

SUM OF Cb

SUM OF Cr

MIN LUMA

MAX LUMA

MIN Cb

MAX Cb

MIN Cr

MAX Cr

COMPRESSED FIELD SIZE HI

COMPRESSED FIELD SIZE LO

RBW0

BW0

RBW41

BW41

Figure 11. Map of ADV611/ADV612 Direct and Indirect Registers

UNDEF

UNDEF

UNDEF

UNDEF

UNDEF

UNDEF

UNDEF

UNDEF

0x0

0x0

UNDEF

UNDEF

UNDEF

UNDEF

–10–

REV. 0

ADV611/ADV612

ADV611/ADV612 REGISTER DESCRIPTIONS

Indirect Address Register

Direct (Write) Register Byte Offset 0x00.

This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All
indirect write registers are 16 bits wide. The address in this register is auto-incremented on each subsequent access of the indirect
data register. This capability enhances I/O performance during modes of operation where the host is calculating Bin Width controls.

[15:0] Indirect Address Register, IAR[15:0]. Holds a 16-bit value (index) that selects the indirect register to read or write through

the indirect data register (undefined at reset).

[31:16] Reserved (undefined read/write zero)

Indirect Register Data

Direct (Read/Write) Register Byte Offset 0x04

This register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register.

[15:0] Indirect Register Data, IRD[15:0]. A 16-bit value read or written to the indexed indirect register. Undefined at reset.

[31:16] Reserved (undefined read/write zero)

Compressed Data Register

Direct (Read/Write) Register Byte Offset 0x08

This register holds a 32-bit sequence from the compressed video bitstream. This register is buffered by a 512 position, 32-bit FIFO.
For Word (16-bit) accesses, access Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3) for correct auto-increment. For a
description of the data sequence, see the Compressed Data Stream Definition section.

[31:0] Compressed Data Register, CDR[31:0]. 32-bit value containing compressed video stream data. At reset, contents undefined.

Interrupt Mask / Status Register

Direct (Read/Write) Register Byte Offset 0x0C
This 16-bit register contains interrupt mask and status bits that control the state of the ADV611/ADV612’s HIRQ pin. With the

seven mask bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR), select the con­ditions that are ORed together to determine the output of the HIRQ pin.

Six of the status bits (LCODE, STATSR, FIFOSTP, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are
sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the
condition coming true, they cannot be read or tested for stable level true conditions multiple times.

The FIFOSRQ bit is not sticky. This bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by
using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers.

[0] CCIR-656 Error in CCIR-656 data stream, CCIRER. This read only status bit indicates the following:

0 No CCIR-656 Error condition, reset value
1 Unrecoverable error in CCIR-656 data stream (missing sync codes)

[1] Statistics Ready, STATSR. This read only status bit indicates the following:

0 No Statistics Ready condition, reset value (STATS_R pin LO)
1 Statistics Ready for BW calculator (STATS_R pin HI)

[2] Last Code Read, LCODE. This read only status bit indicates the last compressed data word for field will be

retrieved from the FIFO on the next read from the host bus.

0 No Last Code condition, reset value (LCODE pin LO)
1 Next read retrieves last word for field in FIFO (LCODE pin HI)

[3] FIFO Service Request, FIFOSRQ. This read only status bit indicates the following:

0 No FIFO Service Request condition, reset value (FIFO_SRQ pin LO)
1 FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)

[4] FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV611/ADV612’s

compressed data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted
until MERR indicates that the DRAM has also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:

0 No FIFO Error condition, reset value (FIFO_ERR pin LO)
1 FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)

REV. 0

–11–

ADV611/ADV612

[5] FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode. In

decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when FIFOSTP
is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely be performed.
This status bit indicates the following:

0 No FIFO Stop condition, reset value (FIFO_STP pin LO)
1 FIFO empty (encode) or full (decode) (FIFO_STP pin HI)

[6] Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can

be caused by a defective DRAM, the inability of the Host to keep up with the ADV611/ADV612 compressed data stream, or bit
errors in the data stream. Note that the ADV611/ADV612 recovers from this condition without host intervention.

0 No memory error condition, reset value
1 Memory error

[7] Reserved (always read/write zero)

[8] Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:

0 Disable CCIR-656 data error interrupt, reset value
1 Enable interrupt on error in CCIR-656 data

[9] Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:

0 Disable Statistics Ready interrupt, reset value
1 Enable interrupt on Statistics Ready

[10] Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:

0 Disable Last Code Read interrupt, reset value
1 Enable interrupt on Last Code Read from FIFO

[11] Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:

0 Disable FIFO Service Request interrupt, reset value
1 Enable interrupt on FIFO Service Request

[12] Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:

0 Disable FIFO Stop interrupt, reset value
1 Enable interrupt on FIFO Stop

[13] Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:

0 Disable FIFO Error interrupt, reset value
1 Enable interrupt on FIFO Error

[14] Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:

0 Disable memory error interrupt, reset value
1 Enable interrupt on memory error

[15] Reserved (always read/write zero)

Mode Control Register

Indirect (Read/Write) Register Index 0x00

This register holds configuration data for the ADV611/ADV612’s video interface format and controls several other video interface
features. For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:

[3:0] Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all

other values are reserved):

0x0 CCIR-656, reset value
0x2 MLTPX (Philips)

[4] VCLK Output Divided by two, VCLK2. This bit controls the following:

0 Do not divide VCLK output (VCLKO = VCLK), reset value
1 Divide VCLK output by two (VCLKO = VCLK/2)

[5] Video Interface Master/Slave Mode Select, M/S. This bit selects the following:

0 Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value
1 Master mode video interface (ADV611/ADV612 controls video timing, HSYNC-VSYNC are outputs)

[6] Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:

0 525 mode video interface, reset value
1 625 mode video interface

–12–

REV. 0

ADV611/ADV612

[7] Video Interface Encode/Decode Mode Select, E/D. This bit selects the following:

0 Decode mode video interface (compressed-to-raw)
1 Encode mode video interface (raw-to-compressed), reset value

[8] Reserved (always write zero)

[9] Video Interface Bipolar/Unipolar Color Component Select, BUC. This bit selects the following:

0 Bipolar color component mode video interface, reset value
1 Unipolar color component mode video interface

[10] Reserved (always write zero)

[11] Video Interface Software Reset, SWR. This bit has the following effects on ADV611/ADV612 operations:

0 Normal operation
1 Software Reset. This bit is set on hardware reset and must be cleared before the ADV611/ADV612 can begin processing.

(reset value)
When this bit is set during encode, the ADV611/ADV612 completes processing the current field then suspends operation

until the SWR bit is cleared. When this bit is set during decode, the ADV611/ADV612 suspends operation immediately and
does not resume operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode
register is changed.

[12] HSYNC pin Polarity, PHSYNC. This bit has the following effects on ADV611/ADV612 operations:

0 HSYNC is HI during blanking, reset value
1 HSYNC is LO during blanking (HI during active)

[13] HIRQ pin Polarity, PHIRQ. This bit has the following effects on ADV611/ADV612 operations:

0 HIRQ is active LO, reset value
1 HIRQ is active HI

[14] Quality Box Enable, QBE. This bit has the following effect on ADV611/ADV612 operations:

0 Video area registers (HSTART, HEND, VSTART, VEND). Crop video area, setting cropped area to all 0

quantizations (ADV601 mode), reset value

1 Video area registers (HSTART, HEND, VSTART, VEND). Select Quality Box. Quantization of the area outside

the box is selected with the background Contrast Control register. See the video area registers for more information
on the Quality Box.

[15] Video Stall Enable, VSE. This bit has the following effect on ADV611/ADV612 operations:

0 Video Stall disabled (ADV601 mode), reset value
1 Video Stall enabled.

FIFO Control Register

Indirect (Read/Write) Register Index 0x01
This register holds the service-request settings for the ADV611/ADV612’s host interface FIFO, causing interrupts for the “nearly full” and
“nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by 32
(decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV611/ADV612
uses these settings to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin).

[3:0] Encode Service Level, ESL[3:0]. The value in this field determines when the FIFO is considered nearly full on encode; a condi-

tion that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is
512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.

ESL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI during encode)
0001 FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)
1000 FIFO is 1/2 full, reset value
1111 FIFO has only 32 positions empty (480 positions filled)

[7:4] Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a

condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO
is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.

DSL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI)
0001 FIFO has only 32 positions filled (480 positions empty)
1000 FIFO is 1/2 empty, reset value
1111 FIFO has only 32 positions empty (FIFO_SRQ when >= 32 positions are empty)

[15:8] Reserved (always write zero)

REV. 0

–13–

ADV611/ADV612

VIDEO AREA REGISTERS

When the quality box is disabled (Mode Control register, Bit 14 = 0), the area defined by the HSTART, HEND, VSTART and
VEND registers is the active area that the wavelet kernel processes. Video data outside the active video area is set to minimum lumi­nance and zero chrominance (black) by the ADV611/ADV612. These registers allow cropping of the input video during compression
(encode only), but do not change the image size. Figure 12 shows how the video area registers work together.

Some comments on how these registers work are as follows:

• The vertical numbers include the blanking areas of the video.

Specifically, a VSTART value of 21 will include the first line
of active video, and the first pixel in a line corresponds to a
value HSTART of 0 (for NTSC regular).

Note that the vertical coordinates start with 1, whereas the
horizontal coordinates start with 0.

• The default cropping mode is set for the entire frame. Specifi­cally, Field 2 starts at a VSTART value of 283 (for NTSC
regular).

When the quality box is enabled (Mode Control register, Bit 14
= 1), the area defined by the HSTART, HEND, VSTART and
VEND registers is the quality box area, and the rest of the video
area is attenuated according to the value in the background
Contrast Control register (Indirect Register Index 0x9). In this
mode, the range of values for VSTART and VEND is 1–243 for
NTSC and 1–288 for PAL. Also note that VSTART and VEND
do not need to be updated for each field in this mode.

VSTART

VEND

Figure 12. Video Area and Video Area Registers

HSTART HEND

0, 0

ZERO

ZERO

ZERO

ZERO

ACTIVE VIDEO AREA

ZERO

MAX FOR SELECTED VIDEO MODE

ZERO

ZERO

ZERO

X, Y

HSTART Register

Indirect (Write Only) Register Index 0x02

This register holds the setting for the horizontal start of the ADV611/ADV612’s active video area or quality box. The value in this
register is usually set to zero, but in cases where you wish to crop incoming video it is possible to do so by changing HST.

[9:0] Horizontal Start, HST[9:0]. 10-bit value defining the start of the active video region. (0 at reset)
[15:10] Reserved (always write zero)

HEND Register

Indirect (Write Only) Register Index 0x03

This register holds the setting for the horizontal end of the ADV611/ADV612’s active video area or quality box. If the value is larger
than the max size of the selected video mode, the ADV611/ADV612 uses the max size of the selected mode for HEND.

[9:0] Horizontal End, HEN[9:0]. 10-bit value defining the end of the active video region. (0x3FF at reset this value is larger

than the max size of the largest video mode)

[15:10] Reserved (always write zero)

VSTART Register

Indirect (Write Only) Register Index 0x04

This register holds the setting for the vertical start of the ADV611/ADV612’s active video area or quality box. The value in this
register is usually set to zero unless you want to crop the active video.

To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for
each field. The VSTART and VEND contents must be updated on each field unless the quality box is enabled. Perform this updating as
part of the field-by-field BW register update process. To perform this dynamic update correctly, the update software must keep track of
which field is being processed next.

[9:0] Vertical Start, VST[9:0]. 10-bit value defining the starting line of the active video region, with line numbers from 1-to-625

in PAL and 1-to-525 in NTSC. (0 at reset)

[15:10] Reserved (always write zero)

VEND Register

Indirect (Write Only) Register Index 0x05

This register holds the setting for the vertical end of the ADV611/ADV612’s active video area or quality box. If the value is larger
than the max size of the selected video mode, the ADV611/ADV612 uses the max size of the selected mode for VEND.

–14–

REV. 0