Datasheet ADV3205 Datasheet (ANALOG DEVICES)

60 MHz, G = +2, 16 × 16

Data Sheet

FEATURES

16 × 16 high speed nonblocking switch array
Serial or parallel programming of switch array
Serial data out allows daisy-chaining control of multiple

16 × 16 devices to create larger switch arrays

Complete solution

Buffered inputs
16 output amplifiers
Operates on ±5 V supplies
Low supply current of 50 mA

Excellent video performance, V

−3 dB bandwidth: 60 MHz

0.1 dB gain flatness: 10 MHz

0.1% differential gain error (R

0.1° differential phase error (R
Low all hostile crosstalk: −67 dB at 5 MHz
Output disable allows connection of multiple devices

without loading the output bus

RESET

pin allows disabling of all outputs

Power-on reset capability with capacitor to ground

100-lead LQFP (14 mm × 14 mm)

APPLICATIONS

CCTV surveillance
Video routers (NTSC, PAL, S-Video, SECAM)
Video conferencing

= ±5 V

S

= 1 kΩ)

L

= 1 kΩ)

L

Buffered Analog Crosspoint Switch

ADV3205

FUNCTIONAL BLOCK DIAGRAM

SER/PAR

CLK

DATA IN

UPDATE

CE

RESET

ADV3205

16 INPUTS

D0 D1 D2 D3

80-BIT SHIFT REGISTER

WITH 5-BIT

PARALLEL L OADING

80

PARALLEL L ATCH

80

DECODE

16 × 5:16 DECODERS

256

SWITCH
MATRIX

Figure 1.

D4

OUTPUT
BUFFER

G = +2

SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO “OFF”

16

ENABLE/DIS ABLE

A0

A1

A2
A3

DATA
OUT

16
OUTPUTS

10342-001

GENERAL DESCRIPTION

The ADV3205 is a fully buffered crosspoint switch matrix that
operates on ±5 V, making it ideal for video applications. It offers
a −3 dB signal bandwidth of 60 MHz and channel switch times of
less than 60 ns with 0.1% settling. The ADV3205 has excellent
crosstalk performance, and ground/power pins surround all inputs
and outputs to provide extra shielding required for the most
demanding applications. The differential gain and differential
phase of better than 0.1% and 0.1°, respectively, along with 0.1 dB
flatness out to 10 MHz, make the ADV3205 an excellent choice
for many video applications.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The ADV3205 includes 16 independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs.
The ADV3205 has a gain of +2 and operates on voltage supplies
of ±5 V while consuming only 34 mA of current. Channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control, allowing updating of an individual output without
reprogramming the entire array.

The ADV3205 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADV3205 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics (Serial Mode) ....................................... 4

Timing Characteristics (Parallel Mode).................................... 5

Absolute Maximum Ratings............................................................ 6

Power Dissipation......................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Truth Table and Logic Diagram ................................................. 9

Typical Performance Characteristics ........................................... 10

Circuit Diagrams ............................................................................ 13

Theory of Operation ...................................................................... 14

Short-Circuit Output Conditions............................................. 14

Applications Information.............................................................. 15

Serial Programming................................................................... 15

Parallel Programming................................................................ 15

Power-On Reset.......................................................................... 16

Managing Video Signals............................................................ 16

Creating Larger Crosspoint Arrays.......................................... 16

Multichannel Video ................................................................... 17

Crosstalk...................................................................................... 17

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

12/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

Data Sheet ADV3205

SPECIFICATIONS

TA = 25°C, VS = ±5 V, RL = 150 , unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V

V
Gain Flatness 0.1 dB, V
Propagation Delay V
Settling Time 0.1%, 2 V output step 23 ns
Slew Rate 2 V output step 100 V/μs

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC, RL = 1 kΩ 0.1 %
Differential Phase Error NTSC, RL = 1 kΩ 0.1 Degrees
Crosstalk, All Hostile f = 5 MHz −67 dB
Off Isolation f = 5 MHz, one channel −100 dB
Input Voltage Noise 0.1 MHz to 10 MHz 12 nV/√Hz

DC PERFORMANCE

Gain Error 0.5 %
Gain Matching Channel-to-channel 0.7 %
Gain Temperature Coefficient 20 ppm/°C

OUTPUT CHARACTERISTICS

Output Resistance Enabled 0.3 Ω
Disabled 3.4 4 kΩ
Output Capacitance Disabled 5 pF
Output Voltage Swing No Load ±3.2 ±3.5 V
I
Short-Circuit Current 55 mA

INPUT CHARACTERISTICS

Input Offset Voltage All configurations ±5 ±10 mV
Temperature coefficient 10 μV/°C
Input Voltage Range No load ±1.5 V
Input Capacitance Any switch configuration 4 pF
Input Resistance Any number of connected outputs 50 MΩ
Input Bias Current Any number of enabled inputs ±1 μA

SWITCHING CHARACTERISTICS

Enable On Time 80 ns
Switching Time, 2 V Step 50% update to 1% settling 50 ns
Switching Transient (Glitch) 20 mV p-p

POWER SUPPLIES

Supply Current AVCC outputs enabled, no load 45 50 mA
AVCC outputs disabled 31 35 mA
AVEE outputs enabled, no load 45 50 mA
AVEE outputs disabled 31 35 mA
DVCC outputs enabled, no load 8 13 mA
DYNAMIC PERFORMANCE

Supply Voltage Range AVCC 4.5 5.5 V

AVEE −5.5 −4.5 V

DVCC 4.5 5.5 V

PSRR DC 75 80 dB

f = 100 kHz 60 dB

f = 1 MHz 40 dB

= 200 mV p-p 41 60 MHz

OUT

= 2 V p-p 25 MHz

OUT

= 200 mV p-p 10 MHz

OUT

= 2 V p-p 20 ns

OUT

= 20 mA ±2.7 ±3 V

OUT

Rev. 0 | Page 3 of 20

ADV3205 Data Sheet

T

Parameter Test Conditions/Comments Min Typ Max Unit

OPERATING TEMPERATURE RANGE

Temperature Range Operating (still air) 0 70 °C
θJA Operating (still air) 40 °C/W

TIMING CHARACTERISTICS (SERIAL MODE)

Table 2.

Limit
Parameter Symbol Min Typ Max Unit

Serial Data Setup Time t1 20 ns
CLK Pulse Width t2 100 ns
Serial Data Hold Time t3 20 ns
CLK Pulse Separation, Serial Mode t4 100 ns

t

CLK-to-UPDATE Delay
UPDATE Pulse Width
CLK-to-DATA OUT Valid, Serial Mode t7 200 ns
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode 16 μs
CLK, UPDATE Rise and Fall Times
RESET Time

CLK

DATA IN

1 = LATCHED

UPDATE

0 = TRANSPARE N

t

1

0

1

0

t1t

OUT07 (D4)

2

3

t

7

t

4

OUT07 (D3)

0 ns

5

t

50 ns

6

50 ns

100 ns
200 ns

LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE

OUT00 (D0)

t

5

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURI NG LOW LEVEL

t

6

DATA OUT

Figure 2. Timing Diagram, Serial Mode

10342-002

Table 3. Logic Levels

VIH VIL VOH VOL IIH IIL IOH IOL

RESET, SER/PAR
CLK, DATA IN, CE
UPDATE

,

, SER/PAR

RESET
CLK, DATA IN, CE
UPDATE

,

DATA OUT DATA OUT

, SER/PAR

RESET
CLK, DATA IN, CE
UPDATE

RESET

,

CLK, DATA IN, CE
UPDATE

, SER/PAR

,

DATA OUT DATA OUT

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 μA max −400 μA min −400 μA max 3.0 mA min

Rev. 0 | Page 4 of 20

Data Sheet ADV3205

0

T

TIMING CHARACTERISTICS (PARALLEL MODE)

Table 4.

Limit
Parameter Symbol Min Max Unit

Parallel Data Setup Time t1d 20 ns
Address Setup Time t1a 20 ns
CLK Enable Width t2 100 ns
Parallel Data Hold Time t3d 20 ns
Address Hold Time t3a 20 ns
CLK Pulse Separation t4 100 ns

t

CLK-to-UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time

1

CLK

0

1

A0 TO A3

0

1

D0 TO D4

0

1 = LATCHED

UPDATE

= TRANSPAREN

t

2

t

1a

t

1d

t

3a

t

3d

Figure 3. Timing Diagram, Parallel Mode

t

4

0 ns

5

t

50 ns

6

50 ns
100 ns
200 ns

t

t

5

6

10342-003

Table 5. Logic Levels

VIH VIL VOH VOL IIH IIL I

RESET, SER/PAR
CLK, D0, D1, D2,

D3, D4, A0, A1, A2,
A3, CE, UPDATE

RESET, SER/PAR
CLK, D0, D1, D2,

D3, D4, A0, A1, A2,
A3, CE, UPDATE

DATA OUT DATA OUT

RESET, SER/PAR
CLK, D0, D1, D2,

D3, D4, A0, A1, A2,
A3, CE, UPDATE

RESET, SER/PAR
CLK, D0, D1, D2,

D3, D4, A0, A1, A2,
A3, CE, UPDATE

I

OH

OL

DATA OUT DATA OUT

2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 μA max −400 μA min −400 μA max 3.0 mA min

Rev. 0 | Page 5 of 20

ADV3205 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Supply Voltage (AVCC to AVEE) 12 V
Digital Supply Voltage (DVCC to DGND) 6 V
Ground Potential Difference (AGND to

±0.5 V

DGND)
Internal Power Dissipation
Analog Input Voltage

1

2

3.1 W

Maintain linear output
Digital Input Voltage DVCC
Output Voltage (Disabled Output)

(AV

(AV

CC

EE

− 1.5 V) to

+ 1.5 V)
Output Short-Circuit Duration Momentary
Storage Temperature Range −65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C

1

Specification is for device in free air (TA = 25°C):

100-lead plastic LQFP: θJA = 40°C/W.

2

To avoid differential input breakdown, in no case should one-half the output

voltage (1/2 V
differential. See the output voltage swing parameter in Table 1 for the linear
output range.

) and any input voltage be greater than 10 V potential

OUT

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

POWER DISSIPATION

Packaged in a 100-lead LQFP, the ADV3205 junction-to-ambient
thermal impedance (θ
the maximum allowed junction temperature of the plastic
encapsulated die should not exceed 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.

The maximum ADV3205 power dissipation occurs when all
outputs are enabled and driving loads. Supply current increases
approximately linearly with the number of outputs that are enabled.
Refer to the Theory of Operation section for more details regarding
power dissipation calculations. Figure 4 indicates the maximum

ADV3205 power dissipation as a function of ambient temperature.

4.0

3.5

3.0

MAXIMUM POWER (W)

2.5

) is 40°C/W. For long-term reliability,

JA

TJ = 150°C

2.0

Figure 4. Maximum Power Dissipation vs. Ambient Temperature

100 20304050607

AMBIENT TEMPERATURE (°C)

10342-004

0

ESD CAUTION

Rev. 0 | Page 6 of 20

Data Sheet ADV3205

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DV

DGND

AGND

IN08

AGND

IN09

AGND

IN10

AGND

IN11

AGND

IN12

AGND

IN13

AGND

IN14

AGND

IN15

AGND

AV

AV

AVCC15

OUT15

AVEE14/15

OUT14

RESETCEDATA OUT

100

1

CC

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

EE

21

CC

22

23

24

25

PIN 1

CLK

DATA IN

UPDATE

SER/PARNCNCNCNCNCNCNCNCNCA0A1A2A3D0D1D2D3D4

99

98

95

93

97

96

92

94

898887

91

90

ADV3205

TOP VIEW

(Not to Scale)

84

82

86

85

81

83

787776

80

79

75

DV

CC

74

DGND

73

AGND

72

IN07

71

AGND

70

IN06

69

AGND

68

IN05

67

AGND

66

IN04

65

AGND

64

IN03

63

AGND

62

IN02

61

AGND

60

IN01

59

AGND

58

IN00

57

AGND

56

AV

EE

55

AV

CC

54

AVCC00

53

OUT00

52

AVEE00/01

51

OUT01

NC = NO CONNECT

26

13/14

AV

27

28

12/13

OUT13

CC

AV

31

33

32

10/11

AV

34

09/10

OUT10

EE

AV

29

30

11/12

OUT12

OUT11

EE

CC

AV

37

38

39

42

44

05/06

AV

45

43

04/05

OUT05

OUT04

EE

CC

AV

35

36

08/09

OUT09

EE

CC

AV

40

41

06/07

07/08

AV

OUT06

OUT07

EE

CC

AV

OUT08

46

03/04

AV

48

49

50

47

02/03

01/02

OUT03

OUT02

EE

CC

AV

AV

CC

10342-006

Figure 5. Pin Configuration

Table 7. Pin Function Descriptions

Pin Number Mnemonic Description

1, 75 DVCC 5 V for Digital Circuitry.
2, 74 DGND Ground for Digital Circuitry.
3, 5, 7, 9, 11, 13, 15, 17, 19, 57,

AGND Analog Ground for Inputs and Switch Matrix.

59, 61, 63, 65, 67, 69, 71, 73
4, 6, 8, 10, 12, 14, 16, 18, 58, 60,

INxx Analog Inputs; xx = Channel Number 00 through Channel Number 15.

62, 64, 66, 68, 70, 72
20, 56 AVEE −5 V for Inputs and Switch Matrix.
21, 55 AVCC 5 V for Inputs and Switch Matrix.
22, 54 AVCCxx 5 V for Output Amplifier that is used by Channel Number xx.
26, 30, 34, 38, 42, 46, 50 AVCCxx/yy 5 V for Output Amplifier that is shared by Channel Number xx and Channel Number yy.
23, 25, 27, 29, 31, 33, 35, 37,

OUTyy Analog Outputs; yy = Channel Number 00 Through Channel Number 15.

39, 41, 43, 45, 47, 49, 51, 53
24, 28, 32, 36, 40, 44, 48, 52 AVEExx/yy −5 V for Output Amplifier that is shared by Channel Number xx and Channel Number yy.
76 D4 Parallel Data Input, TTL Compatible (Output Enable).
77 D3 Parallel Data Input, TTL Compatible (Input Select MSB).
78 D2 Parallel Data Input, TTL Compatible (Input Select).
79 D1 Parallel Data Input, TTL Compatible (Input Select).

Rev. 0 | Page 7 of 20

ADV3205 Data Sheet

Pin Number Mnemonic Description

80 D0 Parallel Data Input, TTL Compatible (Input Select LSB).
81 A3 Parallel Data Input, TTL Compatible (Output Select MSB).
82 A2 Parallel Data Input, TTL Compatible (Output Select).
83 A1 Parallel Data Input, TTL Compatible (Output Select).
84 A0 Parallel Data Input, TTL Compatible (Output Select LSB).
85 to 93 NC No Connect. Do not connect to this pin.
94
95

96 DATA IN Serial Data Input, TTL Compatible.
97 CLK Clock, TTL Compatible. Falling edge triggered.
98 DATA OUT Serial Data Out, TTL Compatible.
99

100

/PAR

SER
UPDATE

CE
RESET

Selects Serial Data Mode, Low or Parallel Data Mode, High.

Enable (Transparent) Low. Allows serial register to connect directly to switch matrix.

Data latched when high.

Chip Enable, Enable Low. Must be low to clock in and latch data.
Disable Outputs, Active Low.

Rev. 0 | Page 8 of 20

Data Sheet ADV3205

TRUTH TABLE AND LOGIC DIAGRAM

Table 8. Operation Truth Table1

CE

UPDATE

CLK DATA IN DATA OUT

RESET

1 X X X X X X No change in logic.
0 1

0 1

Data i Data

↓2

D0 ... D4,

↓3

A0 ... A3

1 0

i-80

Not
applicable

1 1

in parallel
mode

0 0 X X X 1 X

X X X X X 0 X

1

X = don’t care, 0 = logic low, 1 = logic high, and ↓ = falling edge triggered.

2

↓ = falling edge triggered.

3

↓ = low level triggered.

D0

DATA

D1
D2
D3
D4

D

CLK

S

D1

Q

Q

D0

S

D1

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

D0

D1

D

Q

Q

D0

CLK

PARALLEL

(OUTPUT

ENABLE)

SER/PAR

DATA IN

(SERIAL)

SER

S

D

Q

CLK

Q

/PAR

S

D1

Q

D0

Operation/Comment

The data on the serial DATA IN line is loaded into the serial
register. The first bit clocked into the serial register appears at
DATA OUT 80 clocks later.

The data on the parallel data lines, D0 to D4, are loaded into
the 80-bit serial shift register location addressed by A0 to A3.

Data in the 80-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.

Asynchronous operation. All outputs are disabled. Remainder
of logic is unchanged.

D

CLK

S

D1

Q

D0

S

D1

D

Q

CLK

Q

D0

Q

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

Q

D0

D

CLK

S

D1

Q

D0

D1

Q

D

Q

D0

CLK

S

DATA

Q

D

Q

OUT

CLK

CLK

CE

UPDATE

OUT00 EN

OUT01 EN

OUT02 EN

OUTPUT

ADDRESS

OUT03 EN

OUT04 EN

A0

OUT05 EN

A1

OUT06 EN

A2

OUT07 EN

A3

OUT08 EN

OUT09 EN

OUT10 EN

4 TO 16 DECODER

OUT11 EN

OUT12 EN

OUT13 EN

OUT14 EN

OUT15 EN

(OUTPUT ENABLE)

RESET

LE

OUT00

B0

D

Q

LE

OUT00

B1

D

Q

LE

OUT00

B2

D

Q

LE

OUT00

B3

D

Q

LE

OUT00

EN

D

QCLR

LE

OUT01

B0

D

Q

LE

OUT14

EN

D

QCLR

LE

OUT15

B0

D

Q

LE

OUT15

B1

D

Q

LE

OUT15

B2

D

Q

LE

OUT15

B3

D

Q

LE

OUT15

EN

D

QCLR

DECODE

256

SWITCH MATRIX

16

OUTPUT E NABLE

10342-005

Figure 6. Logic Diagram

Rev. 0 | Page 9 of 20

ADV3205 Data Sheet

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±5 V, RL = 150 , unless otherwise noted.

3

3

0

GAIN (dB)

–3

–6

0.01 0.1 1 10 100

Figure 7. Small Signal Bandwidth, V

FREQUENCY ( MHz)

= 200 mV p-p

OUT

0.3

0.2

0.1

0

–0.1

GAIN FLATNESS (dB)

–0.2

0

GAIN (dB)

–3

–6

0.1 1 10 100

10342-012

Figure 10. Large Signal Bandwidth, V

FREQUENCY ( MHz)

= 2 V p-p

OUT

10342-015

0.3

0.2

0.1

0

–0.1

GAIN FLAT NESS (dB)

–0.2

–0.3

0.1 1 10 100

Figure 8. Small Signal Gain Flatness, V

FREQUENCY (MHz)

= 200 mV p-p

OUT

40

–50

–60

–70

CROSSTALK ( dB)

–80

–90

–100

0.1 1 10 100

Figure 9. Crosstalk vs. Frequency, V

ALL HOST ILE

FREQUENCY (M Hz)

= 2 V p-p

OUT

ADJACENT

10342-013

10342-014

Rev. 0 | Page 10 of 20

–0.3

0.1 1 10 100

Figure 11. Large Signal Gain Flatness, V

FREQUENCY (M Hz)

= 2 V p-p

OUT

50

–60

–70

–80

CROSSTALK ( dB)

–90

–100

–110

0.001 0.01 0.1 1 10010

SECOND HARMONI C

THIRD HARMONI C

FREQUENCY (M Hz)

Figure 12. Distortion vs. Frequency, V

= 2 V p-p

OUT

10342-016

10342-017

Data Sheet ADV3205

√

V

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

0.01 0.1 1 10

+PSRR

–PSRR

FREQUENCY (M Hz)

Figure 13. PSRR vs. Frequency

1k

10342-018

160

140

120

100

Hz)

80

60

NOISE (nV

40

20

0
10 100 1k 1 0k 1M100k 10M

FREQUENCY (Hz )

Figure 16. Noise vs. Frequency

10k

10342-021

100

10

IMPEDANCE (Ω)

1

0.1

0.1 1 10 100 1k

FREQUENCY (M Hz)

Figure 14. Enabled Output Impedance vs. Frequency

0

–20

–40

–60

–80

OFF ISOLATIO N (dB)

–100

1k

100

IMPEDANCE (Ω)

10

1

0.1 1 10 100 1k

10342-019

FREQUENCY (M Hz)

10342-022

Figure 17. Disabled Output Impedance vs. Frequency

INPUT

0.1%/DI

OUTPUT

OUTPUT

2

– INPUT

–120

0.1 1 10 100

Figure 15. Off Isolation vs. Frequency, V

FREQUENCY (M Hz)

= 2 V p-p

OUT

10342-020

Rev. 0 | Page 11 of 20

051052025

30 35 40 45 50

5ns/DIV

Figure 18. Settling Time to 0.1%, 2 V Output Step

10342-023

ADV3205 Data Sheet

300

50mV/DIV

5ns/DIV

10342-024

Figure 19. Small Signal Pulse Response

UPDATE

INPUT 1

10342-025

100ns/DIV

V

OUT

2V/DIV

INPUT 0

Figure 20. Switching Time

500mV/DIV

1V/DIV

20mV/DIV

100ns/DIV

Figure 22. Large Signal Pulse Response

UPDATE

OUTPUT

100ns/DIV

Figure 23. Switching Transient

10342-027

10342-028

250

200

(pF)

150

LOAD

C

100

50

0

0

Figure 21. C

5 101520253035

LOAD

SERIES RESISTANCE (Ω)

vs. Series Resistance for Less than 30% Overshoot

10342-026

Rev. 0 | Page 12 of 20

Data Sheet ADV3205

CIRCUIT DIAGRAMS

AV

CC

DV

CC

ESD

INPUT

ESD

AV

EE

Figure 24. Analog Input

AV

CC

ESD

ESD

AV

EE

Figure 25. Analog Output

DV

CC

ESD

RESET

ESD

DGND

Figure 26. Reset Input

ESD

INPUT

ESD

10342-007

DGND

10342-010

Figure 27. Logic Input

DV

CC

DGND

ESD

ESD

OUTPUT

10342-011

2kΩ

OUTPUT

10342-008

Figure 28. Logic Output

20kΩ

10342-009

Rev. 0 | Page 13 of 20

ADV3205 Data Sheet

THEORY OF OPERATION

The ADV3205 is a gain-of-two crosspoint array with 16 outputs,
each of which can be connected to any one of 16 inputs.
Organized by output row, 16 switchable transconductance
stages are connected to each output buffer in the form of a
16-to-1 multiplexer. Each of the 16 rows of transconductance
stages are wired in parallel to the 16 input pins, for a total array
of 256 transconductance stages. Decoding logic for each output
selects one (or none) of the transconductance stages to drive the
output stage. The transconductance stages are NPN input differential
pairs, sourcing current into the folded cascode output stage.
The compensation networks and emitter follower output buffers
are in the output stage. Voltage feedback sets the gain at +2.

The ADV3205 can drive reverse-terminated video loads,
swinging ±3.0 V into 150 Ω. Disabling unused outputs
and transconductance stages minimizes on-chip power
consumption.

Features of the ADV3205 facilitate the construction of larger
switch matrices. The unused outputs can be disabled, leaving
only a feedback network resistance of 4 k on the output. This
allows multiple ICs to be bused together, provided the output
load impedance is greater than the minimum allowed values.
Because no additional input buffering is necessary, high input
resistance and low input capacitance are easily achieved without
additional signal degradation.

The ADV3205 inputs have a unique bias current compensation
scheme that overcomes a problem common to transconductance
input array architectures. Typically, input bias current increases
as more and more transconductance stages connected to the same
input are turned on. Anywhere from 0 to 16 transconductance
stages can be sharing one input pin, so there is a varying amount of
bias current supplied through the source impedance driving the
input. The ADV3205 samples and cancels the input bias current
contributions from each transconductance stage so that the
residual bias current is nominally zero, regardless of the number
of enabled inputs.

The ADV3205 contains internal crosstalk isolation clamps that
have variable bias levels. These levels were chosen to allow the
necessary input range to accommodate the full output swing
with a gain of +2. Overdriving the inputs beyond the linear
range of the device eventually forward biases these clamps,
increasing the power dissipation. The valid input range is ±1.5 V.
When outputs are disabled and being driven externally, the
voltage applied to them should not exceed the valid input swing
range for the ADV3205.

A flexible TTL-compatible logic interface simplifies the
programming of the matrix. Either parallel or serial loading
into a first rank of latches programs each output. A global latch
simultaneously updates all outputs. In serial mode, a serial data out
pin (DATA OUT) allows devices to be daisy chained together
for single pin programming of multiple ICs. A power-on reset
function can be implemented to avoid bus conflicts by disabling
all outputs.

The digital logic requires 5 V on the DV
DGND. Internal ESD protection diodes require that the DGND
and AGND pins be at the same potential.

pin with respect to

CC

SHORT-CIRCUIT OUTPUT CONDITIONS

Although there is short-circuit current protection on the ADV3205
outputs, the short-circuit output current can reach levels that
can result in device failure. Do not operate the ADV3205 with a
sustained short to ground on any of its outputs.

Rev. 0 | Page 14 of 20

Data Sheet ADV3205

APPLICATIONS INFORMATION

The ADV3205 has two options for changing the programming of
the crosspoint matrix. In the first option, a serial word of 80 bits can
be provided that updates the entire matrix in one serial operation.
The second option allows for changing the programming of a
single output via a parallel interface. The serial option requires
fewer signals but more time (clock cycles) for changing the
programming, whereas the parallel programming technique
requires more signals, but can change a single output at a time,
and requires fewer clock cycles to complete programming.

SERIAL PROGRAMMING

The serial programming mode uses the device pins: CE, CLK,
DATA IN,
low on
for the chip must be low to allow data to be clocked into the
device. The
device when devices are connected in parallel.

The
shifted into the serial port of the device. Although the data still
shifts in when
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as defined by
the shifting data.

UPDATE

SER

/PAR to enable the serial programming mode. CE

CE

signal can be used to address an individual

UPDATE

signal should be high during the time that data is

UPDATE

SER

, and

/PAR. The first step is to assert a

is low, the transparent, asynchronous

PARALLEL PROGRAMMING

When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows for the modification of a
single output at a time. Because this takes only one CLK/
cycle, significant time savings can be realized by using parallel
programming.

One important consideration in using parallel programming is

RESET

that the
When taken low, the
disabled state. This is helpful during power-up to ensure that

two parallel outputs are not active at the same time.

After initial power-up, the internal registers in the device generally
contain random data, even though the
asserted. If parallel programming is used to program one output,
that output is properly programmed but the rest of the device
has a random program state depending on the internal register
content at power-up. Therefore, when using parallel programming,
it is essential that all outputs be programmed to a desired state
after power-up. This ensures that the programming matrix is
always in a known state. From then on, parallel programming
can be used to modify a single output at a time.

signal does not reset all registers in the .

RESET

signal only sets each output to the

RESET

UPDATE

ADV3205

signal has been

The data at DATA IN is clocked in at every down edge of CLK. A
total of 80 bits must be shifted into the shift register via the DATA
IN input to complete the programming. For each of the 16 outputs,
there are four bits (D0 to D3) that determine the source of its
input followed by one bit (D4) that determines the enabled state
of the output. If D4 is low (output disabled), the four associated
bits (D0 to D3) do not matter because no input is switched to
that output.

The most significant output address data is shifted into the shift
register first, following in sequence until the least significant
output address data is shifted in. At this point
taken low, which causes the programming of the device according
to the data that was just shifted in. The

UPDATE

,

UPDATE

, and

is low (and CE is low), the

SER

asynchronous, and when
registers are transparent.

When more than one ADV3205 device is serially programmed in a
system, the DATA OUT signal from one device can be connected
to the DATA IN of the next device to form a serial chain. Connect
all of the CLK,
operate them as previously described. The serial data is input to
the DATA IN pin of the first device of the chain, and it ripples
through to the last. Therefore, the data for the last device in the
chain should come at the beginning of the programming sequence.
The length of the programming sequence is 80 bits times the
number of devices in the chain.

CE

UPDATE

UPDATE

/PAR pins in parallel and

can be

registers are

In similar fashion, if both
initial power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent the crosspoint
from being programmed into an unknown state, do not apply
low logic levels to both
applied. Programming the full shift register one time to a desired
state, by either serial or parallel programming after initial power-up,
eliminates the possibility of programming the matrix to an
unknown state.

To change the output’s programming via parallel programming,

SER

take
signal should be in the high state. Put the 4-bit address of the
output to be programmed on the A0 to A3 pins. The first four
data bits (D0 to D3) should contain the information that identifies
the input that is programmed to the output that is addressed.
The fifth data bit (D4) determines the enabled state of the output. If
D4 is low (output disabled), the data on D0 to D3 does not matter.

After the desired address and data signals are established, they
can be latched into the shift register by a high-to-low transition
of the CLK signal. The matrix is not programmed, however, until
the
new data for several or all of the outputs first via successive
negative transitions of CLK while

have all of the new data take effect when
Use this technique when programming the device for the first
time after power-up when using parallel programming.

/PAR and

UPDATE

signal is taken low. It is thus possible to latch in

CE

CE

UPDATE

UPDATE

and

UPDATE

and

high and take CE low. The CLK

UPDATE

are taken low after

after power is initially

is held high and then

UPDATE

goes low.

Rev. 0 | Page 15 of 20

ADV3205 Data Sheet

V

POWER-ON RESET

When powering up the ADV3205, it is usually desirable to have

RESET

the outputs start up in the disabled state. The

pin, when
taken low, causes all outputs to be in the disabled state. However,
the

RESET

signal does not reset all registers in the .

ADV3205

This is important when operating in parallel programming mode.
Refer to the section for information

Parallel Programming
about programming internal registers after power-up. Serial
programming programs the entire matrix each time; therefore,
no special considerations apply.

Because the data in the shift register is random after power-up,
do not use it to program the matrix or the matrix can enter
unknown states. To prevent this, do not apply logic low signals
to both

CE

shift register with the desired data, and then take

and

UPDATE

initially after power-up. First, load the

UPDATE

low

to program the device.

RESET

The

pin has a 20 kΩ pull-up resistor to DVCC that can be
used to create a simple power-up reset circuit. A capacitor from
RESET

to ground holds

RESET

low for some time while the rest
of the device stabilizes. The low condition causes all outputs to
be disabled. The capacitor then charges through the pull-up resistor
to the high state, thus allowing full programming capability of
the device.

MANAGING VIDEO SIGNALS

Video signals often use controlled impedance transmission lines
that are terminated in their characteristic impedance. Although this
is not always the case, there are some considerations when using
the ADV3205 to route video signals with controlled impedance
transmission lines. Figure 29 shows a schematic of an input
and output treatment of a typical video channel.

75Ω

VIDEO

SOURCE

+5

TYPICAL

INPUT

ADV3205

75Ω

G = 2

–5V

Figure 29. Video Signal Circuit

TYPICAL

OUTPUT

75Ω

75Ω

TRANSMISSI ON

LINE

75Ω

10342-031

The ADV3205 outputs are low impedance and do not properly
terminate the source end of a 75  transmission line. In these
cases, insert a series 75  resistor at an output that drives a video
signal. Then terminate the 75  transmission line with 75  at
its far end. This overall termination scheme divides the amplitude
of the ADV3205 output by two. An overall unity-gain channel is
produced because of the channel gain-of-two of the ADV3205.

CREATING LARGER CROSSPOINT ARRAYS

The ADV3205 is a high density building block for creating
crosspoint arrays of dimensions larger than 16 × 16. Various
features, such as output disable and chip enable, are useful for
creating larger arrays.

The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required. The
16 × 16 architecture of the ADV3205 contains 256 points, which is
a factor of 64 greater than a 4 × 1 crosspoint (or multiplexer). The
printed circuit board (PCB) area, power consumption, and design
effort savings are readily apparent when compared to using
these smaller devices.

For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the
availability of that input to be a source for any other outputs.

Some nonblocking crosspoint architectures require more than this
minimum as previously calculated. In addition, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statistical
basis that is determined when designing the overall system.

The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-OR
the outputs together in the vertical direction. The meaning of
horizontal and vertical can best be understood by looking at a
diagram. Figure 30 illustrates this concept for a 32 × 32 crosspoint
array that uses four ADV3205 devices. Note that the 75 Ω source
terminations are not shown on the outputs, but they are required
when driving the 75 Ω transmission lines.

Video signals most often use 75  transmission lines that need
to be terminated with this value of resistance at each end. When
such a source is delivered to one of the ADV3205 inputs, the
high input impedance does not properly terminate these signals.
Therefore, terminate the line with a 75  shunt resistor to
ground. Because video signals are limited in their peak-to-peak
amplitude (typically no more than 1.5 V p-p), there is no need
to attenuate video signals before they pass through the ADV3205.

Rev. 0 | Page 16 of 20

IN00 TO IN15

IN16 TO IN31

Figure 30. 32 × 32 Crosspoint Array Using Four ADV3205 Devices

16

ADV3205

16

ADV3205

16

ADV3205

75Ω

16

16

75Ω

16

16

8

ADV3205

16

16

10342-032

Data Sheet ADV3205

The inputs are individually assigned to each of the 32 inputs of
the two devices, and the shunt 75  terminations are placed at
the end of the transmission lines. The outputs are wire-OR’ed
together in pairs. Only enable one of the outputs from a wire­ORed pair at any given time. The device programming software
must be properly written to achieve this.

MULTICHANNEL VIDEO

The good video specifications of the ADV3205 make it an ideal
candidate for creating composite video crosspoint switches. These
switches can be made quite dense by taking advantage of the
high level of integration of the ADV3205 and the fact that
composite video requires only one crosspoint channel per system
video channel. There are, however, other video formats that can
be routed with the ADV3205, requiring more than one crosspoint
channel per video channel.

Some systems use twisted pair wiring to carry video signals.
These systems use differential signals and can lower costs
because they use lower cost cables, connectors, and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment
that operates in noisy environments, or where common-mode
voltages are present between transmitting and receiving equipment.

In such systems, the video signals are differential; there are positive
and negative (or inverted) versions of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first-order zero common­mode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.

When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single ADV3205, eight differential video
channels can be assigned to the 16 inputs and 16 outputs. This
effectively forms an 8 × 8 differential crosspoint switch.

Programming such a device requires that the inputs and outputs
be programmed in pairs. This information can be deduced through
inspection of the programming format of the ADV3205 and the
requirements of the system.

There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
and blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R–Y, and B–Y format, sometimes called YUV
format. These three circuit video standards are referred to as
analog component video.

The analog component video standards require three crosspoint
channels per video channel to handle the switching function. In
a fashion similar to the two circuit video formats, the inputs and
outputs are assigned in groups of three, and the appropriate logic
programming is performed to route the video signals.

CROSSTALK

Many video systems have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals of
other nearby channels to a given channel.

When there are many signals in proximity in a system, as is the
case in a system that uses the ADV3205, the crosstalk issues can
be quite complex. A good understanding of the nature of crosstalk
and some definition of terms is required to specify a system that
uses one or more ADV3205 devices.

Types of Crosstalk

Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field, and
sharing of common impedances. This section explains these effects.

Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance (for example, free space) and couples
with the receiver and induces a voltage. This voltage is an unwanted
crosstalk signal in any channel that receives it.

Currents flowing in conductors create magnetic fields that circulate
around the currents. These magnetic fields then generate voltages
in any other conductors with whose paths they link. The undesired
induced voltages in these other channels are crosstalk signals.
The channels that crosstalk can be said to have a mutual inductance
that couples signals from one channel to another.

There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
commonly being used in video systems is S-Video or Y/C Video.
The Y/C Video format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance, chroma, or C) on a second channel.

Because S-Video also uses two separate circuits for one video
channel, creating a crosspoint system requires assigning one
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
format, other aspects of these two systems are the same.

Rev. 0 | Page 17 of 20

The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an input
crosstalk signal for other channels that share the common
impedance.

All these sources of crosstalk are vector quantities; therefore, the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.

ADV3205 Data Sheet

Areas of Crosstalk

A practical ADV3205 circuit must be mounted to some sort of
circuit board to connect it to power supplies and measurement
equipment. This, however, raises the issue that the crosstalk of a
system is a combination of the intrinsic crosstalk of the devices
in addition to the circuit board to which they are mounted. It is
important to try to separate these two areas when attempting to
minimize the effect of crosstalk.

In addition, crosstalk can occur among the inputs to a cross­point and among the outputs. It can also occur from input to
output. Techniques are presented in the following sections for
diagnosing which part of a system is contributing to crosstalk,
as well as minimizing crosstalk.

Measuring Crosstalk

Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as dB
down from the magnitude of the test signal. The crosstalk is
expressed by

|XT| = 20log

where:

s = jw, the Laplace transform variable.
Asel(s) is the amplitude of the crosstalk induced signal in the

selected channel.
Atest(s) is the amplitude of the test signal.

It can be seen that crosstalk is a function of frequency, but not a
function of the magnitude of the test signal (to the first order).
In addition, the crosstalk signal has a phase relative to the test
signal associated with it.

A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magnitude
and phase information about the crosstalk signal.

As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can become
extremely large. For example, in the case of the 16 × 16 matrix
of the ADV3205, note the number of crosstalk terms that can be
considered for a single channel, such as the IN00 input. IN00 is
programmed to connect to one of the ADV3205 outputs where
the measurement can be made.

First, the crosstalk terms associated with driving a test signal into
each of the other 15 inputs can be measured one at a time, while
applying no signal to IN00. Then, the crosstalk terms associated
with driving a parallel test signal into all 15 other inputs can be
measured two at a time in all possible combinations, then three at
a time, and so on, until finally, there is only one way to drive a test
signal into all 15 other inputs in parallel.

(Asel(s)/Atest(s))

10

Rev. 0 | Page 18 of 20

Each of these cases is legitimately different from the others and
may yield a unique value, depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar crosstalk
matrix can be proposed for every other input. In addition, if the
possible combinations and permutations for connecting inputs
to the other outputs (not used for measurement) are taken into
consideration, the numbers grow impractically large. If a larger
crosspoint array of multiple ADV3205 devices is constructed, the
numbers grow larger still.

Clearly, some subset of all these cases must be selected to be used as
a guide for a practical measure of crosstalk. One common method
is to measure all hostile crosstalk; this means that the crosstalk to
the selected channel is measured while all other system channels
are driven in parallel. In general, this yields the worst crosstalk
number, but this is not always the case, due to the vector nature
of the crosstalk signal.

Other useful crosstalk measurements are those that are created by
one nearest neighbor or by the two nearest neighbors on either
side. These crosstalk measurements are generally higher than those
of more distant channels, so they can serve as a worst-case measure
for any other 1-channel or 2-channel crosstalk measurements.

Input and Output Crosstalk

The flexible programming capability of the ADV3205 can be
used to diagnose whether crosstalk is occurring more on the
input side or the output side. Some examples are illustrative. A
given input channel (IN07 in the middle for this example) can
be programmed to drive OUT07 (also in the middle). The input
to IN07 is just terminated to ground (via 50  or 75 ) and no
signal is applied.

All the other inputs are driven in parallel with the same test signal
(provided by a distribution amplifier), with all other outputs
except OUT07 disabled. Because grounded IN07 is programmed
to drive OUT07, no signal should be present. Any signal that is
present can be attributed to the other 15 hostile input signals
because no other outputs are driven (they are all disabled).
Thus, this method measures the all-hostile input contribution
to crosstalk into IN07. Of course, the method can be used for
other input channels and combinations of hostile inputs.

For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 (far away
from IN00), which is terminated to ground. Therefore, OUT07
should not have a signal present because it is listening to a quiet
input. Any signal measured at OUT07 can be attributed to the
output crosstalk of the other 16 hostile outputs. Again, this method
can be modified to measure the other channels and the other
crosspoint matrix combinations.

Data Sheet ADV3205

Effect of Impedances on Crosstalk

The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced cross­talk. However, significant current can flow through the input
termination resistors and the loops that drive them. Thus, the
PCB on the input side can contribute to magnetically coupled
crosstalk.

From a circuit standpoint, the input crosstalk mechanism is
similar to a capacitor coupling to a resistive load. For low
frequencies, the magnitude of the crosstalk is given by

|XT| = 20log

[(RSCM) × s]

10

This crosstalk mechanism can be minimized by keeping the
mutual inductance low and increasing R

. The mutual inductance

L

can be kept low by increasing the spacing of the conductors and
minimizing their parallel lengths.

PCB Layout

Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). The areas that must be
carefully detailed are grounding, shielding, signal routing, and
supply bypassing.

The packaging of the ADV3205 is designed to keep the crosstalk
to a minimum. Each input is separated from every other input
by an analog ground pin. Directly connect all AGND pins to the
ground plane of the circuit board. These ground pins provide
shielding, low impedance return paths, and physical separation
for the inputs. All of these help to reduce crosstalk.

where:

R

is the source resistance.

S

C

is the mutual capacitance between the test signal circuit and

M

the selected circuit.
s is the Laplace transform variable.

From the previous equation, it can be observed that this crosstalk
mechanism has a high-pass nature; it can also be minimized by
reducing the coupling capacitance of the input circuits and
lowering the output impedance of the drivers. If the input is driven
from a 75  terminated cable, the input crosstalk can be reduced
by buffering this signal with a low output impedance buffer.

On the output side, the crosstalk can be reduced by driving a
lighter load. Although the ADV3205 is specified with excellent
differential gain and phase when driving a standard 150  video
load, the crosstalk is higher than the minimum obtainable due
to the high output currents. These currents induce crosstalk via
the mutual inductance of the output pins and bond wires of the

ADV3205.

From a circuit standpoint, this output crosstalk mechanism is
similar to a transformer with a mutual inductance between the
windings that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by

|XT| = 20log

(Mxy × s/RL)

10

Each output is separated from its two neighboring outputs by an
analog supply pin of one polarity or the other. Each of these analog
supply pins provides power to the output stages of only the two
nearest outputs. These supply pins provide shielding, physical
separation, and a low impedance supply for the outputs. Individual
bypassing of each of these supply pins with a 0.1 µF chip capacitor
directly to the ground plane minimizes high frequency output
crosstalk via the mechanism of shared common impedances.

Each output also has an on-chip compensation capacitor that is
individually tied to the nearby analog ground pins. This technique
reduces crosstalk by preventing the currents that flow in these paths
from sharing a common impedance on the IC and in the package
pins. Directly connect these AGND pins to the ground plane.

There are separate digital (logic) and analog supplies. DV

CC

must be at 5 V to be compatible with the 5 V CMOS and TTL
logic. AV

and AVEE can range from ±5 V to ±12 V, depending

CC

on the application.

Locally decouple each power supply pin (or group of adjacent
power supply pins) with a 0.1 µF capacitor. Use a 10 µF capacitor to
decouple power supplies as they come onto the board.

where:
Mxy is the mutual inductance of Output X to Output Y.

is the load resistance on the measured output.

R

L

Rev. 0 | Page 19 of 20

ADV3205 Data Sheet

OUTLINE DIMENSIONS

16.20

16.00 SQ

15.80

PIN 1

TOP VIEW

(PINS DOWN)

0.50
BSC

LEAD PIT CH

0.27

0.22

0.17

76100

75

14.20

14.00 SQ

13.80

51

50

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

1.60 MAX

0.75

0.60

0.45

0.20

0.09
7°

3.5°
0°

0.08
COPLANARITY

25

VIEW A

1

26

COMPLI ANT TO JEDEC STANDARDS MS-026-BED

051706-A

Figure 31. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADV3205JSTZ 0°C to 70°C 100-Lead Low Profile Quad Flat Package [LQFP] ST-100-1
ADV3205-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10342-0-12/11(0)

Rev. 0 | Page 20 of 20