16 × 16 high speed nonblocking switch array
Serial or parallel programming of switch array
Serial data out allows daisy-chaining control of multiple
16 × 16 devices to create larger switch arrays
Complete solution
Buffered inputs
16 output amplifiers
Operates on ±5 V supplies
Low supply current of 50 mA
Excellent video performance, V
−3 dB bandwidth: 60 MHz
0.1 dB gain flatness: 10 MHz
0.1% differential gain error (R
0.1° differential phase error (R
Low all hostile crosstalk: −67 dB at 5 MHz
Output disable allows connection of multiple devices
without loading the output bus
RESET
pin allows disabling of all outputs
Power-on reset capability with capacitor to ground
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
CCTV surveillance
Video routers (NTSC, PAL, S-Video, SECAM)
Video conferencing
= ±5 V
S
= 1 kΩ)
L
= 1 kΩ)
L
Buffered Analog Crosspoint Switch
ADV3205
FUNCTIONAL BLOCK DIAGRAM
SER/PAR
CLK
DATA IN
UPDATE
CE
RESET
ADV3205
16 INPUTS
D0 D1 D2 D3
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL L OADING
80
PARALLEL L ATCH
80
DECODE
16 × 5:16 DECODERS
256
SWITCH
MATRIX
Figure 1.
D4
OUTPUT
BUFFER
G = +2
SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO “OFF”
16
ENABLE/DIS ABLE
A0
A1
A2
A3
DATA
OUT
16
OUTPUTS
10342-001
GENERAL DESCRIPTION
The ADV3205 is a fully buffered crosspoint switch matrix that
operates on ±5 V, making it ideal for video applications. It offers
a −3 dB signal bandwidth of 60 MHz and channel switch times of
less than 60 ns with 0.1% settling. The ADV3205 has excellent
crosstalk performance, and ground/power pins surround all inputs
and outputs to provide extra shielding required for the most
demanding applications. The differential gain and differential
phase of better than 0.1% and 0.1°, respectively, along with 0.1 dB
flatness out to 10 MHz, make the ADV3205 an excellent choice
for many video applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The ADV3205 includes 16 independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs.
The ADV3205 has a gain of +2 and operates on voltage supplies
of ±5 V while consuming only 34 mA of current. Channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control, allowing updating of an individual output without
reprogramming the entire array.
The ADV3205 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.
TA = 25°C, VS = ±5 V, RL = 150 , unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth V
V
Gain Flatness 0.1 dB, V
Propagation Delay V
Settling Time 0.1%, 2 V output step 23 ns
Slew Rate 2 V output step 100 V/μs
NOISE/DISTORTION PERFORMANCE
Differential Gain Error NTSC, RL = 1 kΩ 0.1 %
Differential Phase Error NTSC, RL = 1 kΩ 0.1 Degrees
Crosstalk, All Hostile f = 5 MHz −67 dB
Off Isolation f = 5 MHz, one channel −100 dB
Input Voltage Noise 0.1 MHz to 10 MHz 12 nV/√Hz
DC PERFORMANCE
Gain Error 0.5 %
Gain Matching Channel-to-channel 0.7 %
Gain Temperature Coefficient 20 ppm/°C
OUTPUT CHARACTERISTICS
Output Resistance Enabled 0.3 Ω
Disabled 3.4 4 kΩ
Output Capacitance Disabled 5 pF
Output Voltage Swing No Load ±3.2 ±3.5 V
I
Short-Circuit Current 55 mA
INPUT CHARACTERISTICS
Input Offset Voltage All configurations ±5 ±10 mV
Temperature coefficient 10 μV/°C
Input Voltage Range No load ±1.5 V
Input Capacitance Any switch configuration 4 pF
Input Resistance Any number of connected outputs 50 MΩ
Input Bias Current Any number of enabled inputs ±1 μA
SWITCHING CHARACTERISTICS
Enable On Time 80 ns
Switching Time, 2 V Step 50% update to 1% settling 50 ns
Switching Transient (Glitch) 20 mV p-p
POWER SUPPLIES
Supply Current AVCC outputs enabled, no load 45 50 mA
AVCC outputs disabled 31 35 mA
AVEE outputs enabled, no load 45 50 mA
AVEE outputs disabled 31 35 mA
DVCC outputs enabled, no load 8 13 mA
DYNAMIC PERFORMANCE
Supply Voltage Range AVCC 4.5 5.5 V
AVEE −5.5 −4.5 V
DVCC 4.5 5.5 V
PSRR DC 75 80 dB
f = 100 kHz 60 dB
f = 1 MHz 40 dB
= 200 mV p-p 41 60 MHz
OUT
= 2 V p-p 25 MHz
OUT
= 200 mV p-p 10 MHz
OUT
= 2 V p-p 20 ns
OUT
= 20 mA ±2.7 ±3 V
OUT
Rev. 0 | Page 3 of 20
ADV3205 Data Sheet
T
Parameter Test Conditions/Comments Min Typ Max Unit
OPERATING TEMPERATURE RANGE
Temperature Range Operating (still air) 0 70 °C
θJA Operating (still air) 40 °C/W
TIMING CHARACTERISTICS (SERIAL MODE)
Table 2.
Limit
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t1 20 ns
CLK Pulse Width t2 100 ns
Serial Data Hold Time t3 20 ns
CLK Pulse Separation, Serial Mode t4 100 ns
t
CLK-to-UPDATE Delay
UPDATE Pulse Width
CLK-to-DATA OUT Valid, Serial Mode t7 200 ns
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode 16 μs
CLK, UPDATE Rise and Fall Times
RESET Time
CLK
DATA IN
1 = LATCHED
UPDATE
0 = TRANSPARE N
t
1
0
1
0
t1t
OUT07 (D4)
2
3
t
7
t
4
OUT07 (D3)
0 ns
5
t
50 ns
6
50 ns
100 ns
200 ns
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT00 (D0)
t
5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURI NG LOW LEVEL
t
6
DATA OUT
Figure 2. Timing Diagram, Serial Mode
10342-002
Table 3. Logic Levels
VIH VIL VOH VOL IIH IIL IOH IOL
RESET, SER/PAR
CLK, DATA IN, CE
UPDATE
,
, SER/PAR
RESET
CLK, DATA IN, CE
UPDATE
,
DATA OUT DATA OUT
, SER/PAR
RESET
CLK, DATA IN, CE
UPDATE
RESET
,
CLK, DATA IN, CE
UPDATE
, SER/PAR
,
DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 μA max −400 μA min −400 μA max 3.0 mA min
Rev. 0 | Page 4 of 20
Data Sheet ADV3205
0
T
TIMING CHARACTERISTICS (PARALLEL MODE)
Table 4.
Limit
Parameter Symbol Min Max Unit
Parallel Data Setup Time t1d 20 ns
Address Setup Time t1a 20 ns
CLK Enable Width t2 100 ns
Parallel Data Hold Time t3d 20 ns
Address Hold Time t3a 20 ns
CLK Pulse Separation t4 100 ns
t
CLK-to-UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
1
CLK
0
1
A0 TO A3
0
1
D0 TO D4
0
1 = LATCHED
UPDATE
= TRANSPAREN
t
2
t
1a
t
1d
t
3a
t
3d
Figure 3. Timing Diagram, Parallel Mode
t
4
0 ns
5
t
50 ns
6
50 ns
100 ns
200 ns
t
t
5
6
10342-003
Table 5. Logic Levels
VIH VIL VOH VOL IIH IIL I
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
DATA OUT DATA OUT
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
I
OH
OL
DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 μA max −400 μA min −400 μA max 3.0 mA min
Rev. 0 | Page 5 of 20
ADV3205 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Supply Voltage (AVCC to AVEE) 12 V
Digital Supply Voltage (DVCC to DGND) 6 V
Ground Potential Difference (AGND to
±0.5 V
DGND)
Internal Power Dissipation
Analog Input Voltage
1
2
3.1 W
Maintain linear output
Digital Input Voltage DVCC
Output Voltage (Disabled Output)
(AV
(AV
CC
EE
− 1.5 V) to
+ 1.5 V)
Output Short-Circuit Duration Momentary
Storage Temperature Range −65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
1
Specification is for device in free air (TA = 25°C):
100-lead plastic LQFP: θJA = 40°C/W.
2
To avoid differential input breakdown, in no case should one-half the output
voltage (1/2 V
differential. See the output voltage swing parameter in Table 1 for the linear
output range.
) and any input voltage be greater than 10 V potential
OUT
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
POWER DISSIPATION
Packaged in a 100-lead LQFP, the ADV3205 junction-to-ambient
thermal impedance (θ
the maximum allowed junction temperature of the plastic
encapsulated die should not exceed 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
The maximum ADV3205 power dissipation occurs when all
outputs are enabled and driving loads. Supply current increases
approximately linearly with the number of outputs that are enabled.
Refer to the Theory of Operation section for more details regarding
power dissipation calculations. Figure 4 indicates the maximum
ADV3205 power dissipation as a function of ambient temperature.
4.0
3.5
3.0
MAXIMUM POWER (W)
2.5
) is 40°C/W. For long-term reliability,
JA
TJ = 150°C
2.0
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
10020304050607
AMBIENT TEMPERATURE (°C)
10342-004
0
ESD CAUTION
Rev. 0 | Page 6 of 20
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