ANALOG DEVICES ADV3002 Service Manual

4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication

FEATURES

4 inputs, 1 output HDMI/DVI links ±8 kV ESD protection on input pins HDMI 1.4a receive and transmit compliant

Supports 250 Mbps to 3 Gbps data rates and beyond Supports 25 MHz to 300 MHz pixel clocks and beyond Fully buffered unidirectional inputs/outputs Switchable 50 Ω on-chip input terminations with manual

or automatic control on channel switch

Equalized inputs with low added jitter compensate for

more than 15 meters of HDMI cable at 3 Gbps Loss of signal (LOS) detect circuit on TMDS clock Output disable feature for reduced power dissipation

Bidirectional DDC buffers (SDA and SCL) EDID replication reduces component count, while enabling

simultaneous access to all HDMI sources

5 V combiner provides power to EDID replicator and CEC

buffer when local system power is off

Bidirectional buffered CEC line with integrated pull-up

resistors (26 kΩ)

Hot plug detect pulse low on channel switch with

programmable pulse width or direct manual control Standards compatible: HDMI, DVI, HDCP, I 80-lead, 14 mm × 14 mm LQFP RoHS-compliant package

APPLICATIONS

Advanced television (HDTV) sets Projectors A/V receivers Set-top boxes

GENERAL DESCRIPTION

The ADV3002 is a complete HDMI™/DVI link switch featuring equalized transition minimized differential signaling (TMDS) inputs, ideal for systems with long cable runs. The ADV3002 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. Additionally, the ADV3002 includes an EDID replication function that enables one EDID EEPROM to be shared for all four HDMI ports.

The ADV3002 is provided in a space-saving, 80-lead LQFP surface-mount, Pb-free plastic package and is specified to operate over the 0°C to 85°C temperature range.

2

C

ADV3002

FUNCTIONAL BLOCK DIAGRAM

SEL[1:0] TX_EN

SERIAL

I2C_SDA I2C_SCL

I2C_ADDR[ 1:0]

AVCC

IN_x_CLK+

IN_x_CLK– IN_x_DATA2+ IN_x_DATA2– IN_x_DATA1+ IN_x_DATA1– IN_x_DATA0+ IN_x_DATA0–

AVCC

DDC_xxx_A DDC_xxx_B DDC_xxx_C DDC_xxx_D

CEC_IN

P5V_A P5V_B P5V_C P5V_D

HPD_A HPD_B HPD_C HPD_D

+ –

+ – + –

2

CONFIG

INTERFACE

4 4

4

4 4

2 2 2 2

DDC/CEC

LOS

TMDS

EDID

PRODUCT HIGHLIGHTS

1. Input cable equalizer enables use of long cables at the input.

For a 24 AWG cable, the ADV3002 compensates for more than 15 meters at data rates of up to 3 Gbps.

2. Auxiliary multiplexer isolates and buffers the DDC bus and

the CEC line, increasing total system capacitance limit.

3. EDID replication eliminates the need for multiple EDID

EEPROMs. EDID can be loaded from a single external EEPROM or from a system microcontroller.

4. 5 V power combiner powers the EDID replicator and CEC

buffer when local system power is off.

5. Integrated hot plug detect pulse low on channel switch

with programmable pulse width or direct manual control.

RESETB

PARALLEL

CONTRO L

LOGIC

SWITCH

CORE

EQ

SWITCH

CORE

3.3V 3.3V

BIDIRECTI ONAL

REPLICATOR

CONTRO L

5V

COMBI NER

EDID EEPROM INTERFACE

HPD

CONTROL

HOT PLUG DETECT

Figure 1.

ADV3002

2

AVCC

AVEE

AVCC

+

OUT_CLK+

–

OUT_CLK–

+

OUT_DATA2+

–

OUT_DATA2–

+

OUT_DATA1+

–

OUT_DATA1–

+

OUT_DATA0+

–

OUT_DATA0–

AVCC

DDC_SCL_COM , DDC_SDA_COM

CEC_OUT

EDID_ENABLE

EDID_SCL, EDID_SDA

AMUXVCC

07905-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other rights of third parties that may result from its use. Specifications subject to chan ge without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADV3002

REVISION HISTORY

8/11—Rev. 0 to Rev. A

Changed Data Rate = 2.25 Gbps to

Data Rate = 3 Gbps........................................................ Throughout

Changes to Features Section and Product Highlights Section ... 1

Changes to Table 1............................................................................ 3

Changes to Figure 4 Caption and Figure 6 Caption..................... 8

Added Figure 5 and Figure 7; Renumbered Sequentially ........... 8

Moved Figure 8 and Figure 10 ........................................................ 9

Changes to Figure 8 Caption and Figure 10 Caption .................. 9

Added Figure 9 and Figure 11......................................................... 9

Changes to Figure 12 and Figure 15............................................. 10

Changes to TMDS Input Channels Section and TMDS Output

Channels Section ............................................................................ 12

Changes to Figure 31...................................................................... 16

Changes to Cable Lengths and Equalization Section ................ 24

12/08—Revision 0: Initial Version

Rev. A | Page 2 of 28

ADV3002

SPECIFICATIONS

TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, data rate = 3 Gbps, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

TMDS PERFORMANCE SPECIFICATIONS

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Data Rate (DR) per Channel NRZ 3 Gbps Maximum Clock Rate 300 MHz Bit Error Rate (BER) PRBS 223 − 1 10−9 Added Data Jitter DR ≤ 3 Gbps, PRBS 27 − 1 40 ps p-p Added Clock Jitter 1 ps rms Differential Intrapair Skew At output 1 ps Differential Interpair Skew At output 35 ps

EQUALIZATION PERFORMANCE

High Frequency Gain Boost frequency = 1.5 GHz 16 dB

INPUT CHARACTERISTICS

Input Voltage Swing Differential 150 1200 mV Input Common-Mode Voltage (V

OUTPUT CHARACTERISTICS

High Voltage Level Single-ended high speed channel AVCC − 200 AVCC + 10 mV Low Voltage Level Single-ended high speed channel AVCC − 600 AVCC − 400 mV Rise/Fall time (20% to 80%) DR = 3 Gbps 75 190 ps

TERMINATION

Input Termination Resistance Single-ended 50 Ω Output Termination Resistance Single-ended 50 Ω

LOSS OF SIGNAL (LOS) DETECT

Frequency Cutoff LOS_FC (see Figure 31) 5 MHz Amplitude Threshold

) AVCC − 800 AVCC mV

ICM

Clock rate = 300 MHz, LOS_THR = 00

35 mV

(see Figure 31)

AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DDC CHANNELS

Input Capacitance, C Input Low Voltage, VIL 0.5 V Input High Voltage, VIH 0.7 × AMUXVCC V Output Low Voltage, VOL IOL = 5 mA 0.25 0.4 V Rise Time 10% to 90%, C Fall Time 90% to 10%, C Leakage VIN = 5.0 V 10 μA

DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz 5 15 pF

AUX

= 50 pF, R

LOAD

= 50 pF, R

LOAD

= 2 kΩ 1.45 μs

PULL-UP

= 2 kΩ 20 250 ns

PULL-UP

Rev. A | Page 3 of 28

ADV3002

Parameter Test Conditions/Comments Min Typ Max Unit

CEC CHANNEL

Input Capacitance, C Input Low Voltage, VIL 0.8 V Input High Voltage, VIH 2.0 V Output Low Voltage, VOL IOL = 3 mA 0.1 0.6 V Output High Voltage, VOH 2.5 V Rise Time

Fall Time

Pull-Up Resistance 26 kΩ Leakage Off-leakage test conditions1 1.8 μA

HOT PLUG DETECT

Output Low Voltage, VOL RPU = 800 Ω 0.25 0.4 V

1

Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3c Section 8, Test ID 8-14. To measure CEC leakage, connect the CEC line to

3.63 V via 26 kΩ ± 5 % resistor with an ammeter in series and with the power mains disabled.

POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

POWER SUPPLY

AVCC Operating range (3.3 V ± 10%) 3.0 3.3 3.6 V P5V_x 4.7 5 5.5 V AMUXVCC Output voltage, total load1 = 50 mA 4.0 5 5.5 V

QUIESCENT CURRENT

AVCC Outputs disabled 40 60 mA Outputs enabled 170 150 mA P5V_x Main power on 0.5 10 mA Main power off 20 30 mA AMUXVCC Main power on 20 30 mA

Main power off 0.5 10 mA POWER DISSIPATION Outputs disabled 232 381 mW Outputs enabled 661 885 mW I2C® AND LOGIC INPUTS2

Input High Voltage, VIH 2.4 V

Input Low Voltage, VIL 1.0 V I2C AND LOGIC OUTPUTS2

Output High Voltage, VOH I

Output Low Voltage, VOL I

1

The total load current includes current drawn by the ADV3002 as well as external devices powered from the AMUXVCC supply.

2

The ADV3002 I2C control and logic input pins are listed as Control in the Type column in . I2C pins are 5 V tolerant and based on the 3.3 V I2C bus specification. Table 6

DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz 5 15 pF

AUX

10% to 90%, C

= 3 kΩ

R

PULL-UP

90% to 10%, C R

= 3 kΩ

PULL-UP

OH

OL

= 1500 pF, R

LOAD

= 1500 pF, R

LOAD

= 27 kΩ; or C

PULL-UP

= 27 kΩ; or C

PULL-UP

= 7200 pF,

LOAD

= 7200 pF,

LOAD

= −2 mA AVCC V

= +2 mA 0.4 V

75 250 μs

0.2 50 μs

Rev. A | Page 4 of 28

ADV3002

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

AVCC to AVEE 3.7 V P5V_x 5.8 V AMUXVCC AVCC − 0.3 V < AMUXVCC < 5.8 V Internal Power Dissipation 1.2 W TMDS Single-Ended Input

Voltage

TMDS Differential Input

Voltage Voltage at TMDS Output V DDC Input Voltage AVEE − 0.3 V < VIN < AMUXVCC + 0.3 V CEC Input Voltage AVEE − 0.3 V < VIN < 4.0 V I2C Logic Input Voltage

(EDID_SCL, EDID_SDA,

I2C_SCL, I2C_SDA) Parallel Input Voltage

(I2C_ADDR[1:0],

RESETB) Parallel Input Voltage

(SEL[1:0], TX_EN) Storage Temperature Range −65°C to +125°C Operating Temperature

Range Junction Temperature 150°C ESD Protection (HBM) on

HDMI Input Pins ESD Protection (HBM) on

All Other Pins

AVC C − 1.4 V < V

2.0 V

< 3.7 V

OUT

AVEE − 0.3 V < V

AVEE − 0.3V < V

0°C to +85°C

±8 kV

±2.5 kV

< AVCC + 0.3 V

IN

< 4.0 V

IN

< AMUXVCC + 0.3 V

IN

< AVCC + 0.3 V

IN

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions; a device soldered in a 4-layer JEDEC circuit board for surface-mount packages. θ

is specified for the exposed pad soldered to the circuit board

JC

with no airflow.

Table 5. Thermal Resistance

Package Type θJA θ

80-Lead LQFP (ST-80-2) 51.3 15.3 °C/W

Unit

JC

ESD CAUTION

Rev. A | Page 5 of 28

ADV3002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

P5V_A79P5V_B78P5V_C77P5V_D76DDC_SDA_A75DDC_SCL_A74DDC_SDA_B73DDC_SCL_B72DDC_SDA_C71DDC_SCL_C70DDC_SDA_D69DDC_SCL_D68DDC_SDA_COM67DDC_SCL_COM66CEC_IN65CEC_OUT64AMUXVCC63EDID_ENABLE62EDID_SDA61EDID_SCL

80

39

40

I2C_ADDR1

I2C_SDA

60

IN_C_DATA2+

59

IN_C_DATA2–

58

HPD_C

57

IN_C_DATA1+

56

IN_C_DATA1–

55

HPD_D

54

IN_C_DATA0+

53

IN_C_DATA0–

52

AVC C

51

IN_C_CLK+

50

IN_C_CLK–

49

I2C_ADDR0

48

IN_D_DATA2+

47

IN_D_DATA2–

46

AVE E

45

IN_D_DATA1+

44

IN_D_DATA1–

43

AVC C

42

IN_D_DATA0+

41

IN_D_DATA0–

IN_B_CLK–

IN_B_CLK+

HPD_B

IN_B_DATA0–

IN_B_DATA0+

HPD_A

IN_B_DATA1–

IN_B_DATA1+

AVC C

IN_B_DATA2–

IN_B_DATA2+

SEL0

IN_A_CLK–

IN_A_CLK+

SEL1

IN_A_DATA0–

IN_A_DATA0+

AVC C

IN_A_DATA1–

IN_A_DATA1+

1

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

24

25

23

AVE E

TX_EN

IN_A_DATA2+

OUT_DATA2+

IN_A_DATA2–

26

27

OUT_DATA2–

ADV3002

(Not to Scale)

28

29

I2C_SCL

OUT_DATA1+

TOP VIEW

30

31

AVE E

OUT_DATA1–

33

34

35

36

32

AVC C

OUT_CLK+

OUT_DATA0–

OUT_DATA0+

38

37

RESETB

OUT_CLK–

IN_D_CLK–

IN_D_CLK+

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type Description

1 IN_B_CLK− TMDS High Speed TMDS Input B Clock Complement. 2 IN_B_CLK+ TMDS High Speed TMDS Input B Clock. 3 HPD_B HPD Hot Plug Detect Output B. 4 IN_B_DATA0− TMDS High Speed TMDS Input B Data Complement. 5 IN_B_DATA0+ TMDS High Speed TMDS Input B Data. 6 HPD_A HPD Hot Plug Detect Output A. 7 IN_B_DATA1− TMDS High Speed TMDS Input B Data Complement. 8 IN_B_DATA1+ TMDS High Speed TMDS Input B Data. 9, 18, 33, 43, 52 AVCC Power Positive Analog Supply 3.3 V. 10 IN_B_DATA2− TMDS High Speed TMDS Input B Data Complement. 11 IN_B_DATA2+ TMDS High Speed TMDS Input B Data. 12 SEL0 Control Channel Select Parallel Control LSB. 13 IN_A_CLK− TMDS High Speed TMDS Input A Clock Complement. 14 IN_A_CLK+ TMDS High Speed TMDS Input A Clock. 15 SEL1 Control Channel Select Parallel Control MSB. 16 IN_A_DATA0− TMDS High Speed TMDS Input A Complement. 17 IN_A_DATA0+ TMDS High Speed TMDS Input A Data. 19 IN_A_DATA1− TMDS High Speed TMDS Input A Data Complement. 20 IN_A_DATA1+ TMDS High Speed TMDS Input A Data. 21, 30, 46 AVEE Power Negative Analog Supply 0.0 V. 22 IN_A_DATA2− TMDS High Speed TMDS Input A Data Complement. 23 IN_A_DATA2+ TMDS High Speed TMDS Input A Data.

Rev. A | Page 6 of 28

07905-002

ADV3002

Pin No. Mnemonic Type Description

24 TX_EN Control TMDS Output Enable Parallel Control. 25 OUT_DATA2+ TMDS High Speed TMDS Output. 26 OUT_DATA2− TMDS High Speed TMDS Output Complement. 27 I2C_SCL Control Serial Control Clock Input. 28 OUT_DATA1+ TMDS High Speed TMDS Output. 29 OUT_DATA1− TMDS High Speed TMDS Output Complement. 31 OUT_DATA0+ TMDS High Speed TMDS Output. 32 OUT_DATA0− TMDS High Speed TMDS Output Complement. 34 OUT_CLK+ TMDS High Speed TMDS Output Clock. 35 OUT_CLK− TMDS High Speed TMDS Output Clock Complement. 36 RESETB Control Configuration Registers Reset. Active low. 37 IN_D_CLK− TMDS High Speed TMDS Input D Clock Complement. 38 IN_D_CLK+ TMDS High Speed TMDS Input D Clock. 39 I2C_ADDR1 Control Serial Control External Address MSB. 40 I2C_SDA Control Serial Control Data Input/Output. 41 IN_D_DATA0− TMDS High Speed TMDS Input D Data Complement. 42 IN_D_DATA0+ TMDS High Speed TMDS Input D Data. 44 IN_D_DATA1− TMDS High Speed TMDS Input D Data Complement. 45 IN_D_DATA1+ TMDS High Speed TMDS Input D Data. 47 IN_D_DATA2− TMDS High Speed TMDS Input D Data Complement. 48 IN_D_DATA2+ TMDS High Speed TMDS Input D Data. 49 I2C_ADDR0 Control Serial Control External Address LSB. 50 IN_C_CLK− TMDS High Speed TMDS Input C Clock Complement. 51 IN_C_CLK+ TMDS High Speed TMDS Input C Clock. 53 IN_C_DATA0− TMDS High Speed TMDS Input C Data Complement. 54 IN_C_DATA0+ TMDS High Speed TMDS Input C Data. 55 HPD_D HPD Hot Plug Detect Output D. 56 IN_C_DATA1− TMDS High Speed TMDS Input C Data Complement. 57 IN_C_DATA1+ TMDS High Speed TMDS Input C Data. 58 HPD_C HPD Hot Plug Detect Output C. 59 IN_C_DATA2− TMDS High Speed TMDS Input C Data Complement. 60 IN_C_DATA2+ TMDS High Speed TMDS Input C Data. 61 EDID_SCL Control External EDID EEPROM Serial Interface Clock. 62 EDID_SDA Control External EDID EEPROM Serial Interface Data. 63 EDID_ENABLE Control EDID Replication Enable. 64 AMUXVCC Power Positive Power Supply 5.0 V. 65 CEC_OUT CEC Consumer Electronics Control Output. 66 CEC_IN CEC Consumer Electronics Control Input. 67 DDC_SCL_COM DDC Display Data Channel Serial Clock Common Input/Output. 68 DDC_SDA_COM DDC Display Data Channel Serial Data Common Input/Output. 69 DDC_SCL_D DDC Display Data Channel Serial Clock Input/Output D. 70 DDC_SDA_D DDC Display Data Channel Serial Data Input/Output D. 71 DDC_SCL_C DDC Display Data Channel Serial Clock Input/Output C. 72 DDC_SDA_C DDC Display Data Channel Serial Data Input/Output C. 73 DDC_SCL_B DDC Display Data Channel Serial Clock Input/Output B. 74 DDC_SDA_B DDC Display Data Channel Serial Data Input/Output B. 75 DDC_SCL_A DDC Display Data Channel Serial Clock Input/Output B. 76 DDC_SDA_A DDC Display Data Channel Serial Data Input/Output A. 77 P5V_D Power 5 V HDMI Supply from Source D. 78 P5V_C Power 5 V HDMI Supply from Source C. 79 P5V_B Power 5 V HDMI Supply from Source B. 80 P5V_A Power 5 V HDMI Supply from Source A.

Rev. A | Page 7 of 28

ADV3002

V

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 3 Gbps, TMDS outputs terminated with external 50  resistors to 3.3 V, unless otherwise noted.

HDMI CABLE

DIGITAL

PATTERN

GENERATOR

ADV3002

EVALUATIO N

BOARD

SMA COAX CABLE

SERIAL DATA

ANALYZER

REFERENCE EYE DI AGRAM AT TP1

Figure 3. Test Circuit for Eye Diagrams

250mV/DI

0.167UI/DI V AT 2.25Gb ps

Figure 4. Eye Diagram at TP2 for 2 Meter Cable, Data Rate = 2.25 Gbps

TP1 TP2 TP3

250mV/DI

07905-022

0.167UI/DI V AT 2.25Gbps

Figure 6. Eye Diagram at TP3 for 2 Meter Cable, Data Rate = 2.25 Gbps

07905-021

07905-024

250mV/DIV

0.167UI/DIV AT 3.0Gbps

Figure 5. Eye Diagram at TP2 for 2 Meter Cable, Data Rate = 3 Gbps

07905-205

250mV/DIV

0.167UI/DIV AT 3.0Gbps

Figure 7. Eye Diagram at TP3 for 2 Meter Cable, Data Rate = 3 Gbps

07905-207

Rev. A | Page 8 of 28

ADV3002

V

TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 3 Gbps, TMDS outputs terminated with external 50  resistors to 3.3 V, unless otherwise noted.

250mV/DI

0.167UI/DI V AT 2.25Gb ps

07905-023

Figure 8. Eye Diagram at TP2 for 20 Meter 24 AWG Cable,

Data Rate = 2.25 Gbps

250mV/DIV

0.167UI/DIV AT 3.0Gbps

07905-209

Figure 9. Eye Diagram at TP2 for15 Meter 24 AWG Cable, Data Rate = 3 Gbps

250mV/DI

0.167UI/DI V AT 2.25Gbps

Figure 10. Eye Diagram at TP3 for 20 Meter 24 AWG Cable,

Data Rate = 2.25 Gbps

250mV/DIV

0.167UI/DIV AT 3.0Gbps

Figure 11. Eye Diagram at TP3 for 15 Meter 24 AWG Cable,

Data Rate = 3 Gbps

07905-025

07905-211

Rev. A | Page 9 of 28

ANALOG DEVICES ADV3002 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TMDS PERFORMANCE SPECIFICATIONS

AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS

POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS