ANALOG DEVICES ADUM3440 Service Manual

Quad Channel, High Speed

Data Sheet

FEATURES

Low power operation

5 V operation

1.7 mA per channel maximum @ 0 Mbps to 2 Mbps 68 mA per channel maximum @ 150 Mbps

3.3 V operation

1.0 mA per channel maximum @ 0 Mbps to 2 Mbps 33 mA per channel maximum @ 150 Mbps

Bidirectional communication

3.3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 150 Mbps (NRZ) Precise timing characteristics

5 ns maximum pulse width distortion

5 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body package

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V

= 560 V peak

IORM

APPLICATIONS

High speed multichannel isolation SPI interface/data converter isolation Instrumentation

Digital Isolators

ADuM3440/ADuM3441/ADuM3442

FUNCTIONAL BLOCK DIAGRAMS

V

GND

DD1

V

1 2

1

3

V

V V

NC

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

ENCODE DECODE

ID

7 8

1

ADuM3440

Figure 1. ADuM3440 Functional Block Diagram

V

GND

V

GND

DD1

V V

V

1 2

1

3

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

DECODE ENCODE

OD

7

E1

8

1

ADuM3441

Figure 2. ADuM3441 Functional Block Diagram

V

GND

V V

GND

DD1

V V

V

1 2

1

3

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

OC

6

DECODE ENCODE

OD

7

E1

8

1

ADuM3442

Figure 3. ADuM3442 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

06837-001

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

V

E2

9

GND

2

06837-002

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

V

E2

9

GND

2

06837-003

GENERAL DESCRIPTION

The ADuM344x1 are four channel, digital isolators based on the Analog Devices, Inc., iCoupler® technology supporting data rates up to 150 Mbps. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM344x isolators provide four independent isolation channels in a variety of channel configurations (see the Ordering Guide). The ADuM344x operates with the supply voltage on either side ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. In addition, the ADuM344x provides low pulse width distortion and tight channel-to-channel matching. Unlike other optocoupler alternatives, the ADuM344x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during the power-up/power-down condition.

ADuM3440/ADuM3441/ADuM3442 Data Sheet

REVISION HISTORY

2/12—Rev. C to Rev. D

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 18

Updated Outline Dimensions ....................................................... 21

1/09—Rev. B to Rev. C

Change to Propagation Delay Parameter (Table 1) ......................

Change to Propagation Delay Parameter (Table 2) ...................... 5

Change to Propagation Delay Parameter (Table 3) ...................... 8

3

Absolute Maximum Ratings ......................................................... 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13

Typical Performance Characteristics ........................................... 16

Applications Information .............................................................. 18

PC Board Layout ........................................................................ 18

Propagation Delay-Related Parameters ................................... 18

System-Level ESD Considerations and Enhancements ........ 18

DC Correctness and Magnetic Field Immunity........................... 18

Power Consumption .................................................................. 19

Insulation Lifetime ..................................................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

9/08—Rev. A to Rev. B

Changes to Pulse Width Distortion, |t

PLH

− t

| Parameter and

PHL

Channel-to-Channel Matching, Codirectional Channels

Parameter, Table 1 ............................................................................. 3

Changes to Pulse Width Distortion, |t

PLH

− t

| Parameter and

PHL

Channel-to-Channel Matching, Codirectional Channels

Parameter, Table 2 ............................................................................. 5

Changes to Pulse Width Distortion, |t

PLH

− t

| Parameter and

PHL

Channel-to-Channel Matching, Codirectional Channels

Parameter, Table 3 ............................................................................. 8

5/08—Rev. 0 to Rev. A

Changes to Ordering Guide .......................................................... 21

11/07—Rev. 0: Initial Version

Rev. D | Page 2 of 24

Data Sheet ADuM3440/ADuM3441/ADuM3442

DDO (Q)

DD1

DD1 (Q)

V

DD1

Supply Current

I

DD1 (150)

120

220

mA

75 MHz logic signal frequency

V

DD1

Supply Current

I

DD1 (Q)

2.8

3.6

mA

DC to 1 MHz logic signal frequency

DD1

DD1 (150)

DD1

DD2

DD1 (Q)

DD2 (Q)

V

DD1

or V

DD2

Supply Current

I

DD1 (150)

, I

DD2 (150)

83

130

mA

75 MHz logic signal frequency

E1

DD1

DD2

EL

DD2

OCL

ODL

IxL

PHL

PLH

Propagation Delay Skew6

t

PSK

12

ns

CL = 15 pF, CMOS signal levels

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM3440, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

DD2

150 Mbps

V

Supply Current I

DD2

ADuM3441, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD2

150 Mbps

V

Supply Current I

V

Supply Current I

DD2

ADuM3442, Total Supply Current, Four Channels1

DC to 2 Mbps

V

or V

Supply Current I

150 Mbps

DDI (Q)

DD2 (Q)

DD2 (150)

DD2 (Q)

DD2 (150)

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications

DD2

= 25°C, V

A

DD1

= V

DD2

= 5 V.

0.75 1.3 mA

0.5 1.2 mA

3 3.9 mA DC to 1 MHz logic signal frequency 2 3 mA DC to 1 MHz logic signal frequency

47 55 mA 75 MHz logic signal frequency

2.3 2.9 mA DC to 1 MHz logic signal frequency

101 165 mA 75 MHz logic signal frequency 65 80 mA 75 MHz logic signal frequency

, I

2.5 3.5 mA DC to 1 MHz logic signal frequency

For All Models

Input Currents IIA, IIB, IIC,

, IE1, I

I

ID

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

VIH, V VIL, V

OAH

V

OCH

, V , V

E2

EH

,

OBH

ODH

(V

Logic Low Output Voltages V

, V

,

OAL

OBL

, V

V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

−10 +0.01 +10 µA

0 ≤ VIA, VIB, VIC, VID ≤ V 0

≤ V

, VE2 ≤ V

2.0 V

0.8 V (V

DD1

V

DD2

DD1

V

5.0 V I

or

) − 0.1

or

4.8 V IOx = −4 mA, VIx = V

) − 0.4

= −20 µA, VIx = V

Ox

0.0 0.1 V IOx = 20 µA, VIx = V

or V

IxH

IxL

DD1

SWITCHING SPECIFICATIONS

Minimum Pulse Width2 PW 6.67 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 150 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

5

|

, t

20 32 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

5

Channel-to-Channel Matching,

Opposing Directional Channels

5

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

or V

DD2

,

Rev. D | Page 3 of 24

ADuM3440/ADuM3441/ADuM3442 Data Sheet

DDI (D)

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Disable Propagation Delay

t

, t

PHZ

PLH

(High/Low to High Impedance)

Output Enable Propagation Delay

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output

7

|CM

| 25 35 kV/µs VIx = V

H

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.196 mA/Mbps

I

0.1 mA/Mbps

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

6 8 ns CL = 15 pF, CMOS signal levels

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DDO

Rev. D | Page 4 of 24

Data Sheet ADuM3440/ADuM3441/ADuM3442

DDI (Q)

DDO (Q)

DD2

DD2 (Q)

150 Mbps

DD2

DD2 (150)

DC to 2 Mbps

DD2

DD2 (Q)

DD2

DD2 (150)

EH

EL

OCH

ODH

DD2

Logic Low Output Voltages

V

, V

,

0.0

0.1 V IOx = 20 µA, VIx = V

IxL

PHL

PLH

PHL

4

PSK

Codirectional Channels6

Channel-to-Channel Matching,

t

5 ns

CL = 15 pF, CMOS signal levels

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ V over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM3440, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

V

Supply Current I

DD1

V

Supply Current I

ADuM3441, Total Supply Current, Four Channels1

V

Supply Current I

DD1

V

Supply Current I

150 Mbps

V

Supply Current I

DD1

V

Supply Current I

ADuM3442, Total Supply Current, Four Channels1

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

150 Mbps

V

or V

DD1

Supply Current I

DD2

For All Models

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

(V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

SWITCHING SPECIFICATIONS

Minimum Pulse Width2 PW 6.67 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 150 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay4 t

Pulse Width Distortion, |t

− t

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

DD1 (Q)

DD1 (150)

DD1 (Q)

DD1 (150)

DD1 (Q)

DD1 (150)

, IE1, I

I

ID

VIH, V VIL, V

OAH

V

OAL

V

OCL

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

16 ns CL = 15 pF, CMOS signal levels

t

PSKCD

≤ 3.6 V, 3.0 V ≤ V

DD1

≤ 3.6 V. All minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 3.3 V.

DD2

0.43 0.90 mA

0.3 0.60 mA

1.7 2.4 mA DC to 1 MHz logic signal frequency

1.2 1.7 mA DC to 1 MHz logic signal frequency

63 110 mA 75 MHz logic signal frequency 17 25 mA 75 MHz logic signal frequency

1.6 2.2 mA DC to 1 MHz logic signal frequency

1.3 1.9 mA DC to 1 MHz logic signal frequency

52 80 mA 75 MHz logic signal frequency 29 40 mA 75 MHz logic signal frequency

, I

1.5 2.0 mA DC to 1 MHz logic signal frequency

DD2 (Q)

, I

40 66 mA 75 MHz logic signal frequency

DD2 (150)

−10 +0.01 +10 µA

E2

0

≤ V

IA

0

≤ V

E1

, VIB, VIC, VID ≤ V

, V

≤ V

or V

E2

DD1

DD2

or V

DD2

1.6 V

0.4 V

, V

,

(V

or

, V

OBH

OBL

ODL

DD1

V

DD1

V

DD2

3.0 V IOx = −20 µA, VIx = V

) − 0.1

2.8 V I

or

Ox

) − 0.4

= −4 mA, VIx = V

IxH

IxL

, t

20 36 ns CL = 15 pF, CMOS signal levels

2 ns CL = 15 pF, CMOS signal levels

,

Opposing Directional Channels5

PSKOD

Rev. D | Page 5 of 24

ADuM3440/ADuM3441/ADuM3442 Data Sheet

DDI (D)

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Disable Propagation Delay

t

, t

PHZ

PLH

(High/Low to High Impedance)

Output Enable Propagation Delay

t

, t

PZH

PZL

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

|CM

| 25 35 kV/µs VIx = V

H

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.

DD2

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.076 mA/Mbps

I

0.028 mA/Mbps

signal to the 50% level of the rising edge of the VOx signal.

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

6 8 ns CL = 15 pF, CMOS signal levels

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DDO

Rev. D | Page 6 of 24

Data Sheet ADuM3440/ADuM3441/ADuM3442

5 V/3.3 V Operation

0.75

1.3

mA

DDO (Q)

DD1

DD1 (Q)

DD2

DD2 (Q)

150 Mbps

5 V/3.3 V Operation

17

25

mA

75 MHz logic signal frequency

DD1

DD1 (Q)

DD2

DD2 (Q)

5 V/3.3 V Operation

101

165

mA

75 MHz logic signal frequency

DD2

DD2 (150)

DD1

DD1 (Q)

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OR 3.3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3.3 V operation: 4.5 V ≤ V

3.0 V ≤ V unless otherwise noted. All typical specifications are at T

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,

DD2

= 25°C; V

A

= 3.3 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

3.3 V/5 V Operation 0.43 0.9 mA

Output Supply Current per Channel, Quiescent I

5 V/3.3 V Operation 0.3 0.7 mA

3.3 V/5 V Operation 0.5 1.2 mA

ADuM3440, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

5 V/3.3 V Operation 3 3.9 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 1.7 2.4 mA DC to 1 MHz logic signal frequency

V

Supply Current I

5 V/3.3 V Operation 1.2 1.7 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 2 3 mA DC to 1 MHz logic signal frequency

DDI (Q)

≤ 5.5 V, 3.0 V ≤ V

DD1

= 5 V or V

DD2

= 5 V, V

DD1

≤ 3.6 V; 3 V/5 V operation:

DD2

= 3.3 V.

DD2

V

Supply Current I

DD1

DD1 (150)

5 V/3.3 V Operation 120 220 mA 75 MHz logic signal frequency

3.3 V/5 V Operation 63 110 mA 75 MHz logic signal frequency

V

Supply Current I

DD2

DD2 (150)

3.3 V/5 V Operation 47 55 mA 75 MHz logic signal frequency

ADuM3441, Total Supply Current, Four C hannels1

DC to 2 Mbps

V

Supply Current I

5 V/3.3 V Operation 2.8 3.6 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 1.6 2.2 mA DC to 1 MHz logic signal frequency

V

Supply Current I

5 V/3.3 V Operation 1.3 1.9 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 2.3 2.9 mA DC to 1 MHz logic signal frequency

150 Mbps

V

Supply Current I

DD1

DD1 (150)

3.3 V/5 V Operation 52 80 mA 75 MHz logic signal frequency

V

Supply Current I

5 V/3.3 V Operation 29 40 mA 75 MHz logic signal frequency

3.3 V/5 V Operation 65 80 mA 75 MHz logic signal frequency

ADuM3442, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

5 V/3.3 V Operation 2.5 3.5 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 1.5 2.0 mA DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

DD2 (Q)

5 V/3.3 V Operation 1.5 2.0 mA DC to 1 MHz logic signal frequency

3.3 V/5 V Operation 2.5 3.5 mA DC to 1 MHz logic signal frequency

Rev. D | Page 7 of 24

ADuM3440/ADuM3441/ADuM3442 Data Sheet

DD1

DD1 (150)

DD2

DD2 (150)

For All Models

0 ≤

DD1

DD2

Logic High Input Threshold

VIH, V

EH

EL

3.3 V/5 V Operation

0.4 V

OCH

ODH

DD2

Logic Low Output Voltages

V

, V

OCL

ODL

0.0

0.1 V IOx = 20 µA, VIx = V

IxL

SWITCHING SPECIFICATIONS

PHL

PLH

4

PSK

Output Rise/Fall Time (10% to 90%)

CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity

|CML|

25

35 kV/µs

VIx = 0 V, VCM = 1000 V,

3.3 V/5 V Operation

1.1 Mbps

Parameter Symbol Min Typ Max Unit Test Conditions

150 Mbps

V

Supply Current I

5 V/3.3 V Operation 83 130 mA 75 MHz logic signal frequency

3.3 V/5 V Operation 40 66 mA 75 MHz logic signal frequency

V

Supply Current I

5 V/3.3 V Operation 40 66 mA 75 MHz logic signal frequency

3.3 V/5 V Operation 83 130 mA 75 MHz logic signal frequency

Input Currents IIA, IIB, IIC,

, IE1, I

I

ID

−10 +0.01 +10 µA

E2

0 ≤ VIA,VIB, VIC,VID ≤ V

VE1,VE2 ≤ V

or V

DD1

or V

5 V/3.3 V Operation 2.0 V

3.3 V/5 V Operation 1.6 V

Logic Low Input Threshold

VIL, V

5 V/3.3 V Operation 0.8 V

Logic High Output Voltages V

(V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

, V

,

(V

or

(V

or

OAH

OBH

, V

V

OAL

OBL,

V

, V

DD1

) − 0.1

V

or

DD1

) − 0.4

V

DD2

V (V

V

DD1

DD2

)

) − 0.2

V IOx = −20 µA, VIx = V

V I

or

Ox

= −4 mA, VIx = V

IxH

IxL

Minimum Pulse Width2 PW 6.67 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 150 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

|

, t

20 35 ns CL = 15 pF, CMOS signal levels

PWD

0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing Directional Channels

6

5

15 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

For All Models

Output Disable Propagation Delay

t

PHZ

, t

6 8 ns CL = 15 pF, CMOS signal levels

PLH

(High/Low to High Impedance)

Output Enable Propagation Delay

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance to High/Low)

tR/tF 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity

at Logic High Output

7

|CM

| 25 35 kV/µs VIx = V

H

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

,

DD2

at Logic Low Output

Refresh Rate fr

5 V/3.3 V Operation 1.2 Mbps

Input Dynamic Supply Current per Channel8 I

5 V/3.3 V Operation 0.196 mA/Mbps

3.3 V/5 V Operation 0.076 mA/Mbps

Output Dynamic Supply Current per Channel8

5 V/3.3 V Operation 0.028 mA/Mbps

3.3 V/5 V Operation 0.01 mA/Mbps

7

DDI (D)

I

DDO (D)

Rev. D | Page 8 of 24

transient magnitude = 800 V

ANALOG DEVICES ADUM3440 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OR 3.3 V/5 V OPERATION