ANALOG DEVICES ADuM3401 Service Manual

Quad-Channel, Digital Isolators,

Enhanced System-Level ESD Reliability

Data Sheet

FEATURES

Enhanced system-level ESD performance per IEC 61000-4-x Low power operation

5 V operation

1.4 mA per channel maximum @ 0 Mbps to 2 Mbps

4.3 mA per channel maximum @ 10 Mbps 34 mA per channel maximum @ 90 Mbps

3 V operation

0.9 mA per channel maximum @ 0 Mbps to 2 Mbps

2.4 mA per channel maximum @ 10 Mbps

20 mA per channel maximum @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body, RoHS-compliant package

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

= 560 V peak

V

IORM

APPLICATIONS

General-purpose multichannel isolation SPI/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation

FUNCTIONAL BLOCK DIAGRAMS

ADuM3400/ADuM3401/ADuM3402

GENERAL DESCRIPTION

The ADuM340x1 are 4-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

iCoupler devices remove the design difficulties commonly associated with optocouplers. Typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM340x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. The ADuM340x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

In comparison to the ADuM140x isolators, the ADuM340x isolators contain various circuit and layout changes to provide increased capability relative to system-level IEC 61000-4-x testing (ESD/burst/surge). The precise capability in these tests for either the ADuM140x or ADuM340x products is strongly determined by the design and layout of the user’s board or module. For more information, see the AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products.

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.

V

GND

DD1

1 2

1

3

V

IA

V

4

IB

5

V

IC

6

V

ID

7

NC

8

1

ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

05985-001

Figure 1. ADuM3400 Functional Block Diagram

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

1

V

DD1

2

GND

1

3

ENCODE DECODE

V

IA

V

4

ENCODE DECODE

IB

5

ENCODE DECODE

V

IC

6

OD

7

V

E1

8

1

DECODE ENCODE

V

GND

Figure 2. ADuM3401 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

V

E2

9

GND

2

05985-002

V

GND

1

DD1

2

1

3

ENCODE DECODE

V

IA

V

4

ENCODE DECODE

IB

5

OC

6

OD

7

V

E1

8

1

DECODE ENCODE DECODE ENCODE

V V

Figure 3. ADuM3402 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

V

E2

9

GND

2

05985-003

ADuM3400/ADuM3401/ADuM3402 Data Sheet

REVISION HISTORY

2/12—Rev. A to Rev. B

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 20

6/07—Rev. 0 to Rev. A

Updated VDE Certification Throughout ...................................... 1

Changes to Features, General Description, Note 1, Figure 1,

Figure 2, and Figure 3....................................................................... 1

Changes to Regulatory Information Section .............................. 12

Changes to Table 7 and Figure 4 Caption .................................... 13

Added Table 10; Renumbered Sequentially ................................ 14

Added Insulation Lifetime Section .............................................. 22

Inserted Figure 21, Figure 22, and Figure 23 .............................. 22

Changes to Ordering Guide .......................................................... 23

3/06—R

evision 0: Initial Version

Rev. B | Page 2 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

DDI (Q)

Output Supply Current per Channel, Quiescent

I

DDO (Q)

0.29

0.35

mA

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

DD1

DD1 (90)

DD2

DD2 (90)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

V

DD2

Supply Current

I

DD2 (10)

4.4

6.5

mA

5 MHz logic signal freq.

DD1

DD1 (90)

DD2

DD2 (90)

DC to 2 Mbps

DD1

DD2

DD1 (Q)

DD2 (Q)

DD1

DD2

DD1 (10)

DD2 (10)

DD1

DD2

DD1 (90)

DD2 (90)

ID

E2

E1

DD1

DD2

EH

EL

OAH

OBH,

DD1

DD2

IxH

OCH

ODH

DD1

DD2

IxH

OAL

OBL,

IxL

OCL

ODL

IxL

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

ADuM3400, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

V

Supply Current I

90 Mbps (CRW Grade Only)

V

Supply Current I

V

Supply Current I

ADuM3401, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

DD2

= 5 V.

0.57 0.83 mA

2.9 3.5 mA DC to 1 MHz logic signal freq.

1.2 1.9 mA DC to 1 MHz logic signal freq.

9.0 11.6 mA 5 MHz logic signal freq.

3.0 5.5 mA 5 MHz logic signal freq.

72 100 mA 45 MHz logic signal freq. 19 36 mA 45 MHz logic signal freq.

2.5 3.2 mA DC to 1 MHz logic signal freq.

1.6 2.4 mA DC to 1 MHz logic signal freq.

7.4 10.6 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

V

Supply Current I

59 82 mA 45 MHz logic signal freq. 32 46 mA 45 MHz logic signal freq.

ADuM3402, Total Supply Current, Four Channels1

V

or V

Supply Current I

, I

2.0 2.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

or V

Supply Current I

, I

6.0 7.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

or V

Supply Current I

, I

51 62 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V V Logic Low Output Voltages V

V

I

, IE1, I VIH, V VIL, V

, V , V , V , V

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ V

, VE2 ≤ V

2.0 V

0.8 V

(V

or V

) − 0.1 5.0 V IOx = −20 µA, VIx = V

(V

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

or V

DD1

or V

,

DD2

Rev. B | Page 3 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

Propagation Delay4

t

PHL

, t

PLH

50

65

100

ns

CL = 15 pF, CMOS signal levels

PLH

PHL

4

PSK

PSKCD/OD

PHL

PLH

PHL

4

PSK

Maximum Data Rate3

90

120 Mbps

CL = 15 pF, CMOS signal levels

PHL

PLH

PHL

4

PSK

DDI (D)

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM340xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels

Pulse Width Distortion, |t Propagation Delay Skew5 t Channel-to-Channel Matching6 t

− t

|

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

ADuM340xBRW

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

− t

|

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

15 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

ADuM340xCRW

Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels

Propagation Delay4 t Pulse Width Distortion, |t

− t

|

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

For All Models

Output Disable Propagation Delay

10 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

(High/Low-to-High Impedance) Output Enable Propagation Delay

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output

7

| 25 35 kV/µs VIx = V

|CM

H

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8 I

0.20 mA/Mbps

0.05 mA/Mbps

Rev. B | Page 4 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DD2

propagation delay is

PLH

Rev. B | Page 5 of 24

ADuM3400/ADuM3401/ADuM3402 Data Sheet

DDI (Q)

DDO (Q)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

DD1

DD1 (90)

DD2

DD2 (90)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

90 Mbps (CRW Grade Only)

DD1

DD1 (90)

DD2

DD2 (90)

DD1

DD2

DD1 (Q)

DD2 (Q)

DD1

DD2

DD1 (10)

DD2 (10)

DD1

DD2

DD1 (90)

DD2 (90)

ID

E2

EH

EL

OAH

OBH,

DD1

DD2

IxH

OCH

ODH

DD1

DD2

IxH

OAL

OBL

IxL

OCL

ODL

IxL

PHL

PLH

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM3400, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

V

Supply Current I

90 Mbps (CRW Grade Only)

V

Supply Current I

V

Supply Current I

ADuM3401, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

V

Supply Current I

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.31 0.49 mA

0.19 0.27 mA

1.6 2.1 mA DC to 1 MHz logic signal freq.

0.7 1.2 mA DC to 1 MHz logic signal freq.

4.8 7.1 mA 5 MHz logic signal freq.

1.8 2.3 mA 5 MHz logic signal freq.

37 54 mA 45 MHz logic signal freq. 11 15 mA 45 MHz logic signal freq.

1.4 1.9 mA DC to 1 MHz logic signal freq.

0.9 1.5 mA DC to 1 MHz logic signal freq.

4.1 5.6 mA 5 MHz logic signal freq.

2.5 3.3 mA 5 MHz logic signal freq.

V

Supply Current I

V

Supply Current I

31 44 mA 45 MHz logic signal freq. 17 24 mA 45 MHz logic signal freq.

ADuM3402, Total Supply Current, Four Channels1

DC to 2 Mbps

V

or V

Supply Current I

, I

1.2 1.7 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

or V

Supply Current I

, I

3.3 4.4 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

or V

Supply Current I

, I

24 39 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

I

, IE1, I Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V V Logic Low Output Voltages V

V

VIH, V VIL, V

, V , V , V , V

0.2 0.4 V IOx = 4 mA, VIx = V

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ V

, VE2 ≤ V

E1

1.6 V

0.4 V

(V

or V

) − 0.1 3.0 V IOx = −20 µA, VIx = V

(V

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

, 0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

DD1

or V

SWITCHING SPECIFICATIONS

ADuM340xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

or V

DD2

,

DD2

DD1

Rev. B | Page 6 of 24

Data Sheet ADuM3400/ADuM3401/ADuM3402

PLH

PHL

4

PSK

PSKCD/OD

Minimum Pulse Width2

PW

100

ns

CL = 15 pF, CMOS signal levels

PHL

PLH

PHL

PSK

PHL

PLH

PHL

4

PSK

Channel-to-Channel Matching,

t

2

ns

CL = 15 pF, CMOS signal levels

Output Disable Propagation Delay

t

, t

6 8

ns

CL = 15 pF, CMOS signal levels

DDI (D)

Output Dynamic Supply Current per Channel8

I

DDO (D)

0.03 mA/Mbps

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM340xBRW

Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

ADuM340xCRW

Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t

Codirectional Channels6 Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 I

− t

|

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

− t

4

|

22 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

t

6

− t

|

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

16 ns CL = 15 pF, CMOS signal levels

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

6

7

PSKOD

PHZ

PLH

t

, t

PZH

PZL

|CM

| 25 35 kV/µs VIx = V

H

6 8 ns CL = 15 pF, CMOS signal levels

, VCM = 1000 V,

DD1/VDD2

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.10 mA/Mbps

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

Rev. B | Page 7 of 24

propagation delay is

PLH

ADuM3400/ADuM3401/ADuM3402 Data Sheet

DDI (Q)

DDO (Q)

DD1

DD1 (Q)

DD2

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

DD1

DD1 (10)

DD2

DD2 (10)

DD1

DD1 (90)

DD2

DD2 (90)

DD1

DD1 (Q)

DD2

DD2 (Q)

3 V/5 V Operation

1.6

2.4

mA

DC to 1 MHz logic signal freq.

DD1

DD1 (10)

DD2

DD2 (10)

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V

2.7 V ≤ V unless otherwise noted; all typical specifications are at T

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.57 0.83 mA 3 V/5 V Operation 0.31 0.49 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.29 0.27 mA 3 V/5 V Operation 0.19 0.35 mA

ADuM3400, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I 5 V/3 V Operation 2.9 3.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.6 2.1 mA DC to 1 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

= 5 V, V

DD1

≤ 3.6 V; 3 V/5 V operation:

DD2

= 3.0 V.

DD2

V

Supply Current I 5 V/3 V Operation 9.0 11.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.8 7.1 mA 5 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 1.8 2.3 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.0 5.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I 5 V/3 V Operation 72 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 37 54 mA 45 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 19 36 mA 45 MHz logic signal freq.

ADuM3401, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I 5 V/3 V Operation 2.5 3.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.4 1.9 mA DC to 1 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I 5 V/3 V Operation 7.4 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.6 mA 5 MHz logic signal freq.

V

Supply Current I 5 V/3 V Operation 2.5 3.3 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.4 6.5 mA 5 MHz logic signal freq.

Rev. B | Page 8 of 24

ANALOG DEVICES ADuM3401 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION