ANALOG DEVICES ADUM3300 Service Manual
Triple-Channel, Digital Isolators,
Enhanced System-Level ESD Reliability
Data Sheet
FEATURES
Enhanced system-level ESD performance per IEC 61000-4-x
Low power operation
5 V operation
2.0 mA per channel maximum @ 0 Mbps to 2 Mbps
4.1 mA per channel maximum @ 10 Mbps
36 mA per channel maximum @ 90 Mbps
3 V operation
1.0 mA per channel maximum @ 0 Mbps to 2 Mbps
2.8 mA per channel maximum @ 10 Mbps
17 mA per channel maximum @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body, RoHS-compliant package
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
V
= 560 V peak
IORM
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
ADuM3300/ADuM3301
GENERAL DESCRIPTION
The ADuM330x1 are 3-channel digital isolators based on the
Analog Devices, Inc. iCoupler® technology. Combining high
peed
s
CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocoupler devices.
iCoupler devices remove the design difficulties commonly
associated with optocouplers. Typical optocoupler concerns
regarding uncertain current transfer ratios, nonlinear transfer
functions, and temperature and lifetime effects are eliminated
with the simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM330x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). All models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. The
ADuM330x isolators have a patented refresh feature that ensures dc
correctness in the absence of input logic transitions and during
power-up/power-down conditions.
In comparison to ADuM130x isolators, ADuM330x isolators
contain various circuit and layout changes to provide increased
capability relative to system-level IEC 61000-4-x testing (ESD,
burst, and surge). The precise capability in these tests for either
the ADuM130x or ADuM330x products is strongly determined
by the design and layout of the user’s system.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
1
V
DD1
2
GND
1
ENCODE DECODE
3
ENCODE DECODE
4
ENCODE DECODE
5
6
7
8
GND
V
IA
V
IB
V
IC
NC
NC
1
Figure 1. ADuM3300 Functional Block Diagram
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16
V
DD2
15
GND
2
V
14
OA
13
V
OB
V
12
OC
11
NC
V
10
E2
9
GND
2
05984-001
V
GND
GND
1
DD1
2
1
V
IA
V
IB
V
OC
NC
V
E1
1
ENCODE DECODE
3
ENCODE DECODE
4
DECODE ENCODE
5
6
7
8
V
16
DD2
GND
15
V
14
OA
13
V
OB
V
12
IC
11
NC
10
V
E2
9
GND
Figure 2. ADuM3301 Functional Block Diagram
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
2
2
05984-002
ADuM3300/ADuM3301 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 5
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
Package Characteristics .............................................................10
Regulatory Information............................................................. 10
Insulation and Safety-Related Specifications.......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions......................... 13
Typical Performance Characteristics........................................... 15
Application Information................................................................ 17
PC Board Layout ........................................................................ 17
System-Level ESD Considerations and Enhancements ........ 17
Propagation Delay-Related Parameters................................... 17
DC Correctness and Magnetic Field Immunity........................... 17
Power Consumption .................................................................. 18
Insulation Lifetime..................................................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
2/12—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 17
Updated Outline Dimensions....................................................... 20
6/07—Rev. 0 to Rev. A
Updated VDE Certification Throughout...................................... 1
Changes to Features, General Description, and Note 1............... 1
Changes to Regulatory Information Section .............................. 10
Changes to DIN V VDE V 0884-10 (VDE V 0884-10)
Insulation Characteristics.............................................................. 11
Added Table 10 ............................................................................... 12
Added Insulation Lifetime Section .............................................. 19
3/06—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet ADuM3300/ADuM3301
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ V
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I
ADuM3300, Total Supply Current, Four Channels1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
ADuM3301, Total Supply Current, Four Channels1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
For All Models
Input Currents
I
I
Logic High Input Threshold
Logic Low Input Threshold
VIH, V
VIL, V
V
V
Logic Low Output Voltages
V
V
SWITCHING SPECIFICATIONS
ADuM330xARWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
PLH
− t
PHL
4
|
PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching6 t
≤ 5.5 V, 4.5 V ≤ V
DD1
0.66 0.97 mA
DDI (Q)
0.39 0.55 mA
DDO (Q)
2.4 3.3 mA DC to 1 MHz logic signal freq.
DD1 (Q)
1.1 2.1 mA DC to 1 MHz logic signal freq.
DD2 (Q)
7.0 8.1 mA 5 MHz logic signal freq.
DD1 (10)
2.7 3.6 mA 5 MHz logic signal freq.
DD2 (10)
54 77 mA 45 MHz logic signal freq.
DD1 (90)
15 31 mA 45 MHz logic signal freq.
DD2 (90)
2.0 3.1 mA DC to 1 MHz logic signal freq.
DD1 (Q)
1.6 2.3 mA DC to 1 MHz logic signal freq.
DD2 (Q)
5.5 6.9 mA 5 MHz logic signal freq.
DD1 (10)
3.9 5.4 mA 5 MHz logic signal freq.
DD2 (10)
41 57 mA 45 MHz logic signal freq.
DD1 (90)
28 41 mA 45 MHz logic signal freq.
DD2 (90)
, IIB, IIC,
IA
, IE1, I
ID
OAH
OCH
OAL
OCL
−10 +0.01 +10 μA
E2
2.0 V
EH
0.8 V
EL
(V
or
,
DD1
) − 0.1
V
DD2
(V
or
DD1
) − 0.4
V
DD2
0.0 0.1 V IOx = 20 μA, VIx = V
0.04 0.1 V IOx = 400 μA, VIx = V
, V
, V
, V
, V
OBH
ODH
OBL
ODL
,
0.2 0.4 V IOx = 4 mA, VIx = V
, t
50 65 100 ns CL = 15 pF, CMOS signal levels
PHL
PLH
50 ns CL = 15 pF, CMOS signal levels
PSK
50 ns CL = 15 pF, CMOS signal levels
PSKCD/OD
≤ 5.5 V; all minimum/maximum specifications apply
DD2
5.0 V I
4.8 V I
= 25°C, V
A
0 V ≤ V
0 V ≤ V
= −20 μA, VIx = V
Ox
= −4 mA, VIx = V
Ox
= V
DD1
, VIB, VIC, VID ≤ V
IA
, VE2 ≤ V
E1
DD1
IxL
IxL
DD2
or V
IxH
IxH
IxL
= 5 V.
Logic High Output Voltages
DD1
DD2
or V
DD2
,
Rev. B | Page 3 of 20
ADuM3300/ADuM3301 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM330xBRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
PLH
− t
PHL
4
|
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
6
ADuM330xCRWZ
Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
PLH
− t
PHL
4
|
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
6
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
7
7
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel8 I
Output Dynamic Supply Current per Channel8 I
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section.
See Figure through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through
Figure 12
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
t
PSK
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.
6
for total V
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
is the magnitude of the worst-case difference in t
DD1
and V
supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.
DD2
or t
PHL
PLH
, t
20 32 50 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 3 ns CL = 15 pF, CMOS signal levels
15 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
6 ns CL = 15 pF, CMOS signal levels
PSKOD
, t
18 27 32 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
10 ns CL = 15 pF, CMOS signal levels
PSK
2 ns CL = 15 pF, CMOS signal levels
t
PSKCD
5 ns CL = 15 pF, CMOS signal levels
t
PSKOD
t
PHZ
t
PZH
|CM
, t
, t
6 8 ns CL = 15 pF, CMOS signal levels
PLH
6 8 ns CL = 15 pF, CMOS signal levels
PZL
| 25 35 kV/μs
H
= V
or V
V
Ix
DD1
, VCM = 1000 V,
DD2
transient magnitude = 800 V
|CML| 25 35 kV/μs
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
0.20 mA/Mbps
DDI (D)
0.05 mA/Mbps
DDO (D)
ower Consumption
that is measured between units at the same operating temperature, supply voltages, and output load
. CML is the maximum common-mode voltage slew rate
DD2
Power Consumption
Figure 6
9
propagation delay is
PLH
Figure 8
Rev. B | Page 4 of 20
Data Sheet ADuM3300/ADuM3301
ELECTRICAL CHARACTERISTICS—3 V OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ V
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I
ADuM3300, Total Supply Current, Four Channels1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
ADuM3301, Total Supply Current, Four Channels1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM330xARWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
PLH
− t
PHL
4
|
Propagation Delay Skew5 t
Channel-to-Channel Matching6 t
≤ 3.6 V, 2.7 V ≤ V
DD1
0.37 0.57 mA
DDI (Q)
0.25 0.37 mA
DDO (Q)
1.4 1.9 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.7 1.2 mA DC to 1 MHz logic signal freq.
DD2 (Q)
3.8 5.3 mA 5 MHz logic signal freq.
DD1 (10)
1.5 2.1 mA 5 MHz logic signal freq.
DD2 (10)
28 41 mA 45 MHz logic signal freq.
DD1 (90)
8.2 11 mA 45 MHz logic signal freq.
DD2 (90)
1.1 1.6 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.9 1.4 mA DC to 1 MHz logic signal freq.
DD2 (Q)
3.0 4.1 mA 5 MHz logic signal freq.
DD1 (10)
2.2 2.9 mA 5 MHz logic signal freq.
DD2 (10)
22 31 mA 45 MHz logic signal freq.
DD1 (90)
15 21 mA 45 MHz logic signal freq.
DD2 (90)
, IIB, I
I
IA
I
, IE1, I
ID
VIH, V
VIL, V
V
OAH
V
OCH
V
OAL
V
OCL
−10 +0.01 +10 μA
IC,
E2
1.6 V
EH
0.4 V
EL
(V
, V
, V
, V
, V
OBH
ODH
OBL
ODL
or
,
DD1
) − 0.1
V
DD2
(V
or
DD1
) − 0.4
V
DD2
0.0 0.1 V IOx = 20 μA, VIx = V
,
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V I
, t
50 75 100 ns CL = 15 pF, CMOS signal levels
PHL
PLH
≤ 3.6 V; all minimum/maximum specifications apply
DD2
3.0 V I
2.8 V I
= 25°C, V
A
0 V ≤ V
0 V ≤ V
= −20 μA, VIx = V
Ox
= −4 mA, VIx = V
Ox
= 4 mA, VIx = V
Ox
= V
DD1
, VIB, VIC, VID ≤ V
IA
≤ V
E1,VE2
DD1
IxL
= 3.0 V.
DD2
or V
IxH
IxH
IxL
IxL
or V
DD1
DD2
Logic High Output Voltages
PWD 40 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels
PSK
50 ns CL = 15 pF, CMOS signal levels
PSKCD/OD
DD2
,
Rev. B | Page 5 of 20
ADuM3300/ADuM3301 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM330xBRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
PLH
− t
PHL
4
|
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
6
ADuM330xCRWZ
Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
PLH
− t
PHL
4
|
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
6
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
7
7
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel8 I
Output Dynamic Supply Current per Channel8 I
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section.
See Figure through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through
Figure 12
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
t
PSK
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.
6
for total V
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
is the magnitude of the worst-case difference in t
DD1
and V
supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.
DD2
or t
PHL
PLH
, t
20 38 50 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 3 ns CL = 15 pF, CMOS signal levels
22 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
6 ns CL = 15 pF, CMOS signal levels
PSKOD
, t
20 34 45 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
16 ns CL = 15 pF, CMOS signal levels
PSK
2 ns CL = 15 pF, CMOS signal levels
t
PSKCD
5 ns CL = 15 pF, CMOS signal levels
t
PSKOD
t
PHZ
t
PZH
|CM
, t
, t
H
6 8 ns CL = 15 pF, CMOS signal levels
PLH
6 8 ns CL = 15 pF, CMOS signal levels
PZL
| 25 35 kV/μs
= V
or V
V
Ix
DD1
, VCM = 1000 V,
DD2
transient magnitude = 800 V
|CML| 25 35 kV/μs
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
0.10 mA/Mbps
DDI (D)
0.03 mA/Mbps
DDO (D)
ower Consumption
that is measured between units at the same operating temperature, supply voltages, and output load
. CML is the maximum common-mode voltage slew rate
DD2
Power Consumption
Figure 6
9
propagation delay is
PLH
Figure 8
Rev. B | Page 6 of 20
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