ANALOG DEVICES ADUM3100 Service Manual
Digital Isolator, Enhanced
Data Sheet
FEATURES
Enhanced system-level ESD performance per IEC 61000-4-x
High data rate: dc to 100 Mbps (NRZ)
Compatible with 3.3 V and 5.0 V operation/level translation
105°C maximum operating temperature
Low power operation
5 V operation
2.0 mA maximum @ 1 Mbps
5.6 mA maximum @ 25 Mbps
18 mA maximum @ 100 Mbps
3.3 V operation
1.1 mA maximum @ 1 Mbps
4.2 mA maximum @ 25 Mbps
8.3 mA maximum @ 50 Mbps
RoHS-compliant, 8-lead SOIC
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognized: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
V
= 560 V peak
IORM
System-Level ESD Reliability
ADuM3100
APPLICATIONS
Digital fieldbus isolation
Opto-isolator replacement
Computer-peripheral interface
Microprocessor system interface
General instrumentation and data acquisition
FUNCTIONAL BLOCK DIAGRAM
(DATA IN)
V
1
DD1
V
I
2
V
3
DD1
GND
4
1
NOTES
1. FOR PRINCIPLES OF OPERATION, SEE M ETHOD OF OPERATI ON,
DC CORRECTNESS, AND MAGNETI C FI EL D I MMUNITY SECTION.
UPDATE
E
N
C
O
D
E
ADuM3100
D
E
C
O
D
E
WATCHDOG
Figure 1.
8
V
DD2
7
GND
V
O
6
(DATA OUT)
5
GND
2
2
05637-001
GENERAL DESCRIPTION
The ADuM31001 is a digital isolator based on the Analog
Devices, Inc., iCoupler® technology. Combining high speed
CMOS and monolithic transformer technology, this isolation
component provides outstanding performance characteristics
superior to alternatives, such as optocoupler devices.
Configured as a pin-compatible replacement for existing high
speed optocouplers, the ADuM3100 supports data rates as high
as 25 Mbps and 100 Mbps.
The ADuM3100 operates with a voltage supply ranging from
3.0 V to 5.5 V, boasts a propagation delay of <18 ns and an edge
asymmetry of <2 ns, and is compatible with temperatures up to
105°C. It operates at very low power, less than 2.0 mA of quiescent
current (sum of both sides), and a dynamic current of less than
160 μA per Mbps of data rate. Unlike other optocoupler alternatives, the ADuM3100 provides dc correctness with a patented
refresh feature that continuously updates the output signal.
The ADuM3100 is offered in two grades. The ADuM3100AR
and ADuM3100BR can operate up to a maximum temperature
of 105°C and support data rates up to 25 Mbps and 100 Mbps,
respectively.
In comparison to the ADuM1100 digital isolator, the ADuM3100
contains various circuit and layout changes to provide increased
capability relative to system-level IEC 61000-4-x testing (ESD/
burst/surge). The precise capability in these tests for either the
ADuM1100 or ADuM3100 is strongly determined by the design
and layout of the user’s board or module. For more information,
see the AN-793 Application Note, ESD/Latch-Up Considerations
with iCoupler® Isolation Products.
1
Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578;
6,873,065; 7,075,329 and other pending patents.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved.
ADuM3100 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications, 5 V Operation.................................... 3
Electrical Specifications, 3.3 V Operation ................................ 4
Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 5
Package Characteristics ............................................................... 7
Regulatory Information............................................................... 7
Insulation and Safety-Related Specifications............................ 7
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 8
Recommended Operating Conditions .......................................8
Absolute Maximum Ratings ............................................................9
ESD Caution...................................................................................9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics........................................... 11
Applications Information.............................................................. 13
PC Board Layout ........................................................................ 13
System-Level ESD Considerations and Enhancements ........ 13
Propagation Delay-Related Parameters................................... 13
Method of Operation, DC Correctness, and Magnetic Field
Immunity..................................................................................... 14
Power Consumption .................................................................. 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/12—Rev. B to Rev. C
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 13
6/07—Rev. A to Rev. B
Updated VDE Certification Throughout...................................... 1
Changes to Note 1............................................................................. 1
Changes to Regulatory Information Section ................................ 7
Changes to Table 6............................................................................ 7
Changes to DIN V VDE V 0884-10 (VDE V 0884-10)
Insulation Characteristics Section.................................................. 8
3/06—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changes to Product Title, Features, General Description,
and Note 1 ..........................................................................................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3.............................................................................5
Added System-Level ESD Considerations and
Enhancements Section................................................................... 13
Added Power Consumption Section ........................................... 15
10/05—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet ADuM3100
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS, 5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ V
apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent I
Output Supply Current, Quiescent I
Input Supply Current (25 Mbps)
DD1 (Q)
DD2 (Q)
I
DD1 (25)
(See Figure 4)
Output Supply Current1 (25 Mbps)
I
DD2 (25)
(See Figure 5)
Input Supply Current (100 Mbps)
I
DD1 (100)
(See Figure 4)
Output Supply Current1 (100 Mbps)
I
DD2 (100)
(See Figure 5)
Input Current II −10 +0.01 +10 A 0 V ≤ VIN ≤ V
Logic High Output Voltage VOH V
V
Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 µA, VI = VIL
0.03 0.1 V IO = 400 µA, VI = VIL
0.3 0.8 V IO = 4 mA, VI = VIL
SWITCHING SPECIFICATIONS
For ADuM3100ARZ
Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels
For ADuM3100BRZ
Minimum Pulse Width3 PW 6.7 10 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 100 150 Mbps CL = 15 pF, CMOS signal levels
For All Grades
Propagation Delay Time to Logic Low
Propagation Delay Time to Logic High
Pulse-Width Distortion |t
Output
Output
4, 5
(See Figure 6)
4, 5
(See Figure 6)
PLH
− t
|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
PHL
t
PHL
t
PLH
Change vs. Temperature6 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature)
Propagation Delay Skew (Equal Temperature,
Supplies)
5, 7
5, 7
t
PSK1
t
PSK2
Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic Low/High Output
8
Input Dynamic Supply Current9 I
Output Dynamic Supply Current9 I
See notes on Page 6.
|CM
DDI (D)
DDO (D)
≤ 5.5 V, 4.5 V ≤ V
DD1
1.3 1.8 mA VI = 0 V or V
0.15 0.25 mA VI = 0 V or V
≤ 5.5 V. All minimum/maximum specifications
DD2
= 25°C, V
A
DD1
DD1
DD1
= V
DD2
= 5 V.
3.2 4.5 mA 12.5 MHz logic signal freq.
0.6 1.1 mA 12.5 MHz logic signal freq.
10 15 mA 50 MHz logic signal freq.
2.1 2.9 mA
50 MHz logic signal freq.,
ADuM3100BRZ only
DD1
− 0.1 5.0 V IO = −20 A, VI = VIH
DD2
− 0.8 4.6 V IO = −4 mA, VI = VIH
DD2
10.5 18 ns CL = 15 pF, CMOS signal levels
10.5 18 ns CL = 15 pF, CMOS signal levels
8 ns CL = 15 pF, CMOS signal levels
6 ns CL = 15 pF, CMOS signal levels
|, |CMH| 25 35 kV/µs VI = 0 V or V
L
, VCM = 1000 V
DD1
0.09 mA/Mbps
0.02 mA/Mbps
Rev. C | Page 3 of 16
ADuM3100 Data Sheet
ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ V
over the entire recommended operation range, unless otherwise noted. All typical specifications are at T
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent I
Output Supply Current, Quiescent I
Input Supply Current (25 Mbps)
DD1 (Q)
DD2 (Q)
I
DD1 (25)
(See Figure 4)
Output Supply Current1 (25 Mbps)
I
DD2 (25)
(See Figure 5)
Input Supply Current (50 Mbps)
I
DD1 (50)
(See Figure 4)
Output Supply Current1 (50 Mbps)
I
DD2 (50)
(See Figure 5)
Input Current II −10 +0.01 +10 A 0 V ≤ VIN ≤ V
Logic High Output Voltage VOH
Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 A, VI = VIL
0.04 0.1 V IO = 400 A, VI = VIL
0.3 0.4 V IO = 2.5 mA, VI = VIL
SWITCHING SPECIFICATIONS
For ADuM3100ARZ
Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels
For ADuM3100BRZ
Minimum Pulse Width2 PW 10 20 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 50 100 Mbps CL = 15 pF, CMOS signal levels
For All Grades
Propagation Delay Time to Logic Low
Propagation Delay Time to Logic High
Pulse-Width Distortion |t
Output
Output
4, 5
(See Figure 7)
4, 5
(See Figure 7)
PLH
− t
|5 PWD 0.5 3 ns CL = 15 pF, CMOS signal levels
PHL
t
t
Change vs. Temperature6 10 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature)
Propagation Delay Skew (Equal Temperature,
Supplies)
5, 7
5, 7
t
t
Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic Low/High Output
8
Input Dynamic Supply Current9 I
Output Dynamic Supply Current9 I
See notes on Page 6.
|CM
DDI (D)
DDO (D)
≤ 3.6 V, 3.0 V ≤ V
DD1
0.7 0.9 mA VI = 0 V or V
0.1 0.2 mA VI = 0 V or V
≤ 3.6 V. All minimum/maximum specifications apply
DD2
= 25°C, V
A
DD1
= V
DD1
DD1
= 3.3 V.
DD2
2.6 3.4 mA 12.5 MHz logic signal freq.
0.4 0.8 mA 12.5 MHz logic signal freq.
4.6 6.6 mA
25 MHz logic signal freq.,
ADuM3100BRZ only
0.7 1.7 mA
25 MHz logic signal freq.,
ADuM3100BRZ only
DD1
3.3 V I
−
V
DD2
= −20 A, VI = VIH
O
0.1
3.0 V I
−
V
DD2
= −2.5 mA, VI = VIH
O
0.5
14.5 28 ns CL = 15 pF, CMOS signal levels
PHL
15.0 28 ns CL = 15 pF, CMOS signal levels
PLH
15 ns CL = 15 pF, CMOS signal levels
PSK1
12 ns CL = 15 pF, CMOS signal levels
PSK2
|, |CMH| 25 35 kV/µs
L
= 0 V or V
V
I
, VCM = 1000 V,
DD1
transient magnitude = 800 V
0.08 mA/Mbps
0.01 mA/Mbps
Rev. C | Page 4 of 16
Data Sheet ADuM3100
ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V OR 3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V
3.0 V ≤ V
≤ 3.6 V, 4.5 V ≤ V
DD1
unless otherwise noted. All typical specifications are at T
≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
DD2
= 25°C, V
A
= 3.3 V, V
DD1
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent I
DDI (Q)
5 V/3 V Operation 1.3 1.8 mA
3 V/5 V Operation 0.7 0.9 mA
Output Supply Current1, Quiescent I
DDO (Q)
5 V/3 V Operation 0.1 0.2 mA
3 V/5 V Operation 0.15 0.25 mA
Input Supply Current, 25 Mbps I
DDI (25)
5 V/3 V Operation 3.2 4.5 mA 12.5 MHz logic signal freq.
3 V/5 V Operation 2.6 3.4 mA 12.5 MHz logic signal freq.
Output Supply Current1, 25 Mbps I
DDO (25)
5 V/3 V Operation 0.4 0.8 mA 12.5 MHz logic signal freq.
3 V/5 V Operation 0.6 1.1 mA 12.5 MHz logic signal freq.
Input Supply Current, 50 Mbps I
DDI (50)
5 V/3 V Operation 5.5 8.0 mA 25 MHz logic signal freq.
3 V/5 V Operation 4.6 6.6 mA 25 MHz logic signal freq.
Output Supply Current1, 50 Mbps I
DDO (50)
5 V/3 V Operation 0.7 1.7 mA 25 MHz logic signal freq.
3 V/5 V Operation 1.1 1.6 mA 25 MHz logic signal freq.
Input Currents IIA −10 +0.01 +10 μA
Logic High Output Voltage, 5 V/3 V Operation VOH V
V
− 0.1 3.3 V IO = −20 μA, VI = VIH
DD2
− 0.5 3.0 V IO = −2.5 mA, VI = VIH
DD2
Logic Low Output Voltage, 5 V/3 V Operation VOL 0.0 0.1 V IO = 20 μA, VI = VIL
0.04 0.1 V IO = 400 μA, VI = VIL
0.3 0.4 V IO = 2.5 mA, VI = VIL
Logic High Output Voltage, 3 V/5 V Operation VOH V
V
− 0.1 5.0 V IO = −20 μA, VI = VIH
DD2
− 0.8 4.6 V IO = −4 mA, VI = VIH
DD2
Logic Low Output Voltage, 3 V/5 V Operation VOL 0.0 0.1 V IO = 20 μA, VI = VIL
0.03 0.1 V IO = 400 μA, VI = VIL
0.3 0.8 V IO = 4 mA, VI = VIL
SWITCHING SPECIFICATIONS
For ADuM3100AR
Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels
For ADuM3100BR
Minimum Pulse Width2 PW 20 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 50 Mbps CL = 15 pF, CMOS signal levels
For All Grades
t
, t
Propagation Delay Time to Logic Low/High
Output
4, 5
PHL
PLH
5 V/3 V Operation (See Figure 8) 13 21 ns CL = 15 pF, CMOS signal levels
3 V/5 V Operation (See Figure 9) 16 26 ns CL = 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
− t
|5 PWD
PHL
5 V/3 V Operation 0.5 2 ns CL = 15 pF, CMOS signal levels
3 V/5 V Operation 0.5 3 ns CL = 15 pF, CMOS signal levels
≤ 5.5 V, 3.0 V ≤ V
DD1
= 5 V or V
DD2
= 5 V, V
DD1
≤ 3.6 V. 3 V/5 V operation:
DD2
= 3.3 V.
DD2
, VIB, VIC, VID ≤
0 ≤ V
IA
or V
V
DD1
DD2
Rev. C | Page 5 of 16
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