ANALOG DEVICES ADuM2401, ADuM2402 Service Manual

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Preliminary Technical Data

FEATURES

Low power operation

5 V operation:

1.0 mA per channel max @ 0–2 Mbps

3.5 mA per channel max @ 10 Mbps 31 mA per channel max @ 90 Mbps

3 V operation:

0.7 mA per channel max @ 0–2 Mbps

2.1 mA per channel max @ 10 Mbps

20 mA per channel max @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: DC–90 Mbps (NRZ) Precise timing characteristics:

2 ns max. pulsewidth distortion

2 ns max. channel-to-channel matching High common-mode transient immunity: > 25 kV/μs Output enable function Wide body SOIC 16-lead package Safety and regulatory approvals (pending)

UL recognition: 5000 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805):2001-12;EN 60950:2000 V

= 848 V peak

IORM

IEC 60601-1

APPLICATIONS

General-purpose, high voltage, multichannel isolation Medical Equipment Motor Drives Power Supplies

FUNCTIONAL BLOCK DIAGRAMS

DD1

ENCODE DECODE

Figure 1. ADuM2400 Functional Block Diagram

Rev. PrD October 5, 2004

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

ENCODE DECODE

DD2

GND

03786-0-001

dd1

GND

ENCODE

GND

ENCODE

DECODE

Figure 2. ADuM2401 Functional Block Diagram

Quad-Channel Digital Isolators, 5KV

ADuM2400/ADuM2401/ADuM2402

GENERAL DESCRIPTION

The ADuM240x are four-channel digital isolators based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. In comparison to the 2.5KV ADuM140x product family, ADuM240x models have increased insulation thickness to achieve the higher 5.0KV isolation rating.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple, iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discretes is eliminated with these iCoupler products. Furthermore, iCoupler devices run at one-tenth to one-sixth the power consumption of optocouplers at comparable signal data rates.

The ADuM240x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see Ordering Guide). All ADuM240x models operate with the supply voltage of either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM240x provides low pulse width distortion (<2 ns for CRWZ grade), and tight channel-to-channel matching (<2 ns for CRWZ grade). Unlike other optocoupler alternatives, the ADuM240x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

dd2

GND

DECODE

ENCODE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

GND

DD1

ENCODE DECODE

DECODE

DECODE ENCODE

ENCODE

DD2

GND

Figure 3. ADuM2402 Functional Block Diagram

03786-0-003

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

ELECTRICAL CHARACTERISTICS—5 V OPERATION1

4.5 V ≤ V otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent I Output Supply Current, per Channel, Quiescent I ADuM2400, Total Supply Current, Four Channels2 DC to 2 Mbps V V 10 Mbps (BRWZ and CRWZ Grades Only) V V 90 Mbps (CRWZ Grade Only) V V ADuM2401, Total Supply Current, Four Channels2 DC to 2 Mbps V V 10 Mbps (BRWZ and CRWZ Grades Only) V V 90 Mbps (CRWZ Grade Only) V V ADuM2402, Total Supply Current, Four Channels2 DC to 2 Mbps V

10 Mbps (BRWZ and CRWZ Grades Only) V

90 Mbps (CRWZ Grade Only) V

For All Models Input Currents

Logic High Input Threshold Logic Low Input Threshold

Logic Low Output Voltages

≤ 5.5 V, 4.5 V ≤ V

DD1

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

or V

DD2

Supply Current

DD1

≤ 5.5 V. All min/max specifications apply over the entire recommended operation range, unless

DD2

= 25°C, V

= V

DD1

DDI(Q)

DDO(Q)

DD1(Q)

DD2(Q)

DD1(10)

DD2(10)

DD1(90)

DD2(90)

DD1(Q)

DD2(Q)

DD1(10)

DD2(10)

DD1(90)

DD2(90)

DD1(Q)

DD2(Q)

DD1(10)

DD2(10)

DD1(90)

DD2(90)

, IIB, IIC,

, IE1, I

VIH, V VIL, V V

OAH

OCH

OAL

OCL

= 5 V.

DD2

0.50 0.53 mA

0.19 0.21 mA

2.2 2.8 mA DC to 1 MHz logic signal freq.

0.9 1.4 mA DC to 1 MHz logic signal freq.

8.6 10.6 mA 5 MHz logic signal freq.

2.6 3.5 mA 5 MHz logic signal freq.

76 100 mA 45 MHz logic signal freq. 21 25 mA 45 MHz logic signal freq.

1.8 2.4 mA DC to 1 MHz logic signal freq.

1.2 1.8 mA DC to 1 MHz logic signal freq.

7.1 9.0 mA 5 MHz logic signal freq.

4.1 5.0 mA 5 MHz logic signal freq.

62 82 mA 45 MHz logic signal freq. 35 43 mA 45 MHz logic signal freq.

1.5 2.1 mA DC to 1 MHz logic signal freq.

5.6 7.0 mA 5 MHz logic signal freq.

49 62 mA 45 MHz logic signal freq.

–10 0.01 10 µA

2.0 V

0.8

, V

OBH

, V

ODH

, V

OBL

, V

ODL

– 0.1 5. 0 V IOx = –20 µA, VIx = V

DD1, VDD2

– 0.4 4. 8 V IOx = –4 mA, VIx = V

DD1, VDD2

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

, VIB, VIC, VID ≤ V

0 ≤ V

0 ≤ VE1, VE2 ≤ V

DD1

or V

IxL

or V

DD1

DD2,

DD2

Logic High Output Voltages

IxH

IxL

Rev. PrD| Page 2 of 23

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS ADuM240xARW Minimum Pulsewidth3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulsewidth Distortion, |t

PLH-tPHL

| Propagation Delay Skew6 t Channel-to-Channel Matching7 t ADuM240xBRW Minimum Pulsewidth3 PW 100 ns Maximum Data Rate4 10 Mbps Propagation Delay5 t Pulsewidth Distortion, |t

PLH

– t

PHL

| Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching, Co-Directional

Channels Channel-to-Channel Matching, Opposing-Directional

Channels

ADuM240xCRW Minimum Pulsewidth3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulsewidth Distortion, |t

PLH

– t

PHL

| Change Versus Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching, Co-Directional

Channels Channel-to-Channel Matching, Opposing-Directional

Channels

For All Models Output Disable Propagation Delay

(High/Low to High Impedance) Output Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10%–90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic High

Output Common-Mode Transient Immunity at Logic Low

Output

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current, per Channel9 I Output Dynamic Supply Current, per Channel9 I

See Notes on next page.

, t

50 65 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

= 15 pF, CMOS signal levels

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

PSKCD

6 ns CL = 15 pF, CMOS signal levels

PSKOD

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

10 ns CL = 15 pF, CMOS signal levels

PSK

2 ns CL = 15 pF, CMOS signal levels

PSKCD

5 ns CL = 15 pF, CMOS signal levels

PSKOD

PHZ

PZH

|CM

, t

6 8 ns CL = 15 pF, CMOS signal levels

PLH

6 8 ns CL = 15 pF, CMOS signal levels

PZL

| 25 35 kV/µs

= V

, VCM = 1000 V,

DD1/DD2

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.19 mA/Mbps

DDI(D)

0.05 mA/Mbps

DDO(D)

Rev. PrD | Page 3 of 23

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

NOTES

All voltages are relative to their respective ground.

Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on page 20 . See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total I

The minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed.

The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed.

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8V

than can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for

information on per-channel supply current for unloaded and loaded conditions. See Power Consumption section on page 19 for guidance on calculating perchannel supply current for a given data rate.

DD1

and I

supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

DD2

or t

that will be measured between units at the same operating temperature, supply voltages, and output

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

propagation delay

PLH

Rev. PrD| Page 4 of 23

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

ELECTRICAL CHARACTERISTICS—3 V OPERATION1

2.7 V ≤ V otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

10 Mbps (BRWZ and CRWZ Grades Only) V

90 Mbps (CRWZ Grade Only) V

For All Models Input Currents

Logic High Input Threshold Logic Low Input Threshold

Logic Low Output Voltages

≤ 3.6 V, 2.7 V ≤ V

DD1

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

Supply Current I

DD1

Supply Current I

DD2

or V

DD2

Supply Current

DD1

≤ 3.6 V. All min/max specifications apply over the entire recommended operation range, unless

DD2

= 25°C, V

= V

DD1

DDI(Q)

DDO(Q)

DD1(Q)

DD2(Q)

DD1(10)

DD2(10)

DD1(90)

DD2(90)

DD1(Q)

DD2(Q)

DD1(10)

DD2(10)

DD1(90)

DD2(90)

DD1(Q)

DD2(Q)

DD1(10)

DD2(10)

DD1(90)

DD2(90)

, IIB, I

, IE1, I

VIH, V VIL, V V

OAH

OCH

OAL

OCL

= 3.0 V.

DD2

0.26 0.31 mA

0.11 0.14 mA

1.2 1.9 mA DC to 1 MHz logic signal freq.

0.5 0.9 mA DC to 1 MHz logic signal freq.

4.5 6.5 mA 5 MHz logic signal freq.

1.4 2.0 mA 5 MHz logic signal freq.

42 65 mA 45 MHz logic signal freq. 11 15 mA 45 MHz logic signal freq.

1.0 1.6 mA DC to 1 MHz logic signal freq.

0.7 1.2 mA DC to 1 MHz logic signal freq.

3.7 5.4 mA 5 MHz logic signal freq.

2.2 3.0 mA 5 MHz logic signal freq.

34 52 mA 45 MHz logic signal freq. 19 27 mA 45 MHz logic signal freq.

0.9 1.5 mA DC to 1 MHz logic signal freq.

3.0 4.2 mA 5 MHz logic signal freq.

27 39 mA 45 MHz logic signal freq.

–10 0.01 10 µA

IC,

1.6 V

0.4

, V

OBH

, V

ODH

, V

OBL

, V

ODL

– 0.1 3. 0 V IOx = –20 µA, VIx = V

DD1, VDD2

– 0.4 2. 8 V IOx = –4 mA, VIx = V

DD1, VDD2

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V I

, VIB, VIC, VID ≤ V

0 ≤ V

0 ≤ VE1,VE2 ≤ V

= 4 mA, VIx = V

DD1

or V

IxL

or V

DD1

DD2,

DD2

Logic High Output Voltages

IxH

IxL

Rev. PrD | Page 5 of 23

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS ADuM240xARW Minimum Pulsewidth3 PW 1000 ns CL = 15pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15pF, CMOS signal levels Propagation Delay5 t Pulsewidth Distortion, |t

PLH

– t

PHL

| Propagation Delay Skew6 t Channel-to-Channel Matching7 t ADuM240xBRW Minimum Pulsewidth3 PW 100 ns CL = 15pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15pF, CMOS signal levels Propagation Delay5 t Pulsewidth Distortion, |t

PLH

– t

PHL

| Change Versus Temperature 5 ps/°C CL = 15pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching, Co-Directional

Channels Channel-to-Channel Matching, Opposing-Directional

Channels

ADuM240xCRW Minimum Pulsewidth3 PW 8.3 11.1 ns CL = 15pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15pF, CMOS signal levels Propagation Delay5 t Pulsewidth Distortion, |t

PLH

– t

PHL

| Change Versus Temperature 3 ps/°C CL = 15pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching, Co-Directional

Channels Channel-to-Channel Matching, Opposing-Directional

Channels

For All Models Output Disable Propagation Delay

(High/Low to High Impedance) Output Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10%–90%) tR/tF 3 ns CL = 15pF, CMOS signal levels Common Mode Transient Immunity at Logic High

Output Common Mode Transient Immunity at Logic Low

Output

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current, per Channel9 I Output Dynamic Supply Current, per Channel9 I

See Notes on next page.

, t

50 75 100 ns CL = 15pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15pF, CMOS signal levels

50 ns CL = 15pF, CMOS signal levels

PSK

50 ns CL = 15pF, CMOS signal levels

PSKCD/OD

, t

20 38 50 ns CL = 15pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15pF, CMOS signal levels

22 ns CL = 15pF, CMOS signal levels

PSK

3 ns CL = 15pF, CMOS signal levels

PSKCD

6 ns CL = 15pF, CMOS signal levels

PSKOD

, t

20 34 45 ns CL = 15pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15pF, CMOS signal levels

16 ns CL = 15pF, CMOS signal levels

PSK

2 ns CL = 15pF, CMOS signal levels

PSKCD

5 ns CL = 15pF, CMOS signal levels

PSKOD

PHZ

PZH

|CM

, t

6 8 ns CL = 15pF, CMOS signal levels

PLH

6 8 ns CL = 15pF, CMOS signal levels

PZL

| 25 35 kV/µs

= V

, VCM = 1000 V,

DD1/DD2

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.10 mA/Mbps

DDI(D)

0.03 mA/Mbps

DDO(D)

Rev. PrD| Page 6 of 23

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

NOTES

All voltages are relative to their respective ground.

The minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed.

The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed.

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8V

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for

information on per-channel supply current for unloaded and loaded conditions. See Power Consumption section on page 19 for guidance on calculating perchannel supply current for a given data rate.

DD1

and I

supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

DD2

or t

that will be measured between units at the same operating temperature, supply voltages, and output

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

propagation delay

PLH

Rev. PrD | Page 7 of 23

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ANALOG DEVICES ADuM2401, ADuM2402 Service Manual

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