ANALOG DEVICES ADUM 2401 ARWZ, ADUM 2400 ARWZ Datasheet

Quad-Channel Digital Isolators

k

Data Sheet

FEATURES

Low power operation

5 V operation

1.0 mA per channel maximum @ 0 Mbps to 2 Mbps

3.5 mA per channel maximum @ 10 Mbps 31 mA per channel maximum @ 90 Mbps

3 V operation

0.7 mA per channel maximum @ 0 Mbps to 2 Mbps

2.1 mA per channel maximum @ 10 Mbps

20 mA per channel maximum @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body package version (RW-16) 16-lead SOIC wide body enhanced creepage version (RI-16)

Safety and regulatory approvals (RI-16 package)

UL

recognition: 5000 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice 5A

IEC 60601-1: 250 V rms (reinforced)

IEC 60950-1: 400 V rms (reinforced)

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V

= 846 V peak

IORM

APPLICATIONS

General-purpose, high voltage, multichannel isolation Medical equipment Motor drives Power supplies

GENERAL DESCRIPTION

The ADuM2400/ADuM2401/ADuM24021 are 4-channel digital isolators based on Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics that are superior to alternatives, such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and tempera

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.

Document Feedbac

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADuM2400/ADuM2401/ADuM2402

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

2

GND

1

3

V

V V

NC

GND

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

ENCODE DECODE

ID

7 8

1

Figure 1. ADuM24

1

V

DD1

2

GND

1

3

V

GND

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

DECODE ENCODE

OD

7

E1

8

1

Figure 2. ADuM24

1

V

DD1

2

GND

1

3

V

V V

V

GND

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

OC

6

DECODE ENCODE

OD

7

E1

8

1

Figure 3. ADuM24

ture and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. Furthermore, iCoupler devices run at one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM2400/ADuM2401/ADuM2402 isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). The ADuM2400/

ADuM2401/ADuM2402 models operate with the supply voltage

of either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM2400/ADuM2401/ADuM2402 provide low pulse width distortion (<2 ns for CRWZ grade) and tight channel-tochannel matching (<2 ns for CRWZ grade). The ADuM2400/

ADuM2401/ADuM2402 isolators have a patented refresh feature

that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

Tec hn ical Su pp or t www.analog.com

ADuM2400

00

ADuM2401

01

ADuM2402

02

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

05007-001

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

V

E2

9

GND

2

05007-002

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

V

E2

9

GND

2

05007-003

ADuM2400/ADuM2401/ADuM2402 Data Sheet

REVISION HISTORY

7/15—Rev. E to Rev. F

Changes to Table 5 and Table 6 ..................................................... 10

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 22

2/12—Rev. D to Rev. E

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 18

8/11—Rev. C to Rev. D

Added 16-Lead SOIC_IC .................................................. Universal

Changes to Features Section and General Description

Section ................................................................................................ 1

Changes to Table 5 and Table 6 ..................................................... 10

Changes to Table 8 Endnote .......................................................... 11

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

7/08—Rev. B to Rev. C

Changes to Layout ............................................................................ 1

Changes to Table 6 .......................................................................... 10

6/07—Rev. A to Rev. B

Updated VDE Certification Throughout ....................................... 1

Changes to Features and Note 1 ...................................................... 1

Changes to Figure 1, Figure 2, and Figure 3 .................................. 1

Changes to Regulatory Information ............................................ 10

Changes to Table 7 .......................................................................... 11

Changes to Insulation Lifetime Section ...................................... 20

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

1/06—Rev. 0 to Rev. A

Changes to Regulatory Information Section .............................. 13

Updated Outline Dimensions ....................................................... 23

Changes to Ordering Guide .......................................................... 23

9/05—Revision 0: Initial Version

Rev. F | Page 2 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

DDO (Q)

DD1

DD1 (Q)

V

DD1

Supply Current

I

DD1 (10)

8.6

10.6

mA

5 MHz logic signal frequency

DD1

DD1 (90)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD1

DD1 (90)

10 Mbps (BRWZ and CRWZ Grades Only)

DD1

DD2

DD1 (90)

DD2 (90)

EH

EL

DD1

DD2

IxH

IxL

0.04

0.1 V IOx = 400 µA, VIx = V

IxL

PHL

PLH

PHL

Channel-to-Channel Matching7

t

PSKCD/tPSKOD

50

ns

CL = 15 pF, CMOS signal levels

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION1

4.5 V ≤ V unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM2400 Total Supply Current, Four Channels2

ADuM2401 Total Supply Current, Four Channels2

ADuM2402 Total Supply Current, Four Channels2

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.50 0.53 mA

DDI (Q)

DD1

= V

DD2

= 5 V.

0.19 0.21 mA

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal frequency

0.9 1.4 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ and CRWZ Grades Only)

V

Supply Current I

DD2

2.6 3.5 mA 5 MHz logic signal frequency

DD2 (10)

90 Mbps (CRWZ Grade Only)

V

Supply Current I

V

Supply Current I

DD2

70 100 mA 45 MHz logic signal frequency 18 25 mA 45 MHz logic signal frequency

DD2 (90)

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

1.8 2.4 mA DC to 1 MHz logic signal frequency

1.2 1.8 mA DC to 1 MHz logic signal frequency

10 Mbps (BRWZ and CRWZ Grades Only)

V

Supply Current I

V

Supply Current I

DD2

7.1 9.0 mA 5 MHz logic signal frequency

4.1 5.0 mA 5 MHz logic signal frequency

DD2 (10)

90 Mbps (CRWZ Grade Only)

V

Supply Current I

V

Supply Current I

DD2

57 82 mA 45 MHz logic signal frequency 31 43 mA 45 MHz logic signal frequency

DD2 (90)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

1.5 2.1 mA DC to 1 MHz logic signal frequency

DD2 (Q)

V

or V

DD1

Supply Current I

DD2

DD1 (10)

, I

5.6 7.0 mA 5 MHz logic signal frequency

DD2 (10)

90 Mbps (CRWZ Grade Only)

V

or V

Supply Current I

, I

44 62 mA 45 MHz logic signal frequency

For All Models

Input Currents IIA, IIB, IIC,

, IE1, I

I

ID

E2

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

(V

Logic Low Output Voltages V

VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

, V , V

OBH

ODH

OBL

ODL

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ V

E1

2.0 V

0.8 V

,

(V

or V

DD1

,

0.0 0.1 V IOx = 20 µA, VIx = V

) − 0.1 5.0 V IOx = −20 µA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

, VE2 ≤ V

DD1

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM2400ARWZ/ADuM2401ARWZ/

ADuM2402ARWZ

Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse Width Distortion, |t

− t

5

|

Propagation Delay Skew6 t

, t

50 65 100 ns CL = 15 pF, CMOS signal levels

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

Rev. F | Page 3 of 24

or V

IxH

or V

DD1

DD2

,

DD2

ADuM2400/ADuM2401/ADuM2402 Data Sheet

PHL

PLH

Propagation Delay Skew6

t

PSK

15

ns

CL = 15 pF, CMOS signal levels

Opposing-Directional Channels7

ADuM2400CRWZ/ADuM2401CRWZ/

PLH

PHL

5

PSK

DDI (D)

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM2400BRWZ/ADuM2401BRWZ/

ADuM2402BRWZ

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse Width Distortion, |t

PLH

− t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

7

Channel-to-Channel Matching,

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

ADuM2402CRWZ

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse Width Distortion, |t

− t

|

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing-Directional Channels

7

For All Models

Output Disable Propagation Delay

10 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

(High/Low to High Impedance)

Output Enable Propagation Delay

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at

Logic High Output Common-Mode Transient Immunity at

Logic Low Output

8

|CM

| 25 35 kV/µs VIx = V

H

DD1

or V

DD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel9 I Output Dynamic Supply Current per Channel9 I

1

All voltages are relative to their respective ground.

2

Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

and V

DD1

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a given data rate.

supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

DD2

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.19 mA/Mbps

0.05 mA/Mbps

propagation delay is

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

PLH

Rev. F | Page 4 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

DDI (Q)

DDO (Q)

DD2

DD2 (Q)

10 Mbps (BRWZ and CRWZ Grades Only)

DD2

DD2 (10)

V

DD2

Supply Current

I

DD2 (90)

11

15

mA

45 MHz logic signal frequency

DD1

DD1 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

DD2

DD2 (90)

V

DD1

or V

DD2

Supply Current

I

DD1 (Q)

, I

DD2 (Q)

0.9

1.5

mA

DC to 1 MHz logic signal frequency

DD1

DD2

DD1 (10)

DD2 (10)

ID

E2

E1

DD1

DD2

EH

DD1

DD2

IxH

DD1

DD2

IxH

0.04

0.1 V IOx = 400 µA, VIx = V

IxL

5

Propagation Delay Skew6

t

PSK

50

ns

CL = 15 pF, CMOS signal levels

ELECTRICAL CHARACTERISTICS—3 V OPERATION1

2.7 V ≤ V unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I

ADuM2400 Total Supply Current, Four Channels2

ADuM2401 Total Supply Current, Four Channels2

ADuM2402 Total Supply Current, Four Channels2

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.26 0.31 mA

0.11 0.14 mA

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

V

Supply Current I

DD1

V

Supply Current I

1.2 1.9 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.5 0.9 mA DC to 1 MHz logic signal frequency

4.5 6.5 mA 5 MHz logic signal frequency

DD1 (10)

1.4 2.0 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

Supply Current I

DD1

37 65 mA 45 MHz logic signal frequency

DD1 (90)

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

DD2

1.0 1.6 mA DC to 1 MHz logic signal frequency

0.7 1.2 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ and CRWZ Grades Only)

V

Supply Current I

V

Supply Current I

3.7 5.4 mA 5 MHz logic signal frequency

2.2 3.0 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

30 52 mA 45 MHz logic signal frequency

DD1 (90)

18 27 mA 45 MHz logic signal frequency

DC to 2 Mbps

10 Mbps (BRWZ and CRWZ Grades Only)

V

or V

Supply Current I

, I

3.0 4.2 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

or V

DD1

Supply Current I

DD2

DD1 (90)

, I

24 39 mA 45 MHz logic signal frequency

DD2 (90)

For All Models

Input Currents IIA, IIB, IIC,

, IE1, I Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

(V

Logic Low Output Voltages V

I VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

, V , V

EL

, V , V

OBL

ODL

0.2 0.4 V IOx = 4 mA, VIx = V

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ V

1.6 V

0.4 V

,

(V

or V

OBH

ODH

0.0 0.1 V I

,

) − 0.1 3.0 V IOx = −20 µA, VIx = V

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

= 20 µA, VIx = V

Ox

, VE2 ≤ V

IxL

SWITCHING SPECIFICATIONS

ADuM2400ARWZ/ADuM2401ARWZ/

ADuM2402ARWZ

Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse Width Distortion, |t

PLH

− t

PHL

|

Channel-to-Channel Matching7 t

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

or V

IxL

or V

DD2

,

DD1

Rev. F | Page 5 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

PHL

PLH

Propagation Delay Skew6

t

PSK

22

ns

CL = 15 pF, CMOS signal levels

Opposing-Directional Channels7

ADuM2400CRWZ/ADuM2401CRWZ/

PLH

PHL

5

PSK

DDI (D)

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM2400BRWZ/ADuM2401BRWZ/

ADuM2402BRWZ

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse Width Distortion, |t

PLH

− t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

7

Channel-to-Channel Matching,

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

ADuM2402CRWZ

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse Width Distortion, |t

− t

|

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing-Directional Channels

7

For All Models

Output Disable Propagation Delay

16 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

(High/Low to High Impedance)

Output Enable Propagation Delay

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at

Logic High Output Common-Mode Transient Immunity at

Logic Low Output

8

|CM

| 25 35 kV/µs VIx = V

H

DD1

or V

DD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel9 I Output Dynamic Supply Current per Channel9 I

1

All voltages are relative to their respective ground.

2

Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

and V

DD1

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a given data rate.

supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

DD2

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.10 mA/Mbps

0.03 mA/Mbps

propagation delay is

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

PLH

Rev. F | Page 6 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

5 V/3 V Operation

0.50

0.53

mA

DDO (Q)

DD1

DD1 (Q)

DD2

DD2 (Q)

10 Mbps (BRWZ and CRWZ Grades Only)

5 V/3 V Operation

1.4

2.0

mA

5 MHz logic signal frequency

V

DD1

Supply Current

I

DD1 (90)

DD2

DD2 (90)

DD1

DD1 (Q)

3 V/5 V Operation

1.0

1.6

mA

DC to 1 MHz logic signal frequency

DD1

DD1 (10)

V

DD2

Supply Current

I

DD2 (10)

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1

5 V/3 V operation: 4.5 V ≤ V minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

3 V/5 V Operation 0.26 0.31 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA

ADuM2400 Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I 5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal frequency 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal frequency

V

Supply Current I 5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal frequency 3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal frequency

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V; o r V

DD2

≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ V

DD2

= 5 V, V

DD1

DDI (Q)

= 3.0 V.

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All

DD2

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal frequency 3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

DD2 (10)

3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

5 V/3 V Operation 70 100 mA 45 MHz logic signal frequency 3 V/5 V Operation 37 65 mA 45 MHz logic signal frequency

V

Supply Current I 5 V/3 V Operation 11 15 mA 45 MHz logic signal frequency 3 V/5 V Operation 18 25 mA 45 MHz logic signal frequency

ADuM2401 Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I 5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal frequency 3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal frequency

10 Mbps (BRWZ and CRWZ Grades Only)

V

Supply Current I 5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal frequency

5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal frequency 3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 57 82 mA 45 MHz logic signal frequency 3 V/5 V Operation 30 52 mA 45 MHz logic signal frequency

DD1 (90)

Rev. F | Page 7 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

3 V/5 V Operation

0.9

1.5

mA

DC to 1 MHz logic signal frequency

V

DD1

Supply Current

I

DD1 (10)

DD2

DD2 (10)

3 V/5 V Operation

5.6

7.0

mA

5 MHz logic signal frequency

DD1

DD1 (90)

5 V/3 V Operation

44

62

mA

45 MHz logic signal frequency

DD2

DD2 (90)

For All Models

ID

E2

DD1

DD2

EH

Logic Low Output Voltages

V

,

0.0

0.1 V IOx = 20 µA, VIx = V

IxL

PHL

PLH

Pulse-Width Distortion, |t

PLH

− t

PHL

|

5

PWD

40

ns

CL = 15 pF, CMOS signal levels

PSKCD/tPSKOD

PHL

PLH

Parameter Symbol Min Typ Max Unit Test Conditions

V

Supply Current I

DD2

5 V/3 V Operation 18 27 mA 45 MHz logic signal frequency 3 V/5 V Operation 31 43 mA 45 MHz logic signal frequency

ADuM2402 Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal frequency 3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal frequency

10 Mbps (BRWZ and CRWZ Grades Only)

5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal frequency

V

Supply Current I

5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

Supply Current I

3 V/5 V Operation 24 39 mA 45 MHz logic signal frequency

V

Supply Current I 5 V/3 V Operation 24 39 mA 45 MHz logic signal frequency 3 V/5 V Operation 44 62 mA 45 MHz logic signal frequency

DD2 (90)

DD1 (Q)

DD2 (Q)

Input Currents IIA, IIB, IIC,

, IE1, I

I VIH, V

Logic High Input Threshold

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ VE1, VE2 ≤ V

or V

5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input Threshold

VIL, V

EL

5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V

Logic High Output Voltages V

(V

0.04 0.1 V IOx = 400 µA, VIx = V

OAH

V

OCH

OAL, VOBL

V

, V

OCL

, V

,

(V

or V

) −

(V

or V

OBH

DD1

or V

DD2

, V

0.1

ODH

0.4

ODL

) −

(V

0.2

DD1

) V IOx = −20 µA, VIx = V

DD2

or V

) −

V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM2400ARWZ/ADuM2401ARWZ/

ADuM2402ARWZ

Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t

Propagation Delay Skew6 t Channel-to-Channel Matching7 t

ADuM2400BRWZ/ADuM2401BRWZ/

, t

50 70 100 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

ADuM2402BRWZ

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t

, t

15 35 50 ns CL = 15 pF, CMOS signal levels

or V

DD1

DD2,

IxH

IxL

Rev. F | Page 8 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

PSK

Propagation Delay5

t

PHL

, t

PLH

20

30

40

ns

CL = 15 pF, CMOS signal levels

Pulse Width Distortion, |t

PLH

− t

PHL

|

5

PWD 0.5 2 ns

CL = 15 pF, CMOS signal levels

PSK

5 V/3 V Operation

3.0 ns

5 V/3 V Operation

0.03 mA/Mbps

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing-Directional Channels

ADuM2400CRWZ/ADuM2401CRWZ/

ADuM2402CRWZ

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

Output Enable Propagation Delay

(High Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels

PLH

5

− t

PHL

|

PWD 3 ns CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

t

3 ns CL = 15 pF, CMOS signal levels

7

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

14 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

7

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

t

PZH

6 8 ns CL = 15 pF, CMOS signal levels

PLH

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZL

3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at

Logic High Output

Common-Mode Transient Immunity at

Logic Low Output

8

|CM

| 25 35 kV/µs VIx = V

H

DD1

or V

DD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current per Channel9 I

DDI (D)

5 V/3 V Operation 0.19 mA/Mbps

3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current per Channel9 I

DDO (D)

3 V/5 V Operation 0.05 mA/Mbps

1

All voltages are relative to their respective ground.

2

Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

and V

DD1

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

propagation delay is

PLH

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

. CML is the maximum common-mode voltage slew rate

DD2

on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a given data rate.

Rev. F | Page 9 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

Resistance (Input to Output)1

R

I-O

1012 Ω

1

I-O

JCI

JCO

Recognized Under UL 1577

Approved under CSA Component Acceptance

Approved under CQC11-471543-2012

Certified according to

File E214100

File 205078

File: CQC14001108690

File 2471900-4880-0001

Minimum Internal Gap (Internal Clearance)

0.017 min

mm

Insulation distance through insulation

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Capacitance (Input to Output)

C

2.2 pF f = 1 MHz Input Capacitance2 CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ

1

Device considered a 2-terminal device: Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and

Pin 16 shorted together.

2

Input capacitance is from any input data pin to ground.

33 °C/W Thermocouple located at center

28 °C/W

of package underside

REGULATORY INFORMATION

The ADuM2400/ADuM2401/ADuM2402 are approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 5.

UL CSA CQC VDE

Component Recognition Program

1

Single Protection 5000 V rms

Isolation Voltage

RW-16 package: reinforced insulation per

RI-16 package: reinforced insulation per

Notice 5A

Basic insulation per CSA 60950-1-07 and IEC 60950-1, 600 V rms (848 V peak) maximum working voltage

CSA 60950-1-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage; reinforced insulation per IEC 60601-1 125 V rms (176 V peak) maximum working voltage

CSA 60950-1-07 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage; reinforced insulation per IEC 60601-1 250 V rms (353 V peak) maximum working voltage

Basic insulation per GB4943.1-2011, 600 V rms(848 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 m

RW-16 package: reinforced insulation per GB4943.1-2011, 380 V rms (537 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 m

RI-16 package: reinforced insulation per 400 V rms (565 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 m

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

Reinforced insulation, 846 V peak

2

1

In accordance with UL 1577, each ADuM2400/ADuM2401/ADuM2402 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec (current leakage

detection limit = 10 µA).

2

In accordance with DIN V VDE V 0884-10, each ADuM2400/ADuM2401/ADuM2402 is proof tested by applying an insulation test voltage ≥1590 V peak for 1 sec (partial

discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration Minimum External Air Gap L(I01) 8.0 min mm Distance measured from input terminals to output terminals, shortest

Minimum External Tracking (Creepage) RW-16

Package

Minimum External Tracking (Creepage) RI-16

Package

Tracking Resistance (Comparative Tracking

Index)

Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)

approval.

distance through air along the PCB mounting plane, as an aid to PC board layout

L(I02) 7.7 min mm Measured from input terminals to output terminals, shortest distance

path along body

L(I02) 8.3 min mm Measured from input terminals to output terminals, shortest distance

path along body

CTI >400 V DIN IEC 112/VDE 0303 Part 1

Rev. F | Page 10 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

IORM

CASE TEMPERATURE (°C)

SAFETY-L IMIT ING CURRENT (mA)

0

350

300

250

200

150

100

50

50 100 150

200

SIDE #1

SIDE #2

05007-004

Supply Voltages1 (V

DD1

, V

DD2

)

2.7 V to 5.5 V

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits.

Note that the * marking on packages denotes DIN V VDE V 0884-10 approval for 846 V peak working voltage.

Table 7.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 300 V rms I to IV For Rated Mains Voltage ≤ 450 V rms I to II

For Rated Mains Voltage ≤ 600 V rms I to II Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method b1 V

× 1.875 = VPR, 100% production test, tm = 1 sec,

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method a VPR

After Environmental Tests Subgroup 1 V

After Input and/or Safety Test Subgroup 2

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 1375 V peak

V

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 6000 V peak Safety-Limiting Values Maximum value allowed in the event of a failure;

see Figure 4 Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

846 V peak

VPR 1590 V peak

Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting

Values with Case Temperature per DIN V VDE V 0884-10

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Rating

Operating Temperature (TA) −40°C to +105°C

Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground.

Rev. F | Page 11 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

Ambient Operating Temperature

−40°C to +105°C

DD1

DD2

IA

OA

AC Voltage, Unipolar Waveform

VIx Input1

VEx Input

V

DDI

State1

V

DDO

State1

VOx Output1

Notes

L

H or NC

Powered

L

DDI

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Rating

Storage Temperature Range (TST) −65°C to +150°C

Range (TA) Supply Voltage Range (V Input Voltage Range

(V

, VIB, VIC, VID, VE1, VE2)

Output Voltage Range

(V

, VOB, VOC, VOD)

1, 2

, V

)1 −0.5 V to +7.0 V

1, 2

−0.5 V to V

+ 0.5 V

DDI

+ 0.5 V

DDO

Average Output Current Per Pin3

Side 1 (IO1) −18 mA to +18 mA

Side 2 (IO2) −22 mA to +22 mA Common-Mode Transients4 −100 kV/µs to +100 kV/µs

1

All voltages are relative to their respective ground.

2

V

and V

DDI

given channel, respectively. See the PC Board Layout section.

3

See Figure 4 for maximum rated current values for various temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the Absolute Maximum Rating can cause latchup or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

1

Table 10. Maximum Continuous Working Voltage

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime

Reinforced Insulation 846 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC Voltage

Reinforced Insulation 846 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Ta

ble 11. Truth Table (Positive Logic)

H H or NC Powered Powered H

X L Powered Powered Z X H or NC Unpowered Powered H Outputs return to input state within 1 µs of V

power restoration. X L Unpowered Powered Z X X Powered Unpowered Indeterminate Outputs return to input state within 1 µs of V

power restoration if

DDO

VEx state is H or NC. Outputs return to high impedance state within 8 ns of V

1

VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. V

V

refer to the supply voltages on the input and output sides of the given channel, respectively.

DDO

power restoration if VEx state is L.

DDO

and

DDI

Rev. F | Page 12 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

05007-005

V

DD1

1

*GND

1

2

V

IA

3

V

IB

4

V

DD2

16

GND

2

*

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

ID

6

V

OD

11

NC

7

V

E2

10

*GND

1

8

GND

2

*

9

NC = NO CONNECT

ADuM2400

TOP VIEW

(Not to Scale)

*

PIN 2 AND PIN 8 ARE I NTERNALLY CONNECTED, AND CONNECTING BOTH TO GND

1

IS RECOMME NDED. PIN 9 AND PI N 15 ARE INTERNAL LY

CONNECTED, AND CO NNECTING BOTH TO GND

2

IS RECOMMENDED.

DD1

1

IA

5

VIC

Logic Input C.

ID

OD

DD2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. ADuM2400 Pin Configuration

Table 12. ADuM2400 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 GND 3 V

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Logic Input A.

4 VIB Logic Input B.

6 V

Logic Input D. 7 NC No Connect. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.

VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic

high or low is recommended. 11 V

Logic Output D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. F | Page 13 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

05007-006

V

DD1

1

*GND

1

2

V

IA

3

V

IB

4

V

DD2

16

GND

2

*

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

OD

6

V

ID

11

V

E1

7

V

E2

10

*GND

1

8

GND2*

9

ADuM2401

TOP VIEW

(Not to Scale)

*PIN 2 AND PI N 8 ARE INTERNAL LY CONNECTED, AND CONNECTI NG

BOTH TO GND1 IS RECOMME NDED. PIN 9 AND PI N 15 ARE INTERNAL LY CONNECTED, AND CO NNECTING BOTH TO GND2 IS RECOMMENDED.

DD1

1

IA

OD

E1

ID

DD2

Table 13. ADuM2401 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 GND 3 V

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 V

Logic Output D. 7 VE1 Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled

when V

is low. In noisy environments, connecting VE1 to an external logic high or low is recommended. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,

V

, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or

OB

low is recommended.

11 V

Logic Input D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Figure 6. ADuM2401 Pin Configuration

Rev. F | Page 14 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

05007-007

V

DD1

1

*GND

1

2

V

IA

3

V

IB

4

V

DD2

16

GND

2

*

15

V

OA

14

V

OB

13

V

OC

5

V

IC

12

V

OD

6

V

ID

11

V

E1

7

V

E2

10

*GND

1

8

GND

2

*

9

ADuM2402

TOP VIEW

(Not to Scale)

*PIN 2 AND PI N 8 ARE INTERNAL LY CONNECTED, AND CONNECTI NG

BOTH TO GND

1

IS RECOMME NDED. PIN 9 AND PI N 15 ARE INTERNAL LY

CONNECTED, AND CO NNECTING BOTH TO GND

2

IS RECOMMENDED.

DD1

1

IA

4

VIB

Logic Input B.

OD

11

V

ID

Logic Input D.

DD2

Figure 7. ADuM2402 Pin Configuration

Table 14. ADuM2402 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 GND 3 V

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Logic Input A.

5 VOC Logic Output C. 6 V

Logic Output D.

7 VE1 Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected.

VOC and VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or

low is recommended. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected.

and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or

V

OA

low is recommended.

12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. F | Page 15 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

20

80

70

15

10

5V

5

CURRENT/CHANNEL (mA)

0

20 60 8040 100

DATA RATE (Mbps)

3V

Figure 8. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

6

5

4

3

2

CURRENT/CHANNEL (mA)

1

5V

3V

05007-008

60

50

40

30

CURRENT (mA)

20

10

0

20 60 8040 100

Figure 11. Typical ADuM2400 V

25

20

15

10

CURRENT (mA)

5

5V

3V

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD1

for 5 V and 3 V Operation

5V

3V

05007-011

0

20 60 8040 100

DATA RATE (Mbps)

Figure 9. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

10

8

6

4

CURRENT/CHANNEL (mA)

2

0

5V

3V

20 60 8040 100

DATA RATE (Mbps)

Figure 10. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

05007-009

05007-010

Rev. F | Page 16 of 24

0

20 60 8040 100

Figure 12. Typical ADuM2400 V

for 5 V and 3 V Operation

35

30

25

20

15

CURRENT (mA)

10

5

0

20 60 8040 100

Figure 13. Typical ADuM2401 V

for 5 V and 3 V Operation

DATA RATE (Mb ps)

Supply Current vs. Data Rate

DD2

5V

3V

DATA RATE (M bps)

Supply Current vs. Data Rate

DD1

05007-012

05007-013

Data Sheet ADuM2400/ADuM2401/ADuM2402

40

35

40

30

25

20

15

CURRENT (mA)

10

5

0

20 60 8040 100

Figure 14. Typical ADuM2401 V

50

45

40

35

30

25

20

CURRENT (mA)

15

10

5

0

20 60 8040 100

Figure 15. Typical ADuM2402 V

5V

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD2

for 5 V and 3 V Operation

5V

3V

DATA RATE (Mbps)

or V

DD1

Supply Current vs. Data Rate

DD2

for 5 V and 3 V Operation

35

3V

05007-014

30

PROPAGATION DELAY (ns)

25

–50 –25

0507525 100

TEMPERATURE (°C)

3V

5V

05007-016

Figure 16. Propagation Delay vs. Temperature, C Grade

05007-015

Rev. F | Page 17 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

V

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM2400/ADuM2401/ADuM2402 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 17). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V and between Pin 15 and Pin 16 for V

. The capacitor value

DD2

DD1

should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should be considered unless the ground pair on each package side are connected close to the package.

V

DD1

GND

1

V

IA

V

IB IC/VOC ID/VOD

V

E1

GND

1

Figure 17. Recommended Printed Circuit Board Layout

V

DD2

GND V

OA

V

OB

V

OC/VIC

V

OD/VID

V

E2

GND

2

05007-017

In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage.

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to logic high.

INPUT (

OUTPUT (V

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs among channels within a single

ADuM2400/ADuM2401/ADuM2402 component.

Propagation delay skew refers to the maximum amount the propagation delay differs among multiple ADuM2400/

ADuM2401/ADuM2402 components operated under the same

conditions.

)

Ix

t

PLH

)

Ox

Figure 18. Propagation Delay Parameters

50%

t

PHL

50%

05007-018

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than approximately 5 μs, the input side is assumed to be without power or nonfunctional; in which case, the isolator output is forced to a default state (see Table 11) by the watchdog timer circuit.

The limitation on the ADuM2400/ADuM2401/ADuM2402 magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM2400/ADuM2401/ADuM2402 is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)Σ∏r

where:

β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. r

is the radius of the nth turn in the receiving coil (cm).

n

Given the geometry of the receiving coil in the ADuM2400/

ADuM2401/ADuM2402 and an imposed requirement that the

induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19.

100

10

1

0.1

DENSITY ( kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001 1k 10k 10M

Figure 19. Maximum Allowable External Magnetic Flux Density

2

; n = 1, 2,…, N

n

MAGNETIC FIELD FREQUE NCY (Hz )

1M

05007-019

100M100k

Rev. F | Page 18 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

MAGNETIC F IELD F REQUENCY (Hz)

MAXIMUM ALLOWABLE CURRENT (kA)

1000

100

10

1

0.1

0.01 1k 10k

100M

100k

1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

05007-020

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the

ADuM2400/ADuM2401/ADuM2402 transformers. Figure 20

expresses these allowable current magnitudes as a function of frequency for selected distances. As can be seen, the

ADuM2400/ADuM2401/ADuM2402 is immune and can be

affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted, place a 0.5 kA current 5 mm away from the

ADuM2400/ADuM2401/ADuM2402 to affect the component’s

operation.

Figure 20. Maximum Allowable Current for Various Current-to-

ADuM2400/ADuM2401/ADuM2402 Spacings

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM2400/

ADuM2401/ADuM2402 isolator is a function of the supply

voltage, the data rate of the channel, and the output load of the channel.

For each input channel, the supply current is given by:

I

= I

DDI

I

= I

DDI

For each output channel, the supply current is given by:

I

DDO

I

DDO

where:

I

, I

DDI (D)

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

V

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

f

is the input stage refresh rate (Mbps).

r

I

, I

DDI (Q)

DDO (Q)

supply currents (mA).

To calculate the total I input and output channel corresponding to I calculated and totaled. Figure 8 and Figure 9 provide per channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides per channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 provide the total I data rate for the ADuM2400/ADuM2401/ADuM2402 channel configurations.

f ≤ 0.5fr

DDI (Q)

× (2f − fr) + I

= I

= (I

DDI (D)

f ≤ 0.5fr

DDO (Q)

+ (0.5 × 10-3 × CLV

DDO (D)

DDI (Q)

) × (2f − fr) + I

DDO

are the input and output dynamic supply currents

are the specified input and output quiescent

DD1

and I

, the supply currents for each

DD2

and I

DD1

and I

as a function of

DD2

DDO (Q)

DD2

f > 0.5fr

are

Rev. F | Page 19 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

0V

RATED PEAK VOL TAGE

05007-021

0V

RATED PEAK VOL TAGE

05007-022

0V

RATED PEAK VOL TAGE

05007-023

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM2400/

ADuM2401/ADuM2402.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM2400/ADuM2401/

ADuM2402 depends on the voltage waveform type imposed

across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Tab l e 10 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 22 or Figure 23 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10.

Note that the voltage presented in Figure 22 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

Figure 21. Bipolar AC Waveform

Figure 22. Unipolar AC Waveform

Figure 23. DC Waveform

Rev. F | Page 20 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

10.50 (0.4134)

10.10 (0.3976)

0.30 (0.0118)

0.10 (0.0039)

2.65 (0.1043)

2.35 (0.0925)

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

0.75 (0.0295)

0.25 (0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.33 (0.0130)

0.20 (0.0079)

0.51 (0.0201)

0.31 (0.0122)

SEATING PLANE

8° 0°

16

9

8

1

1.27 (0.0500) BSC

03-27-2007-B

11-15-2011-A

16

9

81

SEATING PLANE

COPLANARIT Y

0.1

1.27 BSC

12.85

12.75

12.65

7.60

7.50

7.40

2.64

2.54

2.44

1.01

0.76

0.51

0.30

0.20

0.10

10.51

10.31

10.11

0.46

0.36

2.44

2.24

PIN 1

MARK

1.93 REF

8° 0°

0.32

0.23

0.71

0.50

0.31

45°

0.25 BSC GAGE

PLANE

COMPLIANT TO JEDEC STANDARDS MS-013-AC

OUTLINE DIMENSIONS

Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

Figure 25. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]

Wide Body

(RI-16-2)

Dimensions shown in millimeters

Rev. F | Page 21 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

Number

Maximum

ADuM2400BRWZ

4 0 10

50 3 −40°C to +105°C

16-Lead SOIC_W

RW-16

ADuM2401ARWZ

3 1 1

100

40

−40°C to +105°C

16-Lead SOIC_W

RW-16

ADuM2402ARIZ

2 2 1

100

40

−40°C to +105°C

16-Lead SOIC_IC

RI-16-2

ORDERING GUIDE

Model

1, 2

of Inputs, V

DD1

Side

of Inputs,

Side

V

DD2

Data Rate (Mbps)

Propagation Delay, 5 V (ns)

Pulse Width Distortion (ns)

Temperature Range Package Description

Package Option

ADuM2400ARWZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16

ADuM2400CRWZ 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM2400ARIZ

4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-2 ADuM2400BRIZ 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-2 ADuM2400CRIZ 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_IC RI-16-2

ADuM2401BRWZ 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM2401CRWZ 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM2401ARIZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-2 ADuM2401BRIZ 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-2 ADuM2401CRIZ 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_IC RI-16-2 ADuM2402ARWZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM2402BRWZ 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM2402CRWZ 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16

ADuM2402BRIZ 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-2 ADuM2402CRIZ 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_IC RI-16-2

1

Tape and reel is available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.

2

Z = RoHS Compliant Part.

Rev. F | Page 22 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

NOTES

Rev. F | Page 23 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

NOTES

registered trademarks are the property of their respective owners. D05007-0-7/15(F)

Rev. F | Page 24 of 24

ANALOG DEVICES ADUM 2401 ARWZ, ADUM 2400 ARWZ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE

NOTES

NOTES