ANALOG DEVICES ADUM 2401 ARWZ, ADUM 2400 ARWZ Datasheet

Quad-Channel Digital Isolators

k

Data Sheet

FEATURES

Low power operation

5 V operation

1.0 mA per channel maximum @ 0 Mbps to 2 Mbps

3.5 mA per channel maximum @ 10 Mbps
31 mA per channel maximum @ 90 Mbps

3 V operation

0.7 mA per channel maximum @ 0 Mbps to 2 Mbps

2.1 mA per channel maximum @ 10 Mbps

20 mA per channel maximum @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package version (RW-16)
16-lead SOIC wide body enhanced creepage version (RI-16)

Safety and regulatory approvals (RI-16 package)

UL

recognition: 5000 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice 5A

IEC 60601-1: 250 V rms (reinforced)

IEC 60950-1: 400 V rms (reinforced)

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V

= 846 V peak

IORM

APPLICATIONS

General-purpose, high voltage, multichannel isolation
Medical equipment
Motor drives
Power supplies

GENERAL DESCRIPTION

The ADuM2400/ADuM2401/ADuM24021 are 4-channel digital
isolators based on Analog Devices, Inc., iCoupler® technology.
Combining high speed CMOS and monolithic air core transformer
technology, these isolation components provide outstanding
performance characteristics that are superior to alternatives, such
as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto­couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and tempera

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.

Document Feedbac

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

ADuM2400/ADuM2401/ADuM2402

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

2

GND

1

3

V

V

V
V

NC

GND

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

ENCODE DECODE

ID

7
8

1

Figure 1. ADuM24

1

V

DD1

2

GND

1

3

V

V

V

V

V

GND

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

DECODE ENCODE

OD

7

E1

8

1

Figure 2. ADuM24

1

V

DD1

2

GND

1

3

V

V

V
V

V

GND

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

OC

6

DECODE ENCODE

OD

7

E1

8

1

Figure 3. ADuM24

ture and lifetime effects are eliminated with the simple iCoupler
digital interfaces and stable performance characteristics. Further­more, iCoupler devices run at one-tenth to one-sixth the power
of optocouplers at comparable signal data rates.

The ADuM2400/ADuM2401/ADuM2402 isolators provide four
independent isolation channels in a variety of channel configura­tions and data rates (see the Ordering Guide). The ADuM2400/

ADuM2401/ADuM2402 models operate with the supply voltage

of either side ranging from 2.7 V to 5.5 V, providing compatibil­ity with lower voltage systems as well as enabling a voltage
translation functionality across the isolation barrier. In addition,
the ADuM2400/ADuM2401/ADuM2402 provide low pulse
width distortion (<2 ns for CRWZ grade) and tight channel-to­channel matching (<2 ns for CRWZ grade). The ADuM2400/

ADuM2401/ADuM2402 isolators have a patented refresh feature

that ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2005–2015 Analog Devices, Inc. All rights reserved.

Tec hn ical Su pp or t www.analog.com

ADuM2400

00

ADuM2401

01

ADuM2402

02

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

05007-001

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

V

E2

9

GND

2

05007-002

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

V

E2

9

GND

2

05007-003

ADuM2400/ADuM2401/ADuM2402 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams ............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 5

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation ....................................................................................... 7

Package Characteristics ............................................................. 10

Regulatory Information ............................................................. 10

Insulation and Safety-Related Specifications .......................... 10

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics ............................................................................ 11

Recommended Operating Conditions .................................... 11

Absolute Maximum Ratings ......................................................... 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13

Typical Performance Characteristics ........................................... 16

Application Information ................................................................ 18

PC Board Layout ........................................................................ 18

Propagation Delay-Related Parameters ................................... 18

DC Correctness and Magnetic Field Immunity.......................... 18

Power Consumption .................................................................. 19

Insulation Lifetime ..................................................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 22

REVISION HISTORY

7/15—Rev. E to Rev. F

Changes to Table 5 and Table 6 ..................................................... 10

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 22

2/12—Rev. D to Rev. E

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 18

8/11—Rev. C to Rev. D

Added 16-Lead SOIC_IC .................................................. Universal

Changes to Features Section and General Description

Section ................................................................................................ 1

Changes to Table 5 and Table 6 ..................................................... 10

Changes to Table 8 Endnote .......................................................... 11

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

7/08—Rev. B to Rev. C

Changes to Layout ............................................................................ 1

Changes to Table 6 .......................................................................... 10

6/07—Rev. A to Rev. B

Updated VDE Certification Throughout ....................................... 1

Changes to Features and Note 1 ...................................................... 1

Changes to Figure 1, Figure 2, and Figure 3 .................................. 1

Changes to Regulatory Information ............................................ 10

Changes to Table 7 .......................................................................... 11

Changes to Insulation Lifetime Section ...................................... 20

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

1/06—Rev. 0 to Rev. A

Changes to Regulatory Information Section .............................. 13

Updated Outline Dimensions ....................................................... 23

Changes to Ordering Guide .......................................................... 23

9/05—Revision 0: Initial Version

Rev. F | Page 2 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

DDO (Q)

DD1

DD1 (Q)

V

DD1

Supply Current

I

DD1 (10)

8.6

10.6

mA

5 MHz logic signal frequency

DD1

DD1 (90)

DD1

DD1 (Q)

DD2

DD2 (Q)

DD1

DD1 (10)

DD1

DD1 (90)

10 Mbps (BRWZ and CRWZ Grades Only)

DD1

DD2

DD1 (90)

DD2 (90)

EH

EL

DD1

DD2

IxH

IxL

0.04

0.1 V IOx = 400 µA, VIx = V

IxL

IxL

PHL

PLH

PLH

PHL

Channel-to-Channel Matching7

t

PSKCD/tPSKOD

50

ns

CL = 15 pF, CMOS signal levels

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION1

4.5 V ≤ V
unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM2400 Total Supply Current, Four Channels2

ADuM2401 Total Supply Current, Four Channels2

ADuM2402 Total Supply Current, Four Channels2

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.50 0.53 mA

DDI (Q)

DD1

= V

DD2

= 5 V.

0.19 0.21 mA

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal frequency

0.9 1.4 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ and CRWZ Grades Only)

V

Supply Current I

DD2

2.6 3.5 mA 5 MHz logic signal frequency

DD2 (10)

90 Mbps (CRWZ Grade Only)

V

Supply Current I

V

Supply Current I

DD2

70 100 mA 45 MHz logic signal frequency
18 25 mA 45 MHz logic signal frequency

DD2 (90)

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

1.8 2.4 mA DC to 1 MHz logic signal frequency

1.2 1.8 mA DC to 1 MHz logic signal frequency

10 Mbps (BRWZ and CRWZ Grades Only)

V

Supply Current I

V

Supply Current I

DD2

7.1 9.0 mA 5 MHz logic signal frequency

4.1 5.0 mA 5 MHz logic signal frequency

DD2 (10)

90 Mbps (CRWZ Grade Only)

V

Supply Current I

V

Supply Current I

DD2

57 82 mA 45 MHz logic signal frequency
31 43 mA 45 MHz logic signal frequency

DD2 (90)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

1.5 2.1 mA DC to 1 MHz logic signal frequency

DD2 (Q)

V

or V

DD1

Supply Current I

DD2

DD1 (10)

, I

5.6 7.0 mA 5 MHz logic signal frequency

DD2 (10)

90 Mbps (CRWZ Grade Only)

V

or V

Supply Current I

, I

44 62 mA 45 MHz logic signal frequency

For All Models

Input Currents IIA, IIB, IIC,

, IE1, I

I

ID

E2

Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages V

(V

Logic Low Output Voltages V

VIH, V
VIL, V

OAH

V

OCH

OAL

V

OCL

, V
, V

, V
, V

OBH

ODH

OBL

ODL

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V
0 V ≤ V

E1

2.0 V

0.8 V

,

(V

or V

DD1

,

0.0 0.1 V IOx = 20 µA, VIx = V

) − 0.1 5.0 V IOx = −20 µA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

, VE2 ≤ V

DD1

0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS

ADuM2400ARWZ/ADuM2401ARWZ/

ADuM2402ARWZ

Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t

− t

5

|

Propagation Delay Skew6 t

, t

50 65 100 ns CL = 15 pF, CMOS signal levels

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

Rev. F | Page 3 of 24

or V

IxH

or V

DD1

DD2

,

DD2

ADuM2400/ADuM2401/ADuM2402 Data Sheet

PHL

PLH

Propagation Delay Skew6

t

PSK

15

ns

CL = 15 pF, CMOS signal levels

Opposing-Directional Channels7

ADuM2400CRWZ/ADuM2401CRWZ/

PLH

PHL

5

PSK

DDI (D)

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM2400BRWZ/ADuM2401BRWZ/

ADuM2402BRWZ

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t

PLH

− t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

7

Channel-to-Channel Matching,

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

ADuM2402CRWZ

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t

− t

|

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing-Directional Channels

7

7

For All Models

Output Disable Propagation Delay

10 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

(High/Low to High Impedance)

Output Enable Propagation Delay

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at

Logic High Output
Common-Mode Transient Immunity at

Logic Low Output

8

8

|CM

| 25 35 kV/µs VIx = V

H

DD1

or V

DD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 I
Output Dynamic Supply Current per Channel9 I

1

All voltages are relative to their respective ground.

2

Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8
through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for
total V

and V

DD1

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a
given data rate.

supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

DD2

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.19 mA/Mbps

0.05 mA/Mbps

propagation delay is

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

PLH

Rev. F | Page 4 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

DDI (Q)

DDO (Q)

DD2

DD2 (Q)

10 Mbps (BRWZ and CRWZ Grades Only)

DD2

DD2 (10)

V

DD2

Supply Current

I

DD2 (90)

11

15

mA

45 MHz logic signal frequency

DD1

DD1 (Q)

DD1

DD1 (10)

DD2

DD2 (10)

DD2

DD2 (90)

V

DD1

or V

DD2

Supply Current

I

DD1 (Q)

, I

DD2 (Q)

0.9

1.5

mA

DC to 1 MHz logic signal frequency

DD1

DD2

DD1 (10)

DD2 (10)

ID

E2

E1

DD1

DD2

EH

DD1

DD2

IxH

DD1

DD2

IxH

0.04

0.1 V IOx = 400 µA, VIx = V

IxL

5

Propagation Delay Skew6

t

PSK

50

ns

CL = 15 pF, CMOS signal levels

ELECTRICAL CHARACTERISTICS—3 V OPERATION1

2.7 V ≤ V
unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I

ADuM2400 Total Supply Current, Four Channels2

ADuM2401 Total Supply Current, Four Channels2

ADuM2402 Total Supply Current, Four Channels2

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.26 0.31 mA

0.11 0.14 mA

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

V

Supply Current I

DD1

V

Supply Current I

1.2 1.9 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.5 0.9 mA DC to 1 MHz logic signal frequency

4.5 6.5 mA 5 MHz logic signal frequency

DD1 (10)

1.4 2.0 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

Supply Current I

DD1

37 65 mA 45 MHz logic signal frequency

DD1 (90)

DC to 2 Mbps

V

Supply Current I

V

Supply Current I

DD2

1.0 1.6 mA DC to 1 MHz logic signal frequency

0.7 1.2 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ and CRWZ Grades Only)

V

Supply Current I

V

Supply Current I

3.7 5.4 mA 5 MHz logic signal frequency

2.2 3.0 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

30 52 mA 45 MHz logic signal frequency

DD1 (90)

18 27 mA 45 MHz logic signal frequency

DC to 2 Mbps

10 Mbps (BRWZ and CRWZ Grades Only)

V

or V

Supply Current I

, I

3.0 4.2 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

or V

DD1

Supply Current I

DD2

DD1 (90)

, I

24 39 mA 45 MHz logic signal frequency

DD2 (90)

For All Models

Input Currents IIA, IIB, IIC,

, IE1, I
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages V

(V

Logic Low Output Voltages V

I
VIH, V
VIL, V

OAH

V

OCH

OAL

V

OCL

, V
, V

EL

, V
, V

OBL

ODL

0.2 0.4 V IOx = 4 mA, VIx = V

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V
0 V ≤ V

1.6 V

0.4 V

,

(V

or V

OBH

ODH

0.0 0.1 V I

,

) − 0.1 3.0 V IOx = −20 µA, VIx = V

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

= 20 µA, VIx = V

Ox

, VE2 ≤ V

IxL

SWITCHING SPECIFICATIONS

ADuM2400ARWZ/ADuM2401ARWZ/

ADuM2402ARWZ

Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t

PLH

− t

PHL

|

Channel-to-Channel Matching7 t

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

or V

IxL

or V

DD2

,

DD1

Rev. F | Page 5 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

PHL

PLH

Propagation Delay Skew6

t

PSK

22

ns

CL = 15 pF, CMOS signal levels

Opposing-Directional Channels7

ADuM2400CRWZ/ADuM2401CRWZ/

PLH

PHL

5

PSK

DDI (D)

DDO (D)

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM2400BRWZ/ADuM2401BRWZ/

ADuM2402BRWZ

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t

PLH

− t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

7

Channel-to-Channel Matching,

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

ADuM2402CRWZ

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t

− t

|

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing-Directional Channels

7

7

For All Models

Output Disable Propagation Delay

16 ns CL = 15 pF, CMOS signal levels

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

(High/Low to High Impedance)

Output Enable Propagation Delay

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at

Logic High Output
Common-Mode Transient Immunity at

Logic Low Output

8

8

|CM

| 25 35 kV/µs VIx = V

H

DD1

or V

DD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel9 I
Output Dynamic Supply Current per Channel9 I

1

All voltages are relative to their respective ground.

2

Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8
through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for
total V

and V

DD1

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a
given data rate.

supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

DD2

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.10 mA/Mbps

0.03 mA/Mbps

propagation delay is

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

PLH

Rev. F | Page 6 of 24

Data Sheet ADuM2400/ADuM2401/ADuM2402

5 V/3 V Operation

0.50

0.53

mA

DDO (Q)

DD1

DD1 (Q)

DD2

DD2 (Q)

10 Mbps (BRWZ and CRWZ Grades Only)

5 V/3 V Operation

1.4

2.0

mA

5 MHz logic signal frequency

V

DD1

Supply Current

I

DD1 (90)

DD2

DD2 (90)

DD1

DD1 (Q)

3 V/5 V Operation

1.0

1.6

mA

DC to 1 MHz logic signal frequency

DD1

DD1 (10)

V

DD2

Supply Current

I

DD2 (10)

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1

5 V/3 V operation: 4.5 V ≤ V
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications
are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

3 V/5 V Operation 0.26 0.31 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.11 0.14 mA
3 V/5 V Operation 0.19 0.21 mA

ADuM2400 Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I
5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal frequency

V

Supply Current I
5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal frequency

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V; o r V

DD2

≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ V

DD2

= 5 V, V

DD1

DDI (Q)

= 3.0 V.

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All

DD2

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal frequency
3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

DD2 (10)

3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

5 V/3 V Operation 70 100 mA 45 MHz logic signal frequency
3 V/5 V Operation 37 65 mA 45 MHz logic signal frequency

V

Supply Current I
5 V/3 V Operation 11 15 mA 45 MHz logic signal frequency
3 V/5 V Operation 18 25 mA 45 MHz logic signal frequency

ADuM2401 Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I
5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal frequency

10 Mbps (BRWZ and CRWZ Grades Only)

V

Supply Current I
5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal frequency

5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal frequency
3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 57 82 mA 45 MHz logic signal frequency
3 V/5 V Operation 30 52 mA 45 MHz logic signal frequency

DD1 (90)

Rev. F | Page 7 of 24

ADuM2400/ADuM2401/ADuM2402 Data Sheet

3 V/5 V Operation

0.9

1.5

mA

DC to 1 MHz logic signal frequency

V

DD1

Supply Current

I

DD1 (10)

DD2

DD2 (10)

3 V/5 V Operation

5.6

7.0

mA

5 MHz logic signal frequency

DD1

DD1 (90)

5 V/3 V Operation

44

62

mA

45 MHz logic signal frequency

DD2

DD2 (90)

For All Models

ID

E2

DD1

DD2

EH

Logic Low Output Voltages

V

,

0.0

0.1 V IOx = 20 µA, VIx = V

IxL

IxL

PHL

PLH

Pulse-Width Distortion, |t

PLH

− t

PHL

|

5

PWD

40

ns

CL = 15 pF, CMOS signal levels

PSKCD/tPSKOD

PHL

PLH

Parameter Symbol Min Typ Max Unit Test Conditions

V

Supply Current I

DD2

5 V/3 V Operation 18 27 mA 45 MHz logic signal frequency
3 V/5 V Operation 31 43 mA 45 MHz logic signal frequency

ADuM2402 Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal frequency

10 Mbps (BRWZ and CRWZ Grades Only)

5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal frequency

V

Supply Current I

5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal frequency

90 Mbps (CRWZ Grade Only)

V

Supply Current I

3 V/5 V Operation 24 39 mA 45 MHz logic signal frequency

V

Supply Current I
5 V/3 V Operation 24 39 mA 45 MHz logic signal frequency
3 V/5 V Operation 44 62 mA 45 MHz logic signal frequency

DD2 (90)

DD1 (Q)

DD2 (Q)

Input Currents IIA, IIB, IIC,

, IE1, I

I
VIH, V

Logic High Input Threshold

−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ V
0 V ≤ VE1, VE2 ≤ V

or V

5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V

Logic Low Input Threshold

VIL, V

EL

5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V

Logic High Output Voltages V

(V

0.04 0.1 V IOx = 400 µA, VIx = V

OAH

V

OCH

OAL, VOBL

V

, V

OCL

, V

,

(V

or V

) −

(V

or V

OBH

DD1

DD1

or V

DD2

DD2

, V

0.1

ODH

0.4

ODL

) −

(V

0.2

DD1

DD1

) V IOx = −20 µA, VIx = V

DD2

or V

) −

V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS

ADuM2400ARWZ/ADuM2401ARWZ/

ADuM2402ARWZ

Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t

Propagation Delay Skew6 t
Channel-to-Channel Matching7 t

ADuM2400BRWZ/ADuM2401BRWZ/

, t

50 70 100 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

ADuM2402BRWZ

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t

, t

15 35 50 ns CL = 15 pF, CMOS signal levels

or V

DD1

DD2,

IxH

IxH

IxL

Rev. F | Page 8 of 24