Analog Devices ADuM 2250, ADuM 2251 Service Manual
G
G
Hot-Swappable, Dual I2C Isolators, 5 kV
FEATURES
Bidirectional I2C communication
Open-drain interfaces
Suitable for hot-swap applications
30 mA current sink capability
1000 kHz operation
3.0 V to 5.5 V supply/logic levels
Wide body, 16-lead SOIC package with >8 mm creepage
High temperature operation: 105°C
Safety and regulatory approvals
UL recognition (pending)
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
V
= 846 V peak
IORM
APPLICATIONS
Isolated I2C, SMBus, or PMBus Interfaces
Multilevel I
Power supplies
Networking
Power-over-Ethernet
2
C interfaces
ADuM2250/ADuM2251
GENERAL DESCRIPTION
The ADuM2250/ADuM22511 are hot-swappable digital
isolators with nonlatching bidirectional communication
channels that are compatible with I
eliminates the need for splitting I
transmit and receive signals for use with standalone
optocouplers.
The ADuM2250 provides two bidirectional channels supporting a complete isolated I
2
C interface. The ADuM2251 provides
one bidirectional channel and one unidirectional channel for
those applications where a bidirectional clock is not required.
The ADuM2250/ADuM2251 contain hot-swap circuitry to
prevent data glitches when an unpowered card is inserted
onto an active bus.
These isolators are based on iCoupler® chip-scale transformer
technology from Analog Devices, Inc. iCoupler is a magnetic
isolation technology with performance, size, power consumption, and functional advantages compared to optocouplers.
The ADuM2250/ADuM2251 integrate iCoupler channels
with semiconductor circuitry to enable a complete, isolated
2
I
C interface in a small form-factor package.
1
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329; other patents
pending.
2
C® interfaces. This
2
C signals into separate
FUNCTIONAL BLOCK DIAGRAMS
1
ND
1
ADuM2250
2
NC
3
V
DD1
4
NC
5
SDA
1
SCL
6
1
7
ND
1
8
NC
NC = NO CONNECT
DECODE
ENCODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
Figure 1. ADuM2250 Functional Block Diagram Figure 2. ADuM2251 Functional Block Diagram
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16
GND
2
15
NC
14
V
DD2
13
NC
12
SDA
2
SCL
11
2
10
NC
9
GND
2
06670-001
1
GND
1
ADuM2251
2
NC
3
V
DD1
4
NC
5
SDA
1
SCL
6
1
7
GND
1
8
NC
NC = NO CONNECT
DECODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
16
GND
15
NC
14
V
13
NC
12
SDA
SCL
11
10
NC
9
GND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
DD2
2
2
2
2
06670-002
ADuM2250/ADuM2251
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Test Conditions............................................................................. 5
Package Characteristics ............................................................... 6
Regulatory Information............................................................... 6
Insulation and Safety-Related Specifications............................ 6
REVISION HISTORY
4/07—Revision 0: Initial Version
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ...............................................................................7
Recommended Operating Conditions .......................................7
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configuration and Function Descriptions..............................9
Applications Information.............................................................. 10
Functional Description.............................................................. 10
Startup.......................................................................................... 11
Magnetic Field Immunity............................................................. 11
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Rev. 0 | Page 2 of 16
ADuM2250/ADuM2251
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
DC Specifications
All voltages are relative to their respective ground. All minimum/maximum specifications apply over the entire recommended operating
range, unless otherwise noted. All typical specifications are at T
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM2250
Input Supply Current, Side 1, 5 V I
Input Supply Current, Side 2, 5 V I
Input Supply Current, Side 1, 3.3 V I
Input Supply Current, Side 2, 3.3 V I
ADuM2251
Input Supply Current, Side 1, 5 V I
Input Supply Current, Side 2, 5 V I
Input Supply Current, Side 1, 3.3 V I
Input Supply Current, Side 2, 3.3 V I
LEAKAGE CURRENTS I
SIDE 1 LOGIC LEVELS
Logic Input Threshold1 V
Logic Low Output Voltages V
600 850 mV
Input/Output Logic Low Level Difference2 ΔV
SIDE 2 LOGIC LEVELS
Logic Low Input Voltage V
Logic High Input Voltage V
Logic Low Output Voltage V
1
VIL < 0.5 V, VIH > 0.7 V.
2
ΔV
= V
– V
S1L
there is no possibility of the part latching up the bus to which it is connected.
. This is the minimum difference between the output logic low level and the input logic low threshold within a given component. This ensures that
S1OL
S1IL
2.8 5.0 mA V
DD1
2.7 5.0 mA V
DD2
1.9 3.0 mA V
DD1
1.7 3.0 mA V
DD2
2.8 6.0 mA V
DD1
2.5 4.7 mA V
DD2
1.8 3.0 mA V
DD1
1.6 2.8 mA V
DD2
, I
ISDA1
ISDA2
, V
SDA1IL
SCL1IL
, V
SDA1OL
SCL1OL
, ΔV
SDA1
, V
SDA2IL
SCL2IL
, V
SDA2IH
SCL2IH
, V
SDA2OL
SCL2OL
, I
= 25°C, V
A
, I
0.01 10 μA V
ISCL1
ISCL2
= 5 V, and V
DD1
= 5 V, unless otherwise noted.
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
SDA1
V
SCL1
= 5 V
= 5 V
= 3.3 V
= 3.3 V
= 5 V
= 5 V
= 3.3 V
= 3.3 V
= V
= V
500 700 mV
600 900 mV I
50 mV
SCL1
0.7 × V
0.3 × V
V
DD2
DD2
V
400 mV I
SDA1
I
SDA1
SDA2
= I
= I
= I
, V
DD1
, V
DD1
= 3.0 mA
SCL1
= 0.5 mA
SCL1
= 30 mA
SCL2
SDA2
SCL2
= V
= V
DD2
DD2
,
Rev. 0 | Page 3 of 16
ADuM2250/ADuM2251
AC Specifications
All voltages are relative to their respective ground. All minimum/maximum specifications apply over the entire recommended operating
range, unless otherwise noted. All typical specifications are at T
for a timing test diagram.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
MAXIMUM FREQUENCY 1000 kHz
OUTPUT FALL TIME
5 V Operation 4.5 V ≤ V
Side 1 Output (0.9 V
Side 2 Output (0.9 V
3 V Operation 3.0 V ≤ V
Side 1 Output (0.9 V
Side 2 Output (0.9 V
PROPAGATION DELAY
5 V Operation 4.5 V ≤ V
Side 1 to Side 2, Rising Edge1 t
Side 1 to Side 2, Falling Edge2 t
Side 2 to Side 1, Rising Edge3 t
Side 2 to Side 1, Falling Edge4 t
3 V Operation 3.0 V ≤ V
Side 1 to Side 2, Rising Edge1 t
Side 1 to Side 2, Falling Edge2 t
Side 2 to Side 1, Rising Edge3 t
Side 2 to Side 1, Falling Edge4 t
PULSE-WIDTH DISTORTION
5 V Operation 4.5 V ≤ V
Side 1 -to Side 2, |t
Side 2 to Side 1, |t
3 V Operation 3.0 V ≤ V
Side 1 to Side 2, |t
Side 2 to Side 1, |t
COMMON-MODE TRANSIENT IMMUNITY5 |CMH|, |CML| 25 35 kV/μs
1
t
propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 V
PLH12
2
t
propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
PHL12
3
t
propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 V
PLH21
4
t
propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
PHL21
5
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
to 0.9 V) tf1 13 26 120 ns
DD1
to 0.1 V
DD2
to 0.9 V) tf1 13 32 120 ns
DD1
to 0.1 V
DD2
− t
PLH12
− t
PLH21
− t
PLH12
− t
PLH21
) tf2 32 52 120 ns
DD2
) tf2 32 61 120 ns
DD2
95 130 ns
PLH12
162 275 ns
PHL12
31 70 ns
PLH21
85 155 ns
PHL21
82 125 ns
PLH12
196 340 ns
PHL12
32 75 ns
PLH21
110 210 ns
PHL21
| PWD12 67 145 ns
PHL12
| PWD21 54 85 ns
PHL21
| PWD12 114 215 ns
PHL12
| PWD21 77 135 ns
PHL21
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
O
= 25°C, V
A
= 5 V, and V
DD1
= 5 V, unless otherwise noted. See Figure 3
DD2
, V
≤ 5.5 V, CL1 = 40 pF,
DD1
= 1.6 kΩ, CL2 = 400 pF, R2 = 180 Ω
R
1
= 1.0 kΩ, CL2 = 400 pF, R2 = 120 Ω
R
1
= 1.6 kΩ, R2 = 180 Ω
R
1
= 1.0 kΩ, R2 = 120 Ω
R
1
= 1.6 kΩ, R2 = 180 Ω
R
1
= 1.0 kΩ, R2 = 120 Ω
R
1
.
DD2
.
DD1
. CML is the maximum common-mode voltage slew rate
DD2
DD2
, V
≤ 3.6 V, C
DD1
DD2
, V
≤ 5.5 V, CL1 = CL2 = 0 pF,
DD1
DD2
, V
≤ 3.6 V, CL1 = CL2 = 0 pF,
DD1
DD2
, V
≤ 5.5 V, CL1 = C
DD1
DD2
, V
≤ 3.6 V, CL1 = CL2 = 0 pF,
DD1
DD2
= 40 pF,
L1
= 0 pF,
L2
Rev. 0 | Page 4 of 16
ADuM2250/ADuM2251
TEST CONDITIONS
GND
1
1
2
3
4
5
6
7
8
ADuM2250
DECODE
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DECODE
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ENCODE
DECODE
ENCODE
DECODE
NC
V
DD1
SDA
SCL
GND
NC
1
1
1
R
R
1
1
C
C
L1
L1
NC
NC = NO CONNECT
Figure 3. Timing Test Diagram
GND
2
16
NC
15
V
DD2
14
NC
13
SDA
2
12
SCL
2
11
NC
10
GND
2
9
R
R
2
2
C
C
L2
L2
6670-005
Rev. 0 | Page 5 of 16
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