The ADuM15101 is a unidirectional, 5-channel isolator based
on the Analog Devices, Inc., iCoupler® technology. Combining
high speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
eliminate the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with iCoupler products. In addition,
iCoupler devices run at one-tenth to one-sixth the power
consumption of optocouplers at comparable signal data rates.
The ADuM1510 isolator provides five independent isolation
channels supporting data rates up to 10 Mbps. The ADuM1510
operates with the supply voltage of either side ranging from 4.5 V
to 5.5 V. Unlike other optocoupler alternatives, the ADuM1510
isolator has a patented refresh feature that ensures dc correctness in
the absence of input logic transitions and during power-up/
power-down conditions.
1
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAM
1
V
DD1
ADuM1510
2
GND
1
3
V
V
V
V
V
GND
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
All voltages are relative to their respective ground. 4.5 V ≤ V
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Quiescent Supply Current per Channel I
Output Quiescent Supply Current per Channel I
DDI (Q)
DDO (Q)
Total Supply Current, Five Channels1
V
Supply Current, Quiescent I
DD1
V
Supply Current, Quiescent I
DD2
V
Supply Current, 10 Mbps Data Rate I
DD1
V
Supply Current, 10 Mbps Data Rate I
DD2
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
Input Currents IIA, IIB, IIC, IID, I
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
V
IH
V
IL
, V
V
OAH
, V
V
OCH
V
OEH
, V
V
OAL
, V
V
OCL
SWITCHING SPECIFICATIONS
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t
PLH
− t
PHL
4
|
, t
PHL
PWD 5 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching6 t
30 ns CL = 15 pF, CMOS signal levels
PSK
PSKCD
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic High Output
Common-Mode Transient Immunity at
Logic Low Output
7
7
|CM
H
|CML| 25 35 kV/µs
Refresh Rate fr 1.0 Mbps
Input Dynamic Supply Current per Channel8 I
Output Dynamic Supply Current per Channel8 I
1
Supply current values are for all five channels combined running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate is calculated as described in the section. See Figur through
for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See and for total I
Figure 6
and I
supply currents as a function of the data rate for the ADuM1510.
DD2
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Operation below the minimum pulse width is not
recommended.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the V
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 × V
that can be sustained while maintaining V
transient magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for infor-
mation on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the P section for guidance on
calculating the per-channel supply current for a given data rate.
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The
Ox
DDI (D)
DDO (D)
signal to the 50% level of the rising edge of the VOx signal.
Ix
and/or t
PHL
PLH
≤ 5.5 V, 4.5 V ≤ V
DD1
≤ 5.5 V; all minimum/maximum specifications apply
DD2
= 25°C, V
A
DD1
= V
DD2
= 5 V.
0.40 0.80 mA
0.30 0.50 mA
2.0 4.0 mA VIA = VIB = VIC = VID = VIE = 0 V
1.5 2.5 mA VIA = VIB = VIC = VID = VIE = 0 V
7.5 12.0 mA 5 MHz logic signal frequency
3.1 4.5 mA 5 MHz logic signal frequency
−10 +1 +10 µA VIA, VIB, VIC, VID, VIE ≥ 0 V
IE
2.0 V
0.8 V
V
,
OBH
,
ODH
,
OBL
, V
ODL
OEL
20 30 50 ns CL = 15 pF, CMOS signal levels
PLH
− 0.4 4.8 V IOx = −4 mA, VIx = VIH
DD2
0.2 0.4 V IOx = +4 mA, VIx = VIL
5 ns CL = 15 pF, CMOS signal levels
| 25 35 kV/µs
= V
V
Ix
DD1/VDD2
, VCM = 1000 V,
transient magnitude = 800 V
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
0.122 mA/Mbps
0.036 mA/Mbps
Power Consumption
that is measured between units at the same operating temperature, supply voltages, and output
. CML is the maximum common-mode voltage slew rate
DD2
ower Consumption
Figure 7Figure 8
Figure 4
propagation delay is
PLH
Figure 6
e 4
DD1
Rev. B | Page 3 of 12
ADuM1510 Data Sheet
PACKAGE CHARACTERISTICS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-to-Output)1 R
Capacitance (Input-to-Output)
2
Input Capacitance2 C
IC Junction-to-Case Thermal Resistance, Side 1 θ
IC Junction-to-Case Thermal Resistance, Side 2 θ
1
The device is considered a two-terminal device. Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM1510 has been approved by the following organization upon product release, as shown in Ta b le 3 .
Table 3.
UL
Recognized under UL 1577 Component Recognition Program1
Double/reinforced insulation, 2500 V rms isolation voltage
File E214100
1
In accordance with UL 1577, each ADuM1510 is proof-tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).
1012 Ω
I-O
C
2.2 pF f = 1 MHz
I-O
4.0 pF
I
33 °C/W
JCI
Thermocouple located at center of
package underside
28 °C/W
JCO
Thermocouple located at center of
package underside
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm
Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.1 min mm
Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
565 V peak
Maximum Working Voltage Compatible with 50 Years
Service Life
V
IORM
Continuous peak voltage across the isolation
barrier
RECOMMENDED OPERATING CONDITIONS
All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on
immunity to external magnetic fields.
Table 5.
Parameter Symbol Min Typ Max Unit
Operating Temperature TA −40 +105 °C
Supply Voltages V
Input Signal Rise and Fall Times 1.0 ms
, V
4.5 5.5 V
DD1
DD2
Rev. B | Page 4 of 12
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