Datasheet ADUM1510 Datasheet (ANALOG DEVICES)

5-Channel, Unidirectional Digital Isolator

Data Sheet

FEATURES

RoHS compliant, 16-lead, wide body SOIC package
Low power operation: 5 V

1.3 mA per channel maximum @ 0 Mbps to 2 Mbps

3.3 mA per channel maximum @ 10 Mbps
High temperature operation: 105°C
Up to 10 Mbps data rate (NRZ)
Low default output state

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

APPLICATIONS

General-purpose, unidirectional, multichannel isolation

ADuM1510

GENERAL DESCRIPTION

The ADuM15101 is a unidirectional, 5-channel isolator based
on the Analog Devices, Inc., iCoupler® technology. Combining
high speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices
eliminate the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with iCoupler products. In addition,
iCoupler devices run at one-tenth to one-sixth the power
consumption of optocouplers at comparable signal data rates.

The ADuM1510 isolator provides five independent isolation
channels supporting data rates up to 10 Mbps. The ADuM1510
operates with the supply voltage of either side ranging from 4.5 V
to 5.5 V. Unlike other optocoupler alternatives, the ADuM1510
isolator has a patented refresh feature that ensures dc correctness in
the absence of input logic transitions and during power-up/
power-down conditions.

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.

FUNCTIONAL BLOCK DIAGRAM

1

V

DD1

ADuM1510

2

GND

1

3

V
V

V
V
V

GND

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

ENCODE DECODE

ID

7

ENCODE DECODE

IE

8

1

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

OE

9

GND

2

06790-001

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2012 Analog Devices, Inc. All rights reserved.

ADuM1510 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Package Characteristics ............................................................... 4

Regulatory Information............................................................... 4

Insulation and Safety-Related Specifications............................ 4

Recommended Operating Conditions ...................................... 4

REVISION HISTORY

3/12—Rev. A to Rev. B

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section................................................................. 1

Change to PCB Layout Section....................................................... 8

Updated Outline Dimensions....................................................... 11

9/08—Revision A: Initial Version

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions..............................6

Typical Performance Characteristics..............................................7

Applications Information.................................................................8

PCB Layout ....................................................................................8

Propagation Delay-Related Parameters......................................8

DC Correctness and Magnetic Field Immunity.............................8

Power Consumption .....................................................................9

Power-Up/Power-Down Considerations ...................................9

Outline Dimensions....................................................................... 11

Ordering Guide .......................................................................... 11



Rev. B | Page 2 of 12

Data Sheet ADuM1510

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Quiescent Supply Current per Channel I
Output Quiescent Supply Current per Channel I

DDI (Q)

DDO (Q)

Total Supply Current, Five Channels1

V

Supply Current, Quiescent I

DD1

V

Supply Current, Quiescent I

DD2

V

Supply Current, 10 Mbps Data Rate I

DD1

V

Supply Current, 10 Mbps Data Rate I

DD2

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

Input Currents IIA, IIB, IIC, IID, I
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages

Logic Low Output Voltages

V

IH

V

IL

, V

V

OAH

, V

V

OCH

V

OEH

, V

V

OAL

, V

V

OCL

SWITCHING SPECIFICATIONS

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t

PLH

− t

PHL

4

|

, t

PHL

PWD 5 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching6 t

30 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at

Logic High Output
Common-Mode Transient Immunity at

Logic Low Output

7

7

|CM

H

|CML| 25 35 kV/µs

Refresh Rate fr 1.0 Mbps
Input Dynamic Supply Current per Channel8 I
Output Dynamic Supply Current per Channel8 I

1

Supply current values are for all five channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate is calculated as described in the section. See Figur through

for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See and for total I

Figure 6
and I

supply currents as a function of the data rate for the ADuM1510.

DD2

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Operation below the minimum pulse width is not

recommended.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 × V

that can be sustained while maintaining V
transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for infor-

mation on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the P section for guidance on
calculating the per-channel supply current for a given data rate.

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The

Ox

DDI (D)

DDO (D)

signal to the 50% level of the rising edge of the VOx signal.

Ix

and/or t

PHL

PLH

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

DD2

= 5 V.

0.40 0.80 mA

0.30 0.50 mA

2.0 4.0 mA VIA = VIB = VIC = VID = VIE = 0 V

1.5 2.5 mA VIA = VIB = VIC = VID = VIE = 0 V

7.5 12.0 mA 5 MHz logic signal frequency

3.1 4.5 mA 5 MHz logic signal frequency

−10 +1 +10 µA VIA, VIB, VIC, VID, VIE ≥ 0 V

IE

2.0 V

0.8 V
V

,

OBH

,

ODH

,

OBL

, V

ODL

OEL

20 30 50 ns CL = 15 pF, CMOS signal levels

PLH

− 0.4 4.8 V IOx = −4 mA, VIx = VIH

DD2

0.2 0.4 V IOx = +4 mA, VIx = VIL

5 ns CL = 15 pF, CMOS signal levels

| 25 35 kV/µs

= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

0.122 mA/Mbps

0.036 mA/Mbps

Power Consumption

that is measured between units at the same operating temperature, supply voltages, and output

. CML is the maximum common-mode voltage slew rate

DD2

ower Consumption

Figure 7 Figure 8

Figure 4

propagation delay is

PLH

Figure 6

e 4

DD1

Rev. B | Page 3 of 12

ADuM1510 Data Sheet

PACKAGE CHARACTERISTICS

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output)1 R
Capacitance (Input-to-Output)

2

Input Capacitance2 C
IC Junction-to-Case Thermal Resistance, Side 1 θ

IC Junction-to-Case Thermal Resistance, Side 2 θ

1

The device is considered a two-terminal device. Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM1510 has been approved by the following organization upon product release, as shown in Ta b le 3 .

Table 3.

UL

Recognized under UL 1577 Component Recognition Program1
Double/reinforced insulation, 2500 V rms isolation voltage
File E214100

1

In accordance with UL 1577, each ADuM1510 is proof-tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).

1012 Ω

I-O

C

2.2 pF f = 1 MHz

I-O

4.0 pF

I

33 °C/W

JCI

Thermocouple located at center of
package underside

28 °C/W

JCO

Thermocouple located at center of
package underside

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 4.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm

Measured from input terminals to output
terminals, shortest distance through air

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Measured from input terminals to output

terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

565 V peak

Maximum Working Voltage Compatible with 50 Years

Service Life

V

IORM

Continuous peak voltage across the isolation

barrier

RECOMMENDED OPERATING CONDITIONS

All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on
immunity to external magnetic fields.

Table 5.

Parameter Symbol Min Typ Max Unit

Operating Temperature TA −40 +105 °C
Supply Voltages V
Input Signal Rise and Fall Times 1.0 ms

, V

4.5 5.5 V

DD1

DD2

Rev. B | Page 4 of 12

Data Sheet ADuM1510

ABSOLUTE MAXIMUM RATINGS

Ambient temperature TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature

) Range

(T

A

Supply Voltages1 (V

, V

) −0.5 V to +7.0 V

DD1

DD2

Input Voltages1

, VIB, VIC, VID, VIE)

(V

IA

Output Voltages1

, VOB, VOC, VOD, VOE)

(V

OA

−40°C to +105°C

−0.5 V to V

−0.5 V to V

+ 0.5 V

DDI

+ 0.5 V

DDO

Average Output Current per Pin2

Side 1 (IO1) −18 mA to +18 mA
Side 2 (IO2) −22 mA to +22 mA

Common-Mode Transients3 −100 kV/s to +100 kV/s

1

All voltages are relative to their respective ground.

2

See Figure 3 for maximum rated current values for various temperatures.

3

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch­up or permanent damage.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 5 of 12

ADuM1510 Data Sheet

*

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2, 8 GND

3 V

IA

1

Supply Voltage for Isolator Side 1 (4.5 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to

GND

is recommended.

1

Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 V
7 V

ID

IE

9, 15 GND2

10 V
11 V

OE

OD

Logic Input D.

Logic Input E.

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to

is recommended.

GND

2

Logic Output E.

Logic Output D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 V

Supply Voltage for Isolator Side 2 (4.5 V to 5.5 V).

DD2

1

V

DD1

GND1*

2

V

3

IA

ADuM1510

4

V

IB

TOP VIEW

(Not to Scale)

V

5

IC

V

6

ID

V

7

IE

8

GND1*

PIN 2 AND PIN 8 ARE I NTERNALLY CONNECTED. CONNE CTING BOT H

IS RECOMME NDE D. PIN 9 AND PIN 15 ARE INTERNALLY

TO GND

1

CONNECTED. CO NNECTING BOT H TO GND

Figure 2. Pin Configuration

16

V

DD2

GND2*

15

V

14

OA

13

V

OB

V

12

OC

V

11

OD

V

10

OE

9

GND2*

IS RECOMMENDED.

2

6790-002

Table 8. Truth Table (Positive Logic)

VIx
Input1

V

DD1

State

V

DD2

State

VOx
Output

1

Description

H Powered Powered H Normal operation, data is high.
L Powered Powered L Normal operation, data is low.
X Unpowered Powered L

Input unpowered. Outputs return to input state within 1 µs of V
See the Power-Up/Power-Down Considerations section for more details.

X Powered Unpowered Z

Output unpowered. Output pins are in high impedance state. Outputs return to
input state within 1 µs of V

power restoration. See the Power-Up/Power-Down

DD2

Considerations section for more details.

1

VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, or E).

Rev. B | Page 6 of 12

power restoration.

DD1

Data Sheet ADuM1510

TYPICAL PERFORMANCE CHARACTERISTICS

350

1.6

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

0

SIDE 2

SIDE 1

50 100 150 200

CASE TEMPERATURE (°C)

Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

1.6

1.4

1.2

1.0

0.8

0.6

CURRENT/CHANNEL (mA)

0.4

DD1

V

0.2

1.4

1.2

1.0

0.8

0.6

0.4

CURRENT/CHANNEL, 15pF LOAD ( mA)

0.2

DD2

V

0

0

06790-003

246810

DATA RATE (Mbps)

6790-006

Figure 6. Typical Output Supply Current per Channel vs. Data Rate

(15 pF Output Load)

8

7

6

5

4

CURRENT (mA)

3

DD1

V

2

1

0

0

246810

DATA RATE (Mbps)

Figure 4. Typical Input Supply Current per Channel vs. Data Rate

1.6

1.4

1.2

1.0

0.8

0.6

CURRENT/CHANNEL (mA)

0.4

DD2

V

0.2

0

0

24681

DATA RATE (Mbps)

Figure 5. Typical Output Supply Current per Channel vs. Data Rate

(No Output Load)

06790-004

0

06790-005

Rev. B | Page 7 of 12

0

0

Figure 7. Typical Total V

8

7

6

5

4

3

2

CURRENT, 15pF LOAD (mA)

DD2

V

1

0

0

Figure 8. Typical Total V

246810

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD1

246810

DATA RATE (Mb ps)

Supply Current vs. Data Rate

DD2

06790-007

06790-008

(15 pF Output Load)

ADuM1510 Data Sheet

V

APPLICATIONS INFORMATION

PCB LAYOUT

The ADuM1510 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 9). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for V
for V

. The capacitor value should be between 0.01 μF and

DD2

and between Pin 15 and Pin 16

DD1

0.1 μF. The total lead length between both ends of the capacitor
and the input power supply pin must not exceed 10 mm. Bypass­ing between Pin 1 and Pin 8 and between Pin 9 and Pin 16
should also be considered unless the ground pair on each
package side is connected close to the package.

V

GND

GND

DD1

1

V

IA

V

IB

V

IC

V

ID

V

IE

1

ADuM1510

Figure 9. Recommended PCB Layout

V

DD2

GND
V

OA

V

OB

V

OC

V

OD

V

OE

GND

2

2

6790-009

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a component.
The propagation delay to a logic low output can differ from the
propagation delay to a logic high output.

INPUT (

OUTPUT (V

)

Ix

t

PLH

)

Ox

t

PHL

50%

50%

Figure 10. Propagation Delay Parameters

Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM1510 component.

Propagation delay skew refers to the maximum amount that
the propagation delay differs among multiple ADuM1510
components operated under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent via the transformer to
the decoder. The decoder is bistable and is, therefore, either set
or reset by the pulses indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs,
a periodic set of refresh pulses indicative of the correct input
state is sent to ensure dc correctness at the output.

06790-010

If the decoder receives no pulses for more than approximately 5 μs,
the input side is assumed to be unpowered or nonfunctional, in
which case, the isolator output is forced to a default low state by
the watchdog timer circuit (see Tab l e 8 ).

The limitation on the magnetic field immunity of the device is
set by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The analysis below defines such conditions. In the follow­ing analysis, the ADuM1510 is examined in a 3 V operating
condition because it represents the most susceptible mode of
operation of all products in its product family.

The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold of approximately

0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by

V = (−dβ/dt) Σπr

2

; n = 1, 2, … N

n

where:

β is the magnetic flux density (gauss).
r

is the radius of the nth turn in the receiving coil (cm).

n

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM1510 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field can be calculated, as shown in Figure 11.

100

10

1

0.1

DENSITY ( kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001
1k 10k 10M

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

06790-011

Figure 11. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maxi­mum allowable magnetic field of 0.2 kgauss induces a voltage of

0.25 V at the receiving coil. This voltage is approximately 50% of
the sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and is of the worst-case polarity), the received pulse is reduced
from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold
of the decoder.

Rev. B | Page 8 of 12

Data Sheet ADuM1510

The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM1510 transformers. Figure 12 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen in Figure 12, the ADuM1510 is extremely
immune and is affected only by extremely large currents
operated at high frequency and very close to the component.
For example, at a magnetic field frequency of 1 MHz, a 0.5 kA
current would need to be placed 5 mm away from the
ADuM1510 to affect the operation of the component.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALL OWABLE CURRENT ( kA)

0.01
1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 12. Maximum Allowable Current for

Various Current-to-ADuM1510 Spacings

06790-012

Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Care should be taken in the layout of such
traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM1510
isolator is a function of the supply voltage, the channel
data rate, and the channel output load.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

I

DDI

= I

× (2f − fr) + I

DDI (D)

f > 0.5fr

DDI (Q)

For each output channel, the supply current is given by

I

I

DDO

DDO

= I

= (I

f ≤ 0.5fr

DDO (Q)

DDO (D)

+ CLV

) × (2f − fr) + I

DDO

DDO (Q)

where:

I

, I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

I

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

is the output supply voltage (V).

V

DDO

f ≤ 0.5fr

f ≤ 0.5fr

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

f

is the input stage refresh rate (Mbps).

r

To calculate the total I

DD1

and I

supply current, the supply

DD2

currents for each input and output channel corresponding to
I

DD1

and I

are calculated and totaled. Figure 4 and Figure 5

DD2

provide per-channel supply currents as a function of the data
rate for an unloaded output condition. Figure 6 provides per­channel supply current as a function of the data rate for a 15 pF
output condition. Figure 7 and Figure 8 provide total I
I

supply current as a function of the data rate for ADuM1510

DD2

DD1

and

products.

POWER-UP/POWER-DOWN CONSIDERATIONS

Given that the ADuM1510 has separate supplies on each side of
the isolation barrier, the power-up and power-down charac­teristics relative to each supply voltage need to be considered
individually.

As shown in Table 8, when V
ADuM1510 outputs take on a default low logic condition. As
the V

supply is increased or decreased, the output of each

DD1

channel transitions from/to the default condition to/from the
state matching its respective signals (see Figure 13 and Figure 14).

OUTPUT
DATA

2V

(TYP)

Figure 13. V

Power-Up/Power-Down Characteristics, Input Data = High

DD1

V

OUTPUT DATA

Figure 14. V

When V

Power-Up/Power-Down Characteristics, Input Data = Low

DD1

crosses the threshold for activating the refresh circuit

DD1

(approximately 2 V), there can be a delay of up to 2 μs before the
output is updated to the correct state, depending on the timing
of the next refresh pulse. When V
below the 2 V threshold, there can be a delay of up to 5 μs before
the output takes on its default low state. This corresponds to the
duration that the watchdog timer circuit at the input is designed
to wait before triggering an output default state.

input power is off, the

DD1

V

DD1

DD1

is reduced from an on state

DD1

6790-013

06790-014

Rev. B | Page 9 of 12

ADuM1510 Data Sheet

V

V

V

V

When the V
ADuM1510 output transistors are biased (approximately 1 V),
the outputs take on a high impedance state.

When V
output takes on a state matching that of its respective input.
Between the values of 1 V and 2 V, the outputs are set low. This
behavior is shown in Figure 15 and Figure 16.

output supply is below the level at which the

DD2

is above a value of approximately 2 V, each channel

DD2

~2

~1

Figure 15. V

~2

OUTPUT HI GH

OUTPUT

HIGH-Z

OUTPUT

LOW

2

D

D

V

Power-Up/Power-Down Characteristics, Input Data = High

DD2

OUTPUT LOW

OUTPUT

HIGH-Z

OUTPUT

LOW

OUTPUT

LOW

LOW

HIGH-Z

V

DD

2

OUTPUT

HIGH-Z

OUTPUT

OUTPUT

06790-015

~1

Figure 16. V

2

D

D

V

Power-Up/Power-Down Characteristics, Input Data = Low

DD2

V

DD

2

06790-016

Rev. B | Page 10 of 12

Data Sheet ADuM1510

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

ORDERING GUIDE

Model1

ADuM1510BRWZ
ADuM1510BRWZ-RL

1

Z = RoHS Compliant Part.

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

0
0

.

7

.

2

(

5

0

(

5

0

.

0

2

9

5

)

.

0

0

9

8

)

1.27 (0.0500)

0.40 (0.0157)

45°

03-27-2007-B

0.30 (0.0118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 17. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

Number
of Inputs,
V

Side

DD1

Number
of Inputs,
V

Side

DD2

Maximum
Data Rate

Maximum
Propagation
Delay, 5 V

Maximum
Pulse Width
Distortion

Temperature
Range

Package Description

Package
Option

5 0 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16
5 0 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W,

RW-16

13” Tape and Reel

Rev. B | Page 11 of 12

ADuM1510 Data Sheet

NOTES

©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06790-0-3/12(B)

Rev. B | Page 12 of 12