ANALOG DEVICES ADUM 1410 ARWZ Datasheet

Quad-Channel Digital Isolators

ADuM1410/ADuM1411/ADuM1412

ENCODE DECODE

ENCODE

DECODE

ENCODE DECODE

V

DD1

GND

1

V

IA

V

IB

V

IC

V

ID

DISABLE

GND

1

V

DD2

GND

2

V

OA

V

OB

V

OC

V

OD

CTRL

2

GND

2

1 2 3

4

5

6 7 8

16 15 14

13

12

11 10

9

ADuM1410

06580-001

DECODE

ENCODE

ENCODE DECODE

ENCODE

DECODE

V

DD1

GND

1

V

IA

V

IB

V

IC

V

OD

CTRL

1

GND

1

V

DD2

GND

2

V

OA

V

OB

V

OC

V

ID

CTRL

2

GND

2

1 2 3

4

5

6 7 8

16 15 14

13

12

11 10

9

ADuM1411

06580-002

DECODE ENCODE

ENCODE DECODE

V

DD1

GND

1

V

IA

V

IB

V

OC

V

OD

CTRL

1

GND

1

V

DD2

GND

2

V

OA

V

OB

V

IC

V

ID

CTRL

2

GND

2

1 2 3

4

5

6 7 8

16 15 14

13

12

11 10

9

ADuM1412

06580-003

Data Sheet

FEATURES

Low power operation

5 V operation

1.3 mA per channel maximum at 0 Mbps to 2 Mbps

4.0 mA per channel maximum at 10 Mbps

3 V operation

0.8 mA per channel maximum at 0 Mbps to 2 Mbps

1.8 mA per channel maximum at 10 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C Up to 10 Mbps data rate (NRZ) Programmable default output state High common-mode transient immunity: >25 kV/µs 16-lead, RoHS compliant, SOIC wide body package

Safety and regulatory approvals

UL recognition: 3750 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 V

= 560 V peak

IORM

TÜV approval: IEC/EN 60950-1

FUNCTIONAL BLOCK DIAGRAMS

Figure 1. ADuM1410

Figure 2. ADuM1411

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation

GENERAL DESCRIPTION

The ADuM1410/ADuM1411/ADuM14121 are four-channel digital isolators based on Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The usual concerns that arise with optocouplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects, are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.

Rev. M Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the prop erty of their respective own ers.

devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM1410/ADuM1411/ADuM1412 isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide) up to 10 Mbps. All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have a default output control pin. This allows the user to define the logic state the outputs are to adopt in the absence of the input power. Unlike other optocoupler alternatives, the ADuM1410/ADuM1411/

ADuM1412 isolators have a patented refresh feature that ensures

dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

Technical Support www.analog.com

Figure 3. ADuM1412

ADuM1410/ADuM1411/ADuM1412 Data Sheet

REVISION HISTORY

8/15—Rev. L to Re v. M

Changes to Table 5 and Table 6 ..................................................... 10

7/15—Rev. K to Rev. L

Changes to Table 5 and Table 6 ..................................................... 10

4/15—Rev. J to Re v. K

Changed ADuM141x to ADuM1410/ADuM1411/

ADuM1412 ..................................................................... Throughout

Change to Features Section ............................................................. 1

Changes to Table 5 and Table 6 ..................................................... 10

4/14—Rev. I to Re v. J

Change to Table 5 ........................................................................... 10

3/12—Rev. H to Rev. I

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 19

11/10—Rev. G to Re v. H

Added TÜV Approval to Features Section .................................... 1

Added TÜV Column, Table 5 ....................................................... 10

6/07—Rev. F to Re v. G

Updated VDE Certification Throughout ...................................... 1

Absolute Maximum Ratings ......................................................... 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13

Typical Performance Characteristics ........................................... 17

Applications Information .............................................................. 19

PC Board Layout ........................................................................ 19

Propagation Delay-Related Parameters ................................... 19

DC Correctness and Magnetic Field Immunity ........................... 19

Power Consumption .................................................................. 20

Insulation Lifetime ..................................................................... 20

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

Changes to Features and Applications ............................................ 1

Changes to DC Specifications in Table 1 ........................................ 3

Changes to DC Specifications in Table 2 ........................................ 5

Changes to DC Specifications in Table 3 ........................................ 7

Changes to Regulatory Information Section .............................. 10

Adde d Tabl e 10 ............................................................................... 12

Added Insulation Lifetime Section .............................................. 21

2/07—Rev. E to Rev. F

Added ADuM1410ARWZ ................................................ Universal

Updated Pin Name CTRL to CTRL

Changes to Ordering Guide .......................................................... 21

10/06—Rev. D to Re v. E

Added ADuM1411 and ADuM1412 ............................... Universal

Deleted ADuM1310 ........................................................... Universal

Changes to Features .......................................................................... 1

Changes to Specifications Section ................................................... 3

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 20

3/06—Rev. C to Re v. D

Added Note 1 and Changes to Figure 2 .......................................... 1

Changes to Absolute Maximum Ratings ..................................... 11

11/05—Revision C: Initial Version

Throughout ........................ 1

2

Rev. M | Page 2 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

V

Supply Current

I

5.4

7.6

mA

5 MHz logic signal frequency

V

or V

Supply Current

I

, I

2.0

2.6

mA

DC to 1 MHz logic signal frequency

Logic Low Output Voltages

0.0

0.1 V IOx = 20 µA, VIx = V

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

Input Supply Current per Channel,

Output Supply Current per Channel,

ADuM1410, Total Supply Current,

ADuM1411, Total Supply Current,

ADuM1412, Total Supply Current,

All Models

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.50 0.73 mA

I

DDI (Q)

DD1

= V

= 5 V. All voltages are relative to their respective ground.

DD2

Quiescent

I

0.38 0.53 mA

DDO (Q)

Quiescent

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.4 3.2 mA DC to 1 MHz logic signal frequency

DD1 (Q)

1.2 1.6 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Four Channels

1

8.8 12 mA 5 MHz logic signal frequency

DD1 (10)

2.8 4.0 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal frequency

DD1 (Q)

1.8 2.4 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

DD1

V

Supply Current I

DD2

1

Four Channels

DD1 (10)

3.8 5.3 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

DD1

DD2

DD1 (Q)

(Q)

DD2

10 Mbps (BRWZ Version Only)

V

or V

DD1

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

DD1 (10)

, IIB, IIC,

I

IA

I

, I

ID

I

CTRL2

V

IH

V

IL

V

OAH

V

OCH

V

OAL

V

OCL

CTRL1

, I

, V , V

, I

4.6 6.5 mA 5 MHz logic signal frequency

DD2 (10)

−10 +0.01 +10 µA

,

DISABLE

2.0 V

0.8 V (V

or V

OBH

ODH

OBL

ODL

,

DD1

(V

DD1

,

0.04 0.1 V IOx = 400 µA, VIx = V

) − 0.1 5.0 V IOx = −20 µA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V

0 V ≤ V 0 V ≤ V 0 V ≤ V

, VIB, VIC, VID ≤ V

IA

, V

CTRL1

CTRL2

≤ V

DISABLE

DD1

≤ V

IxH

IxL

or V

DD2

, ,

DD1

IxH

IxL

Rev. M | Page 3 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet

All Models

Refresh Rate

fr 1.2 Mbps

Output Dynamic Supply Current

I

0.04

mA/

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

SWITCHING SPECIFICATIONS

ADuM1410ARWZ/ADuM1411ARWZ/

ADuM1412ARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM1410BRWZ/ADuM1411BRWZ/

ADuM1412BRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

, t

20 65 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

20 30 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 5 ns CL = 15 pF, CMOS signal levels

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

| 25 35 kV/µs

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

Input Enable Time8 t Input Disable Time8 t Input Dynamic Supply Current

per Channel

9

per Channel9

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

DD2

|CM

H

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

ENABLE

DISABLE

I

0.12

DDI (D)

2.0 µs VIA, VIB, VIC, VID = 0 V or V

5.0 µs VIA, VIB, VIC, VID = 0 V or V mA/

Mbps

DDO (D)

Mbps

propagation delay is

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. |CML| is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

DD1

is set high

Rev. M | Page 4 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

V

Supply Current

I

0.8

1.0

mA

V

Supply Current

I

3.1

4.5

mA

5 MHz logic signal frequency

0.04

0.1 V IOx = 400 µA, VIx = V

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V unless otherwise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

Input Supply Current per Channel,

Output Supply Current per Channel,

ADuM1410, Total Supply Current,

ADuM1411, Total Supply Current,

ADuM1412, Total Supply Current,

All Models

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.25 0.38 mA

I

DDI (Q)

DD1

= V

= 3.0 V. All voltages are relative to their respective ground.

DD2

Quiescent

I

0.19 0.33 mA

DDO (Q)

Quiescent

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

DD2

1.2 1.6 mA

DD1 (Q)

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

1

Four Channels

4.5 6.5 mA 5 MHz logic signal frequency

DD1 (10)

1.4 1.8 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.9 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.9 1.7 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

DD1

V

Supply Current I

DD2

Four Channels

1

DD1 (10)

2.1 3.0 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

1.0 1.8 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

or V

DD1

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

Logic Low Output Voltages

, I

DD1 (10)

, IIB, IIC, IID,

I

IA

I

CTRL1,ICTRL2

V

IH

V

IL

, V

V

OAH

, V

V

OCH

, V

V

OAL

OBL

, V

V

OCL

ODL

2.6 3.8 mA 5 MHz logic signal frequency

DD2 (10)

−10 +0.01 +10 µA

, I

DISABLE

1.6 V

0.4 V (V

or V

OBH

ODH

,

DD1

(V

DD1

0.0 0.1 V I

) − 0.1 3.0 V IOx = −20 µA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V

DC to 1 MHz logic signal frequency

, VIB, VIC, VID ≤ V

0 V ≤ V

IA

CTRL1

DISABLE

, V

0 V ≤ V 0 V ≤ V

= 20 µA, VIx = V

Ox

CTRL2

≤ V

DD1

≤ V

IxH

IxL

DD1

IxH

IxL

or V

DD2

, ,

Rev. M | Page 5 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet

All Models

Refresh Rate

fr 1.1 Mbps

Output Dynamic Supply Current

I

0.02

mA/

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

SWITCHING SPECIFICATIONS

ADuM1410ARWZ/ADuM1411ARWZ/

ADuM1412ARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM1410BRWZ/ADuM1411BRWZ/

ADuM1412BRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

, t

20 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

20 40 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 5 ns CL = 15 pF, CMOS signal levels

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

| 25 35 kV/µs

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

Input Enable Time8 t Input Disable Time8 t Input Dynamic Supply Current

per Channel

9

per Channel9

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

DD2

DISABLE

|CM

H

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

ENABLE

DISABLE

I

0.07

DDI (D)

2.0 µs VIA, VIB, VIC, VID = 0 V or V

5.0 µs VIA, VIB, VIC, VID = 0 V or V mA/

DD1

Mbps

DDO (D)

Mbps

propagation delay is

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. |CML| is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

is set high

DISABLE

Rev. M | Page 6 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

3 V/5 V Operation

2.6

3.0

mA

5 MHz logic signal frequency

3 V/5 V Operation

V

Supply Current

I

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

5 V/3 V operation: 4.5 V ≤ V minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.50 0.73 mA 3 V/5 V Operation 0.25 0.38 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.19 0.33 mA 3 V/5 V Operation 0.38 0.53 mA

ADuM1410, Total Supply Current,

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation

3 V/5 V Operation

V

Supply Current I

DD2

5 V/3 V Operation

3 V/5 V Operation

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 8.6 11 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.4 6.5 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 1.4 1.8 mA 5 MHz logic signal frequency

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V; or V

DD2

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

= 5 V, V

DD1

DD2

= 3.0 V. All voltages are relative to their respective ground.

DD2

DDI (Q)

DDO (Q)

DD1

DD1 (Q)

2.4 3.2 mA

1.2 1.6 mA

DD2 (Q)

0.8 1.0 mA

1.2 1.6 mA

DD1 (10)

DD2 (10)

≤ 3.6 V, 4.5 V ≤ V

DC to 1 MHz logic signal frequency

≤ 5.5 V; all

DD2

ADuM1411, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation

3 V/5 V Operation

V

Supply Current I

DD2

5 V/3 V Operation

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 5.4 7.6 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.1 4.5 mA 5 MHz logic signal frequency

DD2

5 V/3 V Operation 2.1 3.0 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.8 5.3 mA 5 MHz logic signal frequency

DD1 (Q)

2.2 2.8 mA

1.0 1.9 mA

DD2 (Q)

0.9 1.7 mA

1.7 2.4 mA

DD1 (10)

DD2 (10)

Rev. M | Page 7 of 22

DC to 1 MHz logic signal frequency

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

ADuM1412, Total Supply Current, Four Channels1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation

3 V/5 V Operation

V

Supply Current I

DD2

5 V/3 V Operation

3 V/5 V Operation

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 4.6 6.5 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.6 3.8 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 2.6 3.8 mA 5 MHz logic signal frequency 3 V/5 V Operation 4.6 6.5 mA 5 MHz logic signal frequency

All Models

Input Currents

Logic High Input Threshold

5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input Threshold

5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V

Logic High Output Voltages

Logic Low Output Voltages

SWITCHING SPECIFICATIONS

ADuM1410ARWZ/ADuM1411ARWZ/

ADuM1412ARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

DD1 (Q)

DC to 1 MHz logic signal

2.0 2.6 mA

frequency DC to 1 MHz logic signal

1.0 1.8 mA

DD2 (Q)

frequency

DC to 1 MHz logic signal

1.0 1.8 mA

frequency DC to 1 MHz logic signal

2.0 2.6 mA

DD1 (10)

DD2 (10)

, IIB, IIC,

I

IA

, I

, V , V

OBH

ODH

,

CTRL2

−10 +0.01 +10 μA

or

(V

DD1

V

) − 0.1

DD2

,

(V

or

DD1

) − 0.4

V

DD2

or

(V

DD1

V

DD2)

(V

DD1

V

DD2

V I

or

) − 0.2 V IOx = −4 mA, VIx = V

I

ID,ICTRL1

I

DISABLE

V

IH

V

IL

V

OAH

V

OCH

0.0 0.1 V I

, V

V

OAL

OBL

, V

V

OCL

ODL

, t

PHL

PLH

0.04 0.1 V IOx = 400 μA, VIx = V

,

0.2 0.4 V IOx = 4 mA, VIx = V

25 70 100 ns CL = 15 pF, CMOS signal levels

frequency

, VIB, VIC, VID ≤ V

0 V ≤ V

IA

0 V ≤ V 0 V ≤ V

Ox

, V

CTRL1

≤ V

DISABLE

= −20 μA, VIx = V

= 20 μA, VIx = V

CTRL2

≤ V

DD1

IxL

or V

DD1

or V

DD1

IxH

IxL

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

DD2

,

Rev. M | Page 8 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

5 V/3 V Operation

1.2 Mbps

5 V Operation

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

ADuM1410BRWZ/ADuM1411BRWZ/

ADuM1412BRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

t

All Models

Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels

5 V/3 V Operation 2.5 ns

3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at

Logic High Output Common-Mode Transient Immunity at

Logic Low Output

7

Refresh Rate fr

, t

25 35 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 5 ns CL = 15 pF, CMOS signal levels

30 ns CL = 15 pF, CMOS signal levels

PSK

t

5 ns CL = 15 pF, CMOS signal levels

PSKCD

6 ns CL = 15 pF, CMOS signal levels

PSKOD

|CM

| 25 35 kV/µs

H

VIx = V transient magnitude = 800 V

DD1

or V

DD2

, VCM = 1000 V,

VIx = 0 V, VCM = 1000 V, transient

|CML| 25 35 kV/µs

magnitude = 800 V

3 V/5 V Operation 1.1 Mbps

Input Enable Time8 t Input Disable Time8 t

Input Dynamic Supply Current

per Channel

9

ENABLE

DISABLE

I

DDI (D)

2.0 µs VIA, VIB, VIC, VID = 0 V or V

5.0 µs VIA, VIB, VIC, VID = 0 V or V

DD1

mA/

0.12

3 V Operation

0.07

Output Dynamic Supply Current per

Channel

9

I

DDO (D)

5 V Operation

0.04

3 V Operation

0.02

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

DD2

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. |CML| is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

Mbps mA/

Mbps

mA/ Mbps

propagation delay is

PLH

is set high

DISABLE

Rev. M | Page 9 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Resistance (Input to Output)1 R Capacitance (Input to Output)

1

Input Capacitance2 C

10

I-O

C

2.2 pF f = 1 MHz

I-O

4.0 pF

I

IC Junction to Case Thermal Resistance

Side 1 θ Side 2 θ

1

The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

33 °C/W Thermocouple located at center of package underside

JCI

28 °C/W

JCO

REGULATORY INFORMATION

The ADuM1410/ADuM1411/ADuM1412 have been approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 5.

UL CSA CQC VDE TÜV

Recognized Under

1577 Component Recognition Program

1

Single Protection,

3750 V rms Isolation Voltage

Reinforced insulation

File E214100 File 205078 File CQC14001108689 File 2471900-4880-0001 Certificate B 10 03 56232 006

1

In accordance with UL 1577, each ADuM1410/ADuM1411/ADuM1412 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage

detection limit = 5 μA).

2

In accordance with DIN V VDE V 0884-10, each ADuM1410/ADuM1411/ADuM1412 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second

(partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10

Approved under CSA Component Acceptance Notice 5A

Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage

per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage

Approved under CQC11-471543-2012

Basic insulation per GB4943.1-2011, 600 V rms (848 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 m

Reinforced insulation per GB4943.1-2011, 380 V rms (537 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 m

12

Ω

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122

Reinforced insulation, 560 V peak

Approved according to IEC 60950-1:2005 and EN 60950-1:2006

3000 V rms reinforced isolation at a 400 V rms working voltage, 3000 V rms basic isolation at a 600 V rms working voltage

approval.

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 3750 V rms 1-minute duration Minimum External Tracking (Creepage) L(I02) 7.71 mm min

Minimum External Air Gap (Clearance) L(I01) 7.7 mm min

2

Minimum Clearance in the Plane of the

L(PCB) 8.1

mm min

Printed Circuit Board (PCB Clearance) Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation Tracking Resistance (Comparative Tracking

CTI >400 V DIN IEC 112/VDE 0303 Part 1

Index) Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)

1

Clearance and creepage measured by VDE is >8 mm for SOIC wide packages.

2

This value is for information only, to aid in PCB design. Package clearance is identical to creepage as specified in L(I02).

Rev. M | Page 10 of 22

Measured from input terminals to output terminals, shortest distance path along package body

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane

Data Sheet ADuM1410/ADuM1411/ADuM1412

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.

Table 7.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A V

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR

IORM

After Environmental Tests Subgroup 1 896 V peak

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak

After Input and/or Safety Test Subgroup 2

V

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak Safety Limiting Values

Maximum value allowed in the event of a failure;

see Figure 4 Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

350

300

250

SIDE #2

200

150

SIDE #1

100

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +105 °C Supply Voltages1 V Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground. See the DC Correctness

and Magnetic Field Immunity section for information on immunity to external magnetic fields.

560 V peak

IORM

1050 V peak

V

PR

, V

2.7 5.5 V

DD1

DD2

SAFETY- LIMIT ING CURRENT (mA)

50

0

Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Temperature per DIN V VDE V 0884-10

50 100 150 200

CASE TEMPERATURE ( °C)

06580-007

Rev. M | Page 11 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Output Voltages (VOA, VOB, VOC, VOD)

1, 2

−0.5 V to V

+ 0.5 V

DC Voltage

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 9.

Parameter Rating

Storage Temperature ( TST) Range −65°C to +150°C Ambient Operating Temperature

) Range

(T

A

Supply Voltages (V Input Voltages (VIA, VIB, VIC, VID, V

, V

V

CTRL2

DISABLE

, V

)1 −0.5 V to +7.0 V

DD1

DD2

1, 2

)

−40°C to +105°C

−0.5 V to V

,

CTRL1

+ 0.5 V

DDI

DDO

Average Output Current per Pin3

Side 1 (IO1) −18 mA to +18 mA Side 2 (IO2) −22 mA to +22 mA

Common-Mode Transients4 −100 kV/μs to +100 kV/μs

1

All voltages are relative to their respective ground.

2

V

and V

DDI

given channel, respectively. See the PC Board Layout section.

3

See Figure 4 for maximum rated current values for various temperatures.

4

Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

Table 10. Maximum Continuous Working Voltage

1

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Rev. M | Page 12 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

V

DD1

1

GND1*

2

V

IA

3

V

IB

4

V

DD2

16

GND

2

*

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

ID

6

V

OD

11

DISABLE

7

CTRL

2

10

GND

1

*

8

GND

2

*

9

ADuM1410

TOP VIEW

(Not to S cale)

*PIN 2 AND PIN 8 ARE INT E RNALLY CONNECTED. CONNECT ING BOTH

TO GND

1

IS RECOMM ENDE D. PIN 9 AND PIN 15 ARE INTERNALLY

CONNECTED. CONNECTING BOTH TO G ND2 IS RECOMMENDED.

06580-004

7

DISABLE

Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state

10

CTRL2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. ADuM1410 Pin Configuration

Table 11. ADuM1410 Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 GND

3 V

DD1

1

IA

4 VIB Logic Input B. 5 VIC Logic Input C. 6 V

ID

Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended. Logic Input A.

Logic Input D.

determined by CTRL2.

8 GND1

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND recommended.

9 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND recommended.

Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, VOC, and

outputs are high when CTRL2 is high or disconnected and V

V

11 V

OD

CTRL

is low and V

2

Logic Output D.

is off. When V

DD1

power is on, this pin has no effect.

DD1

12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND recommended.

16 V

Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

DD2

Rev. M | Page 13 of 22

is

1

is

2

is off. VOA, VOB, VOC, and VOD outputs are low when

is

2

ADuM1410/ADuM1411/ADuM1412 Data Sheet

V

DD1

1

GND

1

*

2

V

IA

3

V

IB

4

V

DD2

16

GND

2

*

15

V

OA

14

V

OB

13

V

IC

5

V

OC

12

V

OD

6

V

ID

11

CTRL

1

7

CTRL

2

10

GND

1

*

8

GND

2

*

9

ADuM1411

TOP VIEW

(Not to S cale)

*

PIN 2 AND PIN 8 ARE I NTERNALLY CONNECTED. CO NNE CTING BOTH TO GND

1

IS RECOMM ENDE D. PIN 9 AND PIN 15 ARE INTERNALLY

CONNECTED. CONNECTING BOTH TO G ND

2

IS RECOMMENDED.

06580-005

4

VIB

Logic Input B.

8

GND1

Table 12. ADuM1411 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND

1

Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended.

3 V

IA

Logic Input A.

5 VIC Logic Input C. 6 V

OD

7 CTRL1

Logic Output D. Default Output Control. Controls the logic state the outputs assume when the input power is off. V

when CTRL

is high or disconnected and V

1

power is on, this pin has no effect. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended.

9 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND recommended.

10 CTRL2

Default Output Control. Controls the logic state the outputs assume when the input power is off. V outputs are high when CTRL

11 V

low and V

ID

Logic Input D.

is off. When V

DD1

12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND recommended.

16 V

Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

DD2

Figure 6. ADuM1411 Pin Configuration

is off. VOD output is low when CTRL1 is low and V

DD2

is high or disconnected and V

2

power is on, this pin has no effect.

DD1

output is high

OD

is off. When V

DD2

, VOB, and VOC

is off. VOA, VOB, and VOC outputs are low when CTRL2 is

DD1

OA

DD2

is

2

is

2

Rev. M | Page 14 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

V

DD1

1

GND1*

2

V

IA

3

V

IB

4

V

DD2

16

GND2*

15

V

OA

14

V

OB

13

V

OC

5

V

IC

12

V

OD

6

V

ID

11

CTRL

1

7

CTRL

2

10

GND

1

*

8

GND

2

*

9

ADuM1412

TOP VIEW

(Not to S cale)

*PIN 2 AND PIN 8 ARE INT E RNALLY CONNECT E D. CONNECTI NG BOTH

TO GND1 IS RECOMME NDE D. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO G ND

2

IS RECOMMENDED.

06580-006

8

GND1

Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

Table 13. ADuM1412 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND

1

Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is

recommended.

3 V

IA

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 V

OD

7 CTRL1

Logic Output D.

Default Output Control. Controls the logic state the outputs assume when the input power is off. V

outputs are high when CTRL

and V

is off. When V

DD2

power is on, this pin has no effect.

DD2

recommended. 9 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND

recommended. 10 CTRL2

Default Output Control. Controls the logic state the outputs assume when the input power is off. V

outputs are high when CTRL

11 V

and V

ID

Logic Input D.

is off. When V

DD1

power is on, this pin has no effect.

DD1

12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2

Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND

recommended. 16 V

Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

DD2

Figure 7. ADuM1412 Pin Configuration

is high or disconnected and V

1

is high or disconnected and V

2

and VOD

is off. VOC and VOD outputs are low when CTRL1 is low

DD2

is off. VOA and VOB outputs are low when CTRL2 is low

DD1

OC

and VOB

OA

is

2

is

2

Rev. M | Page 15 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet

L

X

Powered

L

Normal operation, data is low.

X L X

Unpowered

Powered

L

Table 14. Truth Table (Positive Logic)

VIx Input1

H X

X

X L H X Powered L

X

X X X Powered Unpowered Z

1

VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).

2

CTRLX refers to the default output control signal on the input side of a given channel (A, B, C, or D).

3

Available only on the ADuM1410.

4

V

5

V

CTRLX Input2

V

DISABLE

State3

L or

V

DDI

State4

V

DDO

State5

VOx Output1

Powered Powered H Normal operation, data is high.

NC L or

NC

H or

H X Powered H

NC

H or

X Unpowered Powered H

NC

refers to the power supply on the input side of a given channel (A, B, C, or D).

DDI

refers to the power supply on the output side of a given channel (A, B, C, or D).

DDO

Description

Inputs disabled. Outputs are in the default state as determined by CTRL

.

X

Inputs disabled. Outputs are in the default state as determined by CTRLX.

Input unpowered. Outputs are in the default state as determined by CTRL Outputs return to input state within 1 µs of V

.

X

power restoration.

DDI

See the pin function descriptions (Table 11, Table 12, and Table 13) for more details.

Input unpowered. Outputs are in the default state as determined by CTRL Outputs return to input state within 1 µs of V

.

X

power restoration.

DDI

See the pin function descriptions (Table 11, Table 12, and Table 13) for more details.

Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 µs of V

power restoration.

DDO

See the pin function descriptions (Table 11, Table 12, and Table 13) for more details.

Rev. M | Page 16 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

DATA RATE (Mbps)

CURRENT/CHANNEL ( mA)

0

1.0

0.5

1.5

2.0

2 6 84

10

5V

3V

06580-008

DATA RATE (Mbps)

CURRENT/CHANNEL ( mA)

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

2 6

84 10

5V

3V

06580-009

DATA RATE (Mbps)

CURRENT/CHANNEL ( mA)

0

1.4

1.2

1.0

0.8

0.6

0.4

0.2

2 6 84

10

5V

3V

06580-010

DATA RATE (Mbps)

CURRENT (mA)

0

10

8

6

4

2

6 84 10

5V

3V

06580-011

DATA RATE (Mbps)

CURRENT (mA)

0

10

8

6

4

2

2 6 8

4 10

5V

3V

06580-012

DATA RATE (Mbps)

CURRENT (mA)

0

10

8

6

4

2

2 6 84 10

5V

3V

06580-013

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. Typical Supply Current per Input Channel vs. Data Rate

for 5 V and 3 V Operation

Figure 9. Typical Supply Current per Output Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

Figure 11. Typical ADuM1410 V

for 5 V and 3 V Operation

Figure 12. Typical ADuM1410 V

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD1

Supply Current vs. Data Rate

DD2

Figure 10. Typical Supply Current per Output Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

Rev. M | Page 17 of 22

Figure 13. Typical ADuM1411 V

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD1

ADuM1410/ADuM1411/ADuM1412 Data Sheet

DATA RATE (Mbps)

CURRENT (mA)

0

10

8

6

4

2

2 6

8

4

10

5V

3V

06580-014

DATA RATE (Mbps)

CURRENT (mA)

0

10

8

6

4

2

2 6 8

4 10

5V

3V

06580-015

Figure 14. Typical ADuM1411 V

Supply Current vs. Data Rate

DD2

for 5 V and 3 V Operation

Figure 15. Typical ADuM1412 V

or V

DD1

Supply Current vs. Data Rate

DD2

for 5 V and 3 V Operation

Rev. M | Page 18 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

V

DD1

GND

1

V

IA

V

IB

V

IC

V

ID

DISABLE

GND

1

V

DD2

GND

2

V

OA

V

OB

V

OC

V

OD

CTRL

2

GND

2

06580-016

ADuM1410

INPUT (VIx)

OUTPUT (VOx)

t

PLH

t

PHL

50%

06580-017

MAGNETI C FIELD FRE QUENCY (Hz)

100

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY (kgauss)

0.001 1M

10

0.01

1k 10k 10M

0.1

1

100M100k

06580-018

APPLICATIONS INFORMATION

PC BOARD LAYOUT

The ADuM1410/ADuM1411/ADuM1412 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V and between Pin 15 and Pin 16 for V

. The capacitor value

DD2

DD1

should be between 0.01 µF and 0.1 µF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless both ground pins on each package are connected together close to the package.

Figure 16. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, users should design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may differ from the propagation delay time of a low-to-high transition.

,

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 µs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Tabl e 14) by the watchdog timer circuit.

The magnetic field immunity of the ADuM1410/ADuM1411/

ADuM1412 is determined by the changing magnetic field, which

induces a voltage in the transformer’s receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM1410/ADuM1411/ADuM1412 is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt) ∑ π r

where: β is magnetic flux density (gauss).

is the radius of the nth turn in the receiving coil (cm).

r

n

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM1410/

ADuM1411/ADuM1412 and an imposed requirement that the

induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 18.

2

; n = 1, 2, … , N

n

Figure 17. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single

ADuM1410/ADuM1411/ADuM1412 component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM1410/

ADuM1411/ADuM1412 components operating under the same

conditions.

Rev. M | Page 19 of 22

Figure 18. Maximum Allowable External Magnetic Flux Density

ADuM1410/ADuM1411/ADuM1412 Data Sheet

MAGNETI C FIELD FRE QUENCY (Hz)

MAXIMUM AL LOWABLE CURRE NT (kA)

1000

100

10

1

0.1

0.01 1k 10k 100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

06580-019

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurred during a transmitted pulse (and had the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the

ADuM1410/ADuM1411/ADuM1412 transformers. Figure 19

shows these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM1410/

ADuM1411/ADuM1412 is extremely immune and can be affected

only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted previously, a

0.5 kA current would have to be placed 5 mm away from the

ADuM1410/ADuM1411/ADuM1412 to affect the operation of

the component.

POWER CONSUMPTION

The supply current at a given channel of the ADuM1410/

ADuM1411/ADuM1412 isolators is a function of the supply

voltage, the data rate of the channel, and the output load of the channel.

For each input channel, the supply current is given by

= I

I

DDI

DDI (Q)

= I

I

DDI

× (2f − fr) + I

DDI (D)

DDI (Q)

For each output channel, the supply current is given by

I

DDO

= I

= (I

f ≤ 0.5 fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

where:

I

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

V

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz); it is half the input

data rate, expressed in units of Mbps.

f

is the input stage refresh rate (Mbps).

r

I

, I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

f ≤ 0.5 fr

f > 0.5 fr

DDO (Q)

f > 0.5 fr

Figure 19. Maximum Allowable Current for Various

Current-to-ADuM1410/ADuM1411/ADuM1412 Spacings

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

To calculate the total V

DD1

and V

supply current, the supply

DD2

currents for each input and output channel corresponding to V

DD1

and V

are calculated and totaled. Figure 8 and Figure 9

DD2

show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 shows the per-channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 show the total V

supply current as a function of data rate for ADuM1410/

V

DD2

DD1

and

ADuM1411/ADuM1412 channel configurations.

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM1410/

ADuM1411/ADuM1412.

Rev. M | Page 20 of 22

Data Sheet ADuM1410/ADuM1411/ADuM1412

0V

RATED PEAK VOLTAGE

06580-020

0V

RATED PEAK VOLTAGE

06580-021

0V

RATED PEAK VOLTAGE

06580-022

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Tabl e 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM1410/ADuM1411/

ADuM1412 depends on the voltage waveform type imposed

across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22 illustrate these different isolation voltage waveforms.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Tabl e 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any cross-insulation voltage waveform that does not conform to Figure 21 or Figure 22 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Tabl e 10.

Note that the voltage presented in Figure 21 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

Figure 20. Bipolar AC Waveform

Figure 21. Unipolar AC Waveform

Figure 22. DC Waveform

Rev. M | Page 21 of 22

ADuM1410/ADuM1411/ADuM1412 Data Sheet

CONTROLLING DIMENSION

S AR

E IN

MILLIMETERS; INCH DIMENSIONS

(IN PAREN

THE

SES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS

FO

R

REFER

EN

CE ONLYAND ARE NOT APPROPRIATE FOR USE IN DE

SI

GN

.

C

OMPLIANT TO JEDEC STANDARDS MS-013-AA

1

0

.50 (

0

.4

1

34

)

10.10 (0.3976)

0

.3

0 (

0

.0

11

8

)

0

.1

0 (

0

.0

03

9

)

2.

6

5 (

0.

1

04

3)

2.

3

5 (

0.

0

925)

10.65 (0.4193) 1

0

.0

0 (

0

.3

9

37

)

7

.

60

(0

.

2992)

7

.

40

(0

.

29

13

)

0

.

7

5

(

0

.

0

2

9

5

)

0

.

2

5

(

0

.

0

9

8

)

4

5

°

1

.2

7 (

0

.0

50

0

)

0

.

40

(0

.

01

57

)

C

O

PL

A

NA

RI

T

Y

0

.1

0

0.

33 (0

.0

1

30

)

0.20 (0.0079)

0

.5

1 (

0

.0

20

1

)

0

.

31

(0

.

01

22

)

S

EA

TI

N

G

P

LA

NE

8° 0

°

1

6

9

8

1

1.

2

7 (

0

.0500)

BS

C

03-

27-2

007

-B

ADuM1410ARWZ

4 0 1 Mbps

100 ns

40 ns

−40°C to +105°C

16-Lead SOIC_W

RW-16

OUTLINE DIMENSIONS

Figure 23. 16-Lead Standard Small Outline Package [SOIC_W]

Dimensions shown in millimeters and (inches)

Wide Body (RW-16)

ORDERING GUIDE

Number of Inputs,

Model1

V

DD1

ADuM1410ARWZ-RL 4 0 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1410BRWZ 4 0 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1410BRWZ-RL 4 0 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1411ARWZ 3 1 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1411ARWZ-RL 3 1 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1411BRWZ 3 1 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1411BRWZ-RL 3 1 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1412ARWZ 2 2 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1412ARWZ-RL 2 2 1 Mbps 100 ns 40 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16 ADuM1412BRWZ 2 2 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W RW-16 ADuM1412BRWZ-RL 2 2 10 Mbps 50 ns 5 ns −40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16

1

Z = RoHS Compliant Part.

Side

Number of Inputs, V

DD2

Side

Maximum Data Rate

Maximum Propagation Delay, 5 V

Maximum Pulse Width Distortion

Temperature Range

Package Description

Package Option

registered trademarks are the property of their respective owners. D06580-0-8/15(M)

Rev. M | Page 22 of 22

ANALOG DEVICES ADUM 1410 ARWZ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

OUTLINE DIMENSIONS

ORDERING GUIDE