ANALOG DEVICES ADUM1410 Service Manual

Quad-Channel Digital Isolators

Data Sheet

FEATURES

Low power operation

5 V operation

1.3 mA per channel maximum @ 0 Mbps to 2 Mbps

4.0 mA per channel maximum @ 10 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

1.8 mA per channel maximum @ 10 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
Up to 10 Mbps data rate (NRZ)
Programmable default output state
High common-mode transient immunity: >25 kV/μs
16-lead, RoHS-compliant, SOIC wide body package

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
V

= 560 V peak

IORM

TÜV approval: IEC/EN 60950-1

APPLICATIONS

General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation

GENERAL DESCRIPTION

The ADuM141x1 are four-channel digital isolators based on

Analog Devices, Inc. iCoupler® technology. Combining high

s

peed CMOS and monolithic air core transformer technologies,
these isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto­couplers. The usual concerns that arise with optocouplers, such
as uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects, are eliminated with the simple
iCoupler digital interfaces and stable performance characteristics.
The need for external drivers and other discrete components is
eliminated with these iCoupler products. Furthermore, iCoupler

1

Protected by U.S. Patents 5,952,849 6,873,065 and 7,075,329.

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

ADuM1410/ADuM1411/ADuM1412

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

ADuM1410

2

GND

1

3

V

V

V
V

DISABLE

GND

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

ENCODE DECODE

ID

7
8

1

Figure 1. ADuM1410

1

V

DD1

ADuM1411

2

GND

1

3

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

DECODE ENCODE

7

1

8

1

V

CTRL

GND

V

V

V

OD

Figure 2. ADuM1411

1

V

DD1

ADuM1412

2

GND

1

3

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

6

DECODE ENCODE

7

1

8

1

V
V

CTRL

GND

V

V

OC

OD

Figure 3. ADuM1412

devices consume one-tenth to one-sixth the power of optocou­plers at comparable signal data rates.

The ADuM141x isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide) up to 10 Mbps. All models operate
with the supply voltage on either side ranging from 2.7 V to 5.5 V,
providing compatibility with lower voltage systems as well as
enabling voltage translation functionality across the isolation
barrier. All products also have a default output control pin. This
allows the user to define the logic state the outputs are to adopt
in the absence of the input power. Unlike other optocoupler
alternatives, the ADuM141x isolators have a patented refresh
feature that ensures dc correctness in the absence of input logic
transitions and during power-up/power-down conditions.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2012 Analog Devices, Inc. All rights reserved.

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

CTRL

2

9

GND

2

06580-001

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

CTRL

2

9

GND

2

06580-002

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

CTRL

2

9

GND

2

06580-003

ADuM1410/ADuM1411/ADuM1412 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Recommended Operating Conditions.................................... 11

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 5

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation....................................................................................... 7

Package Characteristics .............................................................10

Regulatory Information............................................................. 10

Insulation and Safety-Related Specifications.......................... 10

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

Insulation Characteristics.......................................................... 11

REVISION HISTORY

3/12—Rev. H to Rev. I

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section................................................................. 1

Change to PC Board Layout Section............................................ 19

11/10—Rev. G to Rev. H

Added TÜV Approval to Features Section.................................... 1

Added TÜV Column, Table 5....................................................... 10

6/07—Rev. F to Rev. G

Updated VDE Certification Throughout...................................... 1

Changes to Features and Applications........................................... 1

Changes to DC Specifications in Table 1....................................... 3

Changes to DC Specifications in Table 2....................................... 5

Changes to DC Specifications in Table 3....................................... 7

Changes to Regulatory Information Section .............................. 10

Added Table 10 ...............................................................................12

Added Insulation Lifetime Section .............................................. 21

Absolute Maximum Ratings ......................................................... 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions......................... 13

Typical Performance Characteristics........................................... 17

Applications Information.............................................................. 19

PC Board Layout ........................................................................ 19

Propagation Delay-Related Parameters................................... 19

DC Correctness and Magnetic Field Immunity........................... 19



Power Consumption.................................................................. 20

Insulation Lifetime..................................................................... 20

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22



2/07—Rev. E to Rev. F

Added ADuM1410ARWZ ...............................................Universal

Updated Pin Name CTRL to CTRL

Changes to Ordering Guide.......................................................... 21

10/06—Rev. D to Rev. E

Added ADuM1411 and ADuM1412 ...............................Universal

Deleted ADuM1310 ........................................................... Universal

Changes to Features ..........................................................................1

Changes to Specifications Section...................................................3

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide.......................................................... 20

3/06—Rev. C to Rev. D

Added Note 1 and Changes to Figure 2..........................................1

Changes to Absolute Maximum Ratings..................................... 11

11/05—Revision C: Initial Version

Throughout ........................1

2

Rev. I | Page 2 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V
unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel,

Output Supply Current per Channel,

ADuM1410, Total Supply Current,

ADuM1411, Total Supply Current,

ADuM1412, Total Supply Current,

All Models

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.50 0.73 mA

I

DDI (Q)

DD1

= V

= 5 V. All voltages are relative to their respective ground.

DD2

Quiescent

I

0.38 0.53 mA

DDO (Q)

Quiescent

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.4 3.2 mA DC to 1 MHz logic signal frequency

DD1 (Q)

1.2 1.6 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Four Channels

1

8.8 12 mA 5 MHz logic signal frequency

DD1 (10)

2.8 4.0 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal frequency

DD1 (Q)

1.8 2.4 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

1

Four Channels

5.4 7.6 mA 5 MHz logic signal frequency

DD1 (10)

3.8 5.3 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

2.0 2.6 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

or V

DD1

Supply Current I

DD2

Input Currents

Logic High Input Threshold
Logic Low Input Threshold

Logic Low Output Voltages

DD1 (10)

, IIB, IIC,

I

IA

, I

I

ID

I

CTRL2

V

IH

V

IL

V

OAH

V

OCH

V

OAL

V

OCL

CTRL1

, I

, V
, V

, V
, V

, I

4.6 6.5 mA 5 MHz logic signal frequency

DD2 (10)

−10 +0.01 +10 µA

,

DISABLE

2.0 V

0.8 V
(V

or V

OBH

ODH

OBL

ODL

,

,

DD1

(V

DD1

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

) − 0.1 5.0 V IOx = −20 µA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V

0 V ≤ V
0 V ≤ V
0 V ≤ V

, VIB, VIC, VID ≤ V

IA

, V

CTRL1

CTRL2

≤ V

DISABLE

DD1

≤ V

IxH

IxL

IxL

or V

or V

DD2

DD2

,
,

DD1

DD1

Logic High Output Voltages

IxH

IxL

Rev. I | Page 3 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM141xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t
Channel-to-Channel Matching6 t

ADuM141xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t

PLH

− t

|4 PWD 5 ns CL = 15 pF, CMOS signal levels

PHL

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,

Codirectional Channels

6

Channel-to-Channel Matching,

Opposing-Directional Channels

All Models

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

7

Refresh Rate fr 1.2 Mbps
Input Enable Time8 t
Input Disable Time8 t
Input Dynamic Supply Current

per Channel

Output Dynamic Supply Current

per Channel

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section.
See Figure through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through
Figure 15

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.

8

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

is the magnitude of the worst-case difference in t

DD1

9

9

and V

supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

DD2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

, t

20 65 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

20 30 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

6

| 25 35 kV/µs

|CM

H

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

ENABLE

DISABLE

0.12

I

DDI (D)

2.0 µs VIA, VIB, VIC, VID = 0 V or V

5.0 µs VIA, VIB, VIC, VID = 0 V or V
mA/

Mbps

0.04

I

DDO (D)

mA/
Mbps

ower Consumption

propagation delay is

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. |CML| is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

DISABLE

Figure 10

Power Consumption

logic state (see Table 14).

2

Figure 8

DD1

DD1

11

is set high

Rev. I | Page 4 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V
unless otherwise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel,

Output Supply Current per Channel,

ADuM1410, Total Supply Current,

ADuM1411, Total Supply Current,

ADuM1412, Total Supply Current,

All Models

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.25 0.38 mA

I

DDI (Q)

DD1

= V

= 3.0 V. All voltages are relative to their respective ground.

DD2

Quiescent

I

0.19 0.33 mA

DDO (Q)

Quiescent

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.2 1.6 mA

DD1 (Q)

0.8 1.0 mA

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

1

Four Channels

4.5 6.5 mA 5 MHz logic signal frequency

DD1 (10)

1.4 1.8 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.9 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.9 1.7 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Four Channels

1

3.1 4.5 mA 5 MHz logic signal frequency

DD1 (10)

2.1 3.0 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

1.0 1.8 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Version Only)

V

or V

DD1

Supply Current I

DD2

Input Currents

Logic High Input Threshold
Logic Low Input Threshold

Logic Low Output Voltages

DD1 (10)

, IIB, IIC,

I

IA

, I

I

ID

CTRL1

I

CTRL2

V

IH

V

IL

V

OAH

V

OCH

V

OAL

V

OCL

, I

, V
, V

, V
, V

, I

2.6 3.8 mA 5 MHz logic signal frequency

DD2 (10)

−10 +0.01 +10 µA

,

DISABLE

1.6 V

0.4 V
(V

or V

OBH

ODH

OBL

ODL

,

,

DD1

(V

DD1

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

) − 0.1 3.0 V IOx = −20 µA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V I

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

, VIB, VIC, VID ≤ V

0 V ≤ V

IA

0 V ≤ V

CTRL1

0 V ≤ V

DISABLE

= 4 mA, VIx = V

Ox

, V

CTRL2

≤ V

DD1

≤ V

IxH

IxL

IxL

DD1

DD1

Logic High Output Voltages

IxH

IxL

or V

or V

DD2

DD2

,
,

Rev. I | Page 5 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM141xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t

PLH

− t

PHL

4

|
Propagation Delay Skew5 t
Channel-to-Channel Matching6 t

ADuM141xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing-Directional Channels

6

6

All Models

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

7

Refresh Rate fr 1.1 Mbps
Input Enable Time8 t
Input Disable Time8 t
Input Dynamic Supply Current

per Channel

Output Dynamic Supply Current

per Channel

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section.
See Figure through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through
Figure 15

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

PSK

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

7

|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.

8

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

is the magnitude of the worst-case difference in t

DD1

9

9

and V

supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

DD2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DISABLE

, t

20 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

20 40 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 5 ns CL = 15 pF, CMOS signal levels

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

| 25 35 kV/µs

|CM

H

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

ENABLE

DISABLE

0.07

I

DDI (D)

2.0 µs VIA, VIB, VIC, VID = 0 V or V

5.0 µs VIA, VIB, VIC, VID = 0 V or V
mA/

DD1

DD1

Mbps

0.02

I

DDO (D)

mA/
Mbps

ower Consumption

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. |CML| is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

logic state (see Table 14).

2

Power Consumption

Figure 8

Figure 10

11

propagation delay is

PLH

is set high

DISABLE

Rev. I | Page 6 of 24

Data Sheet ADuM1410/ADuM1411/ADuM1412

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

5 V/3 V operation: 4.5 V ≤ V
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel,

Quiescent
5 V/3 V Operation 0.50 0.73 mA
3 V/5 V Operation 0.25 0.38 mA

Output Supply Current per Channel,

Quiescent
5 V/3 V Operation 0.19 0.33 mA
3 V/5 V Operation 0.38 0.53 mA

ADuM1410, Total Supply Current,

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.4 3.2 mA

3 V/5 V Operation 1.2 1.6 mA

V

Supply Current I

DD2

5 V/3 V Operation 0.8 1.0 mA

3 V/5 V Operation 1.2 1.6 mA

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 8.6 11 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.4 6.5 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 1.4 1.8 mA 5 MHz logic signal frequency
3 V/5 V Operation 2.6 3.0 mA 5 MHz logic signal frequency

ADuM1411, Total Supply Current,

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.2 2.8 mA

3 V/5 V Operation 1.0 1.9 mA

V

Supply Current I

DD2

5 V/3 V Operation 0.9 1.7 mA

3 V/5 V Operation 1.7 2.4 mA

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 5.4 7.6 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.1 4.5 mA 5 MHz logic signal frequency

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V; or V

DD2

I

DDI (Q)

I

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (Q)

DD2 (Q)

DD1 (10)

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

= 5 V, V

DD1

= 3.0 V. All voltages are relative to their respective ground.

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

DD2

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

≤ 5.5 V; all

Rev. I | Page 7 of 24

ADuM1410/ADuM1411/ADuM1412 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

V

Supply Current I

DD2

5 V/3 V Operation 2.1 3.0 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.8 5.3 mA 5 MHz logic signal frequency

ADuM1412, Total Supply Current,

Four Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.0 2.6 mA

3 V/5 V Operation 1.0 1.8 mA

V

Supply Current I

DD2

5 V/3 V Operation 1.0 1.8 mA

3 V/5 V Operation 2.0 2.6 mA

10 Mbps (BRWZ Version Only)

V

Supply Current I

DD1

5 V/3 V Operation 4.6 6.5 mA 5 MHz logic signal frequency
3 V/5 V Operation 2.6 3.8 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 2.6 3.8 mA 5 MHz logic signal frequency
3 V/5 V Operation 4.6 6.5 mA 5 MHz logic signal frequency

All Models

Input Currents

Logic High Input Threshold

5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V

Logic Low Input Threshold

5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V

Logic Low Output Voltages

SWITCHING SPECIFICATIONS

ADuM141xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t

Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t

Channel-to-Channel Matching6 t

ADuM141xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t

PLH

− t

|4 PWD 5 ns CL = 15 pF, CMOS signal levels

PHL

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

DD2 (10)

DD1 (Q)

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

DD2 (Q)

DC to 1 MHz logic signal
frequency

DC to 1 MHz logic signal
frequency

DD1 (10)

DD2 (10)

, IIB, IIC, IID,

I

IA

, I

I

CTRL1

I

DISABLE

V

IH

V

IL

, V

V

OAH

, V

V

OCH

, V

V

OAL

, V

V

OCL

, t

PHL

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/OD

, t

PHL

30 ns CL = 15 pF, CMOS signal levels

PSK

−10 +0.01 +10 µA

,

CTRL2

0 V ≤ V
0 V ≤ V
0 V ≤ V

,V

IA

CTRL1

DISABLE

, V

,V

≤ V

IB

IC

ID

,V

≤ V

CTRL2

≤ V

DD1

(V

or V
or V

) − 0.1 ( V

DD2

) − 0.4 ( V

DD2

,

OBH

ODH

OBL

ODL

DD1

(V

DD1

0.0 0.1 V IOx = 20 µA, VIx = V

,

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V I

25 70 100 ns CL = 15 pF, CMOS signal levels

PLH

DD1

DD1

or V

V IOx = −20 µA, VIx = V

DD2)

or V

) − 0.2 V IOx = −4 mA, VIx = V

DD2

= 4 mA, VIx = V

Ox

IxH

IxH

IxL

IxL

IxL

50 ns CL = 15 pF, CMOS signal levels

25 35 60 ns CL = 15 pF, CMOS signal levels

PLH

DD1

Logic High Output Voltages

DD1

or V

or V

DD2

DD2

,

,

Rev. I | Page 8 of 24