Page 1
Quad-Channel Digital Isolators
FEATURES
Low power operation
5 V operation
1.0 mA per channel max @ 0 Mbps to 2 Mbps
3.5 mA per channel max @ 10 Mbps
31 mA per channel max @ 90 Mbps
3 V operation
0.7 mA per channel max @ 0 Mbps to 2 Mbps
2.1 mA per channel max @ 10 Mbps
20 mA per channel max @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns max pulse width distortion
2 ns max channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package, Pb-free models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
= 560 V peak
V
IORM
TÜV approval: IEC/EN/UL/CSA 61010-1
APPLICATIONS
General-purpose multichannel isolation
SPI® interface/data converter isolation
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation
FUNCTIONAL BLOCK DIAGRAMS
ADuM1400/ADuM1401/ADuM1402
GENERAL DESCRIPTION
The ADuM140x1 are 4-channel digital isolators based on
Analog Devices’ iCoupler® technology. Combining high speed
CMOS and monolithic air core transformer technology, these
isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler
devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM140x isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM140x provides low pulse width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM140x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.
1
Ordering Guide). All models operate with the supply
Protected by U.S. Patents 5,952,849 and 6,873,065. Other patents pending.
V
GND
GND
DD1
V
1
2
1
3
V
IA
4
IB
5
V
IC
6
V
ID
7
NC
8
1
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
16
V
DD2
15
GND
2
14
V
OA
13
V
OB
12
V
OC
11
V
OD
10
V
E2
9
GND
2
03786-001
Figure 1. ADuM1400 Functional Block Diagram
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
1
V
DD1
2
GND
1
3
V
V
V
V
V
GND
ENCODE DECODE
IA
4
ENCODE DECODE
IB
5
ENCODE DECODE
IC
6
DECODE ENCODE
OD
7
E1
8
1
Figure 2. ADuM1401 Functional Block Diagram
16
V
DD2
15
GND
2
14
V
OA
13
V
OB
12
V
OC
11
V
ID
10
V
E2
9
GND
2
03786-002
V
GND
V
V
GND
DD1
V
V
1
2
1
3
V
ENCODE DECODE
IA
4
ENCODE DECODE
IB
5
DECODE ENCODE
OC
6
DECODE ENCODE
OD
7
E1
8
1
Figure 3. ADuM1402 Functional Block Diagram
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
16
V
DD2
15
GND
2
14
V
OA
13
V
OB
12
V
IC
11
V
ID
10
V
E2
9
GND
2
03786-003
Page 2
ADuM1400/ADuM1401/ADuM1402
TABLE OF CONTENTS
Features.............................................................................................. 1
Absolute Maximum Ratings ......................................................... 14
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 6
Electrical Characteristics—
Mixed 5 V/3 V or 3 V/5 V Operation........................................
Package Characteristics .............................................................12
Regulatory Information............................................................. 12
Insulation and Safety-Related Specifications.......................... 12
DIN EN 60747-5-2 (VDE 0884 Part 2)
Insulation Characteristics..........................................................
Recommended Operating Conditions ....................................13
13
ESD Caution................................................................................ 14
Pin Configurations and Function Descriptions......................... 15
Typical Performance Characteristics........................................... 17
Application Information................................................................ 19
PC Board Layout ........................................................................ 19
Propagation Delay-Related Parameters................................... 19
DC Correctness and Magnetic Field Immunity........................... 19
Power Consumption.................................................................. 20
8
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
2/06—Rev. C to Rev. D
Updated Format..................................................................Universal
Added TÜV Approval........................................................Universal
5/05—Rev. B to Rev. C
Changes to Format .............................................................Universal
Changes to Figure 2.......................................................................... 1
Changes to Table 3............................................................................ 8
Changes to Table 6.......................................................................... 12
Changes to Ordering Guide.......................................................... 21
6/04—Rev. A to Rev. B
Changes to Format .............................................................Universal
Changes to Features.......................................................................... 1
Changes to Electrical Characteristics—5 V Operation ............... 3
Changes to Electrical Characteristics—3 V Operation ............... 5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation............................................................................ 7
Changes to DIN EN 60747-5-2 (VDE 0884 Part 2)
Insulation Characteristics Title..................................................... 11
Changes to the Ordering Guide.................................................... 19
5/04—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changes to the Features....................................................................1
Changes to Table 7 and Table 8 .................................................... 14
Changes to Table 9.......................................................................... 15
Changes to the DC Correctness and Magnetic Field Immunity
Section.............................................................................................. 20
Changes to the Power Consumption Section ............................. 21
Changes to the Ordering Guide ................................................... 22
9/03—Revision 0: Initial Version.
Rev. D | Page 2 of 24
Page 3
ADuM1400/ADuM1401/ADuM1402
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION1
4.5 V ≤ V
otherwise noted; all typical specifications are at T
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I
ADuM1400, Total Supply Current, Four Channels2
ADuM1401, Total Supply Current, Four Channels2
ADuM1402, Total Supply Current, Four Channels2
For All Models
≤ 5.5 V, 4.5 V ≤ V
DD1
≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless
DD2
= 25°C, V
A
DDI (Q)
DDO (Q)
= V
DD2
= 5 V.
DD1
0.50 0.53 mA
0.19 0.21 mA
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
2.2 2.8 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.9 1.4 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
8.6 10.6 mA 5 MHz logic signal freq.
DD1 (10)
2.6 3.5 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
70 100 mA 45 MHz logic signal freq.
DD1 (90)
18 25 mA 45 MHz logic signal freq.
DD2 (90)
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
1.8 2.4 mA DC to 1 MHz logic signal freq.
DD1 (Q)
1.2 1.8 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
7.1 9.0 mA 5 MHz logic signal freq.
DD1 (10)
4.1 5.0 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
57 82 mA 45 MHz logic signal freq.
DD1 (90)
31 43 mA 45 MHz logic signal freq.
DD2 (90)
DC to 2 Mbps
V
or V
DD1
Supply Current I
DD2
DD1 (Q)
, I
1.5 2.1 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
or V
DD1
Supply Current I
DD2
DD1 (10)
, I
5.6 7.0 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
or V
DD1
Supply Current I
DD2
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic Low Output Voltages
DD1 (90)
, IIB, IIC,
I
IA
I
, IE1, I
ID
VIH, V
VIL, V
V
OAH
V
OCH
V
OAL
V
OCL
, V
, V
, V
, V
EH
EL
, I
44 62 mA 45 MHz logic signal freq.
DD2 (90)
−10 +0.01 +10 μA
E2
2.0 V
0.8 V
V
, V
OBH
ODH
OBL
ODL
,
,
− 0.1 5.0 V IOx = −20 μA, VIx = V
DD1
DD2
V
, V
− 0.4 4.8 V IOx = −4 mA, VIx = V
DD1
DD2
0.0 0.1 V IOx = 20 μA, VIx = V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
0 ≤ V
0 ≤ V
IA
E1
, VIB, VIC, VID ≤ V
, VE2 ≤ V
DD1
or V
IxH
IxL
IxL
or V
DD1
DD2
Logic High Output Voltages
IxH
,
DD2
IxL
Rev. D | Page 3 of 24
Page 4
ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Propagation Delay Skew6 t
Channel-to-Channel Matching7 t
ADuM140xBRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
ADuM140xCRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
8
8
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 I
Output Dynamic Supply Current per Channel9 I
, t
50 65 100 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 40 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels
PSK
50 ns CL = 15 pF, CMOS signal levels
PSKCD/OD
, t
20 32 50 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 3 ns CL = 15 pF, CMOS signal levels
15 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
6 ns CL = 15 pF, CMOS signal levels
PSKOD
, t
18 27 32 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
10 ns CL = 15 pF, CMOS signal levels
PSK
2 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
5 ns CL = 15 pF, CMOS signal levels
PSKOD
t
, t
PHZ
PLH
, t
t
PZH
PZL
| 25 35 kV/μs
|CM
H
6 8 ns CL = 15 pF, CMOS signal levels
6 8 ns CL = 15 pF, CMOS signal levels
= V
V
Ix
DD1/VDD2
, VCM = 1000 V,
transient magnitude = 800 V
|CML| 25 35 kV/μs
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
0.19 mA/Mbps
DDI (D)
0.05 mA/Mbps
DDO (D)
Rev. D | Page 4 of 24
Page 5
ADuM1400/ADuM1401/ADuM1402
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
t
is the magnitude of the worst-case difference in t
PSK
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
DD1
and V
supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
DD2
or t
that is measured between units at the same operating temperature, supply voltages, and output load
PHL
PLH
. CML is the maximum common-mode voltage slew rate
DD2
propagation delay is
PLH
Rev. D | Page 5 of 24
Page 6
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—3 V OPERATION1
2.7 V ≤ V
otherwise noted; all typical specifications are at T
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I
ADuM1400, Total Supply Current, Four Channels2
ADuM1401, Total Supply Current, Four Channels2
ADuM1402, Total Supply Current, Four Channels2
For All Models
SWITCHING SPECIFICATIONS
ADuM140xARW
≤ 3.6 V, 2.7 V ≤ V
DD1
≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless
DD2
= 25°C, V
A
DDI (Q)
DDO (Q)
= V
DD1
= 3.0 V.
DD2
0.26 0.31 mA
0.11 0.14 mA
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
1.2 1.9 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.5 0.9 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
4.5 6.5 mA 5 MHz logic signal freq.
DD1 (10)
1.4 2.0 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
37 65 mA 45 MHz logic signal freq.
DD1 (90)
11 15 mA 45 MHz logic signal freq.
DD2 (90)
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
1.0 1.6 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.7 1.2 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
3.7 5.4 mA 5 MHz logic signal freq.
DD1 (10)
2.2 3.0 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
30 52 mA 45 MHz logic signal freq.
DD1 (90)
18 27 mA 45 MHz logic signal freq.
DD2 (90)
DC to 2 Mbps
V
or V
DD1
Supply Current I
DD2
DD1 (Q)
, I
0.9 1.5 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
or V
DD1
Supply Current I
DD2
DD1 (10)
, I
3.0 4.2 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
or V
DD1
Supply Current I
DD2
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic Low Output Voltages
DD1 (90)
, IIB, I
I
IA
I
, IE1, I
ID
VIH, V
VIL, V
V
OAH
V
OCH
V
OAL
V
OCL
, I
24 39 mA 45 MHz logic signal freq.
DD2 (90)
−10 +0.01 +10 μA
, V
, V
, V
, V
IC,
E2
EH
EL
OBL
ODL
1.6 V
0.4 V
V
, V
,
OBH
ODH
V
0.0 0.1 V IOx = 20 μA, VIx = V
,
0.04 0.1 V IOx = 400 μA, VIx = V
− 0.1 3.0 V IOx = −20 μA, VIx = V
DD1
DD2
, V
− 0.4 2.8 V IOx = −4 mA, VIx = V
DD1
DD2
0.2 0.4 V I
, VIB, VIC, VID ≤ V
0 ≤ V
IA
0 ≤ V
E1,VE2
= 4 mA, VIx = V
Ox
≤ V
DD1
or V
IxH
IxL
IxL
or V
DD1
DD2
DD2
Logic High Output Voltages
IxH
IxL
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Propagation Delay Skew6 t
Channel-to-Channel Matching7 t
, t
50 75 100 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 40 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels
PSK
50 ns CL = 15 pF, CMOS signal levels
PSKCD/OD
,
Rev. D | Page 6 of 24
Page 7
ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM140xBRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
ADuM140xCRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
8
8
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel9 I
Output Dynamic Supply Current per Channel9 I
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the V
6
t
is the magnitude of the worst-case difference in t
PSK
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
DD1
and V
supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
DD2
signal to the 50% level of the rising edge of the VOx signal.
Ix
or t
PHL
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
O
, t
20 38 50 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 3 ns CL = 15 pF, CMOS signal levels
22 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
6 ns CL = 15 pF, CMOS signal levels
PSKOD
, t
20 34 45 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
16 ns CL = 15 pF, CMOS signal levels
PSK
2 ns CL = 15 pF, CMOS signal levels
t
PSKCD
5 ns CL = 15 pF, CMOS signal levels
t
PSKOD
, t
t
PHZ
PLH
, t
t
PZH
PZL
| 25 35 kV/μs
|CM
H
6 8 ns CL = 15 pF, CMOS signal levels
6 8 ns CL = 15 pF, CMOS signal levels
= V
V
Ix
DD1/VDD2
, VCM = 1000 V,
transient magnitude = 800 V
|CML| 25 35 kV/μs
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
0.10 mA/Mbps
DDI (D)
0.03 mA/Mbps
DDO (D)
propagation delay is
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Rev. D | Page 7 of 24
Page 8
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V ≤ V
specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
V
= 3.0 V, V
DD1
= 5 V or V
DD2
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
5 V/3 V Operation 0.50 0.53 mA
3 V/5 V Operation 0.26 0.31 mA
Output Supply Current per Channel, Quiescent I
5 V/3 V Operation 0.11 0.14 mA
3 V/5 V Operation 0.19 0.21 mA
ADuM1400, Total Supply Current, Four Channels2
DC to 2 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq.
3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
5 V/3 V Operation 70 100 mA 45 MHz logic signal freq.
3 V/5 V Operation 37 65 mA 45 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 11 15 mA 45 MHz logic signal freq.
3 V/5 V Operation 18 25 mA 45 MHz logic signal freq.
ADuM1401, Total Supply Current, Four Channels2
DC to 2 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.
≤ 5.5 V, 2.7 V ≤ V
DD1
= 5 V, V
DD1
DD2
= 3.0 V.
≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V
DD2
DDI (Q)
DDO (Q)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
DD1 (90)
DD2 (90)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
≤ 3.6 V, 4.5 V ≤ V
DD1
≤ 5.5 V; all min/max
DD2
= 25°C;
A
Rev. D | Page 8 of 24
Page 9
ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
5 V/3 V Operation 57 82 mA 45 MHz logic signal freq.
3 V/5 V Operation 30 52 mA 45 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 18 27 mA 45 MHz logic signal freq.
3 V/5 V Operation 31 43 mA 45 MHz logic signal freq.
ADuM1402, Total Supply Current, Four Channels2
DC to 2 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq.
3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
5 V/3 V Operation 44 62 mA 45 MHz logic signal freq.
3 V/5 V Operation 24 39 mA 45 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 24 39 mA 45 MHz logic signal freq.
3 V/5 V Operation 44 62 mA 45 MHz logic signal freq.
For All Models
Input Currents
Logic High Input Threshold
5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V
Logic Low Input Threshold
5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Propagation Delay Skew6 t
Channel-to-Channel Matching7 t
DD1 (90)
DD2 (90)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
DD1 (90)
DD2 (90)
, IIB, IIC,
I
IA
I
, IE1, I
ID
VIH, V
VIL, V
V
OAH
V
OCH
V
OAL, VOBL,
V
, V
OCL
, t
PHL
EH
EL
, V
, V
PLH
−10 +0.01 +10 μA
E2
0 ≤ V
0 ≤ V
IA,VIB
E1,VE2
, VIC,VID ≤ V
≤ V
or V
DD1
DD1
or V
DD2
V
, V
DD1
DD1
, V
− 0.1 V
DD2
− 0.4 V
DD2
OBH
ODH
,
V
0.0 0.1 V IOx = 20 μA, VIx = V
ODL
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V I
V IOx = −20 μA, VIx = V
DD1, VDD2
, V
− 0.2 V IOx = −4 mA, VIx = V
DD1
DD2
Ox
= 4 mA, VIx = V
Logic High Output Voltages
IxH
IxH
IxL
IxL
IxL
50 70 100 ns CL = 15 pF, CMOS signal levels
DD2
PWD 40 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels
PSK
50 ns CL = 15 pF, CMOS signal levels
PSKCD/OD
,
Rev. D | Page 9 of 24
Page 10
ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM140xBRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
ADuM140xCRW
Minimum Pulse Width3 PW 8.3 11.1 ns
Maximum Data Rate4 90 120 Mbps
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tf C
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
8
8
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current per Channel9 I
5 V/3 V Operation 0.19 mA/Mbps
3 V/5 V Operation 0.10 mA/Mbps
Output Dynamic Supply Current per Channel9 I
5 V/3 V Operation 0.03 mA/Mbps
3 V/5 V Operation 0.05 mA/Mbps
, t
15 35 50 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 3 ns CL = 15 pF, CMOS signal levels
22 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
6 ns CL = 15 pF, CMOS signal levels
PSKOD
= 15 pF, CMOS signal levels
C
L
C
= 15 pF, CMOS signal levels
L
, t
20 30 40 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
14 ns CL = 15 pF, CMOS signal levels
PSK
2 ns CL = 15 pF, CMOS signal levels
t
PSKCD
5 ns CL = 15 pF, CMOS signal levels
t
PSKOD
, t
t
PHZ
PLH
, t
t
PZH
PZL
|CMH| 25 35 kV/μs
6 8 ns CL = 15 pF, CMOS signal levels
6 8 ns CL = 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
L
= V
V
Ix
DD1/VDD2
, VCM = 1000 V,
transient magnitude = 800 V
|CML| 25 35 kV/μs
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
DDI (D)
DDI (D)
Rev. D | Page 10 of 24
Page 11
ADuM1400/ADuM1401/ADuM1402
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
t
is the magnitude of the worst-case difference in t
PSK
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
DD1
and V
supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
DD2
or t
that is measured between units at the same operating temperature, supply voltages, and output load
PHL
PLH
. CML is the maximum common-mode voltage slew rate
DD2
propagation delay is
PLH
Rev. D | Page 11 of 24
Page 12
ADuM1400/ADuM1401/ADuM1402
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-to-Output)1 R
Capacitance (Input-to-Output)
1
Input Capacitance2 C
IC Junction-to-Case Thermal Resistance, Side 1 θ
IC Junction-to-Case Thermal Resistance, Side 2 θ
1
Device considered a 2-terminal device; Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.
2
Input capacitance is from any input data pin to ground.
10
I-O
C
2.2 pF f = 1 MHz
I-O
4.0 pF
I
33 °C/W
JCI
28 °C/W
JCO
REGULATORY INFORMATION
The ADuM140x have been approved by the organizations listed in Tab le 5 .
Table 5.
UL1 CSA VDE2 TÜV
Recognized under
1577 component
recognition
program
1
Double/reinforced
insulation,
2500 V rms
isolation voltage
Reinforced insulation, 560 V peak
File E214100 File 205078 File 2471900-4880-0001 Certificate U8V 05 06 56232 002
1
In accordance with UL1577, each ADuM140x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2
In accordance with DIN EN 60747-5-2, each ADuM140x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN EN 60747-5-2 approval.
Approved under CSA
Component
Acceptance Notice #5A
Reinforced insulation per
CSA 60950-1-03 and
IEC 60950-1,
400 V rms maximum
working voltage
Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-012
Basic insulation, 560 V peak
Complies with DIN EN 60747-5-2 (VDE 0884 Part 2):
2003-01,
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
1, 2
Ω
Approved according to:
IEC 61010-1:2001 (2nd Edition),
EN 61010-1:2001 (2
UL 61010-1:2004
CSA C22.2.61010.1:2005
Reinforced insulation,
400 V rms maximum working
voltage
Thermocouple located
at center of package
underside
nd
Edition)
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm
Minimum External Tracking (Creepage) L(I02) 8.1 min mm
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. D | Page 12 of 24
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Page 13
ADuM1400/ADuM1401/ADuM1402
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 7.
Description Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤150 V rms I-IV
For Rated Mains Voltage ≤300 V rms I-III
For Rated Mains Voltage ≤400 V rms I-II
Climatic Classification 40/105/21
Pollution Degree (DIN VDE 0110, Table 1) 2
Maximum Working Insulation Voltage V
Input-to-Output Test Voltage, Method b1 VPR 1050 V peak
V
× 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
IORM
Input-to-Output Test Voltage, Method a VPR
After Environmental Tests Subgroup 1 896 V peak
V
× 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
IORM
After Input and/or Safety Test Subgroup 2/3 672 V peak
V
× 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
IORM
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) VTR 4000 V peak
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; also see Figure 4)
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
Insulation Resistance at TS, VIO = 500 V RS >109 Ω
These isolators are suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits.
560 V peak
IORM
The * marking on packages denotes DIN EN 60747-5-2 approval.
350
300
250
200
150
100
SAFETY-LIMITING CURRENT (mA)
50
0
0
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN EN 60747-5-2
SIDE #2
SIDE #1
50 100 150 200
CASE TEMPERAT URE (°C)
03786-004
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +105 °C
Supply Voltages1 V
Input Signal Rise and Fall Times 1.0 ms
1
All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section fo r information on immunity to external
magnetic fields.
, V
2.7 5.5 V
DD1
DD 2
Rev. D | Page 13 of 24
Page 14
ADuM1400/ADuM1401/ADuM1402
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9.
Parameter Symbol Min Max Unit
Storage Temperature TST −65 +150 °C
Ambient Operating Temperature TA −40 +105 °C
Supply Voltages1 V
Input Voltage
Output Voltage
1, 2
1, 2
Average Output Current per Pin3
Side 1 IO1 −18 +18 mA
Side 2 IO2 −22 +22 mA
Common-Mode Transients4 −100 +100 kV/μs
1
All voltages are relative to their respective ground.
2
V
and V
DDI
3
See Figure 4 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or
permanent damage.
refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section.
DDO
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
, V
−0.5 +7.0 V
DD1
DD2
VIA, VIB, VIC, VID, VE1,V
E2
−0.5 V
VOA, VOB, VOC, VOD −0.5 V
+ 0.5 V
DDI
+ 0.5 V
DDO
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Table 10. Truth Table (Positive Logic)
VIX Input1 VEX Input2 V
H H or NC Powered Powered H
L H or NC Powered Powered L
X L Powered Powered Z
X H or NC Unpowered Powered H Outputs return to the input state within 1 μs of V
X L Unpowered Powered Z
X X Powered Unpowered Indeterminate
1
VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. V
refer to the supply voltages on the input and output sides of the given channel, respectively.
V
DDO
2
In noisy environments, connecting VEX to an external logic high or low is recommended.
State1 V
DDI
State1 VOX Output1 Notes
DDO
Outputs return to the input state within 1 μs of V
if V
8 ns of V
power restoration.
DDI
power restoration
state is H or NC. Outputs return to high impedance state within
EX
power restoration if VEX state is L.
DDO
DDO
DDI
and
Rev. D | Page 14 of 24
Page 15
ADuM1400/ADuM1401/ADuM1402
*
*
*
*
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
V
DD1
2
*GND
1
V
3
IA
ADuM1400
V
4
IB
TOP VIEW
(Not to Scale)
5
V
IC
V
6
ID
NC
7
8
*GND
1
NC = NO CONNECT
Figure 5. ADuM1400 Pin Configuration
16
15
14
13
12
11
10
9
V
DD2
GND2*
V
OA
V
OB
V
OC
V
OD
V
E2
GND2*
1
V
DD1
2
GND
1
V
3
IA
ADuM1401
V
4
IB
TOP VIEW
(Not to S cale)
5
V
IC
V
6
OD
V
7
E1
8
GND
1
03786-005
NC = NO CONNECT
Figure 6. ADuM1401 Pin Configuration
16
15
14
13
12
11
10
9
V
DD2
GND2*
V
OA
V
OB
V
OC
V
ID
V
E2
GND2*
1
V
DD1
2
GND
1
V
3
IA
ADuM1402
V
4
IB
TOP VIEW
(Not to Scale)
5
V
OC
V
6
OD
V
7
E1
8
GND
1
03786-006
NC = NO CONNECT
16
15
14
13
12
11
10
9
V
DD2
GND2*
V
OA
V
OB
V
IC
V
ID
V
E2
GND2*
Figure 7. ADuM1402 Pin Configuration
* Pins 2 and 8 are internally connected, and connecting both to GND1 is recommended. Pins 9 and 15 are internally connected, and connecting both to GND2 is
recommended. In noisy environments, connecting the output enables (Pin 7 for ADuM1401/ADuM1402 and Pin 10 for all models) to an external logic high or low is
recommended.
Table 11. ADuM1400 Pin Function Descriptions
Pin
No. Mnemonic Function
1 V
DD1
2 GND
3 V
IA
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for isolator Side 1.
1
Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 V
ID
Logic Input D.
7 NC No Connect.
8 GND1 Ground 1. Ground reference for isolator Side 1.
9 GND2 Ground 2. Ground reference for isolator Side 2.
10 VE2
Output Enable 2. Active high logic input. V
, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high
V
OA
, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
OA
or low is recommended.
11 V
OD
Logic Output D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for isolator Side 2.
16 V
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
DD2
03786-007
Rev. D | Page 15 of 24
Page 16
ADuM1400/ADuM1401/ADuM1402
Table 12. ADuM1401 Pin Function Descriptions
Pin
No. Mnemonic Function
1 V
DD1
2 GND
3 V
IA
4 VIB Logic Input B.
5 VIC Logic Input C.
6 V
OD
7 VE1
8 GND1 Ground 1. Ground reference for isolator Side 1.
9 GND2 Ground 2. Ground reference for isolator Side 2.
10 VE2
11 V
ID
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for isolator Side 2.
16 V
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
DD2
Table 13. ADuM1402 Pin Function Descriptions
Pin
No. Mnemonic Function
1 V
DD1
2 GND
3 V
IA
4 VIB Logic Input B.
5 VOC Logic Output C.
6 V
OD
7 VE1
8 GND1 Ground 1. Ground reference for isolator Side 1.
9 GND2 Ground 2. Ground reference for isolator Side 2.
10 VE2
11 V
ID
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground Reference for Isolator Side 2.
16 V
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
DD2
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for isolator Side 1.
1
Logic Input A.
Logic Output D.
Output Enable 1. Active high logic input. V
In noisy environments, connecting V
Output Enable 2. Active high logic input. V
outputs are disabled when V
is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.
E2
Logic Input D.
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for isolator Side 1.
1
Logic Input A.
Logic Output D.
Output Enable 1. Active high logic input. V
are disabled when V
is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
E1
Output Enable 2. Active high logic input. V
are disabled when V
is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.
E2
Logic Input D.
output is enabled when VE1 is high or disconnected. VOD is disabled when VE1 is low.
OD
to an external logic high or low is recommended.
E1
, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC
OA
and VOD outputs are enabled when VE1 is high or disconnected. VOC and VOD outputs
OC
and VOB outputs are enabled when VE2 is high or disconnected. VOA and VOB outputs
OA
Rev. D | Page 16 of 24
Page 17
ADuM1400/ADuM1401/ADuM1402
TYPICAL PERFORMANCE CHARACTERISTICS
20
80
70
15
10
5V
5
CURRENT/CHANNEL (mA)
0
0
20 60 8040 100
DATA RATE (Mb ps)
3V
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
6
5
4
3
2
CURRENT/CHANNEL (mA)
1
5V
3V
60
50
40
30
CURRENT (mA)
20
10
0
0
03786-008
Figure 11. Typical ADuM1400 V
5V
3V
20 60 8040 100
DATA RATE (Mb ps)
Supply Current vs. Data Rate
DD1
03786-011
for 5 V and 3 V Operation
20
15
10
10
CURRENT (mA)
5
5V
3V
0
0
20 60 8040 100
DATA RATE (Mb ps)
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
10
8
6
4
CURRENT/CHANNEL (mA)
2
0
0
5V
3V
20 60 8040 100
DATA RATE (Mb ps)
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Rev. D | Page 17 of 24
0
0
03786-009
Figure 12. Typical ADuM1400 V
20 60 8040 100
DATA RATE (Mb ps)
Supply Current vs. Data Rate
DD2
03786-012
for 5 V and 3 V Operation
35
30
25
20
15
CURRENT (mA)
10
5
0
0
03786-010
Figure 13. Typical ADuM1401 V
5V
3V
20 60 8040 100
DATA RATE (Mb ps)
Supply Current vs. Data Rate
DD1
03786-013
for 5 V and 3 V Operation
Page 18
ADuM1400/ADuM1401/ADuM1402
40
35
40
30
25
20
15
CURRENT (mA)
10
5
0
0
5V
20 60 8040 100
DATA RATE (Mb ps)
Figure 14. Typical ADuM1401 V
for 5 V and 3 V Operation
50
45
40
35
30
25
20
CURRENT (mA)
15
10
5
0
0
5V
20 60 8040 100
DATA RATE (Mb ps)
Figure 15. Typical ADuM1402 V
Data Rate for 5 V and 3 V Operation
3V
Supply Current vs. Data Rate
DD2
3V
or V
DD1
Supply Current vs.
DD2
35
30
PROPAGATION DELAY (ns)
25
–50 –25
03786-014
0507525 100
TEMPERATURE ( °C)
3V
5V
03786-016
Figure 16. Propagation Delay vs. Temperature, C Grade
03786-015
Rev. D | Page 18 of 24
Page 19
ADuM1400/ADuM1401/ADuM1402
V
V
V
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM140x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins
Figure 17). Bypass capacitors are most conveniently connected
(
between Pins 1 and 2 for V
V
. The capacitor value should be between 0.01 μF and 0.1 μF.
DD2
and between Pins 15 and 16 for
DD1
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm.
Bypassing between Pins 1 and 8 and between Pins 9 and 16
should also be considered unless the ground pair on each
package side is connected close to the package.
V
DD1
GND
1
V
IA
V
IB
IC/OC
ID/OD
V
E1
GND
1
Figure 17. Recommended Printed Circuit Board Layout
V
DD2
GND
V
OA
V
OB
V
OC/IC
V
OD/ID
V
E2
GND
2
2
3786-017
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the device’s
Absolute Maximum Ratings, thereby leading to latch-up or
permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high.
INPUT (
)
IX
OUTPUT (V
t
PLH
)
OX
t
PHL
Figure 18. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM140x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM140x
components operating under the same conditions.
50%
50%
03786-018
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 2 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see
by the watchdog timer circuit.
The limitation on the ADuM140x’s magnetic field immunity is
set by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this may occur. The 3 V operating condition of the
ADuM140x is examined because it represents the most
susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)
2
∑∏r
; n = 1, 2, … , N
n
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
is the radius of the nth turn in the receiving coil (cm).
r
n
Given the geometry of the receiving coil in the ADuM140x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in
100
10
1
0.1
DENSITY ( kgauss)
0.01
MAXIMUM ALLOWABLE MAGNETIC FLUX
0.001
1k 10k 10M
Figure 19. Maximum Allowable External Magnetic Flux Density
MAGNETIC FIELD FREQUENCY (Hz)
Figure 19.
1M
Tabl e 10 )
100M100k
03786-019
Rev. D | Page 19 of 24
Page 20
ADuM1400/ADuM1401/ADuM1402
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM140x transformers.
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM140x is extremely immune and
can be affected only by extremely large currents operated at
high frequency very close to the component. For the 1 MHz
example noted, one would have to place a 0.5 kA current 5 mm
away from the ADuM140x to affect the component’s operation.
1000
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
MAXIMUM ALL OWABLE CURRENT ( kA)
0.01
1k 10k 100M100k 1M 10M
Figure 20. Maximum Allowable Current
for Various Current-to-ADuM140x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
Figure 20 expresses these allowable
DISTANCE = 1m
MAGNETIC FIELD FREQUENCY (Hz)
03786-020
POWER CONSUMPTION
The supply current at a given channel of the ADuM140x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
For each input channel, the supply current is given by
= I
I
DDI
DDI (Q)
= I
I
DDI
For each output channel, the supply current is given by
I
DDO
= (I
I
DDO
where:
I
, I
DDI (D)
DDO (D)
per channel (mA/Mbps).
C
is the output load capacitance (pF).
L
V
is the output supply voltage (V).
DDO
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
is the input stage refresh rate (Mbps).
f
r
, I
I
DDI (Q)
DDO (Q)
supply currents (mA).
To calculate the total V
currents for each input and output channel corresponding to
V
and V
DD1
provide per-channel supply currents as a function of data rate
for an unloaded output condition.
channel supply current as a function of data rate for a 15 pF
output condition.
V
and V
DD1
ADuM1400/ADuM1401/ADuM1402 channel configurations.
× (2f − fr) + I
= I
DDI (D)
f ≤ 0.5 fr
DDO (Q)
+ (0.5 × 10−3) × CL × V
DDO (D)
DDI (Q)
) × (2f − fr) + I
DDO
are the input and output dynamic supply currents
are the specified input and output quiescent
and V
DD1
are calculated and totaled. Figure 8 and Figure 9
DD2
supply current, the supply
DD2
Figure 10 provides per-
Figure 11 through Figure 15 provide total
supply current as a function of data rate for
DD2
f ≤ 0.5 fr
f > 0.5 fr
DDO (Q)
f > 0.5 fr
Rev. D | Page 20 of 24
Page 21
ADuM1400/ADuM1401/ADuM1402
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.51 (0.0201)
0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
9
7.60 (0.2992)
7.40 (0.2913)
8
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
10.65 (0.4193)
10.00 (0.3937)
0.33 (0.0130)
0.20 (0.0079)
0.75 (0.0295)
0.25 (0.0098)
8°
0°
×
45°
1.27 (0.0500)
0.40 (0.0157)
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimension shown in millimeters and (inches)
ORDERING GUIDE
Number of
Inputs,
Model
V
Side
DD1
ADuM1400ARW2 4 0 1 100 40 −40 to +105 RW-16
ADuM1400BRW2 4 0 10 50 3 −40 to +105 RW-16
ADuM1400CRW2 4 0 90 32 2 −40 to +105 RW-16
ADuM1400ARWZ
ADuM1400BRWZ
ADuM1400CRWZ
2, 3
4 0 1 100 40 −40 to +105 RW-16
2, 3
4 0 10 50 3 −40 to +105 RW-16
2, 3
4 0 90 32 2 −40 to +105 RW-16
ADuM1401ARW2 3 1 1 100 40 −40 to +105 RW-16
ADuM1401BRW2 3 1 10 50 3 −40 to +105 RW-16
ADuM1401CRW2 3 1 90 32 2 −40 to +105 RW-16
ADuM1401ARWZ
ADuM1401BRWZ
ADuM1401CRWZ
2, 3
3 1 1 100 40 −40 to +105 RW-16
2, 3
3 1 10 50 3 −40 to +105 RW-16
2, 3
3 1 90 32 2 −40 to +105 RW-16
ADuM1402ARW2 2 2 1 100 40 −40 to +105 RW-16
ADuM1402BRW2 2 2 10 50 3 −40 to +105 RW-16
ADuM1402CRW2 2 2 90 32 2 −40 to +105 RW-16
ADuM1402ARWZ
ADuM1402BRWZ
ADuM1402CRWZ
2, 3
2 2 1 100 40 −40 to +105 RW-16
2, 3
2 2 10 50 3 −40 to +105 RW-16
2, 3
2 2 90 32 2 −40 to +105 RW-16
EVAL-ADuM1402EBA Evaluation Board
EVAL-ADuM1402EBB Evaluation Board
EVAL-ADuM1402EBC Evaluation Board
1
RW-16 = 16-lead wide body SOIC.
2
Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.
3
Z = Pb-free part.
Number of
Inputs,
V
Side
DD2
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns) Temperature Range (°C)
Package
Option1
Rev. D | Page 21 of 24
Page 22
ADuM1400/ADuM1401/ADuM1402
NOTES
Rev. D | Page 22 of 24
Page 23
ADuM1400/ADuM1401/ADuM1402
NOTES
Rev. D | Page 23 of 24
Page 24
ADuM1400/ADuM1401/ADuM1402
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03786-0-2/06(D)
Rev. D | Page 24 of 24
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