Quad-Channel Digital Isolators
FEATURES
Low power operation
5 V operation
1.0 mA per channel max @ 0 Mbps to 2 Mbps
3.5 mA per channel max @ 10 Mbps
31 mA per channel max @ 90 Mbps
3 V operation
0.7 mA per channel max @ 0 Mbps to 2 Mbps
2.1 mA per channel max @ 10 Mbps
20 mA per channel max @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns max pulse width distortion
2 ns max channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package, Pb-free models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
= 560 V peak
V
IORM
TÜV approval: IEC/EN/UL/CSA 61010-1
APPLICATIONS
General-purpose multichannel isolation
SPI® interface/data converter isolation
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation
FUNCTIONAL BLOCK DIAGRAMS
ADuM1400/ADuM1401/ADuM1402
GENERAL DESCRIPTION
The ADuM140x1 are 4-channel digital isolators based on
Analog Devices’ iCoupler® technology. Combining high speed
CMOS and monolithic air core transformer technology, these
isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler
devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM140x isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM140x provides low pulse width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM140x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.
1
Ordering Guide). All models operate with the supply
Protected by U.S. Patents 5,952,849 and 6,873,065. Other patents pending.
V
GND
GND
DD1
V
1
2
1
3
V
IA
4
IB
5
V
IC
6
V
ID
7
NC
8
1
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
16
V
DD2
15
GND
2
14
V
OA
13
V
OB
12
V
OC
11
V
OD
10
V
E2
9
GND
2
03786-001
Figure 1. ADuM1400 Functional Block Diagram
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
1
V
DD1
2
GND
1
3
V
V
V
V
V
GND
ENCODE DECODE
IA
4
ENCODE DECODE
IB
5
ENCODE DECODE
IC
6
DECODE ENCODE
OD
7
E1
8
1
Figure 2. ADuM1401 Functional Block Diagram
16
V
DD2
15
GND
2
14
V
OA
13
V
OB
12
V
OC
11
V
ID
10
V
E2
9
GND
2
03786-002
V
GND
V
V
GND
DD1
V
V
1
2
1
3
V
ENCODE DECODE
IA
4
ENCODE DECODE
IB
5
DECODE ENCODE
OC
6
DECODE ENCODE
OD
7
E1
8
1
Figure 3. ADuM1402 Functional Block Diagram
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
16
V
DD2
15
GND
2
14
V
OA
13
V
OB
12
V
IC
11
V
ID
10
V
E2
9
GND
2
03786-003
ADuM1400/ADuM1401/ADuM1402
TABLE OF CONTENTS
Features.............................................................................................. 1
Absolute Maximum Ratings ......................................................... 14
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 6
Electrical Characteristics—
Mixed 5 V/3 V or 3 V/5 V Operation........................................
Package Characteristics .............................................................12
Regulatory Information............................................................. 12
Insulation and Safety-Related Specifications.......................... 12
DIN EN 60747-5-2 (VDE 0884 Part 2)
Insulation Characteristics..........................................................
Recommended Operating Conditions ....................................13
13
ESD Caution................................................................................ 14
Pin Configurations and Function Descriptions......................... 15
Typical Performance Characteristics........................................... 17
Application Information................................................................ 19
PC Board Layout ........................................................................ 19
Propagation Delay-Related Parameters................................... 19
DC Correctness and Magnetic Field Immunity........................... 19
Power Consumption.................................................................. 20
8
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
2/06—Rev. C to Rev. D
Updated Format..................................................................Universal
Added TÜV Approval........................................................Universal
5/05—Rev. B to Rev. C
Changes to Format .............................................................Universal
Changes to Figure 2.......................................................................... 1
Changes to Table 3............................................................................ 8
Changes to Table 6.......................................................................... 12
Changes to Ordering Guide.......................................................... 21
6/04—Rev. A to Rev. B
Changes to Format .............................................................Universal
Changes to Features.......................................................................... 1
Changes to Electrical Characteristics—5 V Operation ............... 3
Changes to Electrical Characteristics—3 V Operation ............... 5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation............................................................................ 7
Changes to DIN EN 60747-5-2 (VDE 0884 Part 2)
Insulation Characteristics Title..................................................... 11
Changes to the Ordering Guide.................................................... 19
5/04—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changes to the Features....................................................................1
Changes to Table 7 and Table 8 .................................................... 14
Changes to Table 9.......................................................................... 15
Changes to the DC Correctness and Magnetic Field Immunity
Section.............................................................................................. 20
Changes to the Power Consumption Section ............................. 21
Changes to the Ordering Guide ................................................... 22
9/03—Revision 0: Initial Version.
Rev. D | Page 2 of 24
ADuM1400/ADuM1401/ADuM1402
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION1
4.5 V ≤ V
otherwise noted; all typical specifications are at T
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I
ADuM1400, Total Supply Current, Four Channels2
ADuM1401, Total Supply Current, Four Channels2
ADuM1402, Total Supply Current, Four Channels2
For All Models
≤ 5.5 V, 4.5 V ≤ V
DD1
≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless
DD2
= 25°C, V
A
DDI (Q)
DDO (Q)
= V
DD2
= 5 V.
DD1
0.50 0.53 mA
0.19 0.21 mA
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
2.2 2.8 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.9 1.4 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
8.6 10.6 mA 5 MHz logic signal freq.
DD1 (10)
2.6 3.5 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
70 100 mA 45 MHz logic signal freq.
DD1 (90)
18 25 mA 45 MHz logic signal freq.
DD2 (90)
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
1.8 2.4 mA DC to 1 MHz logic signal freq.
DD1 (Q)
1.2 1.8 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
7.1 9.0 mA 5 MHz logic signal freq.
DD1 (10)
4.1 5.0 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
57 82 mA 45 MHz logic signal freq.
DD1 (90)
31 43 mA 45 MHz logic signal freq.
DD2 (90)
DC to 2 Mbps
V
or V
DD1
Supply Current I
DD2
DD1 (Q)
, I
1.5 2.1 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
or V
DD1
Supply Current I
DD2
DD1 (10)
, I
5.6 7.0 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
or V
DD1
Supply Current I
DD2
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic Low Output Voltages
DD1 (90)
, IIB, IIC,
I
IA
I
, IE1, I
ID
VIH, V
VIL, V
V
OAH
V
OCH
V
OAL
V
OCL
, V
, V
, V
, V
EH
EL
, I
44 62 mA 45 MHz logic signal freq.
DD2 (90)
−10 +0.01 +10 μA
E2
2.0 V
0.8 V
V
, V
OBH
ODH
OBL
ODL
,
,
− 0.1 5.0 V IOx = −20 μA, VIx = V
DD1
DD2
V
, V
− 0.4 4.8 V IOx = −4 mA, VIx = V
DD1
DD2
0.0 0.1 V IOx = 20 μA, VIx = V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
0 ≤ V
0 ≤ V
IA
E1
, VIB, VIC, VID ≤ V
, VE2 ≤ V
DD1
or V
IxH
IxL
IxL
or V
DD1
DD2
Logic High Output Voltages
IxH
,
DD2
IxL
Rev. D | Page 3 of 24
ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Propagation Delay Skew6 t
Channel-to-Channel Matching7 t
ADuM140xBRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
ADuM140xCRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
8
8
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 I
Output Dynamic Supply Current per Channel9 I
, t
50 65 100 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 40 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels
PSK
50 ns CL = 15 pF, CMOS signal levels
PSKCD/OD
, t
20 32 50 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 3 ns CL = 15 pF, CMOS signal levels
15 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
6 ns CL = 15 pF, CMOS signal levels
PSKOD
, t
18 27 32 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
10 ns CL = 15 pF, CMOS signal levels
PSK
2 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
5 ns CL = 15 pF, CMOS signal levels
PSKOD
t
, t
PHZ
PLH
, t
t
PZH
PZL
| 25 35 kV/μs
|CM
H
6 8 ns CL = 15 pF, CMOS signal levels
6 8 ns CL = 15 pF, CMOS signal levels
= V
V
Ix
DD1/VDD2
, VCM = 1000 V,
transient magnitude = 800 V
|CML| 25 35 kV/μs
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
0.19 mA/Mbps
DDI (D)
0.05 mA/Mbps
DDO (D)
Rev. D | Page 4 of 24
ADuM1400/ADuM1401/ADuM1402
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
t
is the magnitude of the worst-case difference in t
PSK
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
DD1
and V
supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
DD2
or t
that is measured between units at the same operating temperature, supply voltages, and output load
PHL
PLH
. CML is the maximum common-mode voltage slew rate
DD2
propagation delay is
PLH
Rev. D | Page 5 of 24
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—3 V OPERATION1
2.7 V ≤ V
otherwise noted; all typical specifications are at T
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I
ADuM1400, Total Supply Current, Four Channels2
ADuM1401, Total Supply Current, Four Channels2
ADuM1402, Total Supply Current, Four Channels2
For All Models
SWITCHING SPECIFICATIONS
ADuM140xARW
≤ 3.6 V, 2.7 V ≤ V
DD1
≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless
DD2
= 25°C, V
A
DDI (Q)
DDO (Q)
= V
DD1
= 3.0 V.
DD2
0.26 0.31 mA
0.11 0.14 mA
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
1.2 1.9 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.5 0.9 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
4.5 6.5 mA 5 MHz logic signal freq.
DD1 (10)
1.4 2.0 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
37 65 mA 45 MHz logic signal freq.
DD1 (90)
11 15 mA 45 MHz logic signal freq.
DD2 (90)
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
1.0 1.6 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.7 1.2 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
3.7 5.4 mA 5 MHz logic signal freq.
DD1 (10)
2.2 3.0 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
30 52 mA 45 MHz logic signal freq.
DD1 (90)
18 27 mA 45 MHz logic signal freq.
DD2 (90)
DC to 2 Mbps
V
or V
DD1
Supply Current I
DD2
DD1 (Q)
, I
0.9 1.5 mA DC to 1 MHz logic signal freq.
DD2 (Q)
10 Mbps (BRW and CRW Grades Only)
V
or V
DD1
Supply Current I
DD2
DD1 (10)
, I
3.0 4.2 mA 5 MHz logic signal freq.
DD2 (10)
90 Mbps (CRW Grade Only)
V
or V
DD1
Supply Current I
DD2
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic Low Output Voltages
DD1 (90)
, IIB, I
I
IA
I
, IE1, I
ID
VIH, V
VIL, V
V
OAH
V
OCH
V
OAL
V
OCL
, I
24 39 mA 45 MHz logic signal freq.
DD2 (90)
−10 +0.01 +10 μA
, V
, V
, V
, V
IC,
E2
EH
EL
OBL
ODL
1.6 V
0.4 V
V
, V
,
OBH
ODH
V
0.0 0.1 V IOx = 20 μA, VIx = V
,
0.04 0.1 V IOx = 400 μA, VIx = V
− 0.1 3.0 V IOx = −20 μA, VIx = V
DD1
DD2
, V
− 0.4 2.8 V IOx = −4 mA, VIx = V
DD1
DD2
0.2 0.4 V I
, VIB, VIC, VID ≤ V
0 ≤ V
IA
0 ≤ V
E1,VE2
= 4 mA, VIx = V
Ox
≤ V
DD1
or V
IxH
IxL
IxL
or V
DD1
DD2
DD2
Logic High Output Voltages
IxH
IxL
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Propagation Delay Skew6 t
Channel-to-Channel Matching7 t
, t
50 75 100 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 40 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels
PSK
50 ns CL = 15 pF, CMOS signal levels
PSKCD/OD
,
Rev. D | Page 6 of 24
ADuM1400/ADuM1401/ADuM1402
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM140xBRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
ADuM140xCRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse Width Distortion, |t
PLH
− t
PHL
5
|
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
8
8
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel9 I
Output Dynamic Supply Current per Channel9 I
1
All voltages are relative to their respective ground.
2
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the V
6
t
is the magnitude of the worst-case difference in t
PSK
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
DD1
and V
supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
DD2
signal to the 50% level of the rising edge of the VOx signal.
Ix
or t
PHL
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
O
, t
20 38 50 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 3 ns CL = 15 pF, CMOS signal levels
22 ns CL = 15 pF, CMOS signal levels
PSK
3 ns CL = 15 pF, CMOS signal levels
t
PSKCD
t
6 ns CL = 15 pF, CMOS signal levels
PSKOD
, t
20 34 45 ns CL = 15 pF, CMOS signal levels
PHL
PLH
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
16 ns CL = 15 pF, CMOS signal levels
PSK
2 ns CL = 15 pF, CMOS signal levels
t
PSKCD
5 ns CL = 15 pF, CMOS signal levels
t
PSKOD
, t
t
PHZ
PLH
, t
t
PZH
PZL
| 25 35 kV/μs
|CM
H
6 8 ns CL = 15 pF, CMOS signal levels
6 8 ns CL = 15 pF, CMOS signal levels
= V
V
Ix
DD1/VDD2
, VCM = 1000 V,
transient magnitude = 800 V
|CML| 25 35 kV/μs
= 0 V, VCM = 1000 V,
V
Ix
transient magnitude = 800 V
0.10 mA/Mbps
DDI (D)
0.03 mA/Mbps
DDO (D)
propagation delay is
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Rev. D | Page 7 of 24
ADuM1400/ADuM1401/ADuM1402
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V ≤ V
specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
V
= 3.0 V, V
DD1
= 5 V or V
DD2
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
5 V/3 V Operation 0.50 0.53 mA
3 V/5 V Operation 0.26 0.31 mA
Output Supply Current per Channel, Quiescent I
5 V/3 V Operation 0.11 0.14 mA
3 V/5 V Operation 0.19 0.21 mA
ADuM1400, Total Supply Current, Four Channels2
DC to 2 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq.
3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
V
Supply Current I
DD1
5 V/3 V Operation 70 100 mA 45 MHz logic signal freq.
3 V/5 V Operation 37 65 mA 45 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 11 15 mA 45 MHz logic signal freq.
3 V/5 V Operation 18 25 mA 45 MHz logic signal freq.
ADuM1401, Total Supply Current, Four Channels2
DC to 2 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
Supply Current I
DD1
5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.
≤ 5.5 V, 2.7 V ≤ V
DD1
= 5 V, V
DD1
DD2
= 3.0 V.
≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V
DD2
DDI (Q)
DDO (Q)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
DD1 (90)
DD2 (90)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
≤ 3.6 V, 4.5 V ≤ V
DD1
≤ 5.5 V; all min/max
DD2
= 25°C;
A
Rev. D | Page 8 of 24
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