ANALOG DEVICES ADUM 1401 ARW Datasheet

Quad-Channel Digital Isolators

FEATURES

Automotive versions qualified per AEC-Q100 Low power operation

5 V operation

1.0 mA per channel maximum @ 0 Mbps to 2 Mbps

3.5 mA per channel maximum @ 10 Mbps 31 mA per channel maximum @ 90 Mbps

3 V operation

0.7 mA per channel maximum @ 0 Mbps to 2 Mbps

2.1 mA per channel maximum @ 10 Mbps

20 mA per channel maximum @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body package RoHS-compliant models available Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V

= 560 V peak

IORM

TÜV approval: IEC/EN/UL/CSA 61010-1

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Automotive systems

FUNCTIONAL BLOCK DIAGRAMS

V

GND

DD1

V

1 2

1

3

V

IA

4

IB

5

V

IC

6

V

ID

7

NC

8

1

ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

03786-001

Figure 1. ADuM1400

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

V

GND

V

GND

DD1

V

1 2

1

3

V

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

DECODE ENCODE

OD

7

E1

8

1

Figure 2. ADuM1401

ADuM1400/ADuM1401/ADuM1402

GENERAL DESCRIPTION

The ADuM140x1 are quad-channel digital isolators based on Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives, such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics.

The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth of the power of optocouplers at comparable signal data rates.

The ADuM140x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM140x provides low pulse width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM140x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the supplies.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.

Other patents are pending.

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

V

E2

9

GND

2

03786-002

V

GND

V V

GND

DD1

V

1 2

1

3

V

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

OC

6

DECODE ENCODE

OD

7

E1

8

1

16

V

DD2

15

GND

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

V

E2

9

GND

Figure 3. ADuM1402

2

03786-003

ADuM1400/ADuM1401/ADuM1402

REVISION HISTORY

5/08—Rev. F to Rev. G

Added ADuM1400W, ADuM1401W, and ADuM1402W

Parts ..................................................................................... Universal

Added Table 4 .................................................................................. 11

Added Table 5 .................................................................................. 13

Added Table 6 .................................................................................. 15

Added Table 7 .................................................................................. 17

Changes to Table 12 ........................................................................ 20

Changes to Table 13 ........................................................................ 21

Added Automotive Products Section ........................................... 29

Changes to Ordering Guide ........................................................... 30

11/07—Rev. E to Rev. F

Changes to Note 1 ............................................................................. 1

Added ADuM140xARW Change vs. Temperature Parameter ... 4 Added ADuM140xARW Change vs. Temperature Parameter ... 5 Added ADuM140xARW Change vs. Temperature Parameter ... 8

Changes to Figure 17 ...................................................................... 18

6/07—Rev. D to Rev. E

Updated VDE Certification Throughout ....................................... 1

Changes to Features and Note 1 ...................................................... 1

Changes to Figure 1, Figure 2, and Figure 3 .................................. 1

Changes to Regulatory Information Section ............................... 10

Changes to Table 7 .......................................................................... 11

Added Table 10 ................................................................................ 12

Added Insulation Lifetime Section ............................................... 20

Updated Outline Dimensions ........................................................ 21

Changes to Ordering Guide ........................................................... 21

2/06—Rev. C to Rev. D

Updated Format ................................................................. Universal

Added TÜV Approval ....................................................... Universal

5/05—Rev. B to Rev. C

Changes to Format ............................................................. Universal

Changes to Figure 2 .......................................................................... 1

Changes to Table 3 ............................................................................ 8

Changes to Table 6 .......................................................................... 12

Changes to Ordering Guide ........................................................... 21

6/04—Rev. A to Rev. B

Changes to Format ............................................................. Universal

Changes to Features .......................................................................... 1

Changes to Electrical Characteristics—5 V Operation ................ 3

Changes to Electrical Characteristics—3 V Operation ................ 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5

V Operation ....................................................................................... 7

Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics Title ........................................................................ 11

Changes to the Ordering Guide .................................................... 19

5/04—Rev. 0 to Rev. A

Updated Format ................................................................. Universal

Changes to the Features.................................................................... 1

Changes to Table 7 and Table 8 ..................................................... 14

Changes to Table 9 .......................................................................... 15

Changes to the DC Correctness and Magnetic Field Immunity

Section .............................................................................................. 20

Changes to the Power Consumption Section .............................. 21

Changes to the Ordering Guide .................................................... 22

9/03—Revision 0: Initial Version

Rev. G | Page 3 of 32

ADuM1400/ADuM1401/ADuM1402

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION1

4.5 V ≤ V unless otherwise noted; all typical specifications are at T ADuM1401W, and ADuM1402W automotive grade versions.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1400 Total Supply Current, Four Channels

ADuM1401 Total Supply Current, Four Channels

ADuM1402 Total Supply Current, Four Channels

For All Models

SWITCHING SPECIFICATIONS

ADuM140xARW

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.50 0.53 mA

DDI (Q)

0.19 0.21 mA

DDO (Q)

2

DD1

= V

= 5 V. These specifications do not apply to ADuM1400W,

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.9 1.4 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

8.6 10.6 mA 5 MHz logic signal freq.

DD1 (10)

2.6 3.5 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

70 100 mA 45 MHz logic signal freq.

DD1 (90)

18 25 mA 45 MHz logic signal freq.

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.8 2.4 mA DC to 1 MHz logic signal freq.

DD1 (Q)

1.2 1.8 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

7.1 9.0 mA 5 MHz logic signal freq.

DD1 (10)

4.1 5.0 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

57 82 mA 45 MHz logic signal freq.

DD1 (90)

31 43 mA 45 MHz logic signal freq.

DD2 (90)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

1.5 2.1 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

or V

DD1

Supply Current I

DD2

DD1 (10)

, I

5.6 7.0 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

or V

DD1

Supply Current I

DD2

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

DD1 (90)

, IE1, I

I

ID

VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

, V , V

EH

EL

, I

E2

OBH

ODH

OBL

ODL

44 62 mA 45 MHz logic signal freq.

DD2 (90)

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ V

2.0 V

0.8 V

,

(V

or V

DD1

(V

DD1

,

0.0 0.1 V IOx = 20 μA, VIx = V

) − 0.1 5.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

Minimum Pulse Width Maximum Data Rate Propagation Delay

3

PW 1000 ns C

4

5

1 Mbps CL = 15 pF, CMOS signal levels t

, t

50 65 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

DD1

IxL

or V

IxH

IxL

DD1

DD2

, VE2 ≤ V

0 V ≤ V

E1

= 15 pF, CMOS signal levels

L

or V

DD2

,

Rev. G | Page 4 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t

PLH

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew

6

Channel-to-Channel Matching

ADuM140xBRW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

3

4

5

PLH

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

6

7

ADuM140xCRW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

3

4

5

PLH

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

6

7

For All Models

Output Disable Propagation Delay (High/Low

to High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic

High Output Common-Mode Transient Immunity at Logic

Low Output

8

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel Output Dynamic Supply Current per Channel

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See F through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through

igure 8

for total V

Figure 15

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

igure 10

and V

DD1

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

5

− t

|

PHL

t

7

5

− t

|

PHL

5

− t

|

PHL

9

I

9

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

PW 100 ns CL = 15 pF, CMOS signal levels 10 Mbps CL = 15 pF, CMOS signal levels t

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

t

15 ns CL = 15 pF, CMOS signal levels

PSK

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels 90 120 Mbps CL = 15 pF, CMOS signal levels t

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

t

10 ns CL = 15 pF, CMOS signal levels

PSK

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

t

, t

PZH

PZL

|CMH| 25 35 kV/μs VIx = V

6 8 ns CL = 15 pF, CMOS signal levels

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.19 mA/Mbps

DDI (D)

I

0.05 mA/Mbps

DDO (D)

Power Consumption

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 8

Power Consumption

igure 11

propagation delay is

PLH

Figure 10

Rev. G | Page 5 of 32

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION1

2.7 V ≤ V unless otherwise noted; all typical specifications are at T ADuM1401W, and ADuM1402W automotive grade versions.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1400 Total Supply Current, Four Channels

ADuM1401 Total Supply Current, Four Channels

ADuM1402 Total Supply Current, Four Channels

For All Models

SWITCHING SPECIFICATIONS

ADuM140xARW

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.26 0.31 mA

DDI (Q)

0.11 0.14 mA

DDO (Q)

2

DD1

= V

= 3.0 V. These specifications do not apply to ADuM1400W,

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.2 1.9 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.5 0.9 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

4.5 6.5 mA 5 MHz logic signal freq.

DD1 (10)

1.4 2.0 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

37 65 mA 45 MHz logic signal freq.

DD1 (90)

11 15 mA 45 MHz logic signal freq.

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.6 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.7 1.2 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

3.7 5.4 mA 5 MHz logic signal freq.

DD1 (10)

2.2 3.0 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

30 52 mA 45 MHz logic signal freq.

DD1 (90)

18 27 mA 45 MHz logic signal freq.

DD2 (90)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

0.9 1.5 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

or V

DD1

Supply Current I

DD2

DD1 (10)

, I

3.0 4.2 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

or V

DD1

Supply Current I

DD2

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

3

PW 1000 ns C

4

5

− t

|

PLH

PHL

, I

DD1 (90)

, IE1, I

I

ID

VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

24 39 mA 45 MHz logic signal freq.

DD2 (90)

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ V

E1

= 20 μA, VIx = V

Ox

, V , V

E2

EH

EL

1.6 V

0.4 V

,

(V

or V

OBH

ODH

OBL

ODL

DD1

(V

DD1

0.0 0.1 V I

,

0.04 0.1 V IOx = 400 μA, VIx = V

) − 0.1 3.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V

= 15 pF, CMOS signal levels

L

, VE2 ≤ V

DD1

IxL

or V

IxH

IxL

DD1

DD2

1 Mbps CL = 15 pF, CMOS signal levels t

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching

6

t

7

50 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

or V

DD2

,

Rev. G | Page 6 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xBRW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

ADuM140xCRW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

For All Models

Output Disable Propagation Delay (High/Low to

High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity at Logic

High Output

Common-Mode Transient Immunity at Logic

Low Output Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel

Output Dynamic Supply Current per Channel

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See F through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through

igure 8

for total V

Figure 15

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

DD1

3

4

5

PLH

6

7

3

4

5

PLH

6

7

8

5

− t

|

PHL

5

− t

|

PHL

PW 100 ns CL = 15 pF, CMOS signal levels 10 Mbps CL = 15 pF, CMOS signal levels t

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

t

22 ns CL = 15 pF, CMOS signal levels

PSK

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels 90 120 Mbps CL = 15 pF, CMOS signal levels t

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

t

16 ns CL = 15 pF, CMOS signal levels

PSK

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

t

, t

PZH

PZL

6 8 ns CL = 15 pF, CMOS signal levels

|CMH| 25 35 kV/μs VIx = V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

9

I

0.10 mA/

DDI (D)

I

0.03 mA/

DDO (D)

igure 10

and V

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

or V

DD1

transient magnitude = 800 V

Mbps

Power Consumption

Figure 8

, VCM = 1000 V,

DD2

igure 11

propagation delay is

PLH

Figure 10

Rev. G | Page 7 of 32

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION1

5 V/3 V operation: 4.5 V ≤ V minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

and ADuM1402W automotive grade versions.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA

ADuM1400 Total Supply Current, Four Channels

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 70 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 37 65 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 18 25 mA 45 MHz logic signal freq.

ADuM1401 Total Supply Current, Four Channels

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

2

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

= 5 V, V

DD1

DDI (Q)

DDO (Q)

= 3.0 V. These specifications do not apply to ADuM1400W, ADuM1401W,

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

≤ 5.5 V; all

DD2

Rev. G | Page 8 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 57 82 mA 45 MHz logic signal freq.

3 V/5 V Operation 30 52 mA 45 MHz logic signal freq. V

Supply Current I

DD2

5 V/3 V Operation 18 27 mA 45 MHz logic signal freq.

3 V/5 V Operation 31 43 mA 45 MHz logic signal freq.

ADuM1402 Total Supply Current, Four Channels

2

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. V

Supply Current I

DD2

5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq.

3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq. V

Supply Current I

DD2

5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq.

3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 44 62 mA 45 MHz logic signal freq.

3 V/5 V Operation 24 39 mA 45 MHz logic signal freq. V

Supply Current I

DD2

5 V/3 V Operation 24 39 mA 45 MHz logic signal freq.

3 V/5 V Operation 44 62 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

Logic High Input Threshold

5 V/3 V Operation 2.0 V

3 V/5 V Operation 1.6 V Logic Low Input Threshold

5 V/3 V Operation 0.8 V

3 V/5 V Operation 0.4 V Logic High Output Voltages V

Logic Low Output Voltages V

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

3

4

1 Mbps C

5

− t

|

PLH

PHL

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew Channel-to-Channel Matching

6

t

7

ADuM140xBRW

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

3

4

5

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

, IE1, I

I

ID

VIH, V

VIL, V

OAH

V

OCH

OAL

V

OCL

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC,VID ≤ V , 0 V ≤ VE1, VE2 ≤ V

E2

EH

EL

, V

,

or V or V

) − 0.1 (V

DD2

) − 0.4 (V

DD2

(V

OBH

, V

, V , V

DD1

ODH

(V

DD1

0.0 0.1 V I

OBL,

ODL

0.04 0.1 V IOx = 400 μA, VIx = V

DD1

or V

) V IOx = −20 μA, VIx = V

DD2

or V

) − 0.2 V IOx = −4 mA, VIx = V

DD2

V

DD2

= 20 μA, VIx = V

Ox

0.2 0.4 V IOx = 4 mA, VIx = V

or

DD1

or V

DD1

DD2

IxH

IxL

PW 1000 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

L

t

, t

50 70 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

PW 100 ns CL = 15 pF, CMOS signal levels

10 Mbps CL = 15 pF, CMOS signal levels

t

, t

15 35 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

Rev. G | Page 9 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

6

7

ADuM140xCRW

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

3

4

5

Pulse Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

6

7

For All Models

Output Disable Propagation Delay (High/Low

to High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at Logic

High Output

Common-Mode Transient Immunity at Logic

Low Output

8

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current per Channel

5 V/3 V Operation 0.19 mA/Mbps

3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current per Channel

5 V/3 V Operation 0.03 mA/Mbps

3 V/5 V Operation 0.05 mA/Mbps

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See F through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through

igure 8

for total V

Figure 15

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

igure 10

and V

DD1

DD2

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

PLH

5

− t

|

PHL

PWD 3 ns CL = 15 pF, CMOS signal levels

t

22 ns CL = 15 pF, CMOS signal levels

PSK

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels

90 120 Mbps CL = 15 pF, CMOS signal levels

t

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

t

14 ns CL = 15 pF, CMOS signal levels

PSK

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

t

, t

PZH

6 8 ns CL = 15 pF, CMOS signal levels

PLH

6 8 ns CL = 15 pF, CMOS signal levels

PZL

L

PLH

5

− t

|

PHL

|CMH| 25 35 kV/μs VIx = V

transient magnitude = 800 V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

9

I

DDI (D)

I

DDO (D)

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DD2

Figure 8

Power Consumption

= 15 pF, CMOS signal levels

or V

DD1

, VCM = 1000 V,

DD2

Power Consumption

igure 11

propagation delay is

PLH

Figure 10

Rev. G | Page 10 of 32

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION1

4.5 V ≤ V unless otherwise noted; all typical specifications are at T ADuM1401W, and ADuM1402W automotive grade versions.

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM1400W, Total Supply Current, Four Channels

ADuM1401W, Total Supply Current, Four Channels

ADuM1402W, Total Supply Current, Four Channels

For All Models

SWITCHING SPECIFICATIONS

ADuM140xWSRWZ

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.50 0.53 mA

DDI (Q)

0.19 0.21 mA

DDO (Q)

2

DD1

= V

= 5 V. These specifications apply to ADuM1400W,

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.9 1.4 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

8.6 10.6 mA 5 MHz logic signal freq.

DD1 (10)

2.6 3.5 mA 5 MHz logic signal freq.

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.8 2.4 mA DC to 1 MHz logic signal freq.

DD1 (Q)

1.2 1.8 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

7.1 9.0 mA 5 MHz logic signal freq.

DD1 (10)

4.1 5.0 mA 5 MHz logic signal freq.

DD2 (10)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

1.5 2.1 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

or V

DD1

Supply Current I

DD2

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

DD1 (10)

, IE1, I

I

ID

VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

, V

, V , V

, I

5.6 7.0 mA 5 MHz logic signal freq.

DD2 (10)

−10 +0.01 +10 μA 0 ≤ VIA, VIB, VIC, VID ≤ V

E2

EH

EL

OBL

ODL

2.0 V

0.8 V

,

(V

or V

OBH

ODH

DD1

(V

DD1

,

0.0 0.1 V IOx = 20 μA, VIx = V

) − 0.1 5.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

3

PW 1000 ns C

4

1 Mbps C

5

t

PLH

6

5

− t

|

PHL

t

7

t

, t

50 65 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

or V

DD1

or V

IxH

IxL

DD1

DD2

IxH

IxL

, VE2 ≤ V

0 ≤ V

E1

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

DD2

,

Rev. G | Page 11 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xWTRWZ

Minimum Pulse Width3 Maximum Data Rate4 Propagation Delay5 Pulse Width Distortion, |t

PLH

− t

PHL

5

|

PW 100 ns C 10 Mbps C

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew6 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

7

For All Models

Output Disable Propagation Delay (High/Low

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

to High Impedance)

Output Enable Propagation Delay (High

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

Impedance to High/Low Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic

High Output Common-Mode Transient Immunity at Logic

Low Output

8

|CM

| 25 35 kV/μs VIx = V

H

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel9 I Output Dynamic Supply Current per Channel9

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.

DD2

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.19 mA/Mbps

DDI (D)

0.05 mA/Mbps

I

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

, VCM = 1000 V,

DD1/VDD2

transient magnitude = 800 V

propagation delay is

PLH

Rev. G | Page 12 of 32

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION1

3.0 V ≤ V unless otherwise noted; all typical specifications are at T ADuM1401W, and ADuM1402W automotive grade versions.

Table 5.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM1400W, Total Supply Current, Four Channels

ADuM1401W, Total Supply Current, Four Channels

ADuM1402W, Total Supply Current, Four Channels

For All Models

SWITCHING SPECIFICATIONS

ADuM140xWSRWZ

≤ 3.6 V, 3.0 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.26 0.31 mA

DDI (Q)

0.11 0.14 mA

DDO (Q)

2

DD1

= V

= 3.0 V. These specifications apply to ADuM1400W,

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.2 1.9 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.5 0.9 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

4.5 6.5 mA 5 MHz logic signal freq.

DD1 (10)

1.4 2.0 mA 5 MHz logic signal freq.

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.6 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.7 1.2 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

3.7 5.4 mA 5 MHz logic signal freq.

DD1 (10)

2.2 3.0 mA 5 MHz logic signal freq.

DD2 (10)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

0.9 1.5 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

or V

DD1

Supply Current I

DD2

Input Currents IIA, IIB, I

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

DD1 (10)

, IE1, I

I

ID

VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

, I

3.0 4.2 mA 5 MHz logic signal freq.

DD2 (10)

−10 +0.01 +10 μA 0 ≤ VIA, VIB, VIC, VID ≤ V

IC,

E2

EH

EL

, V , V

1.6 V

0.4 V

,

(V

or V

OBH

ODH

OBL

ODL

DD1

(V

DD1

0.0 0.1 V I

,

0.04 0.1 V IOx = 400 μA, VIx = V

) − 0.1 3.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

3

PW 1000 ns C

4

1 Mbps C

5

t

PLH

6

5

− t

|

PHL

t

7

t

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

or V

DD1

or V

IxL

DD1

DD2

IxH

IxL

0 ≤ V

Ox

≤ V

E1,VE2

= 20 μA, VIx = V

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

DD2

,

Rev. G | Page 13 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xWTRWZ

Minimum Pulse Width3 Maximum Data Rate4 Propagation Delay5 Pulse Width Distortion, |t

PLH

− t

PHL

5

|

PW 100 ns C 10 Mbps C

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew6 Channel-to-Channel Matching, Codirectional

Channels Channel-to-Channel Matching, Opposing-

Directional Channels

7

For All Models

Output Disable Propagation Delay (High/Low

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

to High Impedance) Output Enable Propagation Delay (High

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity at Logic

High Output

Common-Mode Transient Immunity at Logic

Low Output

8

|CM

| 25 35 kV/μs VIx = V

H

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel9 I Output Dynamic Supply Current per Channel9

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.

DD2

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.10 mA/Mbps

DDI (D)

0.03 mA/Mbps

I

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

, VCM = 1000 V,

DD1/VDD2

transient magnitude = 800 V

propagation delay is

PLH

Rev. G | Page 14 of 32

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1

4.5 V ≤ V unless otherwise noted; all typical specifications are at T ADuM1401W, and ADuM1402W automotive grade versions.

Table 6.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM1400W, Total Supply Current, Four Channels

ADuM1401W, Total Supply Current, Four Channels

ADuM1402W, Total Supply Current, Four Channels

For All Models

SWITCHING SPECIFICATIONS

ADuM140xWSRWZ

≤ 5.5 V, 3.0 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C; V

A

0.50 0.53 mA

DDI (Q)

0.11 0.14 mA

DDO (Q)

2

= 5 V, V

DD1

= 3.0 V. These specifications apply to ADuM1400W,

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.5 0.9 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

8.6 10.6 mA 5 MHz logic signal freq.

DD1 (10)

1.4 2.0 mA 5 MHz logic signal freq.

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.8 2.4 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.7 1.2 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

7.1 9.0 mA 5 MHz logic signal freq.

DD1 (10)

2.2 3.0 mA 5 MHz logic signal freq.

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.5 2.1 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.9 1.5 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents IIA, IIB, IIC,

Logic High Input Threshold

5.6 7.0 mA 5 MHz logic signal freq.

DD1 (10)

3.0 4.2 mA 5 MHz logic signal freq.

DD2 (10)

−10 +0.01 +10 μA 0 ≤ VIA, VIB, VIC, VID ≤ V

, IE1, I

I

ID

E2

VIH, V

EH

5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input Threshold

VIL, V

EL

5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V

Logic High Output Voltages V

Logic Low Output Voltages V

, V

OAH

, V

V

OCH

, V

OAL

V

, V

OCL

(V

OBH

ODH

OBL,

ODL

,

or V or V

) − 0.1 V

DD2

) − 0.4 V

DD2

DD1

(V

DD1

or V

DD1

V IOx = −20 μA, VIx = V

DD2

, V

− 0.2 V IOx = −4 mA, VIx = V

DD2

0.0 0.1 V I

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

3

PW 1000 ns C

4

5

t

PLH

6

5

− t

|

PHL

t

7

t

1 Mbps CL = 15 pF, CMOS signal levels

, t

50 70 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

, 0 ≤ VE1,VE2 ≤ V

V

DD2

= 20 μA, VIx = V

Ox

= 15 pF, CMOS signal levels

L

DD1

or V

DD1

IxH

IxL

or

DD2

Rev. G | Page 15 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xWTRWZ

Minimum Pulse Width3 Maximum Data Rate4 Propagation Delay5 Pulse Width Distortion, |t

PLH

− t

PHL

5

|

PW 100 ns C 10 Mbps C

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew6 Channel-to-Channel Matching, Codirectional

Channels Channel-to-Channel Matching, Opposing-

Directional Channels

7

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

For All Models

Output Disable Propagation Delay (High/Low

t

PHZ

, t

PLH

6 8 ns CL = 15 pF, CMOS signal levels

to High Impedance)

Output Enable Propagation Delay (High

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic

High Output Common-Mode Transient Immunity at Logic

Low Output

8

|CM

| 25 35 kV/μs VIx = V

H

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel9 I Output Dynamic Supply Current per Channel9

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.

DD2

or t

PHL

0.19 mA/Mbps

DDI (D)

0.03 mA/Mbps

I

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

, VCM = 1000 V,

DD1/VDD2

transient magnitude = 800 V

propagation delay is

PLH

Rev. G | Page 16 of 32

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION1

3.0 V ≤ V unless otherwise noted; all typical specifications are at T ADuM1401W, and ADuM1402W automotive grade versions.

Table 7.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

Output Supply Current per Channel, Quiescent I

ADuM1400W, Total Supply Current, Four Channels

ADuM1401W, Total Supply Current, Four Channels

ADuM1402W, Total Supply Current, Four Channels

For All Models

SWITCHING SPECIFICATIONS

ADuM140xWSRWZ

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C; V

A

0.26 0.31 mA

DDI (Q)

0.19 0.21 mA

DDO (Q)

2

= 3.0 V, V

DD1

= 5 V. These specifications apply to ADuM1400W,

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.2 1.9 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.9 1.4 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

4.5 6.5 mA 5 MHz logic signal freq.

DD1 (10)

2.6 3.5 mA 5 MHz logic signal freq.

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.6 mA DC to 1 MHz logic signal freq.

DD1 (Q)

1.2 1.8 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

3.7 5.4 mA 5 MHz logic signal freq.

DD1 (10)

4.1 5.0 mA 5 MHz logic signal freq.

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

0.9 1.5 mA DC to 1 MHz logic signal freq.

DD1 (Q)

1.5 2.1 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (TRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

3.0 4.2 mA 5 MHz logic signal freq.

DD1 (10)

5.6 7.0 mA 5 MHz logic signal freq.

DD2 (10)

−10 +0.01 +10 μA 0 ≤ VIA, VIB, VIC, VID ≤ V

, IE1, I

I

ID

E2

VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

EH

EL

, V

, V , V

1.6 V

0.4 V

,

or V or V

) − 0.1 V

DD2

) − 0.4 V

DD2

(V

OBH

ODH

OBL

ODL

DD1

(V

DD1

,

0.0 0.1 V I

0.04 0.1 V IOx = 400 μA, VIx = V

V IOx = −20 μA, VIx = V

DD1, VDD2

, V

− 0.2 V IOx = −4 mA, VIx = V

DD1

DD2

0.2 0.4 V IOx = 4 mA, VIx = V

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

3

4

1 Mbps C

5

t

5

− t

|

PLH

PHL

6

t

7

t

PW 1000 ns CL = 15 pF, CMOS signal levels

, t

50 70 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

DD1

or V

IxH

IxL

DD1

DD2

, VE2 ≤ V

0 ≤ V

E1

= 20 μA, VIx = V

Ox

= 15 pF, CMOS signal levels

L

or V

DD2

,

Rev. G | Page 17 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xWTRWZ

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

For All Models

Output Disable Propagation Delay (High/Low

to High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic

High Output Common-Mode Transient Immunity at Logic

Low Output Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel Output Dynamic Supply Current per Channel

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See F through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through

igure 8

for total V

Figure 15

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

8

igure 10

and V

DD1

3

4

5

6

7

PLH

5

− t

|

PHL

PW 100 ns CL = 15 pF, CMOS signal levels

10 Mbps CL = 15 pF, CMOS signal levels

t

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

t

22 ns CL = 15 pF, CMOS signal levels

PSK

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

t

, t

PZH

PZL

6 8 ns CL = 15 pF, CMOS signal levels

|CMH| 25 35 kV/μs VIx = V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient

9

I

9

supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.

DD2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.10 mA/Mbps

DDI (D)

I

0.05 mA/Mbps

DDO (D)

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 8

Power Consumption

, VCM = 1000 V,

DD1/VDD2

transient magnitude = 800 V

magnitude = 800 V

igure 11

propagation delay is

PLH

Figure 10

Rev. G | Page 18 of 32

ADuM1400/ADuM1401/ADuM1402

PACKAGE CHARACTERISTICS

Table 8.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output) Capacitance (Input-to-Output) Input Capacitance

2

C

IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ

1

Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,

Pin 15, and Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM140x are approved by the organizations listed in Tabl e 9. Refer to Tabl e 14 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 9.

UL CSA VDE TÜV

Recognized under 1577 Component Recognition Program

Double/reinforced insulation, 2500 V rms isolation voltage

File E214100 File 205078 File 2471900-4880-0001 Certificate U8V 05 06 56232 002

1

In accordance with UL 1577, each ADuM140x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).

2

In accordance with DIN V VDE V 0884-10, each ADuM140x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection

1

limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

1

R

1

C

Approved under CSA Component Acceptance Notice #5A

Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage

Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage

1012 Ω

I-O

2.2 pF f = 1 MHz

I-O

4.0 pF

I

33 °C/W

JCI

28 °C/W

JCO

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

2

Thermocouple located at center of package underside

Approved according to: IEC 61010-1:2001 (2 EN 61010-1:2001 (2 UL 61010-1:2004 CSA C22.2.61010.1:2005

Reinforced insulation, 560 V peak

Reinforced insulation, 400 V rms maximum working voltage

nd

Edition),

nd

Edition)

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 10.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. G | Page 19 of 32

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

ADuM1400/ADuM1401/ADuM1402

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval.

Table 11.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method B1

× 1.875 = VPR, 100% production test, tm = 1 sec,

V

IORM

partial discharge < 5 pC

Input-to-Output Test Voltage, Method A V

× 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR

IORM

After Environmental Tests Subgroup 1 896 V peak

× 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak

After Input and/or Safety Test Subgroup 2

V

IORM

and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak Safety-Limiting Values

Maximum value allowed in the event of a failure

(see Figure 4) Case Temperature TS 150 °C Side 1 Current IS1 265 mA Side 2 Current IS2 335 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

350

300

250

200

150

100

SAFETY-L IMITING CURRENT (mA)

50

0

SIDE #2

SIDE #1

50 100 150 200

CASE TEMPERAT URE (°C)

Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

03786-004

RECOMMENDED OPERATING CONDITIONS

Table 12.

Parameter Rating

Operating Temperature (TA) Operating Temperature (TA) Supply Voltages (V Supply Voltages (V Input Signal Rise and Fall Times 1.0 ms

1

Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive

grade versions.

2

Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade

versions.

3

All voltages are relative to their respective ground. See the

and Magnetic Field Immunity external magnetic fields.

, V

DD1

DD2

, V

DD1

DD2

section for information on immunity to

560 V peak

IORM

1050 V peak

V

PR

1

−40°C to +105°C

2

−40°C to +125°C

3

)1,

2.7 V to 5.5 V

2, 3

)

3.0 V to 5.5 V

DC Correctness

Rev. G | Page 20 of 32

ADuM1400/ADuM1401/ADuM1402

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 13.

Parameter Rating

Storage Temperature (TST) −65°C to +150°C Ambient Operating Temperature (TA)1 −40°C to +105°C Ambient Operating Temperature (TA)2 −40°C to +125°C Supply Voltages (V Input Voltage (VIA, VIB, VIC, VID, VE1, VE2) Output Voltage (VOA, VOB, VOC, VOD)

, V

)3 −0.5 V to +7.0 V

DD1

DD2

3, 4

−0.5 V to V

+ 0.5 V

DDI

+ 0.5 V

DDO

Average Output Current per Pin5

Side 1 (IO1) −18 mA to +18 mA Side 2 (IO2) −22 mA to +22 mA

Common-Mode Transients6 −100 kV/μs to +100 kV/μs

1

Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W

automotive grade versions.

2

Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade

versions.

3

All voltages are relative to their respective ground.

4

V

and V

DDI

given channel, respectively. See the PC Board Layout section.

5

See Figure 4 for maximum rated current values for various temperatures.

6

This refers to common-mode transients across the insulation barrier.

Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage.

refer to the supply voltages on the input and output sides of a

DDO

1

Table 14. Maximum Continuous Working Voltage

Parameter Max Unit Constraint

AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime AC Voltage, Unipolar Waveform

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

DC Voltage

Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation barrier. See the section for more details. Insulation Lifetime

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Table 15. Truth Table (Positive Logic)

VIx Input1VEx Input

1, 2

V

State1V

DDI

State1VOx Output1Notes

DDO

H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H Outputs return to the input state within 1 μs of V

power restoration.

DDI

X L Unpowered Powered Z X X Powered Unpowered Indeterminate

1

VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. V

V

refer to the supply voltages on the input and output sides of the given channel, respectively.

DDO

2

In noisy environments, connecting VEx to an external logic high or low is recommended.

Outputs return to the input state within 1 μs of V if the V within 8 ns of V

state is H or NC. Outputs return to a high impedance state

Ex

power restoration if the VEx state is L.

DDO

power restoration

DDO

Rev. G | Page 21 of 32

DDI

and

ADuM1400/ADuM1401/ADuM1402

*

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

V

DD1

2

*GND

1

V

3

IA

ADuM1400

V

4

IB

TOP VIEW

(Not to Scale)

5

V

IC

V

6

ID

NC

7 8

*GND

1

NC = NO CONNECT

PIN 2 AND PIN 8 ARE INTERNALLY CONNE CTED, AND CONNECT ING BOTH TO GND CONNECTED, AND CO NNE CTING BOT H T O GND

IS RECOMM ENDE D. PIN 9 AND PIN 15 ARE INTERNALLY

1

Figure 5. ADuM1400 Pin Configuration

Table 16. ADuM1400 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND 3 V

IA

1

Supply Voltage for Isolator Side 1. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 V

ID

Logic Input D. 7 NC No Connect. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2

Output Enable 2. Active high logic input. V

, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic

V

OA

, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.

OA

high or low is recommended. 11 V

OD

Logic Output D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2.

DD2

16

V

DD2

15

GND2* V

14

OA

V

13

OB

12

V

OC

V

11

OD

V

10

E2

9

GND2*

IS RECOMMENDED.

2

03786-005

Rev. G | Page 22 of 32

ADuM1400/ADuM1401/ADuM1402

1

V

DD1

*GND

2

1

V

3

IA

ADuM1401

4

V

IB

TOP VIEW

(Not to S cale)

V

5

IC

V

6

OD

7

V

E1

*GND

8

1

*PIN 2 AND PIN 8 ARE INTERNAL LY CONNECTED, AND CONNECTING

BOTH TO GND CONNECTED, AND CONNECTING BOT H TO GND

IS RECOMMENDE D. PIN 9 AND PIN 15 ARE INTERNALLY

1

Figure 6. ADuM1401 Pin Configuration

Table 17. ADuM1401 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND 3 V

IA

1

Supply Voltage for Isolator Side 1. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 V

OD

7 VE1

Logic Output D.

Output Enable 1. Active high logic input. V

V

is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.

E1

output is enabled when VE1 is high or disconnected. VOD is disabled when

OD

8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2

Output Enable 2. Active high logic input. V

, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or

V

OB

, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,

OA

low is recommended. 11 V

ID

Logic Input D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2.

DD2

16

V

DD2

GND2*

15

V

14

OA

13

V

OB

V

12

OC

V

11

ID

10

V

E2

GND2*

9

IS RECOMMENDE D.

2

03786-006

Rev. G | Page 23 of 32

ADuM1400/ADuM1401/ADuM1402

1

V

DD1

2

*GND

1

V

3

IA

ADuM1402

V

4

IB

TOP VIEW

(Not to Scale)

5

V

OC

V

6

OD

V

7

E1

8

*GND

1

*PIN 2 AND PIN 8 ARE INTERNAL LY CONNECTED, AND CONNECTING

BOTH TO GND CONNECTED, AND CONNE CTING BOT H TO GND

IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY

1

Figure 7. ADuM1402 Pin Configuration

Table 18. ADuM1402 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD1

2 GND 3 V

IA

1

Supply Voltage for Isolator Side 1. Ground 1. Ground reference for Isolator Side 1.

Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 V 7 VE1

OD

Logic Output D.

Output Enable 1. Active high logic input. V

outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is

V

OD

and VOD outputs are enabled when VE1 is high or disconnected. VOC and

OC

recommended. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2

Output Enable 2. Active high logic input. V

outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is

V

OB

and VOB outputs are enabled when VE2 is high or disconnected. VOA and

OA

recommended. 11 V

ID

Logic Input D. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 V

Supply Voltage for Isolator Side 2.

DD2

16

V

DD2

15

GND2* V

14

OA

V

13

OB

12

V

IC

V

11

ID

V

10

E2

9

GND2*

IS RECOMMENDE D.

2

03786-007

Rev. G | Page 24 of 32

ADuM1400/ADuM1401/ADuM1402

TYPICAL PERFORMANCE CHARACTERISTICS

20

80

70

15

10

5V

5

CURRENT/CHANNEL (mA)

0

20 60 8040 100

DATA RATE (Mb ps)

3V

Figure 8. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

6

5

4

3

2

CURRENT/CHANNEL (mA)

1

5V

3V

60

50

40

30

CURRENT (mA)

20

10

0

03786-008

Figure 11. Typical ADuM1400 V

5V

3V

20 60 8040 100

DATA RATE (Mb ps)

Supply Current vs. Data Rate

DD1

03786-011

for 5 V and 3 V Operation

20

15

10

CURRENT (mA)

5

5V

3V

0

20 60 8040 100

DATA RATE (Mb ps)

Figure 9. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

10

8

6

4

CURRENT/CHANNEL (mA)

2

0

5V

3V

20 60 8040 100

DATA RATE (Mb ps)

Figure 10. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

03786-009

03786-010

Rev. G | Page 25 of 32

0

20 60 8040 100

DATA RATE (Mb ps)

Figure 12. Typical ADuM1400 V

for 5 V and 3 V Operation

35

30

25

20

15

CURRENT (mA)

10

5

0

5V

20 60 8040 100

DATA RATE (Mb ps)

Figure 13. Typical ADuM1401 V

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD2

3V

Supply Current vs. Data Rate

DD1

03786-012

03786-013

ADuM1400/ADuM1401/ADuM1402

40

35

40

30

25

20

15

CURRENT (mA)

10

5

0

5V

20 60 8040 100

DATA RATE (Mb ps)

Figure 14. Typical ADuM1401 V

for 5 V and 3 V Operation

50

45

40

35

30

25

20

CURRENT (mA)

15

10

5

0

5V

20 60 8040 100

DATA RATE (Mb ps)

Figure 15. Typical ADuM1402 V

Data Rate for 5 V and 3 V Operation

3V

Supply Current vs. Data Rate

DD2

3V

or V

DD1

Supply Current vs.

DD2

35

30

PROPAGATION DELAY (ns)

25

–50 –25

03786-014

0507525 100

TEMPERATURE ( °C)

3V

5V

03786-016

Figure 16. Propagation Delay vs. Temperature, C Grade

03786-015

Rev. G | Page 26 of 32

ADuM1400/ADuM1401/ADuM1402

V

APPLICATIONS INFORMATION

PC BOARD LAYOUT

The ADuM140x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 17). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for V for V

. The capacitor value should be between 0.01 μF and

DD2

and between Pin 15 and Pin 16

DD1

0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered, unless the ground pair on each package side is connected close to the package.

V

DD1

GND

1

V

IA

V

IB

VIC/V

OC

V

ID/VOD

NC/V

E1

GND

1

Figure 17. Recommended Printed Circuit Board Layout

V

DD2

GND V

OA

V

OB

V

OC/VIC

V

OD/VID

V

E2

GND

2

3786-017

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the Absolute Maximum Ratings of the device, thereby leading to latch-up or permanent damage.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a Logic 0 output may differ from the propagation delay to a Logic 1 output.

INPUT (

)

Ix

OUTPUT (V

t

PLH

)

Ox

t

PHL

Figure 18. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM140x component.

Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM140x components operating under the same conditions.

50%

03786-018

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Tab le 1 5 ) by the watchdog timer circuit.

The limitation on the magnetic field immunity of the ADuM140x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM140x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt)

where:

β is magnetic flux density (gauss). N is the number of turns in the receiving coil. r

is the radius of the nth turn in the receiving coil (cm).

n

Given the geometry of the receiving coil in the ADuM140x and an imposed requirement that the induced voltage be 50% at most of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19.

100

10

1

0.1

DENSITY (kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FL UX

0.001 1k 10k 10M

Figure 19. Maximum Allowable External Magnetic Flux Density

2

∑∏r

; n = 1, 2, … , N

n

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

03786-019

Rev. G | Page 27 of 32

ADuM1400/ADuM1401/ADuM1402

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM140x transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM140x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM140x to affect the operation of the component.

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALL OWABLE CURRENT ( kA)

0.01 1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 20. Maximum Allowable Current

for Various Current-to-ADuM140x Spacings

03786-020

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM140x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

I

DDI

= I

× (2f − fr) + I

DDI (D)

DDI (Q)

For each output channel, the supply current is given by

I

DDO

= I

= (I

f ≤ 0.5 fr

DDO (Q)

+ (0.5 × 10−3) × CL × V

DDO (D)

) × (2f − fr) + I

DDO

where:

I

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

V

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz); it is half of the input

data rate expressed in units of Mbps.

f

is the input stage refresh rate (Mbps).

r

, I

I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

To calculate the total V

DD1

and V

supply current, the supply

DD2

currents for each input and output channel corresponding to V

DD1

and V

are calculated and totaled. Figure 8 and Figure 9

DD2

provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides perchannel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 provide total V

DD1

and V

supply current as a function of data rate for

DD2

ADuM1400/ADuM1401/ADuM1402 channel configurations.

f ≤ 0.5 fr

f > 0.5 fr

DDO (Q)

f > 0.5 fr

Rev. G | Page 28 of 32

ADuM1400/ADuM1401/ADuM1402

INSULATION LIFETIME

All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM140x.

Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Tabl e 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than a 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM140x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23 illustrate these different isolation voltage waveforms, respectively.

Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.

In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Tab le 1 4 can be applied while maintaining the 50-year minimum lifetime, provided the voltage

conforms to either the unipolar ac or dc voltage cases. Any crossinsulation voltage waveform that does not conform to Figure 22 or Figure 23 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 1 4.

Note that the voltage presented in Figure 22 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.

RATED PEAK VOL TAGE

0V

Figure 21. Bipolar AC Waveform

03786-021

RATED PEAK VOL TAGE

0V

Figure 22. Unipolar AC Waveform

03786-022

RATED PEAK VOL TAGE

0V

Figure 23. DC Waveform

03786-023

AUTOMOTIVE PRODUCTS

The ADuM1400W, ADuM1401W, and ADuM1402W products are qualified per AEC-Q100 for use in automotive applications. Custom variants of these products may be available to meet stringent automotive performance and quality requirements. For more information, contact your local Analog Devices sales representative.

Rev. G | Page 29 of 32

ADuM1400/ADuM1401/ADuM1402

C

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

Wide Body (RW-16)

Maximum Propagation Delay, 5 V (ns)

8° 0°

0.33 (0.0130)

0.20 (0.0079)

Maximum Pulse Width Distortion (ns)

5

(

0

.

0

2

9

5

.

7

.

2

5

(

0

)

0

9

8

)

.

1.27 (0.0500)

0.40 (0.0157)

0 0

Temperature Range

45°

032707-B

Package Description

Package Option

16

1

1.27 (0.0500)

0.30 (0.0 118)

0.10 (0.0039)

OPLANARITY

0.10

CONTROLL ING DIMENSIONS ARE IN MILLI METERS; I NCH DI M E NS IONS (IN PARENTHESES) ARE ROUNDED-OFF M ILLIM E TER EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DE SIGN.

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Number of Inputs,

Model

ADuM1400ARW ADuM1400BRW ADuM1400CRW

1

ADuM1400ARWZ ADuM1400BRWZ ADuM1400CRWZ ADuM1400WSRWZ ADuM1400WTRWZ ADuM1401ARW ADuM1401BRW ADuM1401CRW

1

ADuM1401ARWZ ADuM1401BRWZ ADuM1401CRWZ ADuM1401WSRWZ ADuM1401WTRWZ ADuM1402ARW ADuM1402BRW ADuM1402CRW

1

ADuM1402ARWZ ADuM1402BRWZ ADuM1402CRWZ ADuM1402WSRWZ ADuM1402WTRWZ

V

Side

DD1

4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

4 0 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16

1, 2

4 0 10 32 3 −40°C to +125°C 16-Lead SOIC_W RW-16 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

3 1 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16

1, 2

3 1 10 32 3 −40°C to +125°C 16-Lead SOIC_W RW-16 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16

1, 2

2 2 1 100 40 −40°C to +125°C 16-Lead SOIC_W RW-16

1, 2

2 2 10 32 3 −40°C to +125°C 16-Lead SOIC_W RW-16 EVAL-ADuM1402EBA 2 2 1 100 40 Evaluation Board EVAL-ADuM1402EBB 2 2 10 50 3 Evaluation Board EVAL-ADuM1402EBC 2 2 90 32 2 Evaluation Board

1

Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.

2

Z = RoHS Compliant Part.

Number of Inputs, V

Side

DD2

Maximum Data Rate (Mbps)

Rev. G | Page 30 of 32

ADuM1400/ADuM1401/ADuM1402

NOTES

Rev. G | Page 31 of 32

ADuM1400/ADuM1401/ADuM1402

NOTES

Rev. G | Page 32 of 32

ANALOG DEVICES ADUM 1401 ARW Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

INSULATION LIFETIME

AUTOMOTIVE PRODUCTS

OUTLINE DIMENSIONS

ORDERING GUIDE