ANALOG DEVICES ADUM 1401 ARW Datasheet

Quad-Channel Digital Isolators

FEATURES

Automotive versions qualified per AEC-Q100 Low power operation

5 V operation

1.0 mA per channel maximum @ 0 Mbps to 2 Mbps

3.5 mA per channel maximum @ 10 Mbps 31 mA per channel maximum @ 90 Mbps

3 V operation

0.7 mA per channel maximum @ 0 Mbps to 2 Mbps

2.1 mA per channel maximum @ 10 Mbps

20 mA per channel maximum @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body package RoHS-compliant models available Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V

= 560 V peak

IORM

TÜV approval: IEC/EN/UL/CSA 61010-1

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Automotive systems

FUNCTIONAL BLOCK DIAGRAMS

V

GND

DD1

V

1 2

1

3

V

IA

4

IB

5

V

IC

6

V

ID

7

NC

8

1

ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

03786-001

Figure 1. ADuM1400

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

V

GND

V

GND

DD1

V

1 2

1

3

V

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

DECODE ENCODE

OD

7

E1

8

1

Figure 2. ADuM1401

ADuM1400/ADuM1401/ADuM1402

GENERAL DESCRIPTION

The ADuM140x1 are quad-channel digital isolators based on Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives, such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics.

The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth of the power of optocouplers at comparable signal data rates.

The ADuM140x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM140x provides low pulse width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM140x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the supplies.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.

Other patents are pending.

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

V

ID

10

V

E2

9

GND

2

03786-002

V

GND

V V

GND

DD1

V

1 2

1

3

V

ENCODE DECODE

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

OC

6

DECODE ENCODE

OD

7

E1

8

1

16

V

DD2

15

GND

14

V

OA

13

V

OB

12

V

IC

11

V

ID

10

V

E2

9

GND

Figure 3. ADuM1402

2

03786-003

ADuM1400/ADuM1401/ADuM1402

REVISION HISTORY

5/08—Rev. F to Rev. G

Added ADuM1400W, ADuM1401W, and ADuM1402W

Parts ..................................................................................... Universal

Added Table 4 .................................................................................. 11

Added Table 5 .................................................................................. 13

Added Table 6 .................................................................................. 15

Added Table 7 .................................................................................. 17

Changes to Table 12 ........................................................................ 20

Changes to Table 13 ........................................................................ 21

Added Automotive Products Section ........................................... 29

Changes to Ordering Guide ........................................................... 30

11/07—Rev. E to Rev. F

Changes to Note 1 ............................................................................. 1

Added ADuM140xARW Change vs. Temperature Parameter ... 4 Added ADuM140xARW Change vs. Temperature Parameter ... 5 Added ADuM140xARW Change vs. Temperature Parameter ... 8

Changes to Figure 17 ...................................................................... 18

6/07—Rev. D to Rev. E

Updated VDE Certification Throughout ....................................... 1

Changes to Features and Note 1 ...................................................... 1

Changes to Figure 1, Figure 2, and Figure 3 .................................. 1

Changes to Regulatory Information Section ............................... 10

Changes to Table 7 .......................................................................... 11

Added Table 10 ................................................................................ 12

Added Insulation Lifetime Section ............................................... 20

Updated Outline Dimensions ........................................................ 21

Changes to Ordering Guide ........................................................... 21

2/06—Rev. C to Rev. D

Updated Format ................................................................. Universal

Added TÜV Approval ....................................................... Universal

5/05—Rev. B to Rev. C

Changes to Format ............................................................. Universal

Changes to Figure 2 .......................................................................... 1

Changes to Table 3 ............................................................................ 8

Changes to Table 6 .......................................................................... 12

Changes to Ordering Guide ........................................................... 21

6/04—Rev. A to Rev. B

Changes to Format ............................................................. Universal

Changes to Features .......................................................................... 1

Changes to Electrical Characteristics—5 V Operation ................ 3

Changes to Electrical Characteristics—3 V Operation ................ 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5

V Operation ....................................................................................... 7

Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics Title ........................................................................ 11

Changes to the Ordering Guide .................................................... 19

5/04—Rev. 0 to Rev. A

Updated Format ................................................................. Universal

Changes to the Features.................................................................... 1

Changes to Table 7 and Table 8 ..................................................... 14

Changes to Table 9 .......................................................................... 15

Changes to the DC Correctness and Magnetic Field Immunity

Section .............................................................................................. 20

Changes to the Power Consumption Section .............................. 21

Changes to the Ordering Guide .................................................... 22

9/03—Revision 0: Initial Version

Rev. G | Page 3 of 32

ADuM1400/ADuM1401/ADuM1402

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION1

4.5 V ≤ V unless otherwise noted; all typical specifications are at T ADuM1401W, and ADuM1402W automotive grade versions.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1400 Total Supply Current, Four Channels

ADuM1401 Total Supply Current, Four Channels

ADuM1402 Total Supply Current, Four Channels

For All Models

SWITCHING SPECIFICATIONS

ADuM140xARW

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.50 0.53 mA

DDI (Q)

0.19 0.21 mA

DDO (Q)

2

DD1

= V

= 5 V. These specifications do not apply to ADuM1400W,

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

2.2 2.8 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.9 1.4 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

8.6 10.6 mA 5 MHz logic signal freq.

DD1 (10)

2.6 3.5 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

70 100 mA 45 MHz logic signal freq.

DD1 (90)

18 25 mA 45 MHz logic signal freq.

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.8 2.4 mA DC to 1 MHz logic signal freq.

DD1 (Q)

1.2 1.8 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

7.1 9.0 mA 5 MHz logic signal freq.

DD1 (10)

4.1 5.0 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

57 82 mA 45 MHz logic signal freq.

DD1 (90)

31 43 mA 45 MHz logic signal freq.

DD2 (90)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

1.5 2.1 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

or V

DD1

Supply Current I

DD2

DD1 (10)

, I

5.6 7.0 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

or V

DD1

Supply Current I

DD2

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

DD1 (90)

, IE1, I

I

ID

VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

, V , V

EH

EL

, I

E2

OBH

ODH

OBL

ODL

44 62 mA 45 MHz logic signal freq.

DD2 (90)

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ V

2.0 V

0.8 V

,

(V

or V

DD1

(V

DD1

,

0.0 0.1 V IOx = 20 μA, VIx = V

) − 0.1 5.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

Minimum Pulse Width Maximum Data Rate Propagation Delay

3

PW 1000 ns C

4

5

1 Mbps CL = 15 pF, CMOS signal levels t

, t

50 65 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

DD1

IxL

or V

IxH

IxL

DD1

DD2

, VE2 ≤ V

0 V ≤ V

E1

= 15 pF, CMOS signal levels

L

or V

DD2

,

Rev. G | Page 4 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t

PLH

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew

6

Channel-to-Channel Matching

ADuM140xBRW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

3

4

5

PLH

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

6

7

ADuM140xCRW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

3

4

5

PLH

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

6

7

For All Models

Output Disable Propagation Delay (High/Low

to High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic

High Output Common-Mode Transient Immunity at Logic

Low Output

8

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel Output Dynamic Supply Current per Channel

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See F through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through

igure 8

for total V

Figure 15

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

igure 10

and V

DD1

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

5

− t

|

PHL

t

7

5

− t

|

PHL

5

− t

|

PHL

9

I

9

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

PW 100 ns CL = 15 pF, CMOS signal levels 10 Mbps CL = 15 pF, CMOS signal levels t

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

t

15 ns CL = 15 pF, CMOS signal levels

PSK

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels 90 120 Mbps CL = 15 pF, CMOS signal levels t

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

t

10 ns CL = 15 pF, CMOS signal levels

PSK

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

t

, t

PZH

PZL

|CMH| 25 35 kV/μs VIx = V

6 8 ns CL = 15 pF, CMOS signal levels

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

0.19 mA/Mbps

DDI (D)

I

0.05 mA/Mbps

DDO (D)

Power Consumption

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 8

Power Consumption

igure 11

propagation delay is

PLH

Figure 10

Rev. G | Page 5 of 32

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION1

2.7 V ≤ V unless otherwise noted; all typical specifications are at T ADuM1401W, and ADuM1402W automotive grade versions.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1400 Total Supply Current, Four Channels

ADuM1401 Total Supply Current, Four Channels

ADuM1402 Total Supply Current, Four Channels

For All Models

SWITCHING SPECIFICATIONS

ADuM140xARW

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

0.26 0.31 mA

DDI (Q)

0.11 0.14 mA

DDO (Q)

2

DD1

= V

= 3.0 V. These specifications do not apply to ADuM1400W,

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.2 1.9 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.5 0.9 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

4.5 6.5 mA 5 MHz logic signal freq.

DD1 (10)

1.4 2.0 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

37 65 mA 45 MHz logic signal freq.

DD1 (90)

11 15 mA 45 MHz logic signal freq.

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.6 mA DC to 1 MHz logic signal freq.

DD1 (Q)

0.7 1.2 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

3.7 5.4 mA 5 MHz logic signal freq.

DD1 (10)

2.2 3.0 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

2

30 52 mA 45 MHz logic signal freq.

DD1 (90)

18 27 mA 45 MHz logic signal freq.

DD2 (90)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

, I

0.9 1.5 mA DC to 1 MHz logic signal freq.

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

or V

DD1

Supply Current I

DD2

DD1 (10)

, I

3.0 4.2 mA 5 MHz logic signal freq.

DD2 (10)

90 Mbps (CRW Grade Only)

V

or V

DD1

Supply Current I

DD2

Input Currents IIA, IIB, IIC,

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V

Logic Low Output Voltages V

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

3

PW 1000 ns C

4

5

− t

|

PLH

PHL

, I

DD1 (90)

, IE1, I

I

ID

VIH, V VIL, V

OAH

V

OCH

OAL

V

OCL

24 39 mA 45 MHz logic signal freq.

DD2 (90)

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ V 0 V ≤ V

E1

= 20 μA, VIx = V

Ox

, V , V

E2

EH

EL

1.6 V

0.4 V

,

(V

or V

OBH

ODH

OBL

ODL

DD1

(V

DD1

0.0 0.1 V I

,

0.04 0.1 V IOx = 400 μA, VIx = V

) − 0.1 3.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

0.2 0.4 V IOx = 4 mA, VIx = V

= 15 pF, CMOS signal levels

L

, VE2 ≤ V

DD1

IxL

or V

IxH

IxL

DD1

DD2

1 Mbps CL = 15 pF, CMOS signal levels t

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching

6

t

7

50 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

or V

DD2

,

Rev. G | Page 6 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xBRW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

ADuM140xCRW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

For All Models

Output Disable Propagation Delay (High/Low to

High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity at Logic

High Output

Common-Mode Transient Immunity at Logic

Low Output Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel

Output Dynamic Supply Current per Channel

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See F through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through

igure 8

for total V

Figure 15

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

DD1

3

4

5

PLH

6

7

3

4

5

PLH

6

7

8

5

− t

|

PHL

5

− t

|

PHL

PW 100 ns CL = 15 pF, CMOS signal levels 10 Mbps CL = 15 pF, CMOS signal levels t

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

t

22 ns CL = 15 pF, CMOS signal levels

PSK

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels 90 120 Mbps CL = 15 pF, CMOS signal levels t

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

t

16 ns CL = 15 pF, CMOS signal levels

PSK

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

PLH

t

, t

PZH

PZL

6 8 ns CL = 15 pF, CMOS signal levels

|CMH| 25 35 kV/μs VIx = V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

9

I

0.10 mA/

DDI (D)

I

0.03 mA/

DDO (D)

igure 10

and V

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

or V

DD1

transient magnitude = 800 V

Mbps

Power Consumption

Figure 8

, VCM = 1000 V,

DD2

igure 11

propagation delay is

PLH

Figure 10

Rev. G | Page 7 of 32

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION1

5 V/3 V operation: 4.5 V ≤ V minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

and ADuM1402W automotive grade versions.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA

ADuM1400 Total Supply Current, Four Channels

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 70 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 37 65 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 18 25 mA 45 MHz logic signal freq.

ADuM1401 Total Supply Current, Four Channels

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

2

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

= 5 V, V

DD1

DDI (Q)

DDO (Q)

= 3.0 V. These specifications do not apply to ADuM1400W, ADuM1401W,

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

≤ 5.5 V; all

DD2

Rev. G | Page 8 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 57 82 mA 45 MHz logic signal freq.

3 V/5 V Operation 30 52 mA 45 MHz logic signal freq. V

Supply Current I

DD2

5 V/3 V Operation 18 27 mA 45 MHz logic signal freq.

3 V/5 V Operation 31 43 mA 45 MHz logic signal freq.

ADuM1402 Total Supply Current, Four Channels

2

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. V

Supply Current I

DD2

5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq.

3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq. V

Supply Current I

DD2

5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq.

3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 44 62 mA 45 MHz logic signal freq.

3 V/5 V Operation 24 39 mA 45 MHz logic signal freq. V

Supply Current I

DD2

5 V/3 V Operation 24 39 mA 45 MHz logic signal freq.

3 V/5 V Operation 44 62 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

Logic High Input Threshold

5 V/3 V Operation 2.0 V

3 V/5 V Operation 1.6 V Logic Low Input Threshold

5 V/3 V Operation 0.8 V

3 V/5 V Operation 0.4 V Logic High Output Voltages V

Logic Low Output Voltages V

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |t

3

4

1 Mbps C

5

− t

|

PLH

PHL

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew Channel-to-Channel Matching

6

t

7

ADuM140xBRW

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

3

4

5

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

, IE1, I

I

ID

VIH, V

VIL, V

OAH

V

OCH

OAL

V

OCL

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC,VID ≤ V , 0 V ≤ VE1, VE2 ≤ V

E2

EH

EL

, V

,

or V or V

) − 0.1 (V

DD2

) − 0.4 (V

DD2

(V

OBH

, V

, V , V

DD1

ODH

(V

DD1

0.0 0.1 V I

OBL,

ODL

0.04 0.1 V IOx = 400 μA, VIx = V

DD1

or V

) V IOx = −20 μA, VIx = V

DD2

or V

) − 0.2 V IOx = −4 mA, VIx = V

DD2

V

DD2

= 20 μA, VIx = V

Ox

0.2 0.4 V IOx = 4 mA, VIx = V

or

DD1

or V

DD1

DD2

IxH

IxL

PW 1000 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

L

t

, t

50 70 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/tPSKOD

50 ns CL = 15 pF, CMOS signal levels

PW 100 ns CL = 15 pF, CMOS signal levels

10 Mbps CL = 15 pF, CMOS signal levels

t

, t

15 35 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

Rev. G | Page 9 of 32

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

6

7

ADuM140xCRW

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

3

4

5

Pulse Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching, Codirectional

Channels

7

Channel-to-Channel Matching, Opposing-

Directional Channels

6

7

For All Models

Output Disable Propagation Delay (High/Low

to High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns Common-Mode Transient Immunity at Logic

High Output

Common-Mode Transient Immunity at Logic

Low Output

8

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current per Channel

5 V/3 V Operation 0.19 mA/Mbps

3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current per Channel

5 V/3 V Operation 0.03 mA/Mbps

3 V/5 V Operation 0.05 mA/Mbps

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See F through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through

igure 8

for total V

Figure 15

3

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

igure 10

and V

DD1

DD2

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

PLH

5

− t

|

PHL

PWD 3 ns CL = 15 pF, CMOS signal levels

t

22 ns CL = 15 pF, CMOS signal levels

PSK

t

3 ns CL = 15 pF, CMOS signal levels

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels

90 120 Mbps CL = 15 pF, CMOS signal levels

t

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

t

14 ns CL = 15 pF, CMOS signal levels

PSK

t

2 ns CL = 15 pF, CMOS signal levels

PSKCD

t

5 ns CL = 15 pF, CMOS signal levels

PSKOD

t

, t

PHZ

t

, t

PZH

6 8 ns CL = 15 pF, CMOS signal levels

PLH

6 8 ns CL = 15 pF, CMOS signal levels

PZL

L

PLH

5

− t

|

PHL

|CMH| 25 35 kV/μs VIx = V

transient magnitude = 800 V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

9

I

DDI (D)

I

DDO (D)

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DD2

Figure 8

Power Consumption

= 15 pF, CMOS signal levels

or V

DD1

, VCM = 1000 V,

DD2

Power Consumption

igure 11

propagation delay is

PLH

Figure 10

Rev. G | Page 10 of 32

ANALOG DEVICES ADUM 1401 ARW Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS