Analog Devices ADuM1400 1 2 B Datasheet

G

Quad-Channel Digital Isolators

FEATURES

Low power operation

5 V operation

1.0 mA per channel max @ 0 Mbps to 2 Mbps

3.5 mA per channel max @ 10 Mbps 31 mA per channel max @ 90 Mbps

3 V operation

0.7 mA per channel max @ 0 Mbps to 2 Mbps

2.1 mA per channel max @ 10 Mbps

20 mA per channel max @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns max pulse-width distortion

2 ns max channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function Wide body 16-lead SOIC package, Pb-free models available Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 V

= 560 V peak

IORM

APPLICATIONS

General-purpose multichannel isolation SPI® interface/data converter isolation RS-232/RS-422/RS-485 transceiver Industrial field bus isolation

ADuM1400/ADuM1401/ADuM1402

GENERAL DESCRIPTION

The ADuM140x are 4-channel digital isolators based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discretes is eliminated with these iCoupler products. Furthermore, iCoupler devices consumes one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM140x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM140x provides low pulse-width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM140x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

2

ND

1

ENCODE DECODE

3

V

IA

ENCODE DECODE

4

V

IB

ENCODE DECODE

5

V

IC

6

V

NC

ND

Figure 1. ADuM1400 Functional Block Diagram

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ENCODE DECODE

ID

7

8

1

16

V

DD2

GND

15

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

03786-0-001

V

GND

1

DD1

2

1

ENCODE DECODE

3

V

IA

ENCODE DECODE

4

V

IB

5

IC

6

7

E1

8

1

DECODE ENCODE

V

OD

V

16

V

DD2

15

GND

2

14

V

OA

V

13

OB

V

12

OC

V

11

ID

V

10

E2

9

GND

2

Figure 2. ADuM1401 Functional Block Diagram

1

V

DD1

GND

2

1

ENCODE DECODE

3

V

IA

ENCODE DECODE

4

V

IB

DECODE

5

V

OC

6

OD

7

E1

8

1

DECODE ENCODE

V

03786-0-002

GND

ENCODE

16

15

14

13

12

11

10

9

Figure 3. ADuM1402 Functional Block Diagram

www.analog.com

V

GND

V

GND

DD2

2

OA

OB

IC

ID

E2

2

03786-0-003

ADuM1400/ADuM1401/ADuM1402

REVISION HISTORY

6/04—Data Sheet Changed from Rev. A to Rev. B.

Changes to Format ............................................................. Universal

Changes to Features.......................................................................... 1

Changes to Electrical Characteristics—5 V Operation ............... 3

Changes to Electrical Characteristics—3 V Operation ............... 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation............................................................................ 7

Changes to DIN EN 60747-5-2 (VDE 0884 Part 2)

Insulation Characteristics Title..................................................... 11

Changes to the Ordering Guide.................................................... 19

Pin Configurations and Pin Function Descriptions .................. 15

Typical Perfor m a n c e C haracter i s t ics ........................................... 17

Application Information................................................................ 19

PC Board Layout ........................................................................ 19

Propagation Delay-Related Parameters................................... 19

DC Correctness and Magnetic Field Immunity........................... 19

Power Consumption .................................................................. 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

5/04—Data Sheet Changed from Rev. 0 to Rev. A.

Updated Format..................................................................Universal

Changes to the Features................................................................... 1

Changes to Table 7 and Table 8..................................................... 14

Changes to Table 9.......................................................................... 15

Changes to the DC Correctness and Magnetic Field Immunity

Section.............................................................................................. 20

Changes to the Power Consumption Section ............................. 21

Changes to the Ordering Guide.................................................... 22

9/03—Revision 0: Initial Version.

Rev. B | Page 2 of 24

ADuM1400/ADuM1401/ADuM1402

SPECIFICATIONS

= V

DD1

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD1 (10)

DD1 (90)

, IIB, IIC,

IA

, IE1, I

ID

, V

OAH

, V

OCH

, V

OAL

, V

OCL

EL

, I

EH

DD2 (Q)

, I

DD2 (10)

, I

DD2 (90)

E2

OBH

ODH

OBL

ODL

1

= 5 V.

DD2

0.50 0.53 mA

0.19 0.21 mA

2.2 2.8 mA DC to 1 MHz logic signal freq.

0.9 1.4 mA DC to 1 MHz logic signal freq.

8.6 10.6 mA 5 MHz logic signal freq.

2.6 3.5 mA 5 MHz logic signal freq.

76 100 mA 45 MHz logic signal freq. 21 25 mA 45 MHz logic signal freq.

1.8 2.4 mA DC to 1 MHz logic signal freq.

1.2 1.8 mA DC to 1 MHz logic signal freq.

7.1 9.0 mA 5 MHz logic signal freq.

4.1 5.0 mA 5 MHz logic signal freq.

62 82 mA 45 MHz logic signal freq. 35 43 mA 45 MHz logic signal freq.

1.5 2.1 mA DC to 1 MHz logic signal freq.

5.6 7.0 mA 5 MHz logic signal freq.

49 62 mA 45 MHz logic signal freq.

–10 +0.01 +10 µA

0 ≤ V 0 ≤ V

IA

E1

, VIB, VIC, VID ≤ V

, VE2 ≤ V

2.0 V

0.8 V V

,

DD1,

V

DD2

V

DD1,

V

DD2

0.0 0.1 V IOx = 20 µA, VIx = V

,

5.0 V I

– 0.1

4.8 V I

– 0.4

= –20 µA, VIx = V

Ox

= –4 mA, VIx = V

Ox

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

DD1

or V

IxH

IxL

DD1

DD2

or V

DD2

,

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V wise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

Output Supply Current, per Channel, Quiescent I

ADuM1400, Total Supply Current, Four Channels2

ADuM1401, Total Supply Current, Four Channels2

ADuM1402, Total Supply Current, Four Channels2

For All Models

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-

DD2

= 25°C, V

A

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

or V

DD1

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

or V

DD1

Input Currents

Supply Current I

DD2

I

I Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

VIH, V

VIL, V

V

Logic Low Output Voltages

V

Rev. B | Page 3 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

ADuM140xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

ADuM140xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/t Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output Refresh Rate f Input Dynamic Supply Current, per Channel Output Dynamic Supply Current, per Channel9 I

See Notes on next page.

3

4

5

– t

|

PLH

PHL

6

7

5

– t

|

PLH

PHL

7

5

– t

|

PLH

PHL

7

8

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

PHL

, t

PLH

50 65 100 ns CL = 15 pF, CMOS signal levels PWD 40 ns CL = 15 pF, CMOS signal levels t

PSK

t

PSKCD/OD

, t

PHL

PLH

50 ns CL = 15 pF, CMOS signal levels

20 32 50 ns CL = 15 pF, CMOS signal levels PWD 3 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

15 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

18 27 32 ns CL = 15 pF, CMOS signal levels PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

t

, t

PHZ

PLH

, t

t

PZH

PZL

F

|CMH| 25 35 kV/µs

10 ns CL = 15 pF, CMOS signal levels

2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

2.5 ns CL = 15 pF, CMOS signal levels = V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

9

I

DDI (D)

DDO (D)

1.2 Mbps

0.19 mA/Mbps

0.05 mA/Mbps

Rev. B | Page 4 of 24

ADuM1400/ADuM1401/ADuM1402

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total I

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section on Page 20 for guidance on calculating the per-channel supply current for a given data rate.

Figure 8

Figure 14

Figure 10 and I

DD1

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

propagation delay is

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DD2

Figure 8

PLH

Figure 10

Power Consumption

Figure 11

Rev. B | Page 5 of 24

ADuM1400/ADuM1401/ADuM1402

= V

, IIB, I , IE1, I

, V , V

, t

EH

EL

PLH

, I

DD2 (10)

, I

DD2 (90)

IC,

E2

OBH

ODH

OBL

ODL

1

= 3.0 V.

DD2

0.26 0.31 mA

0.11 0.14 mA

1.2 1.9 mA DC to 1 MHz logic signal freq.

0.5 0.9 mA DC to 1 MHz logic signal freq.

4.5 6.5 mA 5 MHz logic signal freq.

1.4 2.0 mA 5 MHz logic signal freq.

42 65 mA 45 MHz logic signal freq. 11 15 mA 45 MHz logic signal freq.

1.0 1.6 mA DC to 1 MHz logic signal freq.

0.7 1.2 mA DC to 1 MHz logic signal freq.

3.7 5.4 mA 5 MHz logic signal freq.

2.2 3.0 mA 5 MHz logic signal freq.

34 52 mA 45 MHz logic signal freq. 19 27 mA 45 MHz logic signal freq.

0.9 1.5 mA DC to 1 MHz logic signal freq.

DD2 (Q)

3.0 4.2 mA 5 MHz logic signal freq.

27 39 mA 45 MHz logic signal freq.

–10 +0.01 +10 µA

, VIB, VIC, VID ≤ V

0 ≤ V

IA

V

, 0 ≤ VE1,VE2 ≤ V

DD2

1.6 V

0.4 V V

, V

,

V

0.0 0.1 V IOx = 20 µA, VIx = V

,

– 0.1 3.0 V IOx = –20 µA, VIx = V

DD1

DD2

, V

– 0.4 2.8 V IOx = –4 mA, VIx = V

DD1

DD2

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

50 75 100 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels 50 ns CL = 15 pF, CMOS signal levels

or

DD1

or V

DD1

DD2

IxH

IxL

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V wise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I Output Supply Current, per Channel, Quiescent I ADuM1400, Total Supply Current, Four Channels2

ADuM1401, Total Supply Current, Four Channels2

ADuM1402, Total Supply Current, Four Channels2

For All Models

SWITCHING SPECIFICATIONS

ADuM140xARW

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-

DD2

= 25°C, V

A

DD1

DDI (Q)

DDO (Q)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (90)

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (90)

DD2 (90)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

10 Mbps (BRW and CRW Grades Only)

V

or V

DD1

Supply Current I

DD2

DD1 (10)

90 Mbps (CRW Grade Only)

V

or V

DD1

Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

Logic Low Output Voltages

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

Supply Current I

DD2

3

4

5

– t

|

PLH

PHL

6

7

DD1 (90)

I

IA

I

ID

VIH, V VIL, V V

OAH

V

OCH

V

OAL

V

OCL

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels t

PSK

t

PSKCD/OD

Rev. B | Page 6 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

ADuM140xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/t

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

8

Refresh Rate f Input Dynamic Supply Current, per Channel9I Output Dynamic Supply Current, per Channel9 I

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total I

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section on Page 20 for guidance on calculating the per-channel supply current for a given data rate.

Figure 8

Figure 14

Figure 10 and I

DD1

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

PHL

, t

PLH

20 38 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

22 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

20 34 45 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

, t

t

PHZ

PLH

, t

t

PZH

PZL

F

|CMH| 25 35 kV/µs

16 ns CL = 15 pF, CMOS signal levels 2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

DDI (D)

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

1.1 Mbps

0.10 mA/Mbps

0.03 mA/Mbps

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 8

Figure 11

propagation delay is

PLH

Figure 10

Rev. B | Page 7 of 24

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

5 V/3 V operation: 4.5 V ≤ V specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA

Output Supply Current, per Channel, Quiescent I

5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA

ADuM1400, Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 76 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 42 65 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 21 25 mA 45 MHz logic signal freq.

ADuM1401, Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V; or V

DD2

= 5 V, V

DD1

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

= 3.0 V.

DD2

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

1

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all min/max

DD2

Rev. B | Page 8 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

DD1 (90)

5 V/3 V Operation 62 82 mA 45 MHz logic signal freq. 3 V/5 V Operation 34 52 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (90)

5 V/3 V Operation 19 27 mA 45 MHz logic signal freq. 3 V/5 V Operation 35 43 mA 45 MHz logic signal freq.

ADuM1402, Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

DD1 (90)

5 V/3 V Operation 49 62 mA 45 MHz logic signal freq. 3 V/5 V Operation 27 39 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (90)

5 V/3 V Operation 27 39 mA 45 MHz logic signal freq. 3 V/5 V Operation 49 62 mA 45 MHz logic signal freq.

For All Models

Input Currents

Logic High Input Threshold

, IIB, IIC,

I

IA

I

, IE1, I

ID

VIH, V

E2

EH

5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input Threshold

VIL, V

EL

5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V

Logic High Output Voltages

Logic Low Output Voltages

, V

V

OAH

, V

V

OCH

V

OAL, VOBL,

V

, V

OCL

OBH

ODH

ODL

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

3

4

5

– t

|

PLH

PHL

6

7

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

, t

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels t

PSK

t

PSKCD/OD

–10 +0.01 +10 µA

0 ≤ V V

, VIC,VID ≤ V

IA,VIB

, 0 ≤ VE1,VE2 ≤ V

DD2

V

,

/

DD1

– 0.1

V

DD2

V

/

DD1

V

– 0.4

DD2

V

DD1/VDD2

V

DD1

V

DD2

/ – 0.2

V IOx = –20 µA, VIx = V

V I

= –4 mA, VIx = V

Ox

0.0 0.1 V IOx = 20 µA, VIx = V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

50 70 100 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels 50 ns CL = 15 pF, CMOS signal levels

or

DD1

or V

DD1

DD2

IxH

IxL

Rev. B | Page 9 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xBRW

Minimum Pulse Width Maximum Data Rate Propagation Delay5 t Pulse-Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

ADuM140xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns Maximum Data Rate4 90 120 Mbps Propagation Delay5 t Pulse-Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

Output Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/t

5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output Refresh Rate f

5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current, per Channel9I

5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps

Output Dynamic Supply Current, per Channel9 I

5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps

See Notes on next page.

3

4

5

– t

|

PLH

PHL

6

7

5

– t

|

PLH

PHL

7

8

PW 100 ns CL = 15 pF,CMOS signal levels 10 Mbps CL = 15 pF, CMOS signal levels

PHL

, t

PLH

15 35 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

t

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

22 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

C

L

C

= 15 pF, CMOS signal levels

L

20 30 40 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

, t

t

PHZ

PLH

, t

t

PZH

PZL

f

|CMH| 25 35 kV/µs

14 ns CL = 15 pF, CMOS signal levels 2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

C

= 15 pF, CMOS signal levels

L

= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

DDI (D)

Rev. B | Page 10 of 24

ADuM1400/ADuM1401/ADuM1402

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total I I

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

sustained while maintaining V over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-

channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 20 for guidance on calculating the per-channel supply current for a given data rate.

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range

O

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load within the

PHL

PLH

. CML is the maximum common-mode voltage slew rate that can be

DD2

propagation delay is measured

PLH

and

DD1

Rev. B | Page 11 of 24

ADuM1400/ADuM1401/ADuM1402

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output) Capacitance (Input-Output) Input Capacitance IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ

1

Device considered a 2-terminal device; Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM140x have been approved by the organizations listed in Table 5.

Table 5.

1

UL

Recognized under 1577 component recognition program

Double insulation, 2500 V rms isolation voltage

File E214100

1

In accordance with UL1577, each ADuM140x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).

2

In accordance with DIN EN 60747-5-2, each ADuM140x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection

limit = 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval.

1

2

R

I-O

C

I-O

C

I

JCI

JCO

10

2.2 pF f = 1 MHz

4.0 pF 33 °C/W 28 °C/W

CSA VDE

Approved under CSA Component

1

Acceptance Notice #5A

Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms maximum working voltage

File 205078

12

Ω

Thermocouple located at center of package underside

2

Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

2

Basic insulation, 560 V peak

Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 200301, DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000

Reinforced insulation, 560 V peak

File 2471900-4880-0001

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 8.40 min mm

Minimum External Tracking (Creepage) L(I02) 8.10 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. B | Page 12 of 24

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

ADuM1400/ADuM1401/ADuM1402

DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS

Table 7.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

I–IV I–III

I–II Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage V Input to Output Test Voltage, Method b1

V

× 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC

IORM

Input to Output Test Voltage, Method a

After Environmental Tests Subgroup 1 V

× 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

After Input and/or Safety Test Subgroup 2/3 V

× 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) V Safety-Limiting Values (Maximum value allowed in the event of a failure; also see

Thermal Derating Curve, Figure 4)

Case Temperature Side 1 Current Side 2 Current

Insulation Resistance at TS, VIO = 500 V R

IORM

V

PR

V

PR

TR

T

S

I

S1

I

S2

S

560 V peak

1050 V peak

896

672

4000 V peak

150

265

335

9

>10

This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.

V peak

°C mA mA Ω

The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage.

350

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Temperature per DIN EN 60747-5-2

SIDE #2

SIDE #1

50 100 150 200

CASE TEMPERATURE (°C)

03787-0-003

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature T Supply Voltages Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground.

See the DC Correctness and Magnetic Field Immunity section on Page 19 for

information on immunity to external magnetic fields.

1

A

V

DD1

–40 +105 °C

, V

2.7 5.5 V

DD 2

Rev. B | Page 13 of 24

ADuM1400/ADuM1401/ADuM1402

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 9.

Parameter Symbol Min Max Unit

Storage Temperature T Ambient Operating Temperature T Supply Voltages Input Voltage Output Voltage Average Output Current, Per Pin

1

1, 2

3

Side 1 I Side 2 I

Common-Mode Transients

4

ST

A

V

, V

DD1

DD2

VIA, VIB, VIC, VID, VE1,V VOA, VOB, VOC, V

E2

OD

O1

O2

–100 +100 kV/µs

1

All voltages are relative to their respective ground.

2

V

and V

DDI

3

See for maximum rated current values for various temperatures. Figure 4

4

Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or perma-

nent damage.

refer to the supply voltages on the input and output sides of a given channel, respectively. See the section. PC Board Layout

DDO

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

–65 +150 °C –40 +105 °C –0.5 +7.0 V –0.5 V –0.5 V

+ 0.5 V

DDI

+ 0.5 V

DDO

–18 +18 mA –22 +22 mA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Table 10. Truth Table (Positive Logic)

V

Input1VEX Input2V

IX

H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H

X L Unpowered Powered Z X X Powered Unpowered Indeterminate

1

VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. V

V

refer to the supply voltages on the input and output sides of the given channel, respectively.

DDO

2

In noisy environments, connecting VEX to an external logic high or low is recommended.

State1 V

DDI

State1 VOX Output1 Notes

DDO

Outputs return to the input state within 1 µs of V restoration.

Outputs return to the input state within 1 µs of V restoration if V state within 8 ns of V

power

DDI

power

state is H or NC. Outputs returns to high impedance

EX

power restoration if VEX state is L.

DDO

DDI

and

Rev. B | Page 14 of 24

ADuM1400/ADuM1401/ADuM1402

*

PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS

V

1 16

DD1

GND

2 15

1

V

3 14

IA

(Not to Scale)

V

4 13

IB

V

5 12

IC

V

6 11

ID

NC

7 10

GND

8 9

1

NC = NO CONNECT

ADuM1400

TOP VIEW

V

DD2

GND2* V

OA

V

OB

V

OC

V

OD

V

E2

GND2*

03786-0-005

Figure 5. ADuM1400 Pin Configuration

V

1 16

DD1

GND

2 15

1

ADuM1401

TOP VIEW

V

3 14

IA

(Not to Scale)

V

4 13

IB

V

5 12

IC

V

6 11

OD

V

7 10

E1

GND

8 9

1

Figure 6. ADuM1401 Pin Configuration

V

DD2

GND2* V

OA

V

OB

V

OC

V

ID

V

E2

GND2*

03786-0-006

V

1 16

DD1

GND

2 15

1

V

3 14

IA

V

4 13

IB

V

5 12

OC

V

6 11

OD

V

7 10

E1

GND

8 9

1

ADuM1402

TOP VIEW

(Not to Scale)

V

DD2

GND2* V

OA

V

OB

V

IC

V

ID

V

E2

GND2*

03786-0-007

Figure 7. ADuM1402 Pin Configuration

* Pins 2 and 8 are internally connected. Connecting both to GND1 is recommended. Pins 9 and 15 are internally connected. Connecting both to GND2 is recommended.

Output enable Pin 10 on the ADuM1400 may be left disconnected if outputs are to be always enabled. Output enable Pins 7 and 10 on the ADuM1401/ADuM1402 may be left disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM1401 and ADuM1402) and Pin 10 (for all models) to an external logic high or low is recommended.

Table 11. ADuM1400 Pin Function Descriptions

Pin No.

Mnemonic Function

1 V

DD1

2 GND 3 V

IA

4 V

IB

5 V

IC

6 V

ID

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for isolator Side 1.

1

Logic Input A. Logic Input B. Logic Input C.

Logic Input D. 7 NC No Connect. 8 GND 9 GND 10 V

E2

11 V

OD

12 V

OC

13 V

OB

14 V

OA

15 GND 16 V

DD2

Ground 1. Ground reference for isolator Side 1.

1

Ground 2. Ground reference for isolator Side 2.

2

Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected. VOA, VOB, VOC, and

outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.

V

OD

Logic Output D.

Logic Output C.

Logic Output B.

Logic Output A.

Ground 2. Ground reference for isolator Side 2.

2

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. B | Page 15 of 24

ADuM1400/ADuM1401/ADuM1402

Table 12. ADuM1401 Pin Function Descriptions

Pin No.

Mnemonic Function

1 V

DD1

2 GND 3 V

IA

4 V

IB

5 V

IC

6 V

OD

7 V

E1

8 GND 9 GND 10 V

E2

11 V

ID

12 V

OC

13 V

OB

14 V

OA

15 GND 16 V

DD2

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for isolator Side 1.

1

Logic Input A. Logic Input B. Logic Input C. Logic Output D. Output Enable 1. Active high logic input. V

noisy environments, connecting V Ground 1. Ground reference for isolator Side 1.

1

Ground 2. Ground reference for isolator Side 2.

2

to an external logic high or low is recommended.

E1

Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC outputs are disabled when V

is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.

E2

Logic Input D. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for isolator Side 2.

2

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.

output is enabled when VE1 is high or disconnected. VOD is disabled when VE1 is low. In

OD

Table 13. ADuM1402 Pin Function Descriptions

Mnemonic Function

No.

1 V

DD1

2 GND 3 V

IA

4 V

IB

5 V

OC

6 V

OD

7 V

E1

8 GND 9 GND 10 V

E2

11 V

ID

12 V

IC

13 V

OB

14 V

OA

15 GND 16 V

DD2

Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for isolator Side 1.

1

Logic Input A. Logic Input B. Logic Output C. Logic Output D. Output Enable 1. Active high logic input. V

disabled when V Ground 1. Ground reference for isolator Side 1.

1

Ground 2. Ground reference for isolator Side 2.

2

is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.

E1

Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and VOB outputs are disabled when V

is low. In noisy environments, connecting VE2 to an external logic high or low is recommended.

E2

Logic Input D. Logic Input C. Logic Output B. Logic Output A. Ground 2. Ground Reference for Isolator Side 2.

2

Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

and VOD outputs are enabled when VE1 is high or disconnected. VOC and VOD outputs are

OC

Rev. B | Page 16 of 24

ADuM1400/ADuM1401/ADuM1402

TYPICAL PERFORMANCE CHARACTERISTICS

20

80

70

15

10

5V

5

CURRENT/CHANNEL (mA)

0

20 60 8040 100

DATA RATE (Mbps)

3V

Figure 8. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

6

5

4

3

2

CURRENT/CHANNEL (mA)

1

5V

3V

04407-0-011

60

50

40

30

CURRENT (mA)

20

10

0

20 60 8040 100

Figure 11. Typical ADuM1400 V

for 5 V and 3 V Operation

20

15

10

CURRENT (mA)

5

5V

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD1

3V

03786-0-014

3V

0

20 60 8040 100

DATA RATE (Mbps)

Figure 9. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

10

8

6

4

CURRENT/CHANNEL (mA)

2

0

5V

3V

20 60 8040 100

DATA RATE (Mbps)

Figure 10. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

04407-0-012

04407-0-013

Rev. B | Page 17 of 24

0

20 60 8040 100

Figure 12. Typical ADuM1400 V

for 5 V and 3 V Operation

50

30

25

20

15

CURRENT (mA)

10

5

0

5V

20 60 8040 100

Figure 13. Typical ADuM1401 V

for 5 V and 3 V Operation

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD2

3V

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD1

03786-0-015

03786-0-016

ADuM1400/ADuM1401/ADuM1402

40

35

40

30

25

20

15

CURRENT (mA)

10

5

0

20 60 8040 100

Figure 14. Typical ADuM1401 V

for 5 V and 3 V Operation

50

45

40

35

30

25

20

CURRENT (mA)

15

10

5

0

5V

20 60 8040 100

Figure 15. Typical ADuM1402 V

Data Rate for 5 V and 3 V Operation

5V

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD2

DATA RATE (Mbps)

or V

DD1

3V

Supply Current vs.

DD2

03786-0-017

03786-0-018

35

30

PROPAGATION DELAY (ns)

25

–50 –25

0507525 100

TEMPERATURE (°C)

3V

Figure 16. Propagation Delay vs. Temperature, C Grade

5V

03786-0-023

Rev. B | Page 18 of 24

ADuM1400/ADuM1401/ADuM1402

V

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM140x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (Figure 17). Bypass capacitors are most conveniently connected between Pins 1 and 2 for V

. The capacitor value should be between 0.01 µF and 0.1 µF.

V

DD2

and between Pins 15 and 16 for

DD1

The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pins 1 and 8 and between Pins 9 and 16 should also be considered unless the ground pair on each package side is connected close to the package.

V

DD1

GND

1

V

IA

V

IB IC/OC ID/OD

V

E1

GND

1

Figure 17. Recommended Printed Circuit Board Layout

V

DD2

GND V

OA

V

OB

V

OC/IC

V

OD/ID

V

E2

GND

2

03786-0-019

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latchup or permanent damage.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high.

INPUT (VIX)

OUTPUT (V

t

PLH

)

OX

t

PHL

Figure 18. Propagation Delay Parameters

50%

03786-0-020

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 2 µs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit.

The limitation on the ADuM140x’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM140x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than

1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

2

∑∏r

V = (–dβ/dt)

where:

β is magnetic flux density (gauss). N is the number of turns in the receiving coil.

is the radius of the nth turn in the receiving coil (cm).

r

n

Given the geometry of the receiving coil in the ADuM140x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19.

100.000

10.000

; n = 1, 2,…, N

n

Pulse-width distortion is the maximum difference between

1.000

these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum that amount the propagation delay differs between channels within a single ADuM140x component.

Propagation delay skew refers to the maximum that amount the propagation delay differs between multiple ADuM140x components operating under the same conditions.

Rev. B | Page 19 of 24

0.100

DENSITY (kgauss)

0.010

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001 1k 10k 10M

MAGNETIC FIELD FREQUENCY (Hz)

1M

Figure 19. Maximum Allowable External Magnetic Flux Density

100M100k

03786-0-021

ADuM1400/ADuM1401/ADuM1402

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM140x transformers. a function of frequency for selected distances. As seen, the ADuM140x is extremely immune and can be affected only by extremely large currents operated at high frequency, very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM140x to affect the component’s operation.

Figure 20 expresses these allowable current magnitudes as

1000.00 DISTANCE = 1m

100.00

POWER CONSUMPTION

The supply current at a given channel of the ADuM140x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

I

DDI

= I

× (2f – fr) + I

DDI (D)

DDI (Q)

For each output channel, the supply current is given by

I

DDO

= I

= (I

f ≤ 0.5f

DDO (Q)

+ (0.5 × 10−3) × CLV

DDO (D)

) × (2f – fr) + I

DDO

where:

, I

I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

is output load capacitance (pF).

C

L

f ≤ 0.5f

f > 0.5f

DDO (Q)

f > 0.5f

r

10.00 DISTANCE = 100mm

1.00 DISTANCE = 5mm

0.10

MAXIMUM ALLOWABLE CURRENT (kA)

0.01

1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 20. Maximum Allowable Current

for Various Current-to-ADuM140x Spacings

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

03786-0-022

is the output supply voltage (V).

V

DDO

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

is the input stage refresh rate (Mbps).

f

r

I

, I

DDI (Q)

are the specified input and output quiescent sup-

DDO (Q)

ply currents (mA).

To calculate the total I

DD1

and I

supply current, the supply

DD2

currents for each input and output channel corresponding to

and I

I

DD1

are calculated and totaled. Figure 8 and Figure 9

DD2

provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides perchannel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 14 provide total

and I

I

DD1

supply current as a function of data rate for

DD2

ADuM1400/ADuM1401/ADuM1402 channel configurations.

Rev. B | Page 20 of 24

ADuM1400/ADuM1401/ADuM1402

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

1.27 (0.0500) BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013AA

9

7.60 (0.2992)

7.40 (0.2913)

8

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.75 (0.0295)

0.25 (0.0098)

8° 0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

Figure 21. 16-Lead Standard Small Outline Package [SOIC]

Wide Body (RW-16)

Dimension shown in millimeters (inches)

ORDERING GUIDE

Number of Inputs, V

Side

DD2

Model

ADuM1400ARW

Number of Inputs,

Side

V

2

DD1

4 0 1 100 40 –40 to +105 RW-16 ADuM1400BRW2 4 0 10 50 3 –40 to +105 RW-16 ADuM1400CRW2 4 0 90 32 2 –40 to +105 RW-16 ADuM1400ARWZ ADuM1400BRWZ ADuM1400CRWZ

2, 3

4 0 1 100 40 –40 to +105 RW-16

2, 3

4 0 10 50 3 –40 to +105 RW-16

2, 3

4 0 90 32 2 –40 to +105 RW-16 ADuM1401ARW2 3 1 1 100 40 –40 to +105 RW-16 ADuM1401BRW2 3 1 10 50 3 –40 to +105 RW-16 ADuM1401CRW2 3 1 90 32 2 –40 to +105 RW-16 ADuM1401ARWZ ADuM1401BRWZ ADuM1401CRWZ

2, 3

3 1 1 100 40 –40 to +105 RW-16

2, 3

3 1 10 50 3 –40 to +105 RW-16

2, 3

3 1 90 32 2 –40 to +105 RW-16 ADuM1402ARW2 2 2 1 100 40 –40 to +105 RW-16 ADuM1402BRW2 2 2 10 50 3 –40 to +105 RW-16 ADuM1402CRW2 2 2 90 32 2 –40 to +105 RW-16 ADuM1402ARWZ ADuM1402BRWZ ADuM1402CRWZ

2, 3

2 2 1 100 40 –40 to +105 RW-16

2, 3

2 2 10 50 3 –40 to +105 RW-16

2, 3

2 2 90 32 2 –40 to +105 RW-16

1

RW-16 = 16-lead wide body SOIC.

2

Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option.

3

Z = Pb-free part.

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Maximum Pulse-Width Distortion (ns)

Temperature Range (°C)

Package Option

1

Rev. B | Page 21 of 24

ADuM1400/ADuM1401/ADuM1402

NOTES

Rev. B | Page 22 of 24

ADuM1400/ADuM1401/ADuM1402

NOTES

Rev. B | Page 23 of 24

ADuM1400/ADuM1401/ADuM1402

NOTES

C03786–0–6/04(B)

Rev. B | Page 24 of 24

Analog Devices ADuM1400 1 2 B Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

OUTLINE DIMENSIONS

ORDERING GUIDE