Analog Devices ADuM1400 1 2 B Datasheet

G

Quad-Channel Digital Isolators

FEATURES

Low power operation

5 V operation

1.0 mA per channel max @ 0 Mbps to 2 Mbps

3.5 mA per channel max @ 10 Mbps 31 mA per channel max @ 90 Mbps

3 V operation

0.7 mA per channel max @ 0 Mbps to 2 Mbps

2.1 mA per channel max @ 10 Mbps

20 mA per channel max @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns max pulse-width distortion

2 ns max channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function Wide body 16-lead SOIC package, Pb-free models available Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 V

= 560 V peak

IORM

APPLICATIONS

General-purpose multichannel isolation SPI® interface/data converter isolation RS-232/RS-422/RS-485 transceiver Industrial field bus isolation

ADuM1400/ADuM1401/ADuM1402

GENERAL DESCRIPTION

The ADuM140x are 4-channel digital isolators based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discretes is eliminated with these iCoupler products. Furthermore, iCoupler devices consumes one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM140x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM140x provides low pulse-width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM140x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

2

ND

1

ENCODE DECODE

3

V

IA

ENCODE DECODE

4

V

IB

ENCODE DECODE

5

V

IC

6

V

NC

ND

Figure 1. ADuM1400 Functional Block Diagram

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ENCODE DECODE

ID

7

8

1

16

V

DD2

GND

15

2

14

V

OA

13

V

OB

12

V

OC

11

V

OD

10

V

E2

9

GND

2

03786-0-001

V

GND

1

DD1

2

1

ENCODE DECODE

3

V

IA

ENCODE DECODE

4

V

IB

5

IC

6

7

E1

8

1

DECODE ENCODE

V

OD

V

16

V

DD2

15

GND

2

14

V

OA

V

13

OB

V

12

OC

V

11

ID

V

10

E2

9

GND

2

Figure 2. ADuM1401 Functional Block Diagram

1

V

DD1

GND

2

1

ENCODE DECODE

3

V

IA

ENCODE DECODE

4

V

IB

DECODE

5

V

OC

6

OD

7

E1

8

1

DECODE ENCODE

V

03786-0-002

GND

ENCODE

16

15

14

13

12

11

10

9

Figure 3. ADuM1402 Functional Block Diagram

www.analog.com

V

GND

V

GND

DD2

2

OA

OB

IC

ID

E2

2

03786-0-003

ADuM1400/ADuM1401/ADuM1402

REVISION HISTORY

6/04—Data Sheet Changed from Rev. A to Rev. B.

Changes to Format ............................................................. Universal

Changes to Features.......................................................................... 1

Changes to Electrical Characteristics—5 V Operation ............... 3

Changes to Electrical Characteristics—3 V Operation ............... 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation............................................................................ 7

Changes to DIN EN 60747-5-2 (VDE 0884 Part 2)

Insulation Characteristics Title..................................................... 11

Changes to the Ordering Guide.................................................... 19

Pin Configurations and Pin Function Descriptions .................. 15

Typical Perfor m a n c e C haracter i s t ics ........................................... 17

Application Information................................................................ 19

PC Board Layout ........................................................................ 19

Propagation Delay-Related Parameters................................... 19

DC Correctness and Magnetic Field Immunity........................... 19

Power Consumption .................................................................. 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

5/04—Data Sheet Changed from Rev. 0 to Rev. A.

Updated Format..................................................................Universal

Changes to the Features................................................................... 1

Changes to Table 7 and Table 8..................................................... 14

Changes to Table 9.......................................................................... 15

Changes to the DC Correctness and Magnetic Field Immunity

Section.............................................................................................. 20

Changes to the Power Consumption Section ............................. 21

Changes to the Ordering Guide.................................................... 22

9/03—Revision 0: Initial Version.

Rev. B | Page 2 of 24

ADuM1400/ADuM1401/ADuM1402

SPECIFICATIONS

= V

DD1

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD1 (10)

DD1 (90)

, IIB, IIC,

IA

, IE1, I

ID

, V

OAH

, V

OCH

, V

OAL

, V

OCL

EL

, I

EH

DD2 (Q)

, I

DD2 (10)

, I

DD2 (90)

E2

OBH

ODH

OBL

ODL

1

= 5 V.

DD2

0.50 0.53 mA

0.19 0.21 mA

2.2 2.8 mA DC to 1 MHz logic signal freq.

0.9 1.4 mA DC to 1 MHz logic signal freq.

8.6 10.6 mA 5 MHz logic signal freq.

2.6 3.5 mA 5 MHz logic signal freq.

76 100 mA 45 MHz logic signal freq. 21 25 mA 45 MHz logic signal freq.

1.8 2.4 mA DC to 1 MHz logic signal freq.

1.2 1.8 mA DC to 1 MHz logic signal freq.

7.1 9.0 mA 5 MHz logic signal freq.

4.1 5.0 mA 5 MHz logic signal freq.

62 82 mA 45 MHz logic signal freq. 35 43 mA 45 MHz logic signal freq.

1.5 2.1 mA DC to 1 MHz logic signal freq.

5.6 7.0 mA 5 MHz logic signal freq.

49 62 mA 45 MHz logic signal freq.

–10 +0.01 +10 µA

0 ≤ V 0 ≤ V

IA

E1

, VIB, VIC, VID ≤ V

, VE2 ≤ V

2.0 V

0.8 V V

,

DD1,

V

DD2

V

DD1,

V

DD2

0.0 0.1 V IOx = 20 µA, VIx = V

,

5.0 V I

– 0.1

4.8 V I

– 0.4

= –20 µA, VIx = V

Ox

= –4 mA, VIx = V

Ox

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

DD1

or V

IxH

IxL

DD1

DD2

or V

DD2

,

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V wise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

Output Supply Current, per Channel, Quiescent I

ADuM1400, Total Supply Current, Four Channels2

ADuM1401, Total Supply Current, Four Channels2

ADuM1402, Total Supply Current, Four Channels2

For All Models

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-

DD2

= 25°C, V

A

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

or V

DD1

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

or V

DD1

Input Currents

Supply Current I

DD2

I

I Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

VIH, V

VIL, V

V

Logic Low Output Voltages

V

Rev. B | Page 3 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

ADuM140xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

ADuM140xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/t Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output Refresh Rate f Input Dynamic Supply Current, per Channel Output Dynamic Supply Current, per Channel9 I

See Notes on next page.

3

4

5

– t

|

PLH

PHL

6

7

5

– t

|

PLH

PHL

7

5

– t

|

PLH

PHL

7

8

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

PHL

, t

PLH

50 65 100 ns CL = 15 pF, CMOS signal levels PWD 40 ns CL = 15 pF, CMOS signal levels t

PSK

t

PSKCD/OD

, t

PHL

PLH

50 ns CL = 15 pF, CMOS signal levels

20 32 50 ns CL = 15 pF, CMOS signal levels PWD 3 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

15 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

18 27 32 ns CL = 15 pF, CMOS signal levels PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

t

, t

PHZ

PLH

, t

t

PZH

PZL

F

|CMH| 25 35 kV/µs

10 ns CL = 15 pF, CMOS signal levels

2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

2.5 ns CL = 15 pF, CMOS signal levels = V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

9

I

DDI (D)

DDO (D)

1.2 Mbps

0.19 mA/Mbps

0.05 mA/Mbps

Rev. B | Page 4 of 24

ADuM1400/ADuM1401/ADuM1402

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total I

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section on Page 20 for guidance on calculating the per-channel supply current for a given data rate.

Figure 8

Figure 14

Figure 10 and I

DD1

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

propagation delay is

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

DD2

Figure 8

PLH

Figure 10

Power Consumption

Figure 11

Rev. B | Page 5 of 24

ADuM1400/ADuM1401/ADuM1402

= V

, IIB, I , IE1, I

, V , V

, t

EH

EL

PLH

, I

DD2 (10)

, I

DD2 (90)

IC,

E2

OBH

ODH

OBL

ODL

1

= 3.0 V.

DD2

0.26 0.31 mA

0.11 0.14 mA

1.2 1.9 mA DC to 1 MHz logic signal freq.

0.5 0.9 mA DC to 1 MHz logic signal freq.

4.5 6.5 mA 5 MHz logic signal freq.

1.4 2.0 mA 5 MHz logic signal freq.

42 65 mA 45 MHz logic signal freq. 11 15 mA 45 MHz logic signal freq.

1.0 1.6 mA DC to 1 MHz logic signal freq.

0.7 1.2 mA DC to 1 MHz logic signal freq.

3.7 5.4 mA 5 MHz logic signal freq.

2.2 3.0 mA 5 MHz logic signal freq.

34 52 mA 45 MHz logic signal freq. 19 27 mA 45 MHz logic signal freq.

0.9 1.5 mA DC to 1 MHz logic signal freq.

DD2 (Q)

3.0 4.2 mA 5 MHz logic signal freq.

27 39 mA 45 MHz logic signal freq.

–10 +0.01 +10 µA

, VIB, VIC, VID ≤ V

0 ≤ V

IA

V

, 0 ≤ VE1,VE2 ≤ V

DD2

1.6 V

0.4 V V

, V

,

V

0.0 0.1 V IOx = 20 µA, VIx = V

,

– 0.1 3.0 V IOx = –20 µA, VIx = V

DD1

DD2

, V

– 0.4 2.8 V IOx = –4 mA, VIx = V

DD1

DD2

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

50 75 100 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels 50 ns CL = 15 pF, CMOS signal levels

or

DD1

or V

DD1

DD2

IxH

IxL

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V wise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I Output Supply Current, per Channel, Quiescent I ADuM1400, Total Supply Current, Four Channels2

ADuM1401, Total Supply Current, Four Channels2

ADuM1402, Total Supply Current, Four Channels2

For All Models

SWITCHING SPECIFICATIONS

ADuM140xARW

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-

DD2

= 25°C, V

A

DD1

DDI (Q)

DDO (Q)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (90)

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (90)

DD2 (90)

DC to 2 Mbps

V

or V

DD1

Supply Current I

DD2

DD1 (Q)

10 Mbps (BRW and CRW Grades Only)

V

or V

DD1

Supply Current I

DD2

DD1 (10)

90 Mbps (CRW Grade Only)

V

or V

DD1

Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

Logic Low Output Voltages

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

Supply Current I

DD2

3

4

5

– t

|

PLH

PHL

6

7

DD1 (90)

I

IA

I

ID

VIH, V VIL, V V

OAH

V

OCH

V

OAL

V

OCL

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels t

PSK

t

PSKCD/OD

Rev. B | Page 6 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM140xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

ADuM140xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 t Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

7

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance) Output Enable Propagation Delay

(High Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/t

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

8

Refresh Rate f Input Dynamic Supply Current, per Channel9I Output Dynamic Supply Current, per Channel9 I

1

All voltages are relative to their respective ground.

2

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total I

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section on Page 20 for guidance on calculating the per-channel supply current for a given data rate.

Figure 8

Figure 14

Figure 10 and I

DD1

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

PHL

, t

PLH

20 38 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

22 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

20 34 45 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

, t

t

PHZ

PLH

, t

t

PZH

PZL

F

|CMH| 25 35 kV/µs

16 ns CL = 15 pF, CMOS signal levels 2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

DDI (D)

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

1.1 Mbps

0.10 mA/Mbps

0.03 mA/Mbps

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 8

Figure 11

propagation delay is

PLH

Figure 10

Rev. B | Page 7 of 24

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

5 V/3 V operation: 4.5 V ≤ V specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA

Output Supply Current, per Channel, Quiescent I

5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA

ADuM1400, Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 76 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 42 65 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 21 25 mA 45 MHz logic signal freq.

ADuM1401, Total Supply Current, Four Channels2

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V; or V

DD2

= 5 V, V

DD1

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

= 3.0 V.

DD2

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

1

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all min/max

DD2

Rev. B | Page 8 of 24

Analog Devices ADuM1400 1 2 B Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION