ANALOG DEVICES ADUM1310 Service Manual

Triple-Channel Digital Isolators

Data Sheet

FEATURES

Low power operation

5 V operation

1.7 mA per channel maximum @ 0 Mbps to 2 Mbps

4.0 mA per channel maximum @ 2 Mbps to 10 Mbps

3 V operation

1.0 mA per channel maximum @ 0 Mbps to 2 Mbps

2.1 mA per channel maximum @ 2 Mbps to 10 Mbps Bidirectional communication 3 V/5 V level translation Schmitt trigger inputs High temperature operation: 105°C Up to 10 Mbps data rate (NRZ) Programmable default output state High common-mode transient immunity: >25 kV/μs 16-lead, RoHS-compliant, SOIC wide body package

8.1 mm external creepage

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 V

= 560 V peak working voltage

IORM

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceiver Industrial field bus isolation

ADuM1310/ADuM1311

FUNCTIONAL BLOCK DIAGRAMS

1

V

GND

DISABLE

GND

DD1

V

NC

1

IA

IB

IC

1

ADuM1310

2

ENCODE DECODE

3

ENCODE DECODE

4

ENCODE DECODE

5

6

7

8

Figure 1. ADuM1310

1

V

GND

CTRL

GND

V

DD1

V

OC

NC

1

IA

IB

1

ADuM1311

2

ENCODE DECODE

3

ENCODE DECODE

4

DECODE ENCODE

5

6

7

8

Figure 2. ADuM1311

16

V

DD2

GND

15

2

14

V

OA

13

V

OB

12

V

OC

11

NC

10

CTRL

2

9

GND

2

04904-001

16

V

DD2

GND

15

2

14

V

OA

13

V

OB

12

V

IC

11

NC

10

CTRL

2

9

GND

2

04904-002

GENERAL DESCRIPTION

The ADuM131x1 are 3-channel digital isolators based on

Analog Devices, Inc. iCoupler® technology. Combining high

speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, maximum operating temperature, and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The iCoupler also offers higher channel densities and more options for channel directionality.

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The ADuM131x isolators provide three independent isolation channels in a variety of channel configurations and data rates up to 10 Mbps (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to

5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products allow the user to predetermine the default output state in the absence of input V

power with a simple

DD1

control pin. Unlike other optocoupler alternatives, the ADuM131x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/ power-down conditions.

1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents

pending.

ADuM1310/ADuM1311 Data Sheet

REVISION HISTORY

3/12—Rev. G to Rev. H

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 18

Updated Outline Dimensions ....................................................... 21

6/07—Rev. F to Rev. G

Updated VDE Certification Throughout ...................................... 1

Changes to Features and Applications ........................................... 1

Changes to DC Specifications in Table 1 ....................................... 3

Changes to DC Specifications in Table 2 ....................................... 5

Changes to DC Specifications in Table 3 ....................................... 7

Changes to Regulatory Information Section .............................. 10

Added Table 10 ............................................................................... 12

Added Insulation Lifetime Section .............................................. 19

1/07—Rev. E to Rev. F

Added ADuM1311 ............................................................. Universal

Changes to Typical Performance Characteristics Section ......... 16

Changes to Ordering Guide .......................................................... 20

10/06—Rev. D to Rev. E

Removed ADuM1410 ........................................................ Universal

Updated Format .................................................................. Universal

Change to Figure 3 ......................................................................... 10

Changes to Table 10 ....................................................................... 10

Changes to Application Information Section ............................. 12

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 18

3/06—Rev. C to Rev. D

Added Note 1; Changes to Figure 2 ................................................ 1

Changes to Absolute Maximum Ratings ..................................... 11

11/05—Revision C: Initial Version

Rev. H | Page 2 of 24

Data Sheet ADuM1310/ADuM1311

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V unless otherwise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

ADuM1310, Total Supply Current,

ADuM1311, Total Supply Current,

For All Models

SWITCHING SPECIFICATIONS

ADuM131xARWZ

ADuM131xBRWZ

≤ 5.5 V, 4.5 V ≤ V

DD1

Three Channels

1

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

DD1

= V

= 5 V. All voltages are relative to their respective grounds.

DD2

DC to 2 Mbps

V

Supply Current I

DD1

2.4 3.2 mA

DD1 (Q)

DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

1.2 1.6 mA

DD2 (Q)

DC to 1 MHz logic signal frequency

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

1

Three Channels

6.6 9.0 mA 5 MHz logic signal frequency

DD1 (10)

2.1 3.0 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

2.2 2.8 mA

DD1 (Q)

DC to 1 MHz logic signal frequency

V

Supply Current I

DD2

1.8 2.4 mA

DD2 (Q)

DC to 1 MHz logic signal frequency

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold

4.5 5.7 mA 5 MHz logic signal frequency

DD1 (10)

3.5 4.3 mA 5 MHz logic signal frequency

DD2 (10)

, IIB, IIC, I

I

IA

I

CTRL2

V

IH

V

IL

OAH

OAL

, I

, V

CTRL1

DISABLE

OBH

, V

OBL

−10 +0.01 +10 μA

,

0 V ≤ V 0 V ≤ V 0 V ≤ V

2.0 V

0.8 V (V

or V

, V

OCL

DD1

OCH

(V

DD1

0.0 0.1 V IOx = 20 μA, VIx = V

) − 0.1 5.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

, VIB, VIC ≤ V

IA

, V

CTRL1

CTRL2

≤ V

DISABLE

0.2 0.4 V IOx = 4 mA, VIx = V

≤ V

DD1

or V

DD1

DD2

or V

DD1

DD2,

Logic High Output Voltages V

IxH

Logic Low Output Voltages V

IxL

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

| Propagation Delay Skew5 t Channel-to-Channel Matching6 t

, t

20 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

, t

20 30 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PWD 5 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t

30 ns CL = 15 pF, CMOS signal levels

PSK

,

Rev. H | Page 3 of 24

ADuM1310/ADuM1311 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

5 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

6

Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.2 Mbps Input Enable Time8 t Input Disable Time8 t Input Supply Current per Channel,

Quiescent

Output Supply Current per Channel,

Quiescent

Input Dynamic Supply Current

per Channel

Output Dynamic Supply Current per

Channel

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 13).

9

I

the same orientation as Channel A must be included to account for the total current consumed.

10

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in

DDx (Q)

9

10

and V

DD1

supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.

DD2

t

PSKCD

t

6 ns CL = 15 pF, CMOS signal levels

PSKOD

6

|CMH| 25 35 kV/μs

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

|CML| 25 35 kV/μs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

ENABLE

DISABLE

0.50 0.73 mA

I

DDI (Q)

I

0.38 0.53 mA

DDO (Q)

0.12

I

DDI (D)

2.0 μs VIA, VIB, VIC = 0 V or V

5.0 μs VIA, VIB, VIC = 0 V or V

mA/ Mbps

0.04

I

DDO (D)

mA/ Mbps

ower Consumption

Figure 9

propagation delay is

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

. CML is the maximum common-mode voltage slew rate

DD2

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

Power Consumption

Figure 6

Figure 8

DD1

is set high

Rev. H | Page 4 of 24

Data Sheet ADuM1310/ADuM1311

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V unless otherwise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

ADuM1310, Total Supply Current,

ADuM1311, Total Supply Current,

For All Models

SWITCHING SPECIFICATIONS

ADuM131xARWZ

ADuM131xBRWZ

≤ 3.6 V, 2.7 V ≤ V

DD1

Three Channels

1

≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

DD1

= V

= 3.0 V. All voltages are relative to their respective ground.

DD2

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.2 1.6 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.8 1.0 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Three Channels

1

3.4 4.9 mA 5 MHz logic signal frequency

DD1 (10)

1.1 1.3 mA 5 MHz logic signal frequency

DD2 (10)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.0 1.6 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.9 1.4 DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents

Logic High Input Threshold Logic Low Input Threshold

2.5 3.5 mA 5 MHz logic signal frequency

DD1 (10)

1.9 2.6 5 MHz logic signal frequency

DD2 (10)

, IIB, IIC, I

I

IA

I

CTRL2

V

IH

V

IL

OAH

OAL

, I

, V

DISABLE

OBH

, V

OBL

−10 +0.01 +10 μA

CTRL1

,

0 V ≤ V 0 V ≤ V 0 V ≤ V

1.6 V

0.4 V (V

or V

, V

DD1

OCH

(V

DD1

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

0.2 0.4 V I

) − 0.1 3.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

Ox

, VIB, VIC ≤ V

IA

, V

CTRL1

CTRL2

≤ V

DISABLE

= 4 mA, VIx = V

DD1

≤ V

IxL

IxH

DD1

IxH

Logic Low Output Voltages V

or V

DD1

Logic High Output Voltages V

or V

DD2

DD2,

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

Propagation Delay Skew5 t Channel-to-Channel Matching6 t

, t

20 100 ns CL = 15 pF, CMOS signal levels

PHL

PLH

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

|4 PWD 5 ns CL = 15 pF, CMOS signal levels

PHL

, t

20 30 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels

6

Channel-to-Channel Matching,

Opposing-Directional Channels

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

6

,

Rev. H | Page 5 of 24

ADuM1310/ADuM1311 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

7

|CMH| 25 35 kV/μs

|CML| 25 35 kV/μs

Refresh Rate fr 1.1 Mbps Input Enable Time8 t Input Disable Time8 t Input Supply Current per Channel,

Quiescent

Output Supply Current per Channel,

Quiescent

Input Dynamic Supply Current

per Channel

Output Dynamic Supply Current

per Channel

1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Input enable time is the duration from when V

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 13).

9

I

the same orientation as Channel A must be included to account for the total current consumed.

10

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in

DDx (Q)

9

DD1

10

and V

supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.

DD2

ENABLE

DISABLE

0.25 0.38 mA

I

DDI (Q)

0.19 0.33 mA

I

DDO (Q)

0.07

I

DDI (D)

I

0.02

DDO (D)

or t

that is measured between units at the same operating temperature, supply voltages, and output load

PHL

PLH

is set low until the output states are guaranteed to match the input states in the absence of any input data logic

DISABLE

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

2.0 μs VIA, VIB, VIC = 0 V or V

5.0 μs VIA, VIB, VIC = 0 V or V

mA/ Mbps

ower Consumption

Figure 9

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

Figure 8

DD1

DISABLE

is set high

Rev. H | Page 6 of 24

Data Sheet ADuM1310/ADuM1311

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

5 V/3 V operation: 4.5 V ≤ V minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T

= 25°C; V

A

= 3.0 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

ADuM1310, Total Supply Current,

Three Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.4 3.2 mA

3 V/5 V Operation 1.2 1.6 mA

V

Supply Current I

DD2

5 V/3 V Operation 0.8 1.0 mA

3 V/5 V Operation 1.2 1.6 mA

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 6.5 8.2 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.4 4.9 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 1.1 1.3 mA 5 MHz logic signal frequency 3 V/5 V Operation 1.9 2.2 mA 5 MHz logic signal frequency

ADuM1311, Total Supply Current,

Three Channels

1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 2.2 2.8 mA

3 V/5 V Operation 1.0 1.6 mA

V

Supply Current I

DD2

5 V/3 V Operation 0.9 1.4 mA

3 V/5 V Operation 1.8 2.4 mA

10 Mbps (BRWZ Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 4.5 5.7 mA 5 MHz logic signal frequency 3 V/5 V Operation 2.5 3.5 mA 5 MHz logic signal frequency

V

Supply Current I

DD2

5 V/3 V Operation 1.9 2.6 mA 5 MHz logic signal frequency 3 V/5 V Operation 3.5 4.3 mA 5 MHz logic signal frequency

For All Models

Input Currents

Logic High Input Threshold

V

= 5 V Operation 2.0 V

DDX

V

= 3 V Operation 1.6 V

DDX

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

, IIB, IIC, I

I

IA

I

CTRL2

V

IH

≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V

DD2

= 5 V, V

DD1

= 3.0 V. All voltages are relative to their respective ground.

DD2

≤ 3.6 V, 4.5 V ≤ V

DD1

DC to 1 MHz logic signal frequency

−10 +0.01 +10 μA

, I

DISABLE

CTRL1

,

0 V ≤ V 0 V ≤ V 0 V ≤ V

≤ 5.5 V; all

DD2

, VIB, VIC ≤ V

IA

, V

CTRL1

≤ V

DISABLE

CTRL2

DD1

≤ V

DD1

or V

DD1

or V

DD2

,

Rev. H | Page 7 of 24

ADuM1310/ADuM1311 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

Logic Low Input Threshold

V

= 5 V Operation 0.8 V

DDX

V

= 3 V Operation 0.4 V

DDX

Logic High Output Voltages V

Logic Low Output Voltages V

SWITCHING SPECIFICATIONS

ADuM131xARWZ

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion |t Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM131xBRWZ

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing-Directional Channels

For All Models

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 2.5 ns

3 V/5 V Operation 2.5 ns Common-Mode Transient

Immunity at Logic High Output

Common-Mode Transient

Immunity at Logic Low Output

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Enable Time8 t Input Disable Time8 t Input Supply Current per Channel,

Quiescent

V

DDX

V

DDX

9

= 5 V Operation I = 3 V Operation I

Output Supply Current per

Channel, Quiescent

V

= 5 V Operation I

DDX

V

= 3 V Operation I

DDX

Input Dynamic Supply Current per

Channel

V

10

= 5 V Operation 0.12

DDX

= 3 V Operation 0.07

DDX

PLH

− t

6

PHL

V

IL

, V

OAH

OBH

, V

OAL

OBL

, t

PHL

PLH

, V

(V

or V or V

) − 0.1 (V

DD2

) − 0.4 (V

DD2

OCH

DD1

(V

DD1

, V

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

0.2 0.4 V IOx = 4 mA, VIx = V

DD1

or V

) V IOx = −20 μA, VIx = V

DD2

or V

) − 0.2 V IOx = −4 mA, VIx = V

DD2

IxH

IxL

25 100 ns CL = 15 pF, CMOS signal levels

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

20 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

|4 PWD 5 ns CL = 15 pF, CMOS signal levels

PHL

30 ns CL = 15 pF, CMOS signal levels

PSK

5 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

6

= 15 pF, CMOS signal levels

L

|CMH| 25 35 kV/μs

7

|CML| 25 35 kV/μs

7

ENABLE

DISABLE

2.0 μs VIA, VIB, VIC, VID = 0 V or V

5.0 μs VIA, VIB, VIC, VID = 0 V or V

= V

or V

V

Ix

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

DD1

0.50 0.73 mA

DDI (Q)

0.25 0.38 mA

DDI (Q)

9

0.38 0.53 mA

DDO (Q)

0.19 0.33 mA

DDO (Q)

I

DDI (D)

mA/ Mbps

Rev. H | Page 8 of 24

ANALOG DEVICES ADUM1310 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION