Analog Devices ADuM1300 1 c Datasheet

G

G

Triple-Channel Digital Isolators

FEATURES

Low power operation

5 V operation

1.2 mA per channel max @ 0 Mbps to 2 Mbps

3.5 mA per channel max @ 10 Mbps
32 mA per channel max @ 90 Mbps

3 V operation

0.8 mA per channel max @ 0 Mbps to 2 Mbps

2.2 mA per channel max @ 10 Mbps

20 mA per channel max @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics

2 ns max pulse-width distortion

2 ns max channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
Wide body 16-lead SOIC package, Pb-free models available
Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000
V

= 560 V peak

IORM

APPLICATIONS

General-purpose multichannel isolation
SPI® interface/data converter isolation
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation

FUNCTIONAL BLOCK DIAGRAMS

ADuM1300/ADuM1301

GENERAL DESCRIPTION

The ADuM130x are 3-channel digital isolators based on Analog
Devices’ iCoupler® technology. Combining high speed CMOS
and monolithic transformer technology, these isolation compo­nents provide outstanding performance characteristics superior
to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discretes
is eliminated with these iCoupler products. Furthermore,
iCoupler devices consume one-tenth to one-sixth the power of
optocouplers at comparable signal data rates.

The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM130x provides low pulse-width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM130x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.

V

1

DD1

2

ND

1

V

V

V

NC

NC

ND

ENCODE DECODE

3

IA

ENCODE DECODE

4

IB

ENCODE DECODE

5

IC

6

7

8

1

V

16

DD2

GND

15

V

14

OA

V

13

OB

V

12

OC

NC

11

V

10

E2

GND

9

Figure 1. ADuM1300 Functional Block Diagram

2

2

03789-0-001

V

1

DD1

2

GND

1

ENCODE DECODE

3

IA

ENCODE DECODE

4

IB

5

DECODE ENCODE

6

7

E1

8

1

GND

V

V

V

OC

NC

V

Figure 2. ADuM1301 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

NC

10

OR V

V

E2

9

GND

2

03789-0-002

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADuM1300/ADuM1301

TABLE OF CONTENTS

Specifications..................................................................................... 3

ESD Caution................................................................................ 12

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 5

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation

Package Characteristics ............................................................. 10

Regulatory Information............................................................. 10

Insulation and Safety-Related Specifications.......................... 10

DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics

Recommended Operation Conditions ....................................11

Absolute Maximum Ratings.......................................................... 12

....................................................................................... 7

............................................................................ 11

REVISION HISTORY

6/04—Data Sheet Changed from Rev. B to Rev. C.

Changes to Format ............................................................. Universal

Changes to Features.......................................................................... 1

Changes to Electrical Characteristics—5 V Operation ............... 3

Changes to Electrical Characteristics—3 V Operation ............... 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation ............................................................................ 7

Changes to Ordering Guide.......................................................... 18

Pin Configurations and Pin Function Descriptions .................. 13

Typical Perfor m a n c e Character i stics ........................................... 14

Application Information................................................................ 16

PC Board Layout ........................................................................ 16

Propagation Delay-Related Parameters................................... 16

DC Correctness and Magnetic Field Immunity........................... 16

Power Consumption .................................................................. 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

5/04—Data Sheet Changed from Rev. A to Rev. B.

Changes to the Format.......................................................Universal

Changes to the Features................................................................... 1

Changes to Table 7 and Table 8..................................................... 14

Changes to Table 9.......................................................................... 15

Changes to the DC Correctness and Magnetic Field Immunity

Section.............................................................................................. 19

Changes to the Power Consumption Section ............................. 20

Changes to the Ordering Guide.................................................... 21

9/03—Data Sheet Changed from Rev. 0 to Rev. A.

Edits to Regulatory Information................................................... 13

Edits to Absolute Maximum Ratings ........................................... 15

Deleted the Package Branding Information................................ 16

Rev. C | Page 2 of 20

ADuM1300/ADuM1301

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V
wise noted; all typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I
Output Supply Current, per Channel, Quiescent I
ADuM1300, Total Supply Current, Three Channels2

ADuM1301, Total Supply Current, Three Channels2

For All Models

SWITCHING SPECIFICATIONS

ADuM130xARW

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-

DD2

= 25°C, V

A

DD1

DDI (Q)

DDO (Q)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (90)

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents

Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages

Logic Low Output Voltages V

Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching

3

4

5

5

– t

|

PLH

PHL

6

7

DD1 (90)

DD2 (90)

, IIB, IIC,

I

IA

I

E1

VIH, V
VIL, V
V

OAH

V

OCH

OAL

PW 1000 ns CL = 15 pF, CMOS signal levels
1 Mbps CL = 15 pF, CMOS signal levels
t

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels
t

PSK

t

PSKCD/OD

1

= V

= 5 V.

DD2

0.50 0.53 mA

0.19 0.21 mA

1.6 2.5 mA DC to 1 MHz logic signal freq.

0.7 1.0 mA DC to 1 MHz logic signal freq.

6.5 8.1 mA 5 MHz logic signal freq.

1.9 2.5 mA 5 MHz logic signal freq.

57 77 mA 45 MHz logic signal freq.
16 18 mA 45 MHz logic signal freq.

1.3 2.1 mA DC to 1 MHz logic signal freq.

1.0 1.4 mA DC to 1 MHz logic signal freq.

5.0 6.2 mA 5 MHz logic signal freq.

3.4 4.2 mA 5 MHz logic signal freq.

43 57 mA 45 MHz logic signal freq.
29 37 mA 45 MHz logic signal freq.

–10 +0.01 +10 µA

, I

E2

2.0 V

0.8 V
V

,

V

0.0 0.1 V IOx = 20 µA, VIx = V

, V

OCL

– 0.1 5.0 V IOx = –20 µA, VIx = V

DD1, VDD2

– 0.4 4.8 V IOx = –4 mA, VIx = V

DD1, VDD2

, V

, V

EH

EL

OBH

OBL

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

, t

PLH

50 65 100 ns CL = 15 pF, CMOS signal levels

0 ≤ V
0 ≤ V

, VIB, VIC ≤ V

IA

, VE2 ≤ V

E1

DD1

DD1

or V

IxH

IxH

IxL

IxL

IxL

or V

DD2

DD2

,

50 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels

Rev. C | Page 3 of 20

ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM130xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing-Directional Channels

7

7

ADuM130xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing-Directional Channels

7

7

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance)
Output Enable Propagation Delay

(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/t
Common-Mode Transient Immunity at

Logic High Output

Common-Mode Transient Immunity at

Logic Low Output

8

8

Refresh Rate f
Input Dynamic Supply Current, per Channel

9

Output Dynamic Supply Current, per Channel9 I

1

All voltages are relative to their respective ground.

2

The supply current values for all three channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on
Page 17. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See
through for total I

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 17 for guidance on calculating the per-channel
supply current for a given data rate.

Figure 6

Figure 12

Figure 8
and I

DD1

supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

DD2

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

PHL

, t

PLH

20 32 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

15 ns CL = 15 pF, CMOS signal levels
3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

18 27 32 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

, t

t

PHZ

PLH

, t

t

PZH

PZL

F

|CMH| 25 35 kV/µs

10 ns CL = 15 pF, CMOS signal levels
2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

2.5 ns CL = 15 pF, CMOS signal levels
= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

I

DDI (D)

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

1.2 Mbps

0.19 mA/Mbps

0.05 mA/Mbps

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Figure 8

Figure 9

Rev. C | Page 4 of 20

ADuM1300/ADuM1301

= V

, IIB, I
, I

E2

EH

EL

, V

OAH

OCH

, V

OAL

, t

PHL

PLH

PSK

PSKCD/OD

IC,

DD2

OBH

OBL

1

= 3.0 V.

0.26 0.31 mA

0.11 0.14 mA

0.9 1.7 mA DC to 1 MHz logic signal freq.

0.4 0.7 mA DC to 1 MHz logic signal freq.

3.4 4.9 mA 5 MHz logic signal freq.

1.1 1.6 mA 5 MHz logic signal freq.

31 48 mA 45 MHz logic signal freq.
8 13 mA 45 MHz logic signal freq.

0.7 1.4 mA DC to 1 MHz logic signal freq.

0.6 0.9 mA DC to 1 MHz logic signal freq.

2.6 3.7 mA 5 MHz logic signal freq.

1.8 2.5 mA 5 MHz logic signal freq.

24 36 mA 45 MHz logic signal freq.
16 23 mA 45 MHz logic signal freq.

–10 +0.01 +10 µA

0 ≤ V
0 ≤ V

, VIB, VIC ≤ V

IA

≤ V

E1,VE2

1.6 V

0.4 V
V

,

V

0.0 0.1 V IOx = 20 µA, VIx = V

, V

OCL

– 0.1 3.0 V IOx = –20 µA, VIx = V

DD1, VDD2

– 0.4 2.8 V IOx = –4 mA, VIx = V

DD1, VDD2

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

50 75 100 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels

DD1

DD1

or V

IxH

IxL

IxL

or V

IxH

IxL

DD2

DD2

,

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V
wise noted; all typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I
Output Supply Current, per Channel, Quiescent I
ADuM1300, Total Supply Current, Three Channels2

ADuM1301, Total Supply Current, Three Channels2

For All Models

SWITCHING SPECIFICATIONS

ADuM130xARW

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-

DD2

= 25°C, V

A

DD1

DDI (Q)

DDO (Q)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (90)

DD2 (90)

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

Input Currents

Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages

DD1 (90)

DD2 (90)

I

IA

I

E1

VIH, V
VIL, V
V

V

Logic Low Output Voltages V

Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching

3

4

5

5

– t

|

PLH

PHL

6

7

PW 1000 ns CL = 15 pF, CMOS signal levels
1 Mbps CL = 15 pF, CMOS signal levels
t
PWD 40 ns CL = 15 pF, CMOS signal levels
t
t

Rev. C | Page 5 of 20

ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM130xBRW

Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing-Directional Channels

7

7

ADuM130xCRW

Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
Pulse-Width Distortion, |t

PLH

– t

PHL

5

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing-Directional Channels

7

7

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance)
Output Enable Propagation Delay

(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%) tR/t
Common-Mode Transient Immunity at

Logic High Output
Common-Mode Transient Immunity at

Logic Low Output

8

8

Refresh Rate f
Input Dynamic Supply Current, per Channel

9

Output Dynamic Supply Current, per Channel9 I

1

All voltages are relative to their respective ground.

2

The supply current values for all three channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on
Page 17. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See
through for total I

3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

6

t

is the magnitude of the worst-case difference in t

PSK

within the recommended operating conditions.

7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 17 for guidance on calculating the per-channel
supply current for a given data rate.

Figure 6

Figure 12

DD1

and I

Figure 8

supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

PLH

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

PHL

, t

PLH

20 38 50 ns CL = 15 pF, CMOS signal levels

PWD 3 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

PHL

, t

PLH

26 ns CL = 15 pF, CMOS signal levels
3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

20 34 45 ns CL = 15 pF, CMOS signal levels

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD

t

PSKOD

, t

t

PHZ

PLH

, t

t

PZH

PZL

F

|CMH| 25 35 kV/µs

16 ns CL = 15 pF, CMOS signal levels
2 ns CL = 15 pF, CMOS signal levels

5 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

6 8 ns CL = 15 pF, CMOS signal levels

3 ns CL = 15 pF, CMOS signal levels

= V

V

Ix

DD1/VDD2

, VCM = 1000 V,

transient magnitude = 800 V

|CML| 25 35 kV/µs

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

I

DDI (D)

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

1.1 Mbps

0.10 mA/Mbps

0.03 mA/Mbps

propagation delay is

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Figure 8

Figure 9

Rev. C | Page 6 of 20