ANALOG DEVICES ADUM1300 Service Manual

G

Triple-Channel Digital Isolators

Data Sheet

FEATURES

Qualified for automotive applications Low power operation

5 V operation

1.2 mA per channel maximum @ 0 Mbps to 2 Mbps

3.5 mA per channel maximum @ 10 Mbps 32 mA per channel maximum @ 90 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

2.2 mA per channel maximum @ 10 Mbps

20 mA per channel maximum @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics

2 ns maximum pulse width distortion

2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body package RoHS-compliant models available

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V

= 560 V peak

IORM

TÜV approval: IEC/EN/UL/CSA 61010-1

APPLICATIONS

General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Automotive systems

ADuM1300/ADuM1301

GENERAL DESCRIPTION

The ADuM130x1 are triple-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives, such as optocouplers.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth of the power of optocouplers at comparable signal data rates.

The ADuM130x isolators provide three independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM130x provide low pulse width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM130x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the supplies.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.

FUNCTIONAL BLOCK DIAGRAMS

1

V

DD1

2

ND

1

ENCODE DECODE

3

V

IA

4

V

NC

ND

ENCODE DECODE

IB

5

ENCODE DECODE

IC

6

7

8

1

Figure 1. ADuM1300 Functional Block Diagram

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

OC

11

NC

10

V

E2

9

GND

2

03787-001

1

V

DD1

2

GND

1

ENCODE DECODE

3

V

IA

4

ENCODE DECODE

IB

5

DECODE ENCODE

6

7

E1

8

1

GND

V

OC

NC

V

Figure 2. ADuM1301 Functional Block Diagram

16

V

DD2

15

GND

2

14

V

OA

13

V

OB

12

V

IC

11

NC

10

V

E2

9

GND

2

03787-002

ADuM1300/ADuM1301 Data Sheet

REVISION HISTORY

3/12—Rev. H to Rev. I

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section .................................................................1

Change to PC Board Layout Section ............................................25

Updated Outline Dimensions........................................................28

Moved Automotive Products Section...........................................28

5/08—Rev. G to Rev. H

Added ADuM1300W and ADuM1301W Parts............. Universal

Changes to Features List...................................................................1

Added Table 4 ..................................................................................11

Added Table 5 ..................................................................................13

Added Table 6 ..................................................................................15

Added Table 7 ..................................................................................17

Changes to Table 12 ........................................................................20

Changes to Table 13 ........................................................................21

Added Automotive Products Section ...........................................27

Changes to Ordering Guide...........................................................28

11/07—Rev. F to Rev. G

Changes to Note 1 and Figure 2 ......................................................1

Added ADuM130xARW Change vs. Temperature Parameter ...3 Added ADuM130xARW Change vs. Temperature Parameter ...5 Added ADuM130xARW Change vs. Temperature Parameter ...8

Changes to Figure 14 ......................................................................16

6/07—Rev. E to Rev. F

Updated VDE Certification Throughout.......................................1

Changes to Features, Note 1, Figure 1, and Figure 2 ....................1

Changes to Regulatory Information Section...............................10

Added Table 10 ................................................................................12

Added Insulation Lifetime Section ...............................................17

Updated Outline Dimensions........................................................19

Changes to Ordering Guide...........................................................19

2/06—Rev. D to Rev. E

Updated Format ................................................................. Universal

Added TÜV Approval .......................................................Universal

Changes to Figure 2 ..........................................................................1

5/05—Rev. C to Rev. D

Changes to Format............................................................. Universal

Changes to Figure 2 ..........................................................................1

Changes to Table 6 ..........................................................................10

Changes to Ordering Guide...........................................................18

6/04—Rev. B to Rev. C

Changes to Format............................................................. Universal

Changes to Features.......................................................................... 1

Changes to Electrical Characteristics—5 V Operation................3

Changes to Electrical Characteristics—3 V Operation................5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation ............................................................................7

Changes to Ordering Guide...........................................................18

5/04—Rev. A to Rev. B

Changes to the Format...................................................... Universal

Changes to the Features....................................................................1

Changes to Table 7 and Table 8.....................................................14

Changes to Table 9 ..........................................................................15

Changes to the DC Correctness and Magnetic Field Immunity

Section ..............................................................................................19

Changes to the Power Consumption Section..............................20

Changes to the Ordering Guide....................................................21

9/03—Rev. 0 to Rev. A

Edits to Regulatory Information...................................................13

Edits to Absolute Maximum Ratings............................................15

Deleted the Package Branding Information ................................16

9/03—Revision 0: Initial Version

Rev. I | Page 3 of 32

ADuM1300/ADuM1301 Data Sheet

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1300 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM1301 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V (V Logic Low Output Voltages V

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM130xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 t Channel-to-Channel Matching6 t

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

VIH, V VIL, V

OAH

, V

OAL

, t

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 5 V. These

DD2

0.50 0.53 mA

0.19 0.24 mA

1.6 2.5 mA DC to 1 MHz logic signal freq.

0.7 1.0 mA DC to 1 MHz logic signal freq.

6.5 8.1 mA 5 MHz logic signal freq.

1.9 2.5 mA 5 MHz logic signal freq.

57 77 mA 45 MHz logic signal freq. 16 18 mA 45 MHz logic signal freq.

1.3 2.1 mA DC to 1 MHz logic signal freq.

1.0 1.4 mA DC to 1 MHz logic signal freq.

5.0 6.2 mA 5 MHz logic signal freq.

3.4 4.2 mA 5 MHz logic signal freq.

43 57 mA 45 MHz logic signal freq. 29 37 mA 45 MHz logic signal freq.

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ V

E2

EH

EL

, V

OBH

OBL

50 65 100 ns CL = 15 pF, CMOS signal levels

PLH

2.0 V

0.8 V

, V

(V

or V

OCH

DD1

, V

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

) − 0.1 5.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 4.8 V IOx = −4 mA, VIx = V

DD2

0 V ≤ V

, VE2 ≤ V

E1

DD1

IxL

DD1

or V

IxH

IxL

or V

DD2

50 ns CL = 15 pF, CMOS signal levels

,

DD2

Rev. I | Page 4 of 32

Data Sheet ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM130xBRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PW 100 ns C 10 Mbps C

, t

20 32 50 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

6

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

ADuM130xCRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PW 8.3 11.1 ns C 90 120 Mbps C

, t

18 27 32 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

10 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

6

t

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

For All Models

Output Disable Propagation Delay (High/Low

t

PHZ

, t

PLH

6 8 ns CL = 15 pF, CMOS signal levels

to High Impedance)

Output Enable Propagation Delay (High

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic

High Output Common-Mode Transient Immunity at Logic

Low Output

7

|CM

| 25 35 kV/μs VIx = V

H

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the V

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.19 mA/Mbps

DDI (D)

0.05 mA/Mbps

I

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Power Consumption

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

Power Consumption

Figure 9

propagation delay is

PLH

Figure 8

Rev. I | Page 5 of 32

ADuM1300/ADuM1301 Data Sheet

ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ V over the entire recommended operation range, unless otherwise noted; all typical specifications are at T These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I Output Supply Current per Channel, Quiescent I ADuM1300 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

ADuM1301 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages V (V Logic Low Output Voltages V

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM130xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching6 t

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

VIH, V VIL, V

OAH

OAL

PHL

PWD 40 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V; all minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.26 0.31 mA

0.11 0.15 mA

0.9 1.7 mA DC to 1 MHz logic signal freq.

0.4 0.7 mA DC to 1 MHz logic signal freq.

3.4 4.9 mA 5 MHz logic signal freq.

1.1 1.6 mA 5 MHz logic signal freq.

31 48 mA 45 MHz logic signal freq. 8 13 mA 45 MHz logic signal freq.

0.7 1.4 mA DC to 1 MHz logic signal freq.

0.6 0.9 mA DC to 1 MHz logic signal freq.

2.6 3.7 mA 5 MHz logic signal freq.

1.8 2.5 mA 5 MHz logic signal freq.

24 36 mA 45 MHz logic signal freq. 16 23 mA 45 MHz logic signal freq.

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ V

E2

EH

EL

, V

OBH

, V

OBL

, t

50 75 100 ns CL = 15 pF, CMOS signal levels

PLH

1.6 V

0.4 V

, V

(V

or V

OCH

DD1

, V

0.0 0.1 V IOx = 20 μA, VIx = V

OCL

) − 0.1 3.0 V IOx = −20 μA, VIx = V

DD2

or V

) − 0.4 2.8 V IOx = −4 mA, VIx = V

DD2

0 V ≤ V

, VE2 ≤ V

E1

DD1

IxL

DD1

or V

IxH

IxL

or V

DD2

50 ns CL = 15 pF, CMOS signal levels

,

Rev. I | Page 6 of 32

Data Sheet ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM130xBRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PW 100 ns C 10 Mbps C

, t

20 38 50 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

26 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

6

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

6 ns CL = 15 pF, CMOS signal levels

t

PSKOD

ADuM130xCRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

PW 8.3 11.1 ns C 90 120 Mbps C

, t

20 34 45 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

16 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels

Channel-to-Channel Matching, Opposing-

Directional Channels

6

For All Models

Output Disable Propagation Delay (High/Low to

t

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

t

, t

PHZ

PLH

6 8 ns CL = 15 pF, CMOS signal levels

High Impedance)

Output Enable Propagation Delay (High

t

, t

6 8 ns CL = 15 pF, CMOS signal levels

PZH

PZL

Impedance to High/Low) Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at

Logic High Output Common-Mode Transient Immunity at

Logic Low Output

7

|CM

| 25 35 kV/μs VIx = V

H

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8 I Output Dynamic Supply Current per Channel8

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. See through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through

Figure 6

Figure 12

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

measured from the 50% level of the rising edge of the V

5

t

within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

for total V

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

is the magnitude of the worst-case difference in t

PSK

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current for a given data rate.

DD1

and V

supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

DD2

signal to the 50% level of the rising edge of the VOx signal.

Ix

or t

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

0.10 mA/Mbps

DDI (D)

0.03 mA/Mbps

I

DDO (D)

that is measured between units at the same operating temperature, supply voltages, and output load

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 6

Power Consumption

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

or V

DD1

, VCM = 1000 V,

DD2

transient magnitude = 800 V

Power Consumption

Figure 9

propagation delay is

PLH

Figure 8

Rev. I | Page 7 of 32

ADuM1300/ADuM1301 Data Sheet

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V

2.7 V ≤ V

≤ 3.6 V, 4.5 V ≤ V

DD1

unless otherwise noted; all typical specifications are at T

≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C; V

A

= 3.0 V, V

DD1

tions do not apply to ADuM1300W and ADuM1301W automotive grade versions.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA

Output Supply Current per Channel, Quiescent I

5 V/3 V Operation 0.11 0.15 mA 3 V/5 V Operation 0.19 0.24 mA

ADuM1300 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.6 2.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.7 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.4 0.7 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.7 1.0 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 6.5 8.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.9 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.1 1.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.9 2.5 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 57 77 mA 45 MHz logic signal freq. 3 V/5 V Operation 31 48 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 8 13 mA 45 MHz logic signal freq. 3 V/5 V Operation 16 18 mA 45 MHz logic signal freq.

ADuM1301 Total Supply Current, Three Channels1

DC to 2 Mbps

V

Supply Current I

DD1

5 V/3 V Operation 1.3 2.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.7 1.4 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 0.6 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V

Supply Current I

DD1

5 V/3 V Operation 5.0 6.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.7 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 1.8 2.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.2 mA 5 MHz logic signal freq.

DDI (Q)

DDO (Q)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

DD1 (90)

DD2 (90)

DD1 (Q)

DD2 (Q)

DD1 (10)

DD2 (10)

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5 V or V

DD2

= 5 V, V

DD1

≤ 3.6 V; 3 V/5 V operation:

DD2

= 3.0 V. These specifica-

DD2

Rev. I | Page 8 of 32

Data Sheet ADuM1300/ADuM1301

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 43 57 mA 45 MHz logic signal freq. 3 V/5 V Operation 24 36 mA 45 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 16 23 mA 45 MHz logic signal freq. 3 V/5 V Operation 29 37 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC, IE1, I

Logic High Input Threshold

5 V/3 V Operation 2.0 V

3 V/5 V Operation 1.6 V Logic Low Input Threshold

5 V/3 V Operation 0.8 V

3 V/5 V Operation 0.4 V Logic High Output Voltages V (V Logic Low Output Voltages V

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM130xARW

Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching6 t

ADuM130xBRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional

Channels Channel-to-Channel Matching, Opposing-

Directional Channels

6

ADuM130xCRW

Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |t

PLH

− t

PHL

4

|

Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing-Directional Channels

6

DD1 (90)

DD2 (90)

−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ V

E2

VIH, V

VIL, V

OAH

OAL

PHL

EH

EL

, V

OBH

, V

OBL

, t

PLH

, V

OCL

or V

OCH(VDD1

DD1

or V

) − 0.1 (V

DD2

) − 0.4 (V

DD2

DD1

or V

) V IOx = −20 μA, VIx = V

DD2

or V

) − 0.2 V IOx = −4 mA, VIx = V

DD2

0.0 0.1 V IOx = 20 μA, VIx = V

50 70 100 ns CL = 15 pF, CMOS signal levels

0 V ≤ V

, VE2 ≤ V

E1

DD1

IxL

DD1

or V

IxH

IxL

or V

DD2

PWD 40 ns CL = 15 pF, CMOS signal levels

50 ns CL = 15 pF, CMOS signal levels

PSK

PSKCD/tPSKOD

PW 100 ns C 10 Mbps C t

PHL

50 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

, t

15 35 50 ns CL = 15 pF, CMOS signal levels

PLH

PWD 3 ns CL = 15 pF, CMOS signal levels

6 ns CL = 15 pF, CMOS signal levels

t

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

22 ns CL = 15 pF, CMOS signal levels

t

PSKOD

PW 8.3 11.1 ns C 90 120 Mbps C

, t

20 30 40 ns CL = 15 pF, CMOS signal levels

t

PHL

PLH

= 15 pF, CMOS signal levels

L

= 15 pF, CMOS signal levels

L

PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

14 ns CL = 15 pF, CMOS signal levels

t

PSK

2 ns CL = 15 pF, CMOS signal levels

t

PSKCD

5 ns CL = 15 pF, CMOS signal levels

t

PSKOD

,

Rev. I | Page 9 of 32

ADuM1300/ADuM1301 Data Sheet

Parameter Symbol Min Typ Max Unit Test Conditions

For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

Output Enable Propagation Delay (High

Impedance to High/Low)

Output Rise/Fall Time (10% to 90%) tR/tF C

5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity at

Logic High Output

Common-Mode Transient Immunity at

Logic Low Output

7

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current per Channel8 I

5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps

Output Dynamic Supply Current per Channel8

5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps

1

The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the P section. See through

for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Fi for total V

Figure 8 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation

barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See F through for information on

per-channel supply current for unloaded and loaded conditions. See the P section for guidance on calculating the per-channel supply current for a given data rate.

t

, t

PHZ

PLH

t

, t

PZH

PZL

|CM

| 25 35 kV/μs VIx = V

H

6 8 ns CL = 15 pF, CMOS signal levels

= 15 pF, CMOS signal levels

L

or V

DD1

transient magnitude = 800 V

|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

DDI (D)

I

DDO (D)

ower Consumption

Figure 9 gure 12

propagation delay is measured

PLH

or t

that is measured between units at the same operating temperature, supply voltages, and output load within the

PHL

PLH

. CML is the maximum common-mode voltage slew rate that can be

DD2

ower Consumption

igure 6

Figure 8

, VCM = 1000 V,

DD2

Figure 6

and V

DD1

DD2

Rev. I | Page 10 of 32

ANALOG DEVICES ADUM1300 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION

ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION