High side or low side relative to input: ±700 V
High side/low side differential: 700 V
PEAK
0.1 A peak output current
High frequency operation: 5 MHz maximum
High common-mode transient immunity: >75 kV/μs
High temperature operation: 105°C
Wide body, 16-lead SOIC
UL1577 2500 V rms input-to-output withstand voltage
The ADuM12331 is an isolated, half-bridge gate driver that
employs the Analog Devices, Inc. iCoupler® technology to
provide independent and isolated high-side and low-side
outputs. Combining high speed CMOS and monolithic
transformer technology, this isolation component provides
outstanding performance characteristics superior to
optocoupler-based solutions.
By avoiding the use of LEDs and photodiodes, this iCoupler
gate drive device is able to provide precision timing characteristics
not possible with optocouplers. Furthermore, the reliability and
performance stability problems associated with optocoupler
LEDs are avoided.
In comparison to gate drivers employing high voltage level
translation methodologies, the ADuM1233 offers the benefit of
true, galvanic isolation between the input and each output. Each
output can be operated up to ±700 V
thereby supporting low-side switching to negative voltages. The
differential voltage between the high side and low side can be as
high as 700 V
PEAK
.
As a result, the ADuM1233 provides reliable control over the
switching characteristics of IGBT/MOSFET configurations over
a wide range of positive or negative switching voltages.
relative to the input,
PEAK
FUNCTIONAL BLOCK DIAGRAM
116
V
IA
215
V
IB
314
V
DD1
413
GND
1
DISABLE
5
6
NC
7
NC
8
V
DD1
1
Protected by U.S. Patents 5,952,849 and 6,291,907.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
All voltages are relative to their respective ground. 4.5 V ≤ V
specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T
V
= 5 V, V
DD1
= 15 V, V
DDA
= 15 V.
DDB
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent I
Output Supply Current A or Output Supply
DDI(Q)
I
DDA(Q)
Current B, Quiescent
Input Supply Current, 10 Mbps I
Output Supply Current A or Output Supply
DDI(10)
I
DDA(10)
Current B, 10 Mbps
Input Currents IIA, IIB, I
Logic High Input Threshold VIH 2.0 V
Logic Low Input Threshold VIL 0.8 V
Logic High Output Voltages V
Logic Low Output Voltages V
Output Short-Circuit Pulsed Current
1
OAH,VOBH
OAL,VOBL
I
OA(SC)
SWITCHING SPECIFICATIONS
Minimum Pulse Width
Maximum Switching Frequency
Propagation Delay
2
3
4
PW 100 ns CL = 200 pF
10 Mbps CL = 200 pF
t
PHL
Change vs. Temperature 100 ps/°C CL = 200 pF
Pulse Width Distortion, |t
Channel-to-Channel Matching,
Rising or Falling Edges
Channel-to-Channel Matching,
Rising vs. Falling Edges
Part-to-Part Matching, Rising or Falling Edges
Part-to-Part Matching, Rising vs. Falling Edges
PLH
5
− t
| PWD 8 ns CL = 200 pF
PHL
5 ns CL = 200 pF
6
13 ns CL = 200 pF
7
55 ns CL = 200 pF, Input tR = 3 ns
8
63 ns CL = 200 pF, Input tR = 3 ns
Output Rise/Fall Time (10% to 90%) tR/tF 25 ns CL = 200 pF
1
Short-circuit duration less than 1 second.
2
The minimum pulse width is the shortest pulse width at which the specified timing parameters are guaranteed.
3
The maximum switching frequency is the maximum signal frequency at which the specified timing parameters are guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the V
5
Channel-to-channel matching, rising or falling edges is the magnitude of the propagation delay difference between two channels of the same part when the inputs
are either both rising or falling edges. The supply voltages and the loads on each channel are equal.
6
Channel-to-channel matching, rising vs. falling edges is the magnitude of the propagation delay difference between two channels of the same part when one input is
a rising edge and the other input is a falling edge. The supply voltages and loads on each channel are equal.
7
Part-to-part matching, rising or falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when the inputs
are either both rising or falling edges. The supply voltages, temperatures, and loads of each part are equal.
8
Part-to-part matching, rising vs. falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when one input
is a rising edge and the other input is a falling edge. The supply voltages, temperatures, and loads of each part are equal.
signal to the 50% level of the rising edge of the VOx signal.
Ix
≤ 5.5 V, 12 V ≤ V
DD1
≤ 18 V, 12 V ≤ V
DDA
≤ 18 V. All min/max
DDB
3.0 4.2 mA
, I
0.3 1.2 mA
DDB(Q)
6.0 9.0 mA
, I
16 22 mA CL = 200 pF
DDB(10)
DISABLE
−10 +0.01 +10 μA 0 ≤ VIA, VIB, V
− 0.1,
V
DDA
− 0.1
V
DDB
, V
V
DDA
V IOA, I
DDB
0.1 V IOA, I
, I
100 mA
OB(SC)
, t
97 124 160 ns CL = 200 pF
PLH
= 25°C,
A
DISABLE
= −1 mA
OB
= +1 mA
OB
propagation delay is
PLH
≤ V
DD1
Rev. A | Page 3 of 12
Page 4
ADuM1233
PACKAGE CHARACTERISTICS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-to-Output)
Capacitance (Input-to-Output)
Input Capacitance CI 4.0 pF
IC Junction-to-Ambient Thermal Resistance θJA 76 °C/W
1
The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
REGULATORY INFORMATION
The ADuM1233 has been approved by the organization listed in Tabl e 3.
Table 3.
1
UL
Recognized under 1577 component recognition program
1
In accordance with UL1577, each ADuM1233 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm
Minimum External Tracking (Creepage) L(I02) 8.1 min mm
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
1
1
R
1012 Ω
I-O
C
2.0 pF f = 1 MHz
I-O
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
RECOMMENDED OPERATING CONDITIONS
Table 5.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +105 °C
Input Supply Voltage
Output Supply Voltages
Input Signal Rise and Fall Times 100 ns
Common-Mode Transient Immunity, Input-to-Output
Common-Mode Transient Immunity, Between Outputs
Transient Immunity, Supply Voltages
1
All voltages are relative to their respective ground.
2
See the Common-Mode Transient Immunity section for additional data.
1
1
2
2
2
Rev. A | Page 4 of 12
V
4.5 5.5 V
DD1
V
, V
DDA
12 18
DDB
−75 +75 kV/μs
−75 +75 kV/μs
−75 +75 kV/μs
Page 5
ADuM1233
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
Storage Temperature (TST) −55°C to +150°C
Ambient Operating Temperature (TA) −40°C to +105°C
Input Supply Voltage (V
Output Supply Voltage1 (V
Input Voltage1 (VIA, VIB)
Output Voltage
1
VOA −0.5 V to V
VOB −0.5 V to V
Input-to-Output Voltage
Output Differential Voltage
DD1
1
)
DDA
, V
DDB
)
−0.5 V to +7.0 V
−0.5 V to +27 V
−0.5 V to V
+ 0.5 V
DDI
+ 0.5
DDA
+ 0.5 V
PEAK
PEAK
DDB
to +700 V
PEAK
2
3
−700 V
700 V
Output DC Current (IOA, IOB) −20 mA to +20 mA
Common-Mode Transients
1
All voltages are relative to their respective ground.
2
Input-to-output voltage is defined as GNDA − GND1 or GNDB − GND1.
3
Output differential voltage is defined as GNDA − GNDB.
4
Refers to common-mode transients across any insulation barrier. Common-
mode transients exceeding the Absolute Maximum Ratings may cause
latch-up or permanent damage.
4
−100 kV/μs to +100 kV/μs
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 12
Page 6
ADuM1233
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
V
V
DD1
GND
DISABLE
NC
NC
V
DD1
1
IA
2
IB
3
ADuM1233
4
1
TOP VIEW
(Not to Scale)
5
6
7
8
NC = NO CONNECT
V
16
DDA
V
15
OA
GND
14
A
NC
13
12
NC
11
V
DDB
V
10
OB
GND
9
B
06271-002
Figure 2. Pin Configuration
Table 7. ADuM1233 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
2 V
1
31, 8
IA
IB
V
DD1
4 GND
1
Logic Input A.
Logic Input B.
Input Supply Voltage, 4.5 V to 5.5 V.
Ground Reference for Input Logic Signals.
5 DISABLE Input Disable. Disables the isolator inputs and refresh circuits. Outputs take on default low state.
6, 7, 122, 132NC No Connect.
9 GND
B
Ground Reference for Output B.
10 VOB Output B.
11 V
Output B Supply Voltage, 12 V to 18 V.
DDB
14 GNDA Ground Reference for Output A.
15 VOA Output A.
16 V
1
Pin 3 and Pin 8 are internally connected. Connecting both pins to V
2
Pin 12 and Pin 13 are floating and should be left unconnected.
Output A Supply Voltage, 12 V to 18 V.
DDA
is recommended.
DD1
Table 8. Truth Table (Positive Logic)
VIA/VIB Input V
State DISABLE VOA/VOB Output Notes
DD1
H Powered L H
L Powered L L
X Unpowered X L Output returns to input state within 1 μs of V
X Powered H L
power restoration.
DD1
Rev. A | Page 6 of 12
Page 7
ADuM1233
G
A
A
G
A
A
G
A
A
TYPICAL PERFOMANCE CHARACTERISTICS
7
115
6
5
4
3
2
INPUT CURRENT (mA)
1
0
DATA RATE (Mbps)
Figure 3. Typical Input Supply Current Variation with Data Rate
18
16
14
12
10
8
6
OUTPUT CURRENT (mA)
4
2
0
DATA RATE (Mbps)
Figure 4. Typical Output Supply Current Variation with Data Rate
120
114
113
Y (ns)
112
TION DEL
111
PROPA
110
1004
06271-006
109
CH. B, FALLING EDG E
CH. A, FALLING EDGE
CH. A, RISING EDG E
CH. B, RISING EDGE
OUTPUT SUPPLY VOLTAGE (V)
181215
06271-009
Figure 6. Typical Propagation Delay Variation with Output Supply Voltage
(Input Supply Voltage = 5.0 V)
115
114
113
Y (ns)
112
TION DEL
111
PROPA
110
1004
06271-007
109
CH. B, FALLING EDG E
INPUT SUPPLY VOLTAGE (V)
CH. A, FALLING EDGE
CH. A, RISING EDG E
CH. B, RISING EDGE
5.54.55.0
06271-010
Figure 7. Typical Propagation Delay Variation with Input Supply Voltage
(Output Supply Voltage = 15.0 V)
115
Y (ns)
110
TION DEL
105
PROPA
100
TEMPERATURE (°C)
120–40020–20406080100
06271-008
Figure 5. Typical Propagation Delay Variation with Temperature
Rev. A | Page 7 of 12
Page 8
ADuM1233
APPLICATION NOTES
COMMON-MODE TRANSIENT IMMUNITY
In general, common-mode transients consist of linear and
sinusoidal components. The linear component of a commonmode transient is given by
V
where ΔV/Δt is the slope of the transient shown in
and
Figure 12.
The transient of the linear component is given by
dV
The ability of the ADuM1233 to operate correctly in the
presence of linear transients is characterized by the data in
Figure 8. The data is based on design simulation and is the
maximum linear transient magnitude that the ADuM1233 can
tolerate without an operational error. This data shows a higher
level of robustness than what is listed in
transient immunity values obtained in
data and apply allowances for measurement error and margin.
TRANSIENT IMMUNITY (kV/µs)
The sinusoidal component (at a given frequency) is given by
V
where:
is the magnitude of the sinusoidal.
V
0
f is the frequency of the sinusoidal.
= (ΔV/Δt) t
CM, linear
Figure 11
/dt = ΔV/Δt
CM
Table 5 because the
Tabl e 5 use measured
400
350
300
250
200
150
100
50
0
WORST-CASE PROCESS VARIATION
Figure 8. Transient Immunity (Linear Transients) vs. Temperature
CM, sinusoidal
= V0sin(2πft)
BEST-CASE PROCESS VARIATI ON
100–4004080–202060
TEMPERATURE (° C)
06271-011
The transient magnitude of the sinusoidal component is given by
/dt = 2πf V0.
dV
CM
The ability of the ADuM1233 to operate correctly in the
presence of sinusoidal transients is characterized by the data in
Figure 9 and Figure 10. The data is based on design simulation
and is the maximum sinusoidal transient magnitude (2πf V
)
0
that the ADuM1233 can tolerate without an operational error.
Values for immunity against sinusoidal transients are not
included in
Tabl e 5 because measurements to obtain such values
CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013- AA
Figure 14. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
No. of
Model
ADuM1233BRWZ
Channels
1
2 0.1 15 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM1233BRWZ-RL12 0.1 15 −40°C to +105°C
1
Z = RoHS Compliant Part.
Output Peak
Current (A)
Output
Voltage (V)
Temperature Range Package Description
5
(
0
.
0
2
9
5
.
7
.
2
5
(
0
)
0
0
9
8
)
.
1.27 (0.0500)
0.40 (0.0157)
45°
030707-B
0
0
16-Lead SOIC_W, 13-inch Tape
and Reel Option (1,000 Units)