ANALOG DEVICES ADUM1210 Service Manual

Dual-Channel Digital Isolator

Data Sheet

FEATURES

Narrow body, RoHS-compliant, 8-lead SOIC
Low power operation

5 V operation

1.1 mA per channel maximum @ 0 Mbps to 2 Mbps

3.7 mA per channel maximum @ 10 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

2.2 mA per channel maximum @ 10 Mbps
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 10 Mbps (NRZ)
Precise timing characteristics

3 ns maximum pulse width distortion

3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs

Safety and regulatory approvals

UL recognition

2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

V

= 560 V peak

IORM

APPLICATIONS

Size-critical multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation
Digital field bus isolation
Gate drive interface

ADuM1210

GENERAL DESCRIPTION

The ADuM12101 is a dual-channel, digital isolator based on
Analog Devices, Inc., iCoupler® technology. Combining high
speed CMOS and monolithic transformer technology, this
isolation component provides outstanding performance
characteristics superior to alternatives such as optocoupler
devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto­couplers. The concerns of the typical optocoupler regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with iCoupler products. Furthermore,
iCoupler devices consume one-tenth to one-sixth the power of
optocouplers at comparable signal data rates.

The ADuM1210 isolator provides two independent isolation
channels operable with the supply voltage on either side,
ranging from 2.7 V to 5.5 V. This provides compatibility with
lower voltage systems and enables voltage translation
functionality across the isolation barrier. In addition, the
ADuM1210 provides low pulse width distortion (<3 ns) and
tight channel-to-channel matching (<3 ns). Unlike other opto­coupler alternatives, the ADuM1210 isolator has a patented
refresh feature that ensures dc correctness in the absence of
input logic transitions and during power-up/power-down
conditions. Furthermore, as an alternative to the ADuM1200
dual-channel digital isolator that defaults to an output high
condition, the ADuM1210 outputs default to a logic low state
when input power is off.

1

Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.

FUNCTIONAL BLOCK DIAGRAM

1

V

DD1

ENCODE DECODE

2

V

IA

ENCODE DECODE

3

V

IB

4

GND

1

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

8

V

DD2

7

V

OA

6

V

OB

5

GND

2

05459-001

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2012 Analog Devices, Inc. All rights reserved.

ADuM1210 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 5

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation ....................................................................................... 7

Package Characteristics ............................................................... 9

Regulatory Information ............................................................... 9

Insulation and Safety-Related Specifications ............................ 9

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

Insulation Characteristics .......................................................... 10

REVISION HISTORY

3/12—Rev. C to Rev. D

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 14

6/07—Rev. B to Rev. C

Updated VDE Certification Throughout ...................................... 1

Changes to Features, Applications, and Note 1 ............................ 1

Changes to DC Specifications in Table 1 ....................................... 3

Changes to DC Specifications in Table 2 ....................................... 5

Changes to DC Specifications in Table 3 ....................................... 7

Added Endnote 2 to Table 4 ............................................................ 9

Changes to Regulatory Information Section ................................ 9

Changes to Table 7 .......................................................................... 10

Added Table 10 ............................................................................... 11

Added Insulation Lifetime Section .............................................. 15





Recommended Operating Conditions .................................... 10

Absolute Maximum Ratings ......................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions ........................... 12

Typical Performance Characteristics ........................................... 13

Applications Information .............................................................. 14

PC Board Layout ........................................................................ 14

Propagation Delay-Related Parameters ................................... 14

DC Correctness and Magnetic Field Immunity ........................... 14

Power Consumption .................................................................. 15

Insulation Lifetime ..................................................................... 15

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

3/07—Rev. A to Rev. B

Changes to Table 1 ............................................................................. 3

2/06—Rev. 0 to Rev. A

Updated Format .................................................................. Universal

Added Note 1 ..................................................................................... 1

Changes to Absolute Maximum Ratings ..................................... 11

Changes to DC Correctness and Magnetic Field

Immunity Section ........................................................................... 14

7/05—Revision 0: Initial Version

Rev. D | Page 2 of 20

Data Sheet ADuM1210

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V
unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel,

Output Supply Current, per Channel,

Total Supply Current, Two Channels1

Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ V
Logic High Input Threshold VIH 0.7 × V
Logic Low Input Threshold VIL 0.3 × V
Logic High Output Voltages V
V
Logic Low Output Voltages V

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t

Propagation Delay Skew5 t
Channel-to-Channel Matching,

Channel-to-Channel Matching,

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity

Common-Mode Transient Immunity

Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current,

Output Dynamic Supply Current,

1

Supply current values are for both channels running at identical data rates. Output supply current values are specified with no output load present. The supply current

associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total V
currents as a function of data rate.

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,

DD2

= 25°C, V

A

0.50 0.60 mA

I

DDI (Q)

DD1

= V

= 5 V. All voltages are relative to their respective ground.

DD2

Quiescent

I

0.19 0.25 mA

DDO (Q)

Quiescent

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

1.1 1.4 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.5 0.8 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

− t

PLH

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PHL

4.3 5.5 mA 5 MHz logic signal frequency

DD1 (10)

1.3 2.0 mA 5 MHz logic signal frequency

DD2 (10)

DD1

V

DD1

V

DD1

, V

V

OAH

OBH

, V

OAL

OBL

, t

20 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

− 0.1 5.0 V IOx = −20 μA, VIx = V

DD2

− 0.5 4.8 V IOx = −4 mA, VIx = V

DD2

0.0 0.1 V IOx = 20 μA, VIx = V

IxH

IxH

IxL

IxL

IxL

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

6

Codirectional Channels

Opposing-Directional Channels

7

at Logic High Output

at Logic Low Output

per Channel

per Channel

8

8

7

PSKCD

15 ns CL = 15 pF, CMOS signal levels

t

PSKOD

6

| 25 35 kV/μs

|CM

H

= V

Ix

DD1

, VCM = 1000 V,

V
transient magnitude = 800 V

| 25 35 kV/μs

|CM

L

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

0.19 mA/Mbps

I

DDI (D)

0.05 mA/Mbps

I

DDO (D)

and V

DD2

supply

DD1

Rev. D | Page 3 of 20

ADuM1210 Data Sheet

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

and/or t

PHL

that is measured between units at the same operating temperature, supply voltages, and output

PLH

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on

. CML is the maximum common-mode voltage slew rate

DD2

Figure 4 Figure 6

Power Consumption

calculating per-channel supply current for a given data rate.

propagation delay is

PLH

Rev. D | Page 4 of 20

Data Sheet ADuM1210

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V
unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel,

Output Supply Current, per Channel,

Total Supply Current, Two Channels1

Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB, ≤ V
Logic High Input Threshold VIH 0.7 × V
Logic Low Input Threshold VIL 0.3 × V
Logic High Output Voltages V
V
Logic Low Output Voltages V

0.04 0.1 V IOx = 400 μA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V

SWITCHING SPECIFICATIONS

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse Width Distortion, |t

Propagation Delay Skew5 t
Channel-to-Channel Matching,

Channel-to-Channel Matching,

Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity

Common-Mode Transient Immunity

Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current,

Output Dynamic Supply Current,

1

The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
Figure 4 Figure 6 Figure 7 Figure 8
total V

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range,

DD2

= 25°C, V

A

0.26 0.35 mA

I

DDI (Q)

DD1

= V

= 3.0 V. All voltages are relative to their respective ground.

DD2

Quiescent

I

0.11 0.20 mA

DDO (Q)

Quiescent

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

0.6 1.0 mA DC to 1 MHz logic signal frequency

DD1 (Q)

0.2 0.6 mA DC to 1 MHz logic signal frequency

DD2 (Q)

10 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

− t

PLH

PHL

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

2.2 3.4 mA 5 MHz logic signal frequency

DD1 (10)

0.7 1.1 mA 5 MHz logic signal frequency

DD2 (10)

DD1

V

DD1

V

DD1

, V

V

OAH

OBH

, V

OAL

OBL

, t

20 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

− 0.1 3.0 V IOx = −20 μA, VIx = V

DD2

− 0.5 2.8 V IOx = −4 mA, VIx = V

DD2

0.0 0.1 V IOx = 20 μA, VIx = V

IxH

IxH

IxL

IxL

IxL

Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

22 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

6

Codirectional Channels

Opposing-Directional Channels

7

at Logic High Output

at Logic Low Output

per Channel

per Channel

through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See and for

and V

DD1

8

8

supply currents as a function of data rate.

DD2

7

PSKCD

22 ns CL = 15 pF, CMOS signal levels

t

PSKOD

6

| 25 35 kV/μs

|CM

H

= V

Ix

DD1

, VCM = 1000 V,

V
transient magnitude = 800 V

| 25 35 kV/μs

|CM

L

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

I

0.10 mA/Mbps

DDI (D)

0.03 mA/Mbps

I

DDO (D)

Power Consumption

propagation delay is

PLH

Rev. D | Page 5 of 20

ADuM1210 Data Sheet

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.

and/or t

PHL

that is measured between units at the same operating temperature, supply voltages, and output

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Figure 4 Figure 6

Power Consumption

Rev. D | Page 6 of 20