ANALOG DEVICES ADuM1200, ADuM1201 Service Manual

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FEATURES

Narrow body SOIC 8-lead package
Low power operation

5 V operation

1.1 mA per channel maximum @ 0 Mbps to 2 Mbps

3.7 mA per channel maximum @ 10 Mbps

8.2 mA per channel maximum @ 25 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

2.2 mA per channel maximum @ 10 Mbps

4.8 mA per channel maximum @ 25 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 25 Mbps (NRZ)
Precise timing characteristics

3 ns maximum pulse-width distortion

3 ns maximum channel-to-channel matching
High common-mode transient immunity: > 25 kV/µs
Safety and regulatory approvals

UL recognition

2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000

= 560 V peak

V

IORM

APPLICATIONS

Size-critical multichannel isolation
SPI® interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation
Digital field bus isolation

FUNCTIONAL BLOCK DIAGRAMS

Dual-Channel Digital Isolators

ADuM1200/ADuM1201

GENERAL DESCRIPTION

The ADuM120x are dual-channel digital isolators based on
Analog Devices’ iCoupler® technology. Combining high speed
CMOS and monolithic transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.

The ADuM120x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both parts operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM120x provide low pulse-width distortion
(< 3 ns for CR grade) and tight channel-to-channel matching
(< 3 ns for CR grade). Unlike other optocoupler alternatives, the
ADuM120x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.

1

V

DD1

ENCODE DECODE

2

V

IA

3

ENCODE DECODE

4

ND

V

IB

1

Figure 1. ADuM1200 Functional Block Diagram

8

V

DD2

7

V

OA

6

V

OB

5

GND

2

04642-0-001

1

V

DD1

DECODE ENCODE

2

V

OA

3

ENCODE DECODE

4

ND

V

IB

1

8

V

DD2

7

V

IA

6

V

OB

5

GND

2

04642-0-002

Figure 2. ADuM1201 Functional Block Diagram

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADuM1200/ADuM1201

TABLE OF CONTENTS

Specifications..................................................................................... 3

ESD Caution................................................................................ 12

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 5

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation

Package Characteristics ............................................................. 10

Regulatory Information............................................................. 10

Insulation and Safety-Related Specifications.......................... 10

DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics

Recommended Operating Conditions .................................... 11

Absolute Maximum Ratings.......................................................... 12

....................................................................................... 7

............................................................................ 11

REVISION HISTORY

9/04—Data Sheet Changed from Rev. A to Rev. B

Changes to Table 5.......................................................................... 10

6/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Format ............................................................. Universal

Changes to General Description .................................................... 1

Changes to Electrical Characteristics—5 V Operation ............... 3

Changes to Electrical Characteristics—3 V Operation ............... 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation ............................................................................ 7

Pin Configurations and Function Descriptions ......................... 13

Typical Perfor m a n c e Character i stics ........................................... 14

Application Information................................................................ 15

PC Board Layout ........................................................................ 15

Propagation Delay-Related Parameters................................... 15

DC Correctness and Magnetic Field Immunity........................... 15

Power Consumption .................................................................. 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

4/04—Revision 0: Initial Version

Rev. B | Page 2 of 20

ADuM1200/ADuM1201

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V
entire recommended operating range, unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I
Output Supply Current, per Channel, Quiescent I

DDI (Q)

DDO (Q)

ADuM1200, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (25)

DD2 (25)

ADuM1201, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (25)

DD2 (25)

For All Models

Input Currents IIA, IIB −10 +0.01 +10 µA 0 ≤ VIA, VIB ≤ V
Logic High Input Threshold VIH 0.7 V
Logic Low Input Threshold VIL

Logic High Output Voltages V

V

Logic Low Output Voltages V

V

OAH

OBH

0.0 0.1 V IOx = 20 µA, VIx = V

OAL

OBL

0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS

ADuM120xAR

Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching

2

3

4

− t

PLH

5

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

6

PW 1000 ns CL = 15 pF, CMOS signal levels
1 Mbps CL = 15 pF, CMOS signal levels
t

, t

PHL

t

100 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/OD

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All min/max specifications apply over the

DD2

= 25°C, V

A

DD1

= V

DD2

= 5 V.

0.50 0.60 mA

0.19 0.25 mA

1.1 1.4 mA DC to 1 MHz logic signal freq.

0.5 0.8 mA DC to 1 MHz logic signal freq.

4.3 5.5 mA 5 MHz logic signal freq.

1.3 2.0 mA 5 MHz logic signal freq.

10 13 mA 12.5 MHz logic signal freq.

2.8 3.4 mA 12.5 MHz logic signal freq.

0.8 1.1 mA DC to 1 MHz logic signal freq.

0.8 1.1 mA DC to 1 MHz logic signal freq.

2.8 3.5 mA 5 MHz logic signal freq.

2.8 3.5 mA 5 MHz logic signal freq.

6.3 8.0 mA 12.5 MHz logic signal freq.

6.3 8.0 mA 12.5 MHz logic signal freq.

or V

DD1

, V

V

DD2

V

0.3 V

DD1,

V

DD2

5.0 V I

4.8 V I

= −20 µA, VIx = V

Ox

= −4 mA, VIx = V

Ox

V
V

V
V

DD1

DD2

DD1

DD2

DD1

,

− 0.1
,

− 0.5

0.04 0.1 V IOx = 400 µA, VIx = V

50 150 ns CL = 15 pF, CMOS signal levels

PLH

DD2

IxH

IxH

IxL

IxL

IxL

50 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 3 of 20

ADuM1200/ADuM1201

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM120xBR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse-Width Distortion, |t

PLH

− t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing Directional Channels

6

6

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

ADuM120xCR

Minimum Pulse Width2 PW 20 40 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 25 50 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse-Width Distortion, |t

– t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PLH

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing Directional Channels

6

6

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

For All Models

Common-Mode Transient Immunity

at Logic High Output
Common-Mode Transient Immunity

at Logic Low Output

7

7

Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current, per Channel8I
Output Dynamic Supply Current, per Channel8 I

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11
for total I

2

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply
current for a given data rate.

DD1

Figure 8

and I

supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.

DD2

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

, t

20 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PSK

t

PSKCD

t

PSKOD

PHL

PSK

t

PSKCD

t

PSKOD

15 ns CL = 15 pF, CMOS signal levels
3 ns CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

, t

20 45 ns CL = 15 pF, CMOS signal levels

PLH

15 ns CL = 15 pF, CMOS signal levels
3 ns CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

|CMH| 25 35 kV/µs

| 25 35 kV/µs

|CM

L

DDI (D)

DDO (D)

and/or t

PLH

0.19 mA/Mbps

0.05 mA/Mbps

that is measured between units at the same operating temperature, supply voltages, and output

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

= V

, V

DD1

, VCM = 1000 V,

DD2

V

Ix

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

Figure 9

propagation delay is

PLH

Figure 6

Figure 8

Rev. B | Page 4 of 20

ADuM1200/ADuM1201

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ V
entire recommended operating range, unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I
Output Supply Current, per Channel, Quiescent I

DDI (Q)

DDO (Q)

ADuM1200, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (25)

DD2 (25)

ADuM1201, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (25)

DD2 (25)

For All Models

Input Currents IIA, IIB −10 0.01 10 µA 0 ≤ VIA, VIB, ≤ V
Logic High Input Threshold VIH 0.7 V
Logic Low Input Threshold VIL 0.3 V
Logic High Output Voltages V

V

Logic Low Output Voltages V

V

OAH

OBH

0.0 0.1 V IOx = 20 µA, VIx = V

OAL

OBL

0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS

ADuM120xAR

Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching

2

3

4

− t

PLH

5

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

6

PW 1000 ns CL = 15 pF, CMOS signal levels
1 Mbps CL = 15 pF, CMOS signal levels
t

, t

PHL

t

100 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/OD

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V. All min/max specifications apply over the

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.26 0.35 mA

0.11 0.20 mA

0.6 1.0 mA DC to 1 MHz logic signal freq.

0.2 0.6 mA DC to 1 MHz logic signal freq.

2.2 3.4 mA 5 MHz logic signal freq.

0.7 1.1 mA 5 MHz logic signal freq.

5.2 7.7 mA 12.5 MHz logic signal freq.

1.5 2.0 mA 12.5 MHz logic signal freq.

0.4 0.8 mA DC to 1 MHz logic signal freq.

0.4 0.8 mA DC to 1 MHz logic signal freq.

1.5 2.2 mA 5 MHz logic signal freq.

1.5 2.2 mA 5 MHz logic signal freq.

3.4 4.8 mA 12.5 MHz logic signal freq.

3.4 4.8 mA 12.5 MHz logic signal freq.

or V

DD1

DD2

DD1, VDD2

,

V

DD1

− 0.1

V

DD2

V

,

DD1

V

− 0.5

DD2

0.04 0.1 V IOx = 400 µA, VIx = V

50 150 ns CL = 15 pF, CMOS signal levels

PLH

V

, V

DD1

3.0 V I

2.8 V I

DD2

= −20 µA, VIx = V

Ox

= −4 mA, VIx = V

Ox

IxH

IxH

IxL

IxL

IxL

50 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 5 of 20

ADuM1200/ADuM1201

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM120xBR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse-Width Distortion, |t

−t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PLH

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing Directional Channels

6

6

Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels

ADuM120xCR

Minimum Pulse Width2 PW 20 40 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 25 50 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
Pulse-Width Distortion, |t

PLH

− t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
Channel-to-Channel Matching,

Codirectional Channels
Channel-to-Channel Matching,

Opposing Directional Channels

6

6

Output Rise/Fall Time (10% to 90%) tR/t

For All Models

Common Mode Transient Immunity

at Logic High Output
Common Mode Transient Immunity

at Logic Low Output

7

7

Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current, per Channel

8

Output Dynamic Supply Current, per Channel8 I

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 11
for total I

2

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply
current for a given data rate.

DD1

Figure 8

and I

supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.

DD2

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

, t

20 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

22 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

22 ns CL = 15 pF, CMOS signal levels

PSKOD

, t

PHL

PSK

t

PSKCD

t

PSKOD

|CMH| 25 35 kV/µs

20 55 ns CL = 15 pF, CMOS signal levels

PLH

16 ns CL = 15 pF, CMOS signal levels
3 ns CL = 15 pF, CMOS signal levels

16 ns CL = 15 pF, CMOS signal levels

3.0 ns CL = 15 pF, CMOS signal levels

F

= V

V

, V

Ix

DD1

DD2

transient magnitude = 800 V

| 25 35 kV/µs

|CM

L

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

I

DDI (D)

DDO (D)

and/or t

PLH

0.10 mA/Mbps

0.03 mA/Mbps

9

propagation delay is

PLH

that is measured between units at the same operating temperature, supply voltages, and output

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

Figure 8

, VCM = 1000 V,

Rev. B | Page 6 of 20