Page 1
G
G
Dual-Channel Digital Isolators
FEATURES
Narrow body, RoHS-compliant, SOIC 8-lead package
Low power operation
5 V operation
1.1 mA per channel maximum @ 0 Mbps to 2 Mbps
3.7 mA per channel maximum @ 10 Mbps
8.2 mA per channel maximum @ 25 Mbps
3 V operation
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps
2.2 mA per channel maximum @ 10 Mbps
4.8 mA per channel maximum @ 25 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 125°C
High data rate: dc to 25 Mbps (NRZ)
Precise timing characteristics
3 ns maximum pulse width distortion
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Automotive versions qualified per AEC-Q100
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
V
= 560 V peak
IORM
APPLICATIONS
Size-critical multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation
Digital field bus isolation
Hybrid electric vehicles, battery monitor, and motor drive
ADuM1200/ADuM1201
with optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance char-
acteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the
power of optocouplers at comparable signal data rates.
The ADuM120x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both parts operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier.
In addition, the ADuM120x provide low pulse width distortion
(<3 ns for CR grade) and tight channel-to-channel matching
(<3 ns for CR grade). Unlike other optocoupler alternatives,
the ADuM120x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.
ADuM1200W and ADuM1201W are automotive grade versions
qualified for 125°C operation per AEC-Q100. See the
Automotive Products section for more details.
FUNCTIONAL BLOCK DIAGRAMS
1 8
V
DD1
ENCODE DECODE
2 7
V
IA
ENCODE DECODE
3
V
IB
4
ND
1
Figure 1. ADuM1200 Functional Block Diagram
V
DD2
V
OA
6
V
OB
5
GND
2
04642-001
GENERAL DESCRIPTION
1 8
V
The ADuM120x1 are dual-channel, digital isolators based on
the Analog Devices, Inc., iCoupler® technology. Combining
high speed CMOS and monolithic transformer technologies,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers.
By avoiding the use of LEDs and photodiodes, iCoupler
devices remove the design difficulties commonly associated
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2009 Analog Devices, Inc. All rights reserved.
DD1
DECODE ENCODE
2 7
V
OA
ENCODE DECODE
3
V
IB
4
ND
1
Figure 2. ADuM1201 Functional Block Diagram
V
DD2
V
IA
6
V
OB
5
GND
2
04642-002
Page 2
ADuM1200/ADuM1201
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Electrical Characteristics—5 V, 105°C Operation ................... 4
Electrical Characteristics—3 V, 105°C Operation ................... 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C
Operation ....................................................................................... 8
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics ......................................................... 20
Recommended Operating Conditions .................................... 20
Absolute Maximum Ratings ......................................................... 21
ESD Caution................................................................................ 21
Pin Configurations and Function Descriptions ......................... 22
Typical Performance Characteristics ........................................... 23
Applications Information .............................................................. 24
PCB Layout ................................................................................. 24
Propagation Delay-Related Parameters ................................... 24
Electrical Characteristics—5 V, 125°C Operation ................. 11
Electrical Characteristics—3 V, 125°C Operation ................. 13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation
....................................................................................................... 15
Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation
....................................................................................................... 17
Package Characteristics ............................................................. 19
Regulatory Information ............................................................. 19
Insulation and Safety-Related Specifications .......................... 19
REVISION HISTORY
1/09—Rev. G to Rev. H
Changes to Table 5, Switching Specifications Parameter .......... 13
Changes to Table 6, Switching Specifications Parameter .......... 15
Changes to Table 7, Switching Specifications Parameter .......... 17
9/08—Rev. F to Rev. G
Changes to Table 9 .......................................................................... 19
Changes to Table 13 ........................................................................ 21
Changes to Ordering Guide .......................................................... 27
3/08—Rev. E to Rev. F
Changes to Features Section............................................................ 1
Changes to Applications Section .................................................... 1
Added Table 4 .................................................................................. 11
Added Table 5 .................................................................................. 13
Added Table 6 .................................................................................. 15
Added Table 7 .................................................................................. 17
Changes to Table 12 ........................................................................ 20
Changes to Table 13 ........................................................................ 21
Added Automotive Products Section .......................................... 26
Changes to Ordering Guide .......................................................... 27
DC Correctness and Magnetic Field Immunity ........................... 24
Power Consumption .................................................................. 25
Insulation Lifetime ..................................................................... 25
Automotive Products ................................................................. 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
11/07—Rev. D to Rev. E
Changes to Note 1 ............................................................................. 1
Added ADuM120xAR Change vs. Temperature Parameter ........ 3
Added ADuM120xAR Change vs. Temperature Parameter ........ 5
Added ADuM120xAR Change vs. Temperature Parameter ........ 8
8/07—Rev. C to Rev. D
Updated VDE Certification Throughout ....................................... 1
Changes to Features, Note 1, Figure 1, and Figure 2 .................... 1
Changes to Table 3 ............................................................................. 7
Changes to Regulatory Information Section .............................. 10
Added Table 10 ............................................................................... 12
Added Insulation Lifetime Section .............................................. 16
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
Rev. H | Page 2 of 28
Page 3
ADuM1200/ADuM1201
2/06—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added Note 1 ..................................................................................... 1
Changes to Absolute Maximum Ratings ...................................... 12
Changes to DC Correctness and Magnetic Field
Immunity Section ............................................................................ 15
9/04—Rev. A to Rev. B
Changes to Table 5 .......................................................................... 10
6/04—Rev. 0 to Rev. A
Changes to Format ............................................................. Universal
Changes to General Description ..................................................... 1
Changes to Electrical Characteristics—5 V Operation ................ 3
Changes to Electrical Characteristics—3 V Operation ................ 5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation ............................................................................ 7
4/04—Revision 0: Initial Version
Rev. H | Page 3 of 28
Page 4
ADuM1200/ADuM1201
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ V
over the entire recommended operating range, unless otherwise noted; all typical specifications are at T
does not apply to the ADuM1200W and ADuM1201W automotive grade products.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I
ADuM1200 Total Supply Current, Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (BR and CR Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (CR Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
ADuM1201 Total Supply Current, Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (BR and CR Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (CR Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (V
Logic High Input Threshold VIH 0.7 (V
Logic Low Input Threshold VIL 0.3 (V
Logic High Output Voltages V
(V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
ADuM120xAR CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
2
PW 1000 ns
3
4
t
4
− t
|
PLH
PHL
Change vs. Temperature 11 ps/°C
Propagation Delay Skew
5
t
0.50 0.60 mA
DDI (Q)
0.19 0.25 mA
DDO (Q)
1.1 1.4 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.5 0.8 mA DC to 1 MHz logic signal freq.
DD2 (Q)
4.3 5.5 mA 5 MHz logic signal freq.
DD1 (10)
1.3 2.0 mA 5 MHz logic signal freq.
DD2 (10)
10 13 mA 12.5 MHz logic signal freq.
DD1 (25)
2.8 3.4 mA 12.5 MHz logic signal freq.
DD2 (25)
0.8 1.1 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.8 1.1 mA DC to 1 MHz logic signal freq.
DD2 (Q)
2.8 3.5 mA 5 MHz logic signal freq.
DD1 (10)
2.8 3.5 mA 5 MHz logic signal freq.
DD2 (10)
6.3 8.0 mA 12.5 MHz logic signal freq.
DD1 (25)
6.3 8.0 mA 12.5 MHz logic signal freq.
DD2 (25)
, V
(V
OAH
OBH
, V
0.0 0.1 V IOx = 20 μA, VIx = V
OAL
OBL
1 Mbps
, t
50 150 ns
PHL
PLH
PWD 40 ns
100 ns
PSK
≤ 5.5 V, 4.5 V ≤ V
DD1
or V
) V
DD1
DD2
or V
) − 0.1 5.0 V IOx = −20 μA, VIx = V
DD1
DD2
or V
) − 0.5 4.8 V IOx = −4 mA, VIx = V
DD1
DD2
≤ 5.5 V; all minimum/maximum specifications apply
DD2
DD1
or V
) V
DD2
= 25°C, V
A
DD1
= V
= 5 V; this
DD2
DD1
IxL
IxL
or V
IxH
IxH
IxL
)
DD2
Rev. H | Page 4 of 28
Page 5
ADuM1200/ADuM1201
Parameter Symbol Min Typ Max Unit Test Conditions
Channel-to-Channel Matching
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns
ADuM120xBR
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
3
4
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching 3
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
ADuM120xCR
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
3
4
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching 3 ns
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
For All Models
Common-Mode Transient Immunity
Logic High Output
Logic Low Output
7
|CM
7
Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per Channel
Input I
Output I
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through
Figure 6
for total V
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the V
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
DD1
Figure 8
and V
supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
DD2
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.
6
t
2
PSKCD/tPSKOD
PW 100 ns
50 ns
10 Mbps
t
, t
20 50 ns
PHL
4
− t
|
PLH
2
PHL
5
6
6
PLH
PWD 3 ns
t
15 ns
PSK
t
ns
PSKCD
t
15 ns
PSKOD
PW 20 40 ns
25 50 Mbps
t
, t
20 45 ns
PHL
4
− t
|
PLH
PHL
5
6
6
PLH
PWD 3 ns
t
15 ns
PSK
t
PSKCD
t
15 ns
PSKOD
| 25 35 kV/μs VIx = V
H
DD1
or V
DD2
, VCM =
1000 V, transient
magnitude = 800 V
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
8
0.19 mA/
DDI (D)
Mbps
0.05 mA/
DDO (D)
Mbps
Power Consumption
9 Figure 11
propagation delay is
signal to the 50% level of the rising edge of the VOx signal.
Ix
and/or t
PHL
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
O
that is measured between units at the same operating temperature, supply voltages, and output
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Figure 6
PLH
Figure 8
Power Consumption
Rev. H | Page 5 of 28
Page 6
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground; 2.7 V ≤ V
the entire recommended operating range, unless otherwise noted; all typical specifications are at T
not apply to ADuM1200W and ADuM1201W automotive grade products.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
Output Supply Current per Channel, Quiescent I
ADuM1200 Total Supply Current, Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (BR and CR Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (CR Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
ADuM1201 Total Supply Current, Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (BR and CR Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (CR Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (V
Logic High Input Threshold VIH 0.7 (V
Logic Low Input Threshold VIL 0.3 (V
Logic High Output Voltages V
(V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
ADuM120xAR CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
2
PW 1000 ns
3
4
t
4
− t
|
PLH
PHL
Change vs. Temperature 11 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
5
t
6
t
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns
0.26 0.35 mA
DDI (Q)
0.11 0.20 mA
DDO (Q)
0.6 1.0 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.2 0.6 mA DC to 1 MHz logic signal freq.
DD2 (Q)
2.2 3.4 mA 5 MHz logic signal freq.
DD1 (10)
0.7 1.1 mA 5 MHz logic signal freq.
DD2 (10)
5.2 7.7 mA 12.5 MHz logic signal freq.
DD1 (25)
1.5 2.0 mA 12.5 MHz logic signal freq.
DD2 (25)
0.4 0.8 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.4 0.8 mA DC to 1 MHz logic signal freq.
DD2 (Q)
1.5 2.2 mA 5 MHz logic signal freq.
DD1 (10)
1.5 2.2 mA 5 MHz logic signal freq.
DD2 (10)
3.4 4.8 mA 12.5 MHz logic signal freq.
DD1 (25)
3.4 4.8 mA 12.5 MHz logic signal freq.
DD2 (25)
, V
OAH
OBH
, V
OAL
OBL
1 Mbps
, t
50 150 ns
PHL
PLH
PWD 40 ns
100 ns
PSK
PSKCD/tPSKOD
≤ 3.6 V, 2.7 V ≤ V
DD1
(V
DD1
DD1
or V
or V
or V
DD1
) V
DD2
) − 0.1 3.0 V IOx = −20 μA, VIx = V
DD2
) − 0.5 2.8 V IOx = −4 mA, VIx = V
DD2
≤ 3.6 V; all minimum/maximum specifications apply over
DD2
DD1
= 25°C, V
A
or V
)
DD2
DD1
= V
= 3.0 V; this does
DD2
0.0 0.1 V IOx = 20 μA, VIx = V
50 ns
DD1
IxL
IxL
or V
IxH
IxH
IxL
)
DD2
Rev. H | Page 6 of 28
Page 7
ADuM1200/ADuM1201
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns
ADuM120xCR
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns
For All Models
Common-Mode Transient Immunity
Logic High Output
Logic Low Output
Refresh Rate fr 1.1 Mbps
Dynamic Supply Current per Channel
Input I
Output I
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through
Figure 6
for total V
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
DD1
Figure 8
and V
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.
2
3
4
2
3
4
7
|CM
7
supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
DD2
4
− t
|
PLH
PLH
PHL
5
6
6
4
− t
|
PHL
5
6
6
8
PW 100 ns
10 Mbps
t
, t
20 60 ns
PHL
PLH
PWD 3 ns
t
22 ns
PSK
t
3 ns
PSKCD
t
22 ns
PSKOD
PW 20 40 ns
25 50 Mbps
t
, t
20 55 ns
PHL
PLH
PWD 3 ns
t
16 ns
PSK
t
3 ns
PSKCD
t
16 ns
PSKOD
| 25 35 kV/μs VIx = V
H
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
0.10 mA/
DDI (D)
0.03 mA/
DDO (D)
and/or t
PHL
that is measured between units at the same operating temperature, supply voltages, and output
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Mbps
Mbps
Power Consumption
Figure 6
Power Consumption
or V
DD1
, VCM = 1000 V,
DD2
transient magnitude = 800 V
transient magnitude = 800 V
Figure 9 Figure 11
propagation delay is
PLH
Figure 8
Rev. H | Page 7 of 28
Page 8
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ V
≤ 3.6 V, 4.5 V ≤ V
≤ V
DD1
otherwise noted; all typical specifications are at T
≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless
DD2
= 25°C; V
A
= 3.0 V, V
DD1
DD2
ADuM1200W and ADuM1201W automotive grade products.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
5 V/3 V Operation 0.50 0.6 mA
3 V/5 V Operation 0.26 0.35 mA
Output Supply Current per Channel,
Quiescent
5 V/3 V Operation 0.11 0.20 mA
3 V/5 V Operation 0.19 0.25 mA
ADuM1200 Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
Supply Current I
DD1
5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal freq.
3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal freq.
3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
Supply Current I
DD1
5 V/3 V Operation 10 13 mA 12.5 MHz logic signal freq.
3 V/5 V Operation 5.2 7.7 mA 12.5 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 1.5 2.0 mA 12.5 MHz logic signal freq.
3 V/5 V Operation 2.8 3.4 mA 12.5 MHz logic signal freq.
ADuM1201 Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
5 V/3 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
Supply Current I
DD1
5 V/3 V Operation 2.8 3.5 mA 5 MHz logic signal freq.
3 V/5 V Operation 1.5 2.2 mA 5 MHz logic signal freq.
V
Supply Current I
DD2
5 V/3 V Operation 1.5 2.2 mA 5 MHz logic signal freq.
3 V/5 V Operation 2.8 3.5 mA 5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
Supply Current I
DD1
5 V/3 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq.
3 V/5 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq.
I
DDI (Q)
I
DDO (Q)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
DD1 (25)
DD2 (25)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
DD1 (25)
Rev. H | Page 8 of 28
≤ 5.5 V, 2.7 V ≤ V
DD1
= 5.0 V; or V
= 5.0 V, V
DD1
≤ 3.6 V. 3 V/5 V operation: 2.7 V
DD2
= 3.0 V; this does not apply to
DD2
Page 9
ADuM1200/ADuM1201
Parameter Symbol Min Typ Max Unit Test Conditions
V
Supply Current I
DD2
5 V/3 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq.
3 V/5 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (V
Logic High Input Threshold VIH 0.7 (V
Logic Low Input Threshold VIL 0.3 (V
Logic High Output Voltages V
(V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
ADuM120xAR CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
2
PW 1000 ns
3
4
t
4
− t
|
PLH
PHL
Change vs. Temperature 11 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
5
t
6
t
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns
ADuM120xBR CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
2
3
4
4
− t
|
PLH
PHL
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
5
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
6
6
Output Rise/Fall Time (10% to 90%) tR/tF
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
ADuM120xCR CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
2
3
4
4
– t
|
PLH
PHL
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
5
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
6
6
DD2 (25)
or V
DD1
, V
(V
OAH
OBH
, V
0.0 0.1 V IOx = 20 μA, VIx = V
OAL
OBL
DD1
DD1
or V
or V
) V
DD2
or V
) V
DD2
) − 0.1 V
DD2
) − 0.5 (V
DD2
DD1
DD1
or V
V IOx = −20 μA, VIx = V
DD2
or V
DD1
) − 0.2 V IOx = −4 mA, VIx = V
DD2
1 Mbps
, t
50 150 ns
PHL
PLH
PWD 40 ns
50 ns
PSK
PSKCD/tPSKOD
50 ns
PW 100 ns
10 Mbps
t
, t
15 55 ns
PHL
PLH
PWD 3 ns
t
22 ns
PSK
t
3 ns
PSKCD
t
22 ns
PSKOD
PW 20 40 ns
25 50 Mbps
t
, t
20 50 ns
PHL
PLH
PWD 3 ns
t
15 ns
PSK
t
3 ns
PSKCD
t
15 ns
PSKOD
DD1
IxL
IxL
or V
IxH
IxH
IxL
)
DD2
Rev. H | Page 9 of 28
Page 10
ADuM1200/ADuM1201
Parameter Symbol Min Typ Max Unit Test Conditions
Output Rise/Fall Time (10% to 90%) tR/tF
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
For All Models
Common-Mode Transient Immunity
Logic High Output
Logic Low Output
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current
per Channel
5 V/3 V Operation 0.19 mA/
3 V/5 V Operation 0.10 mA/
Output Dynamic Supply Current per
Channel
8
5 V/3 V Operation 0.03 mA/
3 V/5 V Operation 0.05 mA/
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through
Figure 6
for total V
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
and V
DD1
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
is the magnitude of the worst-case difference in t
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.
7
|CM
7
8
| 25 35 kV/μs VIx = V
H
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
I
DDI (D)
I
DDO (D)
Figure 8
supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
DD2
and/or t
PHL
that is measured between units at the same operating temperature, supply voltages, and output
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Mbps
Mbps
Mbps
Mbps
Power Consumption
Figure 6
Power Consumption
or V
DD1
, VCM = 1000 V,
DD2
transient magnitude = 800 V
transient magnitude = 800 V
Figure 9 Figure 11
propagation delay is
PLH
Figure 8
Rev. H | Page 10 of 28
Page 11
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ V
over the entire recommended operating range, unless otherwise noted; all typical specifications are at T
applies to ADuM1200W and ADuM1201W automotive grade products.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel,
Quiescent
ADUM1200W, Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (TRZ and URZ Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (URZ Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
ADUM1201W, Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (TRZ and URZ Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (URZ Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 ≤ VIA, VIB ≤ (V
Logic High Input Threshold VIH 0.7 (V
Logic Low Input Threshold VIL 0.3 (V
Logic High Output Voltages V
(V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
2
PW 1000 ns
3
4
t
4
− t
|
PLH
PHL
5
t
6
t
Output Rise/Fall Time
(10% to 90%)
ADuM120xWTRZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
2
3
4
I
0.50 0.60 mA
DDI (Q)
I
0.19 0.25 mA
DDO (Q)
1.1 1.4 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.5 0.8 mA DC to 1 MHz logic signal freq.
DD2 (Q)
4.3 5.5 mA 5 MHz logic signal freq.
DD1 (10)
1.3 2.0 mA 5 MHz logic signal freq.
DD2 (10)
10 13 mA 12.5 MHz logic signal freq.
DD1 (25)
2.8 3.4 mA 12.5 MHz logic signal freq.
DD2 (25)
0.8 1.1 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.8 1.1 mA DC to 1 MHz logic signal freq.
DD2 (Q)
2.8 3.5 mA 5 MHz logic signal freq.
DD1 (10)
2.8 3.5 mA 5 MHz logic signal freq.
DD2 (10)
6.3 8.0 mA 12.5 MHz logic signal freq.
DD1 (25)
6.3 8.0 mA 12.5 MHz logic signal freq.
DD2 (25)
, V
(V
OAH
OBH
, V
0.0 0.1 V IOx = 20 μA, VIx = V
OAL
OBL
1 Mbps
, t
20 150 ns
PHL
PLH
PWD 40 ns
100 ns
PSK
PSKCD/tPSKOD
50 ns
tR/tF 2.5 ns
PW 100 ns
10 Mbps
t
, t
20 50 ns
PHL
PLH
≤ 5.5 V, 4.5 V ≤ V
DD1
or V
DD1
DD2
or V
DD1
DD2
or V
DD1
DD2
≤ 5.5 V; all minimum/maximum specifications apply
DD2
= 25°C, V
A
DD1
= V
= 5 V; this
DD2
DD1
) V
or V
DD1
) V
DD2
) − 0.1 5.0 V IOx = −20 μA, VIx = V
) − 0.5 4.8 V IOx = −4 mA, VIx = V
or V
IxH
IxL
IxL
)
DD2
IxH
IxL
Rev. H | Page 11 of 28
Page 12
ADuM1200/ADuM1201
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse-Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
ADuM120xWURZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
2
3
4
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
For All Models
Common-Mode Transient Immunity
Logic High Output
Logic Low Output
7
|CM
7
Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per Channel
Input I
Output I
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the ion. See
through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through
Figure 6
for total I
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the V
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
DD1
igure 8
and I
supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
DD2
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.
4
− t
|
PLH
PHL
5
6
PWD 3 ns
t
15 ns
PSK
t
3 ns
6
PSKCD
t
15 ns
PSKOD
PW 20 40 ns
25 50 Mbps
t
, t
20 45 ns
PHL
4
– t
|
PLH
PHL
5
6
6
PLH
PWD 3 ns
t
15 ns
PSK
t
3 ns
PSKCD
t
15 ns
PSKOD
| 25 35 kV/μs VIx = V
H
DD1
, V
, VCM = 1000 V,
DD2
transient magnitude = 800 V
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
8
0.19 mA/
DDI (D)
Mbps
0.05 mA/
DDO (D)
Mbps
Power Consumption sect
igure 9 Figure 11
propagation delay is
signal to the 50% level of the rising edge of the VOx signal.
Ix
and/or t
PHL
that is measured between units at the same operating temperature, supply voltages, and output
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Figure 6
PLH
Figure 8
Power Consumption
Rev. H | Page 12 of 28
Page 13
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ V
apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at T
V
= V
DD1
= 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
DD2
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel, Quiescent I
ADUM1200W, Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (TRZ and URZ Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (URZ Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
ADUM1201W, Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (TRZ and URZ Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (URZ Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 ≤ VIA, VIB, ≤ (V
Logic High Input Threshold VIH 0.7 (V
Logic Low Input Threshold VIL 0.3 (V
Logic High Output Voltages V
(V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
2
PW 1000 ns
3
4
t
4
− t
|
PLH
PHL
5
t
6
t
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM120xWTRZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
2
3
4
4
−t
|
PLH
PHL
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
5
I
0.26 0.35 mA
DDI (Q)
0.11 0.20 mA
DDO (Q)
0.6 1.0 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.2 0.6 mA DC to 1 MHz logic signal freq.
DD2 (Q)
2.2 3.4 mA 5 MHz logic signal freq.
DD1 (10)
0.7 1.1 mA 5 MHz logic signal freq.
DD2 (10)
5.2 7.7 mA 12.5 MHz logic signal freq.
DD1 (25)
1.5 2.0 mA 12.5 MHz logic signal freq.
DD2 (25)
0.4 0.8 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.4 0.8 mA DC to 1 MHz logic signal freq.
DD2 (Q)
1.5 2.2 mA 5 MHz logic signal freq.
DD1 (10)
1.5 2.2 mA 5 MHz logic signal freq.
DD2 (10)
3.4 4.8 mA 12.5 MHz logic signal freq.
DD1 (25)
3.4 4.8 mA 12.5 MHz logic signal freq.
DD2 (25)
, V
(V
OAH
OBH
, V
0.0 0.1 V IOx = 20 μA, VIx = V
OAL
OBL
1 Mbps
, t
20 150 ns
PHL
PLH
PWD 40 ns
100 ns
PSK
PSKCD/tPSKOD
50 ns
PW 100 ns
10 Mbps
t
, t
20 60 ns
PHL
PLH
PWD 3 ns
t
22 ns
PSK
≤ 3.6 V, 3.0 V ≤ V
DD1
or V
) V
DD2
) − 0.1 3.0 V IOx = −20 μA, VIx = V
DD2
) − 0.5 2.8 V IOx = −4 mA, VIx = V
DD2
DD1
DD1
DD1
or V
or V
≤ 3.6 V. All minimum/maximum specifications
DD2
= 25°C,
A
or V
DD1
)
DD2
DD1
or V
IxH
IxL
IxL
IxL
)
DD2
IxH
Rev. H | Page 13 of 28
Page 14
ADuM1200/ADuM1201
Parameter Symbol Min Typ Max Unit Test Conditions
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns
ADuM120xWCR CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns
For All Models
Common Mode Transient Immunity
Logic High Output
Logic Low Output
Refresh Rate fr 1.1 Mbps
Dynamic Supply Current per Channel
Input I
Output I
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the ion. See
through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through F
Figure 6
for total I
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
DD1
igure 8
and I
supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
DD2
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.
6
6
2
3
4
7
4
− t
|
PLH
PHL
5
6
6
t
3 ns
PSKCD
t
22 ns
PSKOD
PW 20 40 ns
25 50 Mbps
t
, t
20 55 ns
PHL
PLH
PWD 3 ns
t
16 ns
PSK
t
3 ns
PSKCD
t
16 ns
PSKOD
|CMH| 25 35 kV/μs VIx = V
DD1
, V
, VCM = 1000 V,
DD2
transient magnitude = 800 V
7
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
8
0.10 mA/
DDI (D)
Mbps
0.03 mA/
DDO (D)
Mbps
Power Consumption sect
igure 9 igure 11
propagation delay is
PLH
and/or t
PHL
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
O
that is measured between units at the same operating temperature, supply voltages, and output
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Figure 6
Figure 8
Power Consumption
Rev. H | Page 14 of 28
Page 15
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ V
minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications
are at T
= 25°C; V
A
= 5.0 V, V
DD1
= 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
DD2
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel
Quiescent
Output Supply Current, per Channel
Quiescent
ADUM1200W, Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (TRZ and URZ Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (URZ Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
ADUM1201W, Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (TRZ and URZ Grades
Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (URZ Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 ≤ VIA, VIB ≤ (V
Logic High Input Threshold VIH 0.7 (V
Logic Low Input Threshold VIL 0.3 (V
Logic High Output Voltages V
(V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
2
PW 1000 ns
3
4
t
− t
PLH
PHL
5
t
Channel-to-Channel Matching
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM120xWTRZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
2
3
4
I
0.50 0.6 mA
DDI (Q)
I
0.11 0.20 mA
DDO (Q)
1.1 1.4 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.2 0.6 mA DC to 1 MHz logic signal freq.
DD2 (Q)
4.3 5.5 mA 5 MHz logic signal freq.
DD1 (10)
0.7 1.1 mA 5 MHz logic signal freq.
DD2 (10)
10 13 mA 12.5 MHz logic signal freq.
DD1 (25)
1.5 2.0 mA 12.5 MHz logic signal freq.
DD2 (25)
0.8 1.1 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.4 0.8 mA DC to 1 MHz logic signal freq.
DD2 (Q)
2.8 3.5 mA 5 MHz logic signal freq.
DD1 (10)
1.5 2.2 mA 5 MHz logic signal freq.
DD2 (10)
6.3 8.0 mA 12.5 MHz logic signal freq.
DD1 (25)
3.4 4.8 mA 12.5 MHz logic signal freq.
DD2 (25)
or V
) V
DD1
DD2
, V
(V
OAH
OBH
, V
0.0 0.1 V IOx = 20 μA, VIx = V
OAL
OBL
DD1
DD1
or V
or V
) − 0.1 V
DD2
) − 0.5 (V
DD2
DD1
DD1
or V
or V
1 Mbps
, t
15 150 ns
PHL
4
|
6
t
PLH
PWD 40 ns
50 ns
PSK
PSKCD/ tPSKOD
50 ns
PW 100 ns
10 Mbps
t
, t
15 55 ns
PHL
PLH
≤ 5.5 V, 3.0 V ≤ V
DD1
or V
DD1
V IOx = −20 μA, VIx = V
DD2
) − 0.2 V IOx = −4 mA, VIx = V
DD2
≤ 3.6 V. 3 V/5 V operation; all
DD2
) V
DD2
DD1
or V
IxH
IxH
IxL
IxL
IxL
)
DD2
Rev. H | Page 15 of 28
Page 16
ADuM1200/ADuM1201
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time(10% to 90%) tR/tF 3.0 ns
ADuM120xWURZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time(10% to 90%) tR/tF 3.0 ns
For All Models
Common-Mode Transient Immunity
Logic High Output
Logic Low Output
Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per
Channel
8
Input I
Output I
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are tput load
The supp nt associated with an individual channel operating at a given data rate can be calculated as described in the Power Co on section
present. ly curre nsumpti . See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded
for total I
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaran
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
PHL
measured from the 50% level of the rising edge of the V
5
t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
and I
DD1
DD2
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the fallin
is the magnitude of the worst-case difference in t
the isolation barrier. Opposing directional channel
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal d igure 8 for
information on per-channel supply current as a function of da
calculating per-channel supply current for a given data rate.
2
3
4
7
|CM
7
supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
4
− t
PLH
PHL
5
6
PWD 3 ns
|
t
22 ns
PSK
t
3 ns
PSKCD
6
t
22 ns
PSKOD
PW 20 40 ns
25 50 Mbps
t
, t
20 50 ns
PHL
4
– t
|
PLH
PHL
5
6
6
PLH
PWD 3 ns
t
15 ns
PSK
t
3 ns
PSKCD
t
15 ns
PSKOD
| 25 35 kV/μs VIx = V
H
DD1
, V
DD2
, VCM = 1000 V,
transient magnitude = 800 V
|CML| 25 35 kV/μs VIx = V
DD1
, V
DD2
, VCM = 1000 V,
transient magnitude = 800 V
0.19
DDI (D)
0.03
DDO (D)
Mbps
mA/
mA/
Mbps
specified with no ou
conditions. See Figure 9 through Figure 11
teed.
signal to the 50% level of the rising edge of the VOx signal.
g edge of the VOx signal. t
Ix
and/or t that is measured between units at the same operating temperature, supply voltages, and output
PHL PLH
propagation delay is
PLH
-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
. CML is the maximum common-mode voltage slew rate
< 0.8 V. The common-m
O
ode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
DD2
ata rate. See Figure 6 through F
ta rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
Rev. H | Page 16 of 28
Page 17
ADuM1200/ADuM1201
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ V
over the entire recommended operating range, unless otherwise noted; all typical specifications are at T
V
= 5.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
DD2
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel,
Quiescent
ADUM1200W, Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (TRZ and URZ Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (URZ Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
ADUM1201W, Total Supply Current,
Two Channels
1
DC to 2 Mbps
V
Supply Current I
DD1
V
Supply Current I
DD2
10 Mbps (TRZ and URZ Grades Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
25 Mbps (URZ Grade Only)
V
Supply Current I
DD1
V
Supply Current I
DD2
For All Models
Input Currents IIA, IIB −10 +0.01 +10 μA 0 ≤ VIA, VIB ≤ (V
Logic High Input Threshold VIH 0.7 (V
Logic Low Input Threshold VIL 0.3 (V
Logic High Output Voltages V
(V
Logic Low Output Voltages V
0.04 0.1 V IOx = 400 μA, VIx = V
0.2 0.4 V IOx = 4 mA, VIx = V
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
2
PW 1000 ns
3
4
t
− t
PLH
PHL
5
t
Channel-to-Channel Matching
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM120xWTRZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
2
3
4
I
0.26 0.35 mA
DDI (Q)
I
0.19 0.25 mA
DDO (Q)
0.6 1.0 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.5 0.8 mA DC to 1 MHz logic signal freq.
DD2 (Q)
2.2 3.4 mA 5 MHz logic signal freq.
DD1 (10)
1.3 2.0 mA 5 MHz logic signal freq.
DD2 (10)
5.2 7.7 mA 12.5 MHz logic signal freq.
DD1 (25)
2.8 3.4 mA 12.5 MHz logic signal freq.
DD2 (25)
0.4 0.8 mA DC to 1 MHz logic signal freq.
DD1 (Q)
0.8 1.1 mA DC to 1 MHz logic signal freq.
DD2 (Q)
1.5 2.2 mA 5 MHz logic signal freq.
DD1 (10)
2.8 3.5 mA 5 MHz logic signal freq.
DD2 (10)
3.4 4.8 mA 12.5 MHz logic signal freq.
DD1 (25)
6.3 8.0 mA 12.5 MHz logic signal freq.
DD2 (25)
, V
(V
OAH
OBH
DD1
or V
DD1
, V
0.0 0.1 V IOx = 20 μA, VIx = V
OAL
OBL
1 Mbps
, t
15 150 ns
PHL
4
|
6
t
PLH
PWD 40 ns
50 ns
PSK
PSKCD/
t
PSKOD
50 ns
PW 100 ns
10 Mbps
t
, t
15 55 ns
PHL
PLH
≤ 3.6 V, 4.5 V ≤ V
DD1
or V
) V
DD1
DD2
or V
) − 0.1 V
DD2
) − 0.5 (V
DD2
DD1
DD1
or V
or V
≤ 5.5 V; all minimum/maximum specifications apply
DD2
or V
) V
DD1
DD2
V IOx = −20 μA, VIx = V
DD2
) − 0.2 V IOx = −4 mA, VIx = V
DD2
= 25°C; V
A
= 3.0 V,
DD1
DD1
or V
IxH
IxH
IxL
IxL
IxL
)
DD2
Rev. H | Page 17 of 28
Page 18
ADuM1200/ADuM1201
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
ADuM120xWURZ CL = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Change vs. Temperature 5 ps/°C
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
For All Models
Common-Mode Transient Immunity
Logic High Output
Logic Low Output
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current
per Channel
Output Dynamic Supply Current
per Channel
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the ion. See
through F for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F through
Figure 6
for total I
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t
PHL
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
t
is the magnitude of the worst-case difference in t
PSK
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
DD1
and I
igure 8
DD2
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on
calculating per-channel supply current for a given data rate.
2
3
4
7
|CM
7
8
8
supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
4
− t
PLH
PHL
5
6
PWD 3 ns
|
t
22 ns
PSK
t
3 ns
PSKCD
6
t
22 ns
PSKOD
PW 20 40 ns
25 50 Mbps
t
, t
20 50 ns
PHL
4
– t
|
PLH
PHL
5
6
6
PLH
PWD 3 ns
t
15 ns
PSK
t
3 ns
PSKCD
t
15 ns
PSKOD
| 25 35 kV/μs VIx = V
H
DD1
, V
, VCM = 1000 V,
DD2
transient magnitude = 800 V
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
I
0.10 mA/
DDI (D)
Mbps
I
0.05 mA/
DDO (D)
Mbps
Power Consumption sect
igure 9 Figure 11
propagation delay is
PLH
and/or t
PHL
that is measured between units at the same operating temperature, supply voltages, and output
PLH
. CML is the maximum common-mode voltage slew rate
DD2
Figure 6
Figure 8
Power Consumption
Rev. H | Page 18 of 28
Page 19
ADuM1200/ADuM1201
PACKAGE CHARACTERISTICS
Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-to-Output)
Capacitance (Input-to-Output)1 C
Input Capacitance CI 4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θ
IC Junction-to-Case Thermal Resistance, Side 2 θ
1
The device is considered a 2-terminal device; Pin 1, Pin, 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM1200/ADuM1201 and ADuM1200W/ADuM1201W are approved by the organizations listed in Tabl e 9; refer to Table 14 and
the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and
insulation levels.
Table 9.
UL CSA VDE
Recognized Under 1577 Component
Recognition Program
Single/Basic 2500 V rms Isolation Voltage
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM120x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).
2
In accordance with DIN V VDE V 0884-10, each ADuM120x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
1
R
1012 Ω
I-O
1.0 pF f = 1 MHz
I-O
46 °C/W
JCI
Thermocouple located at
center of package underside
41 °C/W
JCO
1
Approved under CSA Component Acceptance
Notice #5A. Approval pending for
Certified according to DIN V VDE
V 0884-10 (VDE V 0884-10): 2006-12
ADuM1200W/ADuM1201W automotive 125°C
temperature grade.
Basic insulation per CSA 60950-1-03 and
Reinforced insulation, 560 V peak
IEC 60950-1, 400 V rms (566 peak) maximum
working voltage
Functional insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak) maximum
working voltage
2
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 10.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 4.90 min mm
Minimum External Tracking (Creepage) L(I02) 4.01 min mm
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. H | Page 19 of 28
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Page 20
ADuM1200/ADuM1201
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation, only within the safety limit data. Maintenance of the safety data is ensured by protective
circuits. Note that the * marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 11.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage V
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
× 1.875 = VPR, 100% production test,
V
IORM
= 1 second, partial discharge < 5 pC
t
m
× 1.6 = VPR, tm = 60 seconds,
V
IORM
partial discharge < 5 pC
After Environmental Tests Subgroup 1 896 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
V
× 1.2 = VPR, tm = 60 seconds,
IORM
partial discharge < 5 pC
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak
Safety-Limiting Values
Maximum value allowed in the event of a failure
(see Figure 3)
Case Temperature TS 150 °C
Side 1 Current IS1 160 mA
Side 2 Current IS2 170 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
560 V peak
IORM
1050 V peak
V
PR
V
PR
672 V peak
200
180
160
140
120
100
SAFETY-LIMITING CURRENT (mA)
SIDE #1
80
60
40
20
0
0
SIDE #2
50 100 150 200
CASE TEMPERAT URE ( °C)
Figure 3. Thermal Derating Curve, Dependence of Safety-
Limiting Values on Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12.
Parameter Rating
Operating Temperature (TA)
Operating Temperature (TA)
Supply Voltages (V
Supply Voltages (V
DD1
DD1
Input Signal Rise and Fall Times 1.0 ms
1
Does not apply to ADuM1200W and ADuM1201W automotive grade
products.
2
Applies to ADuM1200W and ADuM1201W automotive grade products.
3
All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on imm l
magnetic fields.
04642-003
1
−40°C to +105°C
2
−40°C to +125°C
1, 3
, V
)
2.7 V to 5.5 V
DD2
2 3,
, V
)
DD2
3.0 V to 5.5 V
unity to externa
Rev. H | Page 20 of 28
Page 21
ADuM1200/ADuM1201
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter Rating
Storage Temperature (TST) −55°C to +150°C
Ambient Operating Temperature (TA)
Ambient Operating Temperature (TA)
Supply Voltages (V
Input Voltages (VIA, VIB)
Output Voltages (VOA, VOB)
3
, V
)
DD1
−0.5 V to +7.0 V
DD2
3, 4
−0.5 V to V
3, 4
−0.5 V to V
1
−40°C to +105°C
2
−40°C to +125°C
+ 0.5 V
DDI
DDO
+ 0.5 V
Average Output Current per Pin (IO)5−11 mA to +11 mA
Common-Mode Transients (CML, CMH)
1
Does not apply to ADuM1200W and ADuM1200W automotive grade
products.
2
Applies to ADuM1200W and ADuM1201W automotive grade products.
3
All voltages are relative to their respective ground.
4
V
and V
DDI
given channel, respectively.
5
See for maximum rated current values for various temperatures. Figure 3
6
Refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings
can cause latch-up or permanent damage.
refer to the supply voltages on the input and output sides of a
DDO
6
−100 kV/μs to +100 kV/μs
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 14. Maximum Continuous Working Voltage
1
Parameter Max Unit Constraint
AC Voltage,
Bipolar
Waveform
AC Voltage,
Unipolar
Waveform
Functional
Insulation
Basic
Insulation
DC Voltage
Functional
Insulation
Basic
Insulation
1
Refers to continuous voltage magnitude imposed across the isolation barrier.
See the Insulation Lifetime section for more details.
565 V peak
1131 V peak
50-year minimum lifetime
Maximum approved
working voltage per IEC
60950-1
560 V peak Maximum approved
working voltage per IEC
60950-1 and VDE V 088410
1131 V peak
Maximum approved
working voltage per IEC
60950-1
560 V peak Maximum approved
working voltage per IEC
60950-1 and VDE V 088410
ESD CAUTION
Rev. H | Page 21 of 28
Page 22
ADuM1200/ADuM1201
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1 8
V
DD1
ADuM1200
2 7
V
IA
TOP VIEW
3 6
V
IB
(Not to S cale)
4 5
GND
1
Figure 4. ADuM1200 Pin Configuration Figure 5. ADuM1201 Pin Configuration
V
DD2
V
OA
V
OB
GND
2
4642-004
1 8
V
DD1
ADuM1201
2 7
V
OA
3 6
V
IB
4 5
GND
1
TOP VIEW
(Not to Scale)
V
DD2
V
IA
V
OB
GND
2
04642-005
Table 15. ADuM1200 Pin Function Descriptions
Pin
Mnemonic Description
No.
1 V
Supply Voltage for Isolator Side 1.
DD1
2 VIA Logic Input A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground Reference for Isolator Side 1.
5 GND2 Ground 2. Ground Reference for Isolator Side 2.
6 VOB Logic Output B.
7 VOA Logic Output A.
8 V
Supply Voltage for Isolator Side 2.
DD2
Table 16. ADuM1201 Pin Function Descriptions
Pin
Mnemonic Description
No.
1 V
Supply Voltage for Isolator Side 1.
DD1
2 VOA Logic Output A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground Reference for Isolator Side 1.
5 GND2 Ground 2. Ground Reference for Isolator Side 2.
6 VOB Logic Output B.
7 VIA Logic Input A.
8 V
Supply Voltage for Isolator Side 2.
DD2
Table 17. ADuM1200 Truth Table (Positive Logic)
VIA Input VIB Input V
State V
DD1
State VOA Output VOB Output Notes
DD2
H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered H H
X X Powered Unpowered Indeterminate Indeterminate
Table 18. ADuM1201 Truth Table (Positive Logic)
VIA Input VIB Input V
State V
DD1
State VOA Output VOB Output Notes
DD2
H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered Indeterminate H
X X Powered Unpowered H Indeterminate
Outputs return to the input state within
1 μs of V
power restoration.
DDI
Outputs return to the input state within
1 μs of V
power restoration.
DDO
Outputs return to the input state within
1 μs of V
power restoration.
DD1
Outputs return to the input state within
1 μs of V
power restoration.
DDO
Rev. H | Page 22 of 28
Page 23
ADuM1200/ADuM1201
TYPICAL PERFORMANCE CHARACTERISTICS
10
20
8
6
4
5V
CURRENT/CHANNEL (mA)
2
0
0
10 20 30
DATA RATE (Mb ps)
Figure 6. Typical Input Supply Current per Channel vs.
Data Rate for 5 V and 3 V Operation
4
3
2
1
CURRENT/CHANNEL (mA)
15
10
CURRENT (mA)
3V
04642-006
5
0
0
10 20 30
DATA RATE (Mb ps)
Figure 9. Typical ADuM1200 V
5V
3V
Supply Current vs.
DD1
04642-009
Data Rate for 5 V and 3 V Operation
4
3
2
5V
3V
CURRENT (mA)
1
5V
3V
0
0
10 20 30
DATA RATE (Mb ps)
Figure 7. Typical Output Supply Current per Channel vs.
Data Rate for 5 V and 3 V Operation (No Output Load)
4
3
5V
2
1
CURRENT/CHANNEL (mA)
0
0
10 20 30
DATA RATE (Mb ps)
3V
Figure 8. Typical Output Supply Current per Channel vs.
Data Rate for 5 V and 3 V Operation (15 pF Output Load)
04642-007
04642-008
0
0
10 20 30
Figure 10. Typical ADuM1200 V
Data Rate for 5 V and 3 V Operation
10
8
6
4
CURRENT (mA)
2
0
0
10 20 30
Figure 11. Typical ADuM1201 V
Data Rate for 5 V and 3 V Operation
DATA RATE (Mb ps)
DD2
5V
3V
DATA RATE (Mb ps)
or V
DD1
Supply Current vs.
Supply Current vs.
DD2
04642-010
04642-011
Rev. H | Page 23 of
28
Page 24
ADuM1200/ADuM1201
V
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM120x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins.
The capacitor value should be between 0.01 μF and 0.1 μF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic low output can differ from the propagation delay
to a Logic high output.
INPUT (
)
Ix
OUTPUT (VOx)
t
PLH
Figure 12. Propagation Delay Parameters
t
PHL
50%
50%
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)Σ∏r
2
; n = 1, 2, … , N
n
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
r
is the radius of the nth turn in the receiving coil (cm).
n
Given the geometry of the receiving coil in the ADuM120x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 13.
100
04642-012
10
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM120x component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM120x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input send
narrow (~1 ns) pulses to the decoder via the transformer. The
decoder is bistable and is therefore either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions of more than ~1 μs at the input, a periodic set of
refresh pulses indicative of the correct input state is sent to
ensure dc correctness at the output. If the decoder receives
no internal pulses for more than about 5 μs, the input side is
assumed to be unpowered or nonfunctional, in which case
the isolator output is forced to a default state (see Tab le 17
and Tabl e 18 ) by the watchdog timer circuit.
The ADuM120x are extremely immune to external magnetic
fields. The limitation on the magnetic field immunity of the
ADuM120x is set by the condition in which induced voltage
in the receiving coil of the transformer is sufficiently large
enough to either falsely set or reset the decoder. The following
analysis defines the conditions under which this can occur. The
3 V operating condition of the ADuM120x is examined because
it represents the most susceptible mode of operation.
1
0.1
DENSITY (kgauss)
0.01
MAXIMUM ALLOWABLE MAGNETIC FLUX
0.001
1k 10k 10M
Figure 13. Maximum Allowable External Magnetic Flux Density
MAGNETIC F IELD FREQ UE NCY (Hz)
1M
100M100k
04642-013
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and has the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM120x transformers. Figure 14 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen, the ADuM120x are extremely immune and
can be affected only by extremely large currents operating very
close to the component at a high frequency. For the 1 MHz
example, a 0.5 kA current would have to be placed 5 mm away
from the ADuM120x to affect the operation of the component.
Rev. H | Page 24 of 28
Page 25
ADuM1200/ADuM1201
1000
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
MAXIMUM ALLOWABLE CURRENT (kA)
V
DD1
and V
supply current as a function of data rate for
DD2
ADuM1200 and ADuM1201 channel configurations.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM120x.
0.01
1k 10k 100M100k 1M 10M
MAGNETIC F I ELD FREQUENCY (Hz)
Figure 14. Maximum Allowable Current for Various
Current-to-ADuM120x Spacings
04642-014
Note that, at combinations of strong magnetic fields and high
frequencies, any loops formed by PCB traces can induce sufficiently large error voltages to trigger the threshold of succeeding
circuitry. Care should be taken in the layout of such traces to
avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM120x
isolator is a function of the supply voltage, the data rate of the
channel, and the output load of the channel.
For each input channel, the supply current is given by
= I
I
DDI
DDI (Q)
I
DDI
= I
× (2f – fr) + I
DDI (D)
DDI (Q)
For each output channel, the supply current is given by
I
I
DDO
DDO
= I
= (I
f ≤ 0.5fr
DDO (Q)
+ (0.5 × 10−3) × CLV
DDO (D)
) × (2f – fr) + I
DDO
where:
I
, I
DDI (D)
are the input and output dynamic supply currents
DDO (D)
per channel (mA/Mbps).
C
is the output load capacitance (pF).
L
is the output supply voltage (V).
V
DDO
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
f
is the input stage refresh rate (Mbps).
r
I
, I
DDI (Q)
are the specified input and output quiescent
DDO (Q)
supply currents (mA).
f ≤ 0.5fr
f > 0.5fr
DDO (Q)
f > 0.5fr
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 14 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than
the 50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM120x depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar
ac, or dc. Figure 15, Figure 16, and Figure 17 illustrate these
different isolation voltage waveforms, respectively.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at higher
working voltages yet still achieves a 50-year service life. The
working voltages listed in Table 14 can be applied while maintaining the 50-year minimum lifetime provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any cross
insulation voltage waveform that does not conform to Figure 16
or Figure 17 is to be treated as a bipolar ac waveform, and its
peak voltage is to be limited to the 50-year lifetime voltage value
listed in Table 14.
To calculate the total I
DD1
and I
supply currents, the supply
DD2
currents for each input and output channel corresponding to
I
DD1
and I
are calculated and totaled. Figure 6 and Figure 7
DD2
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 8 provides perchannel supply current as a function of data rate for a 15 pF
output condition. Figure 9 through Figure 11 provide total
Rev. H | Page 25 of 28
Page 26
ADuM1200/ADuM1201
Note that the voltage presented in Figure 16 is shown as sinusoidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.
RATED PEAK VOL TAGE
AUTOMOTIVE PRODUCTS
The ADuM1200W and ADuM1201W products are qualified
per AEC-Q100 for use in automotive applications. Custom
variants of these products may be available to meet stringent
automotive performance and quality requirements. For more
information, please contact your local ADI sales representative.
0V
Figure 15. Bipolar AC Waveform
42-021046
RATED PEAK VOL TAGE
0V
Figure 16. Unipolar AC Waveform
04642-022
RATED PEAK VOL TAGE
0V
Figure 17. DC Waveform
04642-023
Rev. H | Page 26 of 28
Page 27
ADuM1200/ADuM1201
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLL ING DIMENSIONS ARE IN MILLI M E TERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DES IGN.
85
1
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
BSC
6.20 (0.2441)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
45°
012407-A
Figure 18. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Number
of Inputs,
V
Side
DD2
Model
Number
of Inputs,
Side
V
DD1
ADuM1200AR 2 0 1 150 40 −40 to +105 R-8
ADuM1200AR-RL7 2 0 1 150 40 −40 to +105 R-8
ADuM1200ARZ
ADuM1200ARZ-RL7
2
2 0 1 150 40 −40 to +105 R-8
2
2 0 1 150 40 −40 to +105 R-8
ADuM1200BR 2 0 10 50 3 −40 to +105 R-8
ADuM1200BR-RL7 2 0 10 50 3 −40 to +105 R-8
ADuM1200BRZ
ADuM1200BRZ-RL7
2
2 0 10 50 3 −40 to +105 R-8
2
2 0 10 50 3 −40 to +105 R-8
ADuM1200CR 2 0 25 45 3 −40 to +105 R-8
ADuM1200CR-RL7 2 0 25 45 3 −40 to +105 R-8
ADuM1200CRZ
ADuM1200CRZ-RL7
ADuM1200WSRZ
ADUM1200WSRZ-RL7
ADuM1200WTRZ
ADuM1200WTRZ-RL7
ADUM1200WURZ
ADUM1200WURZ-RL7
2
2 0 25 45 3 −40 to +105 R-8
2
2 0 25 45 3 −40 to +105 R-8
2
2 0 1 150 40 −40 to +125 R-8
2
2 0 1 150 40 −40 to +125 R-8
2
2 0 10 50 3 −40 to +125 R-8
2
2 0 10 50 3 −40 to +125 R-8
2
2 0 25 45 3 −40 to +125 R-8
2
2 0 25 45 3 −40 to +125 R-8
ADuM1201AR 1 1 1 150 40 −40 to +105 R-8
ADuM1201AR-RL7 1 1 1 150 40 −40 to +105 R-8
ADuM1201ARZ
ADuM1201ARZ-RL7
2
1 1 1 150 40 −40 to +105 R-8
2
1 1 1 150 40 −40 to +105 R-8
ADuM1201BR 1 1 10 50 3 −40 to +105 R-8
ADuM1201BR-RL7 1 1 10 50 3 −40 to +105 R-8
ADuM1201BRZ
ADuM1201BRZ-RL7
2
1 1 10 50 3 −40 to +105 R-8
2
1 1 10 50 3 −40 to +105 R-8
ADuM1201CR 1 1 25 45 3 −40 to +105 R-8
ADuM1201CR-RL7 1 1 25 45 3 −40 to +105 R-8
Maximum
Data Rate
(Mbps)
Rev. H | Page 27 of 28
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Temperature
Range (°C)
Package
Option
1
Page 28
ADuM1200/ADuM1201
Number
of Inputs,
Model
ADuM1201CRZ
2
1 1 25 45 3 −40 to +105 R-8
ADuM1201CRZ-RL7
ADuM1201WSRZ
2
1 1 1 150 40 −40 to +125 R-8
ADUM1201WSRZ-RL7
ADuM1201WTRZ
2
1 1 10 50 3 −40 to +125 R-8
ADuM1201WTRZ-RL7
ADUM1201WURZ
2
1 1 25 45 3 −40 to +125 R-8
ADUM1201WURZ-RL7
1
R-8 = 8-lead narrow-body SOIC_N.
2
Z = RoHS Compliant Part.
V
Side
DD1
2
1 1 25 45 3 −40 to +105 R-8
2
1 1 1 150 40 −40 to +125 R-8
2
1 1 10 50 3 −40 to +125 R-8
2
1 1 25 45 3 −40 to +125 R-8
Number
of Inputs,
V
Side
DD2
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Temperature
Range (°C)
Package
Option
1
©2004–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04642-0-1/09(H)
Rev. H | Page 28 of 28
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