Analog Devices ADuM1200 1 b Datasheet

G

Dual-Channel Digital Isolators

FEATURES

Narrow body SOIC 8-lead package Low power operation

5 V operation

1.1 mA per channel maximum @ 0 Mbps to 2 Mbps

3.7 mA per channel maximum @ 10 Mbps

8.2 mA per channel maximum @ 25 Mbps

3 V operation

0.8 mA per channel maximum @ 0 Mbps to 2 Mbps

2.2 mA per channel maximum @ 10 Mbps

4.8 mA per channel maximum @ 25 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 25 Mbps (NRZ) Precise timing characteristics

3 ns maximum pulse-width distortion

3 ns maximum channel-to-channel matching High common-mode transient immunity: > 25 kV/µs Safety and regulatory approvals

UL recognition

2500 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000

= 560 V peak

V

IORM

APPLICATIONS

Size-critical multichannel isolation SPI® interface/data converter isolation RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation

FUNCTIONAL BLOCK DIAGRAMS

ADuM1200/ADuM1201

GENERAL DESCRIPTION

The ADuM120x are dual-channel digital isolators based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM120x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both parts operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM120x provide low pulse-width distortion (< 3 ns for CR grade) and tight channel-to-channel matching (< 3 ns for CR grade). Unlike other optocoupler alternatives, the ADuM120x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

1

V

DD1

ENCODE DECODE

2

V

IA

3

ENCODE DECODE

4

ND

V

IB

1

Figure 1. ADuM1200 Functional Block Diagram

8

V

DD2

7

V

OA

6

V

OB

5

GND

2

04642-0-001

1

V

DD1

DECODE ENCODE

2

V

OA

3

ENCODE DECODE

4

ND

V

IB

1

8

V

DD2

7

V

IA

6

V

OB

5

GND

2

04642-0-002

Figure 2. ADuM1201 Functional Block Diagram

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

ADuM1200/ADuM1201

REVISION HISTORY

9/04—Data Sheet Changed from Rev. A to Rev. B

Changes to Table 5.......................................................................... 10

6/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Format ............................................................. Universal

Changes to General Description .................................................... 1

Changes to Electrical Characteristics—5 V Operation ............... 3

Changes to Electrical Characteristics—3 V Operation ............... 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation............................................................................ 7

Pin Configurations and Function Descriptions ......................... 13

Typical Perfor m a n c e C haracter i s t ic s ........................................... 14

Application Information................................................................ 15

PC Board Layout ........................................................................ 15

Propagation Delay-Related Parameters................................... 15

DC Correctness and Magnetic Field Immunity........................... 15

Power Consumption .................................................................. 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

4/04—Revision 0: Initial Version

Rev. B | Page 2 of 20

ADuM1200/ADuM1201

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V entire recommended operating range, unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I Output Supply Current, per Channel, Quiescent I

DDI (Q)

DDO (Q)

ADuM1200, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (25)

DD2 (25)

ADuM1201, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (25)

DD2 (25)

For All Models

Input Currents IIA, IIB −10 +0.01 +10 µA 0 ≤ VIA, VIB ≤ V Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL

Logic High Output Voltages V

V

Logic Low Output Voltages V

V

OAH

OBH

0.0 0.1 V IOx = 20 µA, VIx = V

OAL

OBL

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM120xAR

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

2

3

4

− t

PLH

5

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

6

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

, t

PHL

t

100 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/OD

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All min/max specifications apply over the

DD2

= 25°C, V

A

DD1

= V

DD2

= 5 V.

0.50 0.60 mA

0.19 0.25 mA

1.1 1.4 mA DC to 1 MHz logic signal freq.

0.5 0.8 mA DC to 1 MHz logic signal freq.

4.3 5.5 mA 5 MHz logic signal freq.

1.3 2.0 mA 5 MHz logic signal freq.

10 13 mA 12.5 MHz logic signal freq.

2.8 3.4 mA 12.5 MHz logic signal freq.

0.8 1.1 mA DC to 1 MHz logic signal freq.

2.8 3.5 mA 5 MHz logic signal freq.

6.3 8.0 mA 12.5 MHz logic signal freq.

or V

DD1

, V

V

DD2

V

0.3 V

DD1,

V

DD2

5.0 V I

4.8 V I

= −20 µA, VIx = V

Ox

= −4 mA, VIx = V

Ox

V V

DD1

DD2

DD1

DD2

DD1

,

− 0.1 ,

− 0.5

0.04 0.1 V IOx = 400 µA, VIx = V

50 150 ns CL = 15 pF, CMOS signal levels

PLH

DD2

IxH

IxL

50 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 3 of 20

ADuM1200/ADuM1201

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM120xBR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse-Width Distortion, |t

PLH

− t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing Directional Channels

6

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

ADuM120xCR

Minimum Pulse Width2 PW 20 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 50 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse-Width Distortion, |t

– t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PLH

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing Directional Channels

6

Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

For All Models

Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.2 Mbps Input Dynamic Supply Current, per Channel8I Output Dynamic Supply Current, per Channel8 I

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11 for total I

2

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.

DD1

Figure 8

and I

supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.

DD2

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

, t

20 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

PSK

t

PSKCD

t

PSKOD

PHL

PSK

t

PSKCD

t

PSKOD

15 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

, t

20 45 ns CL = 15 pF, CMOS signal levels

PLH

15 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

15 ns CL = 15 pF, CMOS signal levels

|CMH| 25 35 kV/µs

| 25 35 kV/µs

|CM

L

DDI (D)

DDO (D)

and/or t

PLH

0.19 mA/Mbps

0.05 mA/Mbps

that is measured between units at the same operating temperature, supply voltages, and output

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

= V

, V

DD1

, VCM = 1000 V,

DD2

V

Ix

transient magnitude = 800 V

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

Figure 9

propagation delay is

PLH

Figure 6

Figure 8

Rev. B | Page 4 of 20

ADuM1200/ADuM1201

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ V entire recommended operating range, unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I Output Supply Current, per Channel, Quiescent I

DDI (Q)

DDO (Q)

ADuM1200, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (25)

DD2 (25)

ADuM1201, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (Q)

DD2 (Q)

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (10)

DD2 (10)

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

V

Supply Current I

DD2

DD1 (25)

DD2 (25)

For All Models

Input Currents IIA, IIB −10 0.01 10 µA 0 ≤ VIA, VIB, ≤ V Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V Logic High Output Voltages V

V

Logic Low Output Voltages V

V

OAH

OBH

0.0 0.1 V IOx = 20 µA, VIx = V

OAL

OBL

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM120xAR

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

2

3

4

− t

PLH

5

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

6

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

, t

PHL

t

100 ns CL = 15 pF, CMOS signal levels

PSK

t

PSKCD/OD

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

≤ 3.6 V, 2.7 V ≤ V

DD1

≤ 3.6 V. All min/max specifications apply over the

DD2

= 25°C, V

A

DD1

= V

= 3.0 V.

DD2

0.26 0.35 mA

0.11 0.20 mA

0.6 1.0 mA DC to 1 MHz logic signal freq.

0.2 0.6 mA DC to 1 MHz logic signal freq.

2.2 3.4 mA 5 MHz logic signal freq.

0.7 1.1 mA 5 MHz logic signal freq.

5.2 7.7 mA 12.5 MHz logic signal freq.

1.5 2.0 mA 12.5 MHz logic signal freq.

0.4 0.8 mA DC to 1 MHz logic signal freq.

1.5 2.2 mA 5 MHz logic signal freq.

3.4 4.8 mA 12.5 MHz logic signal freq.

or V

DD1

DD2

DD1, VDD2

,

V

DD1

− 0.1

V

DD2

V

,

DD1

V

− 0.5

DD2

0.04 0.1 V IOx = 400 µA, VIx = V

50 150 ns CL = 15 pF, CMOS signal levels

PLH

V

, V

DD1

3.0 V I

2.8 V I

DD2

= −20 µA, VIx = V

Ox

= −4 mA, VIx = V

Ox

IxH

IxL

50 ns CL = 15 pF, CMOS signal levels

Rev. B | Page 5 of 20

ADuM1200/ADuM1201

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM120xBR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse-Width Distortion, |t

−t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PLH

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing Directional Channels

6

Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels

ADuM120xCR

Minimum Pulse Width2 PW 20 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 50 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse-Width Distortion, |t

PLH

− t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing Directional Channels

6

Output Rise/Fall Time (10% to 90%) tR/t

For All Models

Common Mode Transient Immunity

at Logic High Output Common Mode Transient Immunity

at Logic Low Output

7

Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current, per Channel

8

Output Dynamic Supply Current, per Channel8 I

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 11 for total I

2

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.

DD1

Figure 8

and I

supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.

DD2

PHL

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

, t

20 60 ns CL = 15 pF, CMOS signal levels

PHL

PLH

22 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

22 ns CL = 15 pF, CMOS signal levels

PSKOD

, t

PHL

PSK

t

PSKCD

t

PSKOD

|CMH| 25 35 kV/µs

20 55 ns CL = 15 pF, CMOS signal levels

PLH

16 ns CL = 15 pF, CMOS signal levels 3 ns CL = 15 pF, CMOS signal levels

16 ns CL = 15 pF, CMOS signal levels

3.0 ns CL = 15 pF, CMOS signal levels

F

= V

V

, V

Ix

DD1

DD2

transient magnitude = 800 V

| 25 35 kV/µs

|CM

L

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

I

DDI (D)

DDO (D)

and/or t

PLH

0.10 mA/Mbps

0.03 mA/Mbps

9

propagation delay is

PLH

that is measured between units at the same operating temperature, supply voltages, and output

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

Figure 8

, VCM = 1000 V,

Rev. B | Page 6 of 20

ADuM1200/ADuM1201

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V

≤ 3.6 V, 4.5 V ≤ V

≤ V

DD1

noted. All typical specifications are at T

≤ 5.5 V. All min/max specifications apply over the entire recommended operating range, unless otherwise

DD2

= 25°C; V

A

= 3.0 V, V

DD1

= 5.0 V; or V

DD2

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

mA

DDI (Q)

5 V/3 V Operation 0.50 0.6 mA 3 V/5 V Operation 0.26 0.35 mA

Output Supply Current, per Channel, Quiescent I

mA

DDO (Q)

5 V/3 V Operation 0.11 0.20 mA 3 V/5 V Operation 0.19 0.25 mA

ADuM1200, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal freq.

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

DD1 (25)

5 V/3 V Operation 10 13 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 5.2 7.7 mA 12.5 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (25)

5 V/3 V Operation 1.5 2.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.4 mA 12.5 MHz logic signal freq.

ADuM1201, Total Supply Current, Two Channels1

DC to 2 Mbps

V

Supply Current I

DD1

DD1 (Q)

5 V/3 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (Q)

5 V/3 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

V

Supply Current I

DD1

DD1 (10)

5 V/3 V Operation 2.8 3.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.5 2.2 mA 5 MHz logic signal freq.

V

Supply Current I

DD2

DD2 (10)

5 V/3 V Operation 1.5 2.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.5 mA 5 MHz logic signal freq.

≤ 5.5 V, 2.7 V ≤ V

DD1

= 5.0 V, V

DD1

= 3.0 V.

DD2

≤ 3.6 V. 3 V/5 V operation: 2.7 V

DD2

Rev. B | Page 7 of 20

ADuM1200/ADuM1201

Parameter Symbol Min Typ Max Unit Test Conditions

25 Mbps (CR Grade Only)

V

Supply Current I

DD1

5 V/3 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq.

V

Supply Current I

DD2

5 V/3 V Operation 3.4 4.8 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 6.3 8.0 mA 12.5 MHz logic signal freq.

For All Models

Input Currents IIA, IIB −10 0.01 10 µA 0 ≤ VIA, VIB ≤ V Logic High Input Threshold VIH 0.7 V Logic Low Input Threshold VIL 0.3 V

5 V/3 V Operation 0.8 V

3 V/5 V Operation 0.4 V Logic High Output Voltages

Logic Low Output Voltages V

0.04 0.1 V IOx = 400 µA, VIx = V

0.2 0.4 V IOx = 4 mA, VIx = V SWITCHING SPECIFICATIONS

ADuM120xAR

Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse-Width Distortion, |t Propagation Delay Skew Channel-to-Channel Matching

2

3

4

− t

PLH

5

|4 PWD 40 ns CL = 15 pF, CMOS signal levels

PHL

6

Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels

ADuM120xBR

Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse-Width Distortion, |t

PLH

− t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing Directional Channels

6

Output Rise/Fall Time (10% to 90%) tR/tf C

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns

DD1 (25)

DD2 (25)

or V

DD1

, V

DD1

V

,

V

OAH

V

OBH

, V

OAL

OBL

,

DD1

− 0.1

V

DD2

,

V

DD1

V

− 0.5

DD2

0.0 0.1 V IOx = 20 µA, VIx = V

V

DD2

, V

DD1

V

DD1

V

DD2

V

DD1

V

DD2

V I

,

V I

,

− 0.2

V

DD2

= −20 µA, VIx = V

Ox

= −4 mA, VIx = V

Ox

PW 1000 ns CL = 15 pF, CMOS signal levels 1 Mbps CL = 15 pF, CMOS signal levels t

, t

50 150 ns CL = 15 pF, CMOS signal levels

PHL

PLH

t

50 ns CL = 15 pF, CMOS signal levels

PSK

t

50 ns CL = 15 pF, CMOS signal levels

PSKCD/OD

, t

15 55 ns CL = 15 pF, CMOS signal levels

PHL

PLH

22 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

22 ns CL = 15 pF, CMOS signal levels

t

PSKOD

= 15 pF, CMOS signal levels

L

DD2

IxH

IxL

Rev. B | Page 8 of 20

ADuM1200/ADuM1201

Parameter Symbol Min Typ Max Unit Test Conditions

ADuM120xCR

Minimum Pulse Width2 PW 20 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 50 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 t Pulse-Width Distortion, |t

– t

|4 PWD 3 ns CL = 15 pF, CMOS signal levels

PLH

PHL

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 t Channel-to-Channel Matching,

Codirectional Channels Channel-to-Channel Matching,

Opposing Directional Channels

6

Output Rise/Fall Time (10% to 90%) tR/tf C

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns

For All Models

Common-Mode Transient Immunity

at Logic High Output Common-Mode Transient Immunity

at Logic Low Output

7

Refresh Rate f

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps Input Dynamic Supply Current, per Channel8I

5 V/3 V Operation 0.19 mA/Mbps

3 V/5 V Operation 0.10 mA/Mbps Output Dynamic Supply Current, per Channel8 I

5 V/3 V Operation 0.03 mA/Mbps

3 V/5 V Operation 0.05 mA/Mbps

1

The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11 for total I

2

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

4

t

propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. t

PHL

measured from the 50% level of the rising edge of the V

5

t

is the magnitude of the worst-case difference in t

PSK

load within the recommended operating conditions.

6

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

7

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V magnitude is the range over which the common mode is slewed.

8

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for

information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.

DD1

Figure 8

and I

supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.

DD2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

O

, t

20 50 ns CL = 15 pF, CMOS signal levels

PHL

PLH

15 ns CL = 15 pF, CMOS signal levels

PSK

3 ns CL = 15 pF, CMOS signal levels

t

PSKCD

t

15 ns CL = 15 pF, CMOS signal levels

PSKOD

= 15 pF, CMOS signal levels

L

|CMH| 25 35 kV/µs

= V

V

, V

Ix

DD1

transient magnitude = 800 V

| 25 35 kV/µs

|CM

L

= 0 V, VCM = 1000 V,

V

Ix

transient magnitude = 800 V

r

DDI (D)

signal to the 50% level of the rising edge of the VOx signal.

Ix

and/or t

PHL

Figure 9

propagation delay is

PLH

that is measured between units at the same operating temperature, supply voltages, and output

PLH

. CML is the maximum common-mode voltage slew rate

DD2

Power Consumption

Figure 6

Figure 8

, VCM = 1000 V,

DD2

Rev. B | Page 9 of 20

ADuM1200/ADuM1201

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output) Capacitance (Input-Output)1 C Input Capacitance C IC Junction-to-Case Thermal Resistance, Side 1 θ

IC Junction-to-Case Thermal Resistance, Side 2 θ

1

The device is considered a 2-terminal device; Pins 1, 2, 3, and 4 are shorted together, and Pins 5, 6, 7, and 8 are shorted together.

REGULATORY INFORMATION

The ADuM1200/ADuM1201 have been approved by the following organizations:

Table 5.

UL CSA VDE

Recognized under 1577 Component Recognition Program

2500 V rms isolation voltage

File E214100

1

In accordance with UL1577, each ADuM120x is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).

2

In accordance with DIN EN 60747-5-2, each ADuM120x is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection

limit = 5 pC).

1

R

I-O

I

JCI

1012 Ω

1.0 pF f = 1 MHz

4.0 pF 46 °C/W

Thermocouple located at center of package underside

JCO

1

Approved under CSA Component Acceptance Notice #5A

File 205078

41 °C/W

Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 Basic insulation, 560 V peak

Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000, Reinforced insulation, 560 V peak

File 2471900-4880-0001

2

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 4.90 min mm

Minimum External Tracking (Creepage) L(I02) 4.01 min mm

Minimum Internal Gap (Internal

0.017 min mm Insulation distance through insulation

Clearance) Tracking Resistance (Comparative

CTI >175 V DIN IEC 112/VDE 0303 Part 1

Tracking Index) Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. B | Page 10 of 20

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

ADuM1200/ADuM1201

DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS

Table 7.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I−IV For Rated Mains Voltage ≤ 300 V rms I−III

For Rated Mains Voltage ≤ 400 V rms I−II Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage V Input to Output Test Voltage, Method b1 VPR 1050 V peak

V

× 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC

IORM

Input to Output Test Voltage, Method a VPR

After Environmental Tests Subgroup 1

V

× 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC 896 V peak

IORM

After Input and/or Safety Test Subgroup 2/3 672

V

× 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC

IORM

Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) VTR 4000 V peak Safety-Limiting Values (maximum value allowed in the event of a failure; also see the thermal

derating curve, Figure 3)

Case Temperature TS 150 °C

Side 1 Current IS1 160 mA

Side 2 Current IS2 170 mA Insulation Resistance at TS, VIO = 500 V RS >109 Ω

Note that the “*” marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage.

This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.

200

180

160

140

120

100

SAFETY-LIMITING CURRENT (mA)

SIDE #1

80

60

40

20

0

Figure 3. Thermal Derating Curve, Dependence of Safety-

Limiting Values on Case Temperature, per DIN EN 60747-5-2

SIDE #2

50 100 150 200

CASE TEMPERATURE (°C)

04642-0-003

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature TA −40 +105 °C Supply Voltages Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground. See the DC Correctness and

Magnetic Field Immunity section for information on immunity to external magnetic fields.

1

560 V peak

IORM

V

, V

2.7 5.5 V

DD1

DD2

Rev. B | Page 11 of 20

ADuM1200/ADuM1201

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 9.

Parameter Symbol Min Max Unit

Storage Temperature TST −55 150 °C Ambient Operating Temperature TA −40 105 °C Supply Voltages Input Voltage Output Voltage Average Output Current, per Pin Common-Mode Transients

1

All voltages are relative to their respective ground.

2

V

and V

DDI

3

See for maximum rated current values for various temperatures. Figure 3

4

Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or

permanent damage.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1

,1, 2

1, 2

3

4

refer to the supply voltages on the input and output sides of a given channel, respectively.

DDO

V

, V

−0.5 7.0 V

DD1

DD2

VIA, V VOA, V

IB

OB

−0.5 V

IO −35 35 mA

−100 +100 kV/µs

+ 0.5 V

DDI

+ 0.5 V

DDO

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Table 10. ADuM1200 Truth Table (Positive Logic)

VIA Input VIB Input V

H H Powered Powered H H L L Powered Powered L L H L Powered Powered H L L H Powered Powered L H X X Unpowered Powered H H

X X Powered Unpowered Indeterminate Indeterminate

Table 11. ADuM1201 Truth Table (Positive Logic)

VIA Input VIB Input V

H H Powered Powered H H L L Powered Powered L L H L Powered Powered H L L H Powered Powered L H X X Unpowered Powered Indeterminate H

X X Powered Unpowered H Indeterminate

State V

DD1

State V

DD1

State VOA Output VOB Output Notes

DD2

State VOA Output VOB Output Notes

DD2

Outputs return to the input state within 1 µs

power restoration.

of V

DDI

Outputs return to the input state within 1 µs

power restoration.

of V

DDO

Outputs return to the input state within 1 µs

power restoration.

of V

DD1

Outputs return to the input state within 1 µs

power restoration.

of V

DDO

Rev. B | Page 12 of 20

ADuM1200/ADuM1201

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

GND

DD1

V V

IA IB

1

ADuM1200

2

TOP VIEW

(Not to Scale)

3

4

V

8

DD2

V

7

OA

V

6

OB

GND

5

2

04642-0-004

Figure 4. ADuM1200 Pin Configuration

Table 12. ADuM1200 Pin Function Descriptions

Pin No. Mnemonic Function

1 V

DD1

Supply Voltage for Isolator Side 1,

2.7 V to 5.5 V. 2 VIA Logic Input A. 3 VIB Logic Input B. 4 GND1

Ground 1. Ground reference for isolator Side 1.

5 GND2

Ground 2. Ground reference for isolator

Side 2. 6 VOB Logic Output B. 7 VOA Logic Output A. 8 V

DD2

Supply Voltage for Isolator Side 2,

2.7 V to 5.5 V.

V

GND

DD1

V

OA

IB

1

2

3

4

1

ADuM1201

TOP VIEW

(Not to Scale)

V

8

DD2

V

7

IA

V

6

OB

GND

5

2

04642-0-005

Figure 5. ADuM1201 Pin Configuration

Table 13. ADuM1201 Pin Function Descriptions

Pin No. Mnemonic Function

1 V

DD1

Supply Voltage for Isolator Side 1,

2.7 V to 5.5 V. 2 VOA Logic Output A. 3 VIB Logic Input B. 4 GND1

Ground 1. Ground reference for Isolator Side 1.

5 GND2

Ground 2. Ground reference for Isolator

Side 2. 6 VOB Logic Output B. 7 VIA Logic Input A. 8 V

DD2

Supply Voltage for Isolator Side 2,

2.7 V to 5.5 V.

Rev. B | Page 13 of 20

ADuM1200/ADuM1201

TYPICAL PERFORMANCE CHARACTERISTICS

10

20

8

6

4

CURRENT/CHANNEL (mA)

2

0

5V

10 20 30

DATA RATE (Mbps)

3V

Figure 6. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

4

3

2

5V

1

CURRENT/CHANNEL (mA)

3V

04642-0-006

15

10

CURRENT (mA)

5

0

Figure 9. Typical ADuM1200 V

for 5 V and 3 V Operation

4

3

2

CURRENT (mA)

1

5V

3V

10 20 30

DATA RATE (Mbps)

Supply Current vs. Data Rate

DD1

3V

04642-0-009

0

10 20 30

DATA RATE (Mbps)

Figure 7. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

4

3

5V

2

1

CURRENT/CHANNEL (mA)

0

10 20 30

DATA RATE (Mbps)

3V

Figure 8. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

04642-0-007

04642-0-008

Rev. B | Page 14 of 20

0

10 20 30

DATA RATE (Mbps)

Figure 10. Typical ADuM1200 V

for 5 V and 3 V Operation

10

8

6

4

CURRENT (mA)

2

0

10 20 30

DATA RATE (Mbps)

Figure 11. Typical ADuM1201 V

for 5 V and 3 V Operation

Supply Current vs. Data Rate

DD2

5V

3V

or V

DD1

Supply Current vs. Data Rate

DD2

04642-0-010

04642-0-011

ADuM1200/ADuM1201

V

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM120x digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins. The capacitor value should be between 0.01 µF and 0.1 µF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high.

INPUT (

OUTPUT (

Pulse-width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

)

IX

t

PLH

)

OX

Figure 12. Propagation Delay Parameters

t

PHL

50%

04642-0-012

The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

2

=Π−= NnrdtβdV

,...2,1;)/(

∑

n

where:

β is the magnetic flux density (gauss). N is the number of turns in the receiving coil.

is the radius of the nth turn in the receiving coil (cm).

r

n

Given the geometry of the receiving coil in the ADuM120x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 13.

100

10

1

Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM120x component.

Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM120x components operating under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than 2 µs at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 8) by the watchdog timer circuit.

The ADuM120x are extremely immune to external magnetic fields. The limitation on the ADuM120x’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM120x is examined because it represents the most susceptible mode of operation.

0.1

DENSITY (kgauss)

0.01

MAXIMUM ALLOWABLE MAGNETIC FLUX

0.001 1k 10k 10M

Figure 13. Maximum Allowable External Magnetic Flux Density

MAGNETIC FIELD FREQUENCY (Hz)

1M

100M100k

04642-0-013

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and had the worst-case polarity), it would reduce the received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM120x transformers. Figure 14 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the ADuM120x are extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example, one would have to place a 0.5 kA current 5 mm away from the ADuM120x to affect the component’s operation.

Rev. B | Page 15 of 20

ADuM1200/ADuM1201

1000

DISTANCE = 1m

100

10

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

MAXIMUM ALLOWABLE CURRENT (kA)

0.01 1k 10k 100M100k 1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 14. Maximum Allowable Current for Various

Current-to-ADuM120x Spacings

Note that at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

04642-0-014

POWER CONSUMPTION

The supply current at a given channel of the ADuM120x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

For each input channel, the supply current is given by

I

= I

DDI

DDI (Q)

I

DDI

= I

× (2f – fr) + I

DDI (D)

DDI (Q)

for each output channel, the supply current is given by

= I

I

DDO

I

= (I

DDO

f ≤ 0.5f

DDO (Q)

+ (0.5 × 10−3) × CLV

DDO (D)

) × (2f – fr) + I

DDO

where:

, I

I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

is the output load capacitance (pF).

C

L

f ≤ 0.5f

f > 0.5f

DDO (Q)

f > 0.5f

r

is the output supply voltage (V).

V

DDO

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

is the input stage refresh rate (Mbps).

f

r

I

, I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

To calculate the total I

DD1

and I

supply current, the supply

DD2

currents for each input and output channel corresponding to

and I

I

DD1

are calculated and totaled. Figure 6 and Figure 7

DD2

provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides perchannel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 11 provide total I and I

supply current as a function of data rate for

DD2

DD1

ADuM1200 and ADuM1201 channel configurations.

Rev. B | Page 16 of 20

ADuM1200/ADuM1201

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500) BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Figure 15. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

Dimensions shown in millimeters (inches)

ORDERING GUIDE

Maximum Number of Inputs, V

Side

DD2

Model

Number of Inputs,

Side

V

DD1

ADuM1200AR 2 0 1 100 40 −40 to +105 R-8 ADuM1200AR-RL7 2 0 1 100 40 −40 to +105 R-8 ADuM1200ARZ

2

2 0 1 100 40 −40 to +105 R-8 ADuM1200ARZ-RL72 2 0 1 100 40 −40 to +105 R-8 ADuM1200BR 2 0 10 50 3 −40 to +105 R-8 ADuM1200BR-RL7 2 0 10 50 3 −40 to +105 R-8 ADuM1200BRZ2 2 0 10 50 3 −40 to +105 R-8 ADuM1200BRZ-RL72 2 0 10 50 3 −40 to +105 R-8 ADuM1200CR 2 0 25 45 3 −40 to +105 R-8 ADuM1200CR-RL7 2 0 25 45 3 −40 to +105 R-8 ADuM1200CRZ2 2 0 25 45 3 −40 to +105 R-8 ADuM1200CRZ-RL72 2 0 25 45 3 −40 to +105 R-8 ADuM1201AR 1 1 1 100 40 −40 to +105 R-8 ADuM1201AR-RL7 1 1 1 100 40 −40 to +105 R-8 ADuM1201ARZ2 1 1 1 100 40 −40 to +105 R-8 ADuM1201ARZ-RL72 1 1 1 100 40 −40 to +105 R-8 ADuM1201BR 1 1 10 50 3 −40 to +105 R-8 ADuM1201BR-RL7 1 1 10 50 3 −40 to +105 R-8 ADuM1201BRZ2 1 1 10 50 3 −40 to +105 R-8 ADuM1201BRZ-RL72 1 1 10 50 3 −40 to +105 R-8 ADuM1201CR 1 1 25 45 3 −40 to +105 R-8 ADuM1201CR-RL7 1 1 25 45 3 −40 to +105 R-8 ADuM1201CRZ2 1 1 25 45 3 −40 to +105 R-8 ADuM1201CRZ-RL72 1 1 25 45 3 −40 to +105 R-8

1

R-8 = 8-lead narrow body SOIC.

2

Z = Pb-free part.

Maximum Data Rate (Mbps)

Maximum Propagation Delay, 5 V (ns)

Pulse-Width Distortion (ns)

Temperature Range (°C)

Package Option

1

Rev. B | Page 17 of 20

ADuM1200/ADuM1201

NOTES

Rev. B | Page 18 of 20

ADuM1200/ADuM1201

NOTES

Rev. B | Page 19 of 20

ADuM1200/ADuM1201

NOTES

D04642–0–9/04(B)

Rev. B | Page 20 of 20

Analog Devices ADuM1200 1 b Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

ELECTRICAL CHARACTERISTICS—3 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

OUTLINE DIMENSIONS

ORDERING GUIDE