ANALOG DEVICES ADUM 1100 BRZ Datasheet

iCoupler Digital Isolator

Data Sheet

ADuM1100

Rev. K Document Feedback

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V

DD1

V

I

(DATA IN)

V

DD1

GND

1

V

DD2

GND

2

V

O

(DATA OUT)

GND

2

ADuM1100

NOTES

1. FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIEL D IMMUNITY S E CTION.

8

7

6

5

1

2

3

4

02462-001

FEATURES

High data rate: dc to 100 Mbps (NRZ) Compatible with 3.3 V and 5.0 V operation/level translation 125°C maximum operating temperature Low power operation

5 V operation

1.0 mA maximum @ 1 Mbps

4.5 mA maximum @ 25 Mbps

16.8 mA maximum @ 100 Mbps

3.3 V operation

0.4 mA maximum @ 1 Mbps

3.5 mA maximum @ 25 Mbps

7.1 mA maximum @ 50 Mbps 8-lead SOIC_N package (RoHS compliant version available) High common-mode transient immunity: >25 kV/μs

Safety and regulatory approvals

UL recognized

2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

= 560 V peak

IORM

APPLICATIONS

Digital field bus isolation Opto-isolator replacement Computer peripheral interface Microprocessor system interface General instrumentation and data acquisition applications

GENERAL DESCRIPTION

The ADuM11001 is a digital isolator based on Analog Devices Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives, such as optocoupler devices.

Configured as a pin-compatible replacement for existing high speed optocouplers, the ADuM1100 supports data rates as high as 25 Mbps and 100 Mbps.

The ADuM1100 operates with a voltage supply ranging from

3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compatible with temperatures up to 125°C. It operates at very low power, less than 0.9 mA of quiescent current (sum of both sides), and a dynamic current of less than 160 μA per Mbps of data rate. Unlike other optocoupler alternatives, the ADuM1100 provides dc correctness with a patented refresh feature that continuously updates the output signal.

The ADuM1100 is offered in three grades. The ADuM1100AR and ADuM1100BR can operate up to a maximum temperature of 105°C and support data rates up to 25 Mbps and 100 Mbps, respectively. The ADuM1100UR can operate up to a maximum temperature of 125°C and supports data rates up to 100 Mbps.

1

Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578; 6,873,065; 7,075,329.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Device s.

FUNCTIONAL BLOCK DIAGRAM

ure 1.

Fig

ADuM1100 Data Sheet

REVISION HISTORY

7/15—Rev. J to Rev. K

Changes to Table 5 and Table 6 ............................................................. 10

4/15—Rev. I to Rev. J

Changes to Logic Low Output Voltage Parameter, Tes t

Conditions, Ta b l e 2 ..................................................................................... 6

3/12—Rev. H to Rev. I

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 16

3/11—Rev. G to Rev. H

Changes to Data Sheet Title ............................................................. 1

Changes to Ordering Guide ........................................................... 18

6/07—Rev. F to Rev. G

Updated VDE Certification Throughout ....................................... 1

Changes to Features and Endnote 1 ................................................ 1

Changes to Table 5 and Table 6 ....................................................... 9

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 18

3/06—Rev. E to Rev. F

Updated Format.................................................................. Universal

Added Note 1 ..................................................................................... 1

Changes to Table 1 ............................................................................ 4

Changes to Table 2 ............................................................................ 6

Changes to Table 3 ............................................................................ 8

Added Tabl e 11 ................................................................................ 13

Inserted Power Consumption Section.......................................... 18

10/03—Rev. D to Rev. E

Changes to Product Name, Features, and General Description . 1

Changes to Regulatory Information ............................................... 6

Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics ................................................................................... 6

Changes to Absolute Maximum Ratings ........................................ 7

Changes to Recommended Operating Conditions ....................... 7

Changes to Ordering Guide ............................................................. 8

6/03—Rev. C to Rev. D

Changed DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics ................................................................................... 6

Updated Ordering Guide ................................................................. 8

Updated Outline Dimensions ........................................................ 13

4/03—Rev. B to Rev. C

Changes to Features and Patent Note ............................................. 1

Changes to Regulatory Information ............................................... 6

Changes to Insulation Characteristics Section .............................. 6

Changes to Absolute Maximum Ratings........................................ 7

Changes to Package Branding ......................................................... 8

Changes to Method of Operation, DC Correctness, and

Magnetic Field Immunity Section ................................................ 11

Replaced Figure 9 ............................................................................ 12

1/03—Rev. A to Rev. B

Added ADuM1100UR Grade ........................................... Universal

Changed ADuM1100AR/ADuM1100BR to

ADuM1100 ......................................................................... Universal

Changes to Features and General Description .............................. 1

Changes to Specifications................................................................. 2

Added Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V

Operation Table ................................................................................. 4

Updated Regulatory Information ................................................... 6

Changes to VDE 0884 Insulation Characteristics ........................ 6

Changes to Absolute Maximum Ratings........................................ 7

Changes to Package Branding ......................................................... 8

Updated TPC 3 to TPC 8 ................................................................. 9

Deleted iCoupler in Field Bus Networks Section ....................... 11

Changes to Figure 8 ........................................................................ 12

Added Figure 9 and Related Text .................................................. 12

11/02—Rev. 0 to Rev. A

Edits to Features ................................................................................ 1

Edits to Regulatory Information ..................................................... 4

Edits to VDE 0884 Insulation Characteristics ............................... 5

Added Revision History ................................................................. 12

Updated Outline Dimensions........................................................ 12

Rev. K | Page 3 of 20

ADuM1100 Data Sheet

Input Supply Current

I

0.3

0.8

mA

VI = 0 V or V

Logic High Output Voltage

VOH

V

− 0.1

5.0 V

IO = −20 μA, VI = VIH

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

DD1 (Q)

Output Supply Current I Input Supply Current (25 Mbps)

0.01 0.06 mA VI = 0 V or V

DD2 (Q)

I

2.2 3.5 mA 12.5 MHz logic signal frequency

DD1 (25)

(See Figure 5)

Output Supply Current1 (25 Mbps)

I

0.5 1.0 mA 12.5 MHz logic signal frequency

DD2 (25)

(See Figure 6)

Input Supply Current (100 Mbps)

I

9.0 14 mA 50 MHz logic signal frequency,

DD1 (100)

(See Figure 5)

Output Supply Current1 (100 Mbps)

I

2.0 2.8 mA 50 MHz logic signal frequency,

DD2 (100)

(See Figure 6)

Input Current II −10 +0.01 +10 µA 0 V ≤ VIN ≤ V

V Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL

0.03 0.1 V IO = 400 μA, VI = VIL

0.3 0.8 V IO = 4 mA, VI = VIL

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels

For ADuM1100BR/ADuM1100UR

Minimum Pulse Width2 PW 6.7 10 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 100 150 Mbps CL = 15 pF, CMOS signal levels

For All Grades

Propagation Delay Time to Logic Low

Propagation Delay Time to Logic High

Pulse Width Distortion |t

Output

4, 5

(See Figure 7)

4, 5

(See Figure 7)

PLH

− t

|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PHL

10.5 18 ns CL = 15 pF, CMOS signal levels

t

PHL

10.5 18 ns CL = 15 pF, CMOS signal levels

t

PLH

Change vs. Temperature6 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew

(Equal Temperature)

5, 7

Propagation Delay Skew

(Equal Temperature, Supplies)

5, 7

8 ns CL = 15 pF, CMOS signal levels

t

PSK1

6 ns CL = 15 pF, CMOS signal levels

t

PSK2

Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity

at Logic Low/High Output

8

Refresh Rate f Input Dynamic Supply Current9 I Output Dynamic Supply Current9 I

|,

|CM

L

|CM

|

H

r

0.09 mA/Mbps

DDI (D)

0.02 mA/Mbps

DDO (D)

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications

DD2

A

ADuM1100BR/ADuM1100UR only

DD2

− 0.8 4.6 V IO = −4 mA, VI = VIH

DD2

25 35 kV/µs V

= 0 V or V

I

transient magnitude = 800 V

1.2 Mbps

= 25°C, V

DD1

, VCM = 1000 V,

DD1

= V

DD2

= 5 V.

Rev. K | Page 4 of 20

Data Sheet ADuM1100

1

Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See

the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. t

PHL

rising edge of the V

5

Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width

signal to the 50% level of the rising edge of the VO signal.

I

distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters.

6

Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.

7

t

is the magnitude of the worst-case difference in t

PSK1

recommended operating conditions. t temperature, supply voltages, and output load within the recommended operating conditions.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on

is the magnitude of the worst-case difference in t

PSK2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range

O

and/or t

PHL

that is measured between units at the same operating temperature and output load within the

PLH

and/or t

PHL

that is measured between units at the same operating

PLH

. CML is the maximum common-mode voltage slew rate

DD2

supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

is measured from the 50% level of the

PLH

Rev. K | Page 5 of 20

ADuM1100 Data Sheet

For ADuM1100AR

High Output

(See Figure 8)

Pulse Width Distortion |t

− t

|5

PWD

0.5

3

ns

CL = 15 pF, CMOS signal levels

Output Rise/Fall Time

tR, tF 3 ns

CL = 15 pF, CMOS signal levels

ELECTRICAL SPECIFICATIONS—3.3 V OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ V over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current I Output Supply Current I Input Supply Current (25 Mbps)

0.1 0.3 mA VI = 0 V or V

DD1 (Q)

0.005 0.04 mA VI = 0 V or V

DD2 (Q)

I

2.0 2.8 mA 12.5 MHz logic signal frequency

DD1 (25)

(See Figure 5)

Output Supply Current1 (25 Mbps)

I

0.3 0.7 mA 12.5 MHz logic signal frequency

DD2 (25)

(See Figure 6)

Input Supply Current (50 Mbps)

I

4.0 6.0 mA 25 MHz logic signal frequency,

DD1 (50)

(See Figure 5)

Output Supply Current1 (50 Mbps)

I

1.2 1.6 mA 25 MHz logic signal frequency,

DD2 (50)

(See Figure 6) Input Current II −10 +0.01 +10 µA 0 V ≤ VIN ≤ V Logic High Output Voltage VOH V V Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL

0.04 0.1 V IO = 400 μA, VI = VIL

0.3 0.4 V IO = 2.5 mA, VI = VIL

SWITCHING SPECIFICATIONS

≤ 3.6 V, 3.0 V ≤ V

DD1

≤ 3.6 V. All minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

ADuM1100BR/ADuM1100UR only

DD1

− 0.1 3.3 V IO = −20 μA, VI = VIH

DD2

− 0.5 3.0 V IO = −2.5 mA, VI = VIH

DD2

DD1

= V

= 3.3 V.

DD2

Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR

Minimum Pulse Width2 PW 10 20 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 50 100 Mbps CL = 15 pF, CMOS signal levels For All Grades

Propagation Delay Time to Logic Low

Propagation Delay Time to Logic

Output

4, 5

(See Figure 8)

4, 5

PLH

PHL

14.5 28 ns CL = 15 pF, CMOS signal levels

t

PHL

t

15.0 28 ns CL = 15 pF, CMOS signal levels

PLH

Change vs. Temperature6 10 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew

(Equal Temperature)

Propagation Delay Skew

(Equal Temperature, Supplies)

Common-Mode Transient Immunity

at Logic Low/High Output

5, 7

8

Refresh Rate f

Input Dynamic Supply Current9 I

Output Dynamic Supply Current9 I

15 ns CL = 15 pF, CMOS signal levels

t

PSK1

12 ns CL = 15 pF, CMOS signal levels

t

PSK2

|,

|CM |CM

r

DDI (D)

DDO (D)

L

H

25 35 kV/µs V

|

1.1 Mbps

0.08 mA/Mbps

0.04 mA/Mbps

= 0 V or V

I

, VCM = 1000 V,

DD1

transient magnitude = 800 V

Rev. K | Page 6 of 20

Data Sheet ADuM1100

1

Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See

the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. t

PHL

rising edge of the V

5

Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width

signal to the 50% level of the rising edge of the VO signal.

I

distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters.

6

Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.

7

t

is the magnitude of the worst-case difference in t

PSK1

recommended operating conditions. t temperature, supply voltages, and output load within the recommended operating conditions.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on

is the magnitude of the worst-case difference in t

PSK2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range

O

and/or t

PHL

that is measured between units at the same operating temperature and output load within the

PLH

and/or t

PHL

that is measured between units at the same operating

PLH

. CML is the maximum common-mode voltage slew rate

DD2

supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

is measured from the 50% level of the

PLH

Rev. K | Page 7 of 20

ADuM1100 Data Sheet

3 V/5 V Operation

2.0

2.8

mA

12.5 MHz logic signal frequency

3 V/5 V Operation

V

− 0.8

4.6 V

IO = −4 mA, VI = VIH

ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V

3.0 V ≤ V unless otherwise noted. All typical specifications are at T

≤ 3.6 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,

DD2

= 25°C, V

A

= 3.3 V, V

DD1

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, Quiescent I

DDI (Q)

5 V/3 V Operation 0.3 0.8 mA

3 V/5 V Operation 0.1 0.3 mA Output Supply Current, Quiescent I

DDO (Q)

5 V/3 V Operation 0.005 0.04 mA

3 V/5 V Operation 0.01 0.06 mA Input Supply Current, 25 Mbps I

DDI (25)

5 V/3 V Operation 2.2 3.5 mA 12.5 MHz logic signal frequency

≤ 5.5 V, 3.0 V ≤ V

DD1

= 5 V or V

DD2

= 5 V, V

DD1

≤ 3.6 V. 3 V/5 V operation:

DD2

= 3.3 V.

DD2

Output Supply Current1, 25 Mbps I

DDO (25)

5 V/3 V Operation 0.3 0.7 mA 12.5 MHz logic signal frequency

3 V/5 V Operation 0.5 1.0 mA 12.5 MHz logic signal frequency Input Supply Current, 50 Mbps I

DDI (50)

5 V/3 V Operation 4.5 7.0 mA 25 MHz logic signal frequency

3 V/5 V Operation 4.0 6.0 mA 25 MHz logic signal frequency Output Supply Current1, 50 Mbps I

DDO (50)

5 V/3 V Operation 1.2 1.6 mA 25 MHz logic signal frequency

3 V/5 V Operation 1.0 1.5 mA 25 MHz logic signal frequency Input Currents IIA −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ V Logic High Output Voltage VOH V

5 V/3 V Operation V

− 0.1 3.3 V IO = −20 μA, VI = VIH

DD2

− 0.5 3.0 V IO = −2.5 mA, VI = VIH

DD2

Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL

5 V/3 V Operation 0.04 0.1 V IO = 400 μA, VI = VIL

0.3 0.4 V IO = 2.5 mA, VI = VIL Logic High Output Voltage VOH V

− 0.1 5.0 V IO = −20 μA, VI = VIH

DD2

Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL

3 V/5 V Operation 0.03 0.1 V IO = 400 μA, VI = VIL

0.3 0.8 V IO = 4 mA, VI = VIL

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR

Minimum Pulse Width2 PW 20 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 50 Mbps CL = 15 pF, CMOS signal levels For All Grades

Propagation Delay Time to Logic

Low/High Output

4, 5

, t

t

PHL

PLH

5 V/3 V Operation (See Figure 9) 13 21 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation (See Figure 10) 16 26 ns CL = 15 pF, CMOS signal levels

DD1

or V

DD2

Rev. K | Page 8 of 20

Data Sheet ADuM1100

Parameter Symbol Min Typ Max Unit Test Conditions

Pulse Width Distortion, |t

5 V/3 V Operation 0.5 2 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation 0.5 3 ns CL = 15 pF, CMOS signal levels Change in Pulse Width Distortion vs.

Temperature

6

5 V/3 V Operation 3 ps/°C CL = 15 pF, CMOS signal levels 3 V/5 V Operation 10 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew (Equal

Temperature)

5, 7

5 V/3 V Operation 12 ns CL = 15 pF, CMOS signal levels 3 V/5 V Operation 15 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew (Equal

Temperature, Supplies) 5 V/3 V Operation 9 ns CL = 15 pF, CMOS signal levels

3 V/5 V Operation 12 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity at

Logic Low/High Output

Refresh Rate f

5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current9 C

5 V/3 V Operation 0.09 mA/Mbps 3 V/5 V Operation 0.08 mA/Mbps

Output Dynamic Supply Current9 C

5 V/3 V Operation 0.04 mA/Mbps 3 V/5 V Operation 0.02 mA/Mbps

1

Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See

the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. t

PHL

rising edge of the V

5

Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width

distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters.

6

Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.

7

t

is the magnitude of the worst-case difference in t

PSK1

recommended operating conditions. t temperature, supply voltages, and output load within the recommended operating conditions.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on

supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

signal to the 50% level of the rising edge of the VO signal.

I

PLH

− t

|5 PWD

PHL

t

PSK1

t

5, 7

8

is the magnitude of the worst-case difference in t

PSK2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range

O

PSK2

|,

|CM

L

|CM

H

r

PD1

PD2

and/or t

PHL

25 35 kV/µs V

|

that is measured between units at the same operating temperature and output load within the

PLH

and/or t

PHL

PLH

= 0 V or V

I

, VCM = 1000 V,

DD1

transient magnitude = 800 V

is measured from the 50% level of the

PLH

that is measured between units at the same operating

. CML is the maximum common-mode voltage slew rate

DD2

Rev. K | Page 9 of 20

ADuM1100 Data Sheet

Resistance (Input-to-Output)1

R

1012 Ω

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

I-O

Capacitance (Input-to-Output)1 C Input Capacitance2 CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θ IC Junction-to-Case Thermal Resistance, Side 2 θ

Package Power Dissipation PPD 240 mW

1

The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.

2

Input capacitance is measured at Pin 2 (VI).

REGULATORY INFORMATION

The ADuM1100 is approved by the following organizations.

Table 5.

UL CSA CQC VDE

Recognized Under

1577 Component Recognition Program1

Single/Basic Insulation,

2500 V rms Isolation Voltage

File E214100 File 205078 File CQC14001117247 File 2471900-4880-0001

1

In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).

2

In accordance with DIN V VDE V 0884-10, each ADuM1100 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection

limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10

Approved under CSA Component Acceptance Notice 5A

Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage

1.0 pF f = 1 MHz

I-O

46 °C/W Thermocouple located at

JCI

41 °C/W

JCO

center of package underside

Approved under CQC11-471543-2012

Basic insulation per GB4943.1-

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

Reinforced insulation, 560 V peak 2011 400 V rms (588 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 meters

approval.

2

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals,

shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.016 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I) Maximum Working Voltage Compatible with

50 Years Service Life

V

565 V peak Continuous peak voltage across the isolation barrier

IORM

Rev. K | Page 10 of 20

Data Sheet ADuM1100

Input-to-Output Test Voltage, Method B1

V

× 1.875 = VPR, 100% production test,

VPR

1050

V peak

CASE TEMPERATURE (°C)

180

0

SAFETY-LIMIT ING CURRENT (mA)

100

80

0

50 100 150 200

120

160

140

20

40

60

INPUT CURRENT

OUTPUT CURRENT

02462-002

ADuM1100AR/ADuM1100BR

TA

−40

+105

°C

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS

This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.

Table 7.

Description Conditions Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage V

IORM

tm = 1 sec, partial discharge < 5 pC

Input-to-Output Test Voltage, Method A V

× 1.6 = VPR, tm = 60 sec, partial

IORM

discharge < 5 pC After Environmental Tests Subgroup 1 896 V peak After Input and/or Safety Test Subgroup 2 and Subgroup 3 V

× 1.2 = VPR, tm = 60 sec, partial

IORM

discharge < 5 pC

Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak Safety-Limiting Values Maximum value allowed in the event of

a failure (see

Figure 2)

Case Temperature TS 150 °C Side 1 Current IS1 160 mA Side 2 Current IS2 170 mA

Insulation Resistance at TS VIO = 500 V RS >109 Ω

560 V peak

IORM

VPR

672 V peak

Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature

ADuM1100UR TA −40 +125 °C

Supply Voltages1 V

Logic High Input Voltage,

5 V Operation

1, 2

(See Figure 11 and Figure 12)

Logic Low Input Voltage,

5 V Operation (See Figure 11 and Figure 12)

Logic High Input Voltage,

3.3 V Operation

1, 2

(See Figure 11 and Figure 12)

Logic Low Input Voltage,

3.3 V Operation

1, 2

(See Figure 11 and Figure 12)

Input Signal Rise and Fall Times 1.0 ms

1

All voltages are relative to their respective ground.

2

Input switching thresholds have 300 mV of hysteresis. See the Method of

Operation, DC Correctness, and Magnetic Field Immunity section, Figure 19, and Figure 20 for information on immunity to external magnetic fields.

Rev. K | Page 11 of 20

,

DD1

V

DD2

2.0 V

V

IH

V

0.0 0.8 V

IL

VIH 1.5 V

3.0 5.5 V

DD1

V

VIL 0.0 0.5 V

ADuM1100 Data Sheet

−100

+100

kV/µs

VI Input

V

State

V

State

VO Output

8

1

ADuM1100UR, ADuM1100UR-RL7

8

1

ADuM1100BR, ADuM1100BR-RL7

8

1

AD1100A

R YYWW*

XXXXXX

AD1100B

R YYWW*

XXXXXX

AD1100U

R YYWW*

XXXXXX

ADuM1100AR, ADuM1100AR-RL7

02462-003

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Symbol Min Max Unit

Storage Temperature TST −55 +150 °C Ambient Operating

TA −40 +125 °C

Temperature

, V

Supply Voltages1

V Input Voltage1 VI −0.5 V Output Voltage1 VO −0.5 V Average Current, per Pin2

−0.5 +6.5 V

DD1

DD2

+ 0.5 V

DD1

+ 0.5 V

DD2

Temperature ≤ 105°C −25 +25 mA Temperature ≤ 125°C

Input Current −7 +7 mA Output Current −20 +20 mA

Common-Mode Transients3

1

All voltages are relative to their respective ground.

2

See Figure 2 for information on maximum allowable current for various

temperatures.

3

Refers to common-mode transients across the insulation barrier.

Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or permanent damage.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Table 10. Truth Table (Positive Logic)

DD1

DD2

H Powered Powered H L Powered Powered L X Unpowered Powered H1 X Powered Unpowered X1

1

VO returns to VI state within 1 μs of power restoration.

Figure 3 shows the package branding. The asterisk (*) is the DIN EN 60747-5-2 mark, R is the package designator (R denotes SOIC_N), YYWW is the date code, and XXXXXX is the lot code.

Figure 3. Package Branding

Rev. K | Page 12 of 20

Data Sheet ADuM1100

V

DD1

1

V

I

2

V

DD1

1

3

GND

1

4

V

DD2

8

GND

2

7

V

O

6

GND

2

5

ADuM1100

TOP VIEW

(Not to S cale)

02462-004

1

PIN 1 AND PIN 3 ARE I NTERNALLY CONNECTED. E ITHER OR BOTH MAY BE USED FO R V

DD1

.

2

PIN 5 AND PIN 7 ARE I NTERNALLY CONNECTED. E ITHER OR BOTH MAY BE USED FO R GND

2

.

1

V

Input Supply Voltage, 3.0 V to 5.5 V.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 11. Pin Function Descriptions

Pin No. Mnemonic Description

DD1

2 VI Logic Input. 3 V

Input Supply Voltage, 3.0 V to 5.5 V.

DD1

4 GND1 Input Ground Reference. 5 GND2 Output Ground Reference. 6 VO Logic Output. 7 GND2 Output Ground Reference. 8 V

Output Supply Voltage, 3.0 V to 5.5 V.

DD2

Rev. K | Page 13 of 20

ADuM1100 Data Sheet

DATA RATE (Mbps)

20

0

CURRENT (mA)

18

16

2

0

25

50

75

100

125

150

14

12

10

8

6

4

5V

3.3V

02462-005

DATA RATE (Mbps)

5

0

CURRENT (mA)

3

2

1

0

25 50 75 100 125 150

5V

3.3V

4

02462-006

TEMPERATURE (°C)

13

–50

PROPAGATION DELAY ( ns)

11

9

0 50 75 100 125

12

t

PHL

–25 25

t

PLH

10

02462-007

18

–50

14

13

12

–25 25

50 100 125

15

17

16

0

75

t

PHL

t

PLH

TEMPERATURE (°C)

PROPAGATION DELAY ( ns)

02462-008

TEMPERATURE (°C)

PROPAGATION DELAY ( ns)

14

–50

11

10

9

–25 25

50 100 125

12

13

0 75

t

PHL

t

PLH

02462-009

18

–50

14

13

12

–25 25 50 100 125

15

17

16

0 75

t

PHL

t

PLH

TEMPERATURE (°C)

PROPAGATION DELAY ( ns)

02462-010

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Typical Input Supply Current vs. Logic Signal Frequency

for 5 V and 3.3 V Operation

Figure 6. Typical Output Supply Current vs. Logic Signal Frequency

for 5 V and 3.3 V Operation

Figure 8. Typical Propagation Delays vs. Temperature, 3.3 V Operation

Figure 9. Typical Propagation Delays vs. Temperature, 5 V/3 V Operation

Figure 7. Typical Propagation Delays vs. Temperature, 5 V Operation

Figure 10. Typical Propagation Delays vs. Temperature, 3 V/5 V Operation

Rev. K | Page 14 of 20

Data Sheet ADuM1100

1.7

3.0

1.3

1.2

1.1

3.5

4.0 4.5 5.0 5.5

1.4

1.6

1.5

–40°C

+25°C

+125°C

INPUT SUPPLY VOLTAGE, V

DD1

(V)

INPUT THRES HOLD, V

ITH

(V)

02462-011

INPUT SUPPLY VOLTAGE, V

DD1

(V)

1.4

3.0

INPUT THRES HOLD, V

ITH

(V)

1.0

0.9

0.8

3.5 4.0 4.5 5.0 5.5

1.1

1.3

1.2

–40°C

+25°C

+125°C

02462-012

Figure 11. Typical Input Voltage Switching Threshold,

Low-to-High Transition

Figure 12. Typical Input Voltage Switching Threshold,

High-to-Low Transition

Rev. K | Page 15 of 20

ADuM1100 Data Sheet

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM1100 digital isolator requires no external interface circuitry for the logic interfaces. A bypass capacitor is recommended at the input and output supply pins. The input bypass capacitor can conveniently be connected between Pin 3 and Pin 4 (see Figure 13). Alternatively, the bypass capacitor can be located between Pin 1 and Pin 4. The output bypass capacitor can be connected between Pin 7 and Pin 8 or Pin 5 and Pin 8. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm.

V

DD1

VI (DATA IN)

GND

1

Figure 13. Recommended Printed Circuit Board Layout

V

(OPTIONAL)

VO (DATA OUT)

GND

DD2

2

02462-013

See the AN-1109 Application Note for board layout guidelines.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay time describes the length of time it takes for a logic signal to propagate through a component. Propagation delay time to logic low output and propagation delay time to logic high output refer to the duration between an input signal transition and the respective output signal transition (see Figure 14).

INPUT (VI)

50%

Pulse width distortion is the maximum difference between t

PLH

and t

and provides an indication of how accurately the

PHL

input signal’s timing is preserved in the component’s output signal. Propagation delay skew is the difference between the minimum and maximum propagation delay values among multiple ADuM1100 components operated at the same operating temperature and having the same output load.

Depending on the input signal rise/fall time, the measured propagation delay based on the input 50% level can vary from the true propagation delay of the component (as measured from its input switching threshold). This is because the input threshold, as is the case with commonly used optocouplers, is at a different voltage level than the 50% point of typical input signals. This propagation delay difference is given by

Δ

= t′

− t

LH

PLH

Δ

= t′

HL

PHL

= (tR/0.8 VI)(0.5 VI − V

PLH

− t

= (tF/0.8 VI)(0.5 VI − V

PHL

ITH (L-H)

ITH (H-L)

)

where:

t

PLH

and t

are the propagation delays as measured from the

PHL

input 50% level.

t’

PLH

and t’

are the propagation delays as measured from the

PHL

input switching thresholds.

t

and tF are the input 10% to 90% rise/fall times.

R

is the amplitude of the input signal (0 V to VI levels assumed).

V

I

V

ITH (L–H)

and V

are the input switching thresholds.

ITH (H–L)

OUTPUT (V

t

PLH

)

O

Figure 14. Propagation Delay Parameters

∆

V

I

V

ITH(L–H)

INPUT (VI)

OUTPUT (VO)

t

PHL

50%

LH

t

PLH

t'

PLH

50%

02462-014

Figure 15. Impact of Input Rise/Fall Time on Propagation Delay

50%

∆

HL

V

ITH(H–L)

t'

t

PHL

02462-015

Rev. K | Page 16 of 20

Data Sheet ADuM1100

INPUT RISE TIME (10%–90%, ns)

4

1

PROPAGATION DELAY CHANGE, Δ

LH

(ns)

2

0

3

4 8

9

10

3

1

5V INPUT SI GNAL

2

5

6 7

3.3V INPUT S IGNAL

02462-016

INPUT RISE TIME (10%–90%, ns)

0

1

PROPAGATION DELAY CHANGE, Δ

HL

(ns)

–2

–4

3 4 8

9

10

–1

–3

2 5 6 7

02462-017

5V INPUT SI GNAL

3.3V INPUT S IGNAL

INPUT RISE /FALL TIME (10%–90%, ns)

6

1

PULSE WI DTH DISTO RTION ADJUST M E NT,

Δ

PWD

(ns)

0

3 4 8

9

102 5 6 7

5

4

3

2

1

02462-018

3.3V INPUT S IGNAL

5V INPUT SI GNAL

Figure 16. Typical Propagation Delay Change Due to

Input Rise Time Variation (for V

= 3.3 V and 5 V)

DD1

Figure 18. Typical Pulse Width Distortion Adjustment Due to

Input Rise/Fall Time Variation (for V

= 3.3 V and 5 V)

DD1

METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY

The two coils in Figure 1 act as a pulse transformer. Positive and negative logic transitions at the isolator input cause narrow (2 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and therefore either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic update pulse of the appropriate polarity is sent to ensure dc correctness at the output. If the decoder receives none of these update pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a logic high state by the watchdog timer circuit.

Figure 17. Typical Propagation Delay Change Due to

Input Fall Time Variation (for V

= 3.3 V and 5 V)

DD1

The impact of the slower input edge rates can also affect the measured pulse width distortion as based on the input 50% level. This impact can either increase or decrease the apparent pulse width distortion depending on the relative magnitudes of t

, t

, and PWD. The case of interest here is the condition

PHL

PLH

that leads to the largest increase in pulse width distortion. The change in this case is given by

∆

= PWD′ − PWD = ∆LH − ∆HL =

PWD

(t/0.8 V

)(V − V

I

ITH (L-H)

− V

), (for t = tR = tF)

ITH (H-L)

where:

PWD = |t PWD’ = |t’

PLH

− t

− t’

PHL

|.

This adjustment in pulse width distortion is plotted as a function of input rise/fall time in Figure 18.

Rev. K | Page 17 of 20

The limitation on the magnetic field immunity of the

ADuM1100 is set by the condition in which induced voltage in

the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The analysis that follows defines the conditions under which this can occur. The 3.3 V operating condition of the ADuM1100 is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output are greater than 1.0 V in amplitude. The decoder has sensing thresholds at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by

V = (−dβ/dt) ∑π r

2

, n = 1, 2, . . . , N

n

where:

β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. r

is the radius of the nth turn in the receiving coil (cm).

n

ADuM1100 Data Sheet

MAGNETIC FIELD F RE QUENCY (Hz)

100

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY (kgauss)

0.001

10

0.01

0.1

1

1k 10k 100k 1M 10M 100M

02462-019

MAGNETIC FIELD F RE QUENCY (Hz)

1000

MAXIMUM AL LOWABLE CURRE NT (kA)

0.01

100

0.1

1

10

1k

10k 100k

1M 10M 100M

02462-020

DISTANCE = 1m

DISTANCE = 100mm

DISTANCE = 5mm

Given the geometry of the receiving coil in the ADuM1100 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 19.

Figure 19. Maximum Allowable External Magnetic Field

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the

ADuM1100 transformers. Figure 20 expresses these allowable

current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM1100 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted, one would have to place a current of 0.5 kA 5 mm away from the ADuM1100 to affect the comp one nt’s operation.

Figure 20. Maximum Allowable Current for

Various Current-to-ADuM1100 Spacings

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current of the ADuM1100 isolator is a function of the supply voltage, the input data rate, and the output load.

The input supply current is given by

I

= I

DDI

DDI (Q)

= I

I

DDI

× (2f − fr) + I

DDI (D)

DDI (Q)

The output supply current is given by

I

DDO

= I

= (I

f ≤ 0.5fr

DDO (Q)

+ (0.5 × 10−3) × CLV

DDO (D)

) × (2f − fr) + I

DDO

where:

I

, I

DDI (D)

are the input and output dynamic supply currents

DDO (D)

per channel (mA/Mbps).

C

is the output load capacitance (pF).

L

V

is the output supply voltage (V).

DDO

f is the input logic signal frequency (MHz, half the input data

rate, NRZ signaling).

f

is the input stage refresh rate (Mbps).

r

I

, I

DDI (Q)

are the specified input and output quiescent

DDO (Q)

supply currents (mA).

f ≤ 0.5fr

f > 0.5fr

DDO (Q)

f > 0.5fr

Rev. K | Page 18 of 20

Data Sheet ADuM1100

OUTLINE DIMENSIONS

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8° 0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 21. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Maximum Data

Model1 Temperature Range

Rate (Mbps)

ADuM1100AR −40°C to +105°C 25 40 8-Lead SOIC_N R-8 ADuM1100AR-RL7 −40°C to +105°C 25 40 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100ARZ −40°C to +105°C 25 40 8-Lead SOIC_N R-8 ADuM1100ARZ-RL7 −40°C to +105°C 25 40 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100BR −40°C to +105°C 100 10 8-Lead SOIC_N R-8 ADuM1100BR-RL7 −40°C to +105°C 100 10 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100BRZ −40°C to +105°C 100 10 8-Lead SOIC_N R-8 ADuM1100BRZ-RL7 −40°C to +105°C 100 10 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100UR −40°C to +125°C 100 10 8-Lead SOIC_N R-8 ADuM1100UR-RL7 −40°C to +125°C 100 10 8-Lead SOIC_N, 1,000 Piece Reel R-8 ADuM1100URZ −40°C to +125°C 100 10 8-Lead SOIC_N R-8 ADuM1100URZ-RL7 −40°C to +125°C 100 10 8-Lead SOIC_N, 1,000 Piece Reel R-8

1

Z = RoHS Compliant Part.

Minimum Pulse Width (ns)

Package Description

Package Option

Rev. K | Page 19 of 20

ADuM1100 Data Sheet

NOTES

registered trademarks are the property of their respective owners. D02462-0-7/15(K)

Rev. K | Page 20 of 20

ANALOG DEVICES ADUM 1100 BRZ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS—5 V OPERATION

ELECTRICAL SPECIFICATIONS—3.3 V OPERATION

ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATION INFORMATION

PC BOARD LAYOUT

PROPAGATION DELAY-RELATED PARAMETERS

METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY

POWER CONSUMPTION

OUTLINE DIMENSIONS

ORDERING GUIDE