ANALOG DEVICES ADUM 1100 BRZ Datasheet

iCoupler Digital Isolator

Data Sheet

ADuM1100

Rev. K Document Feedback

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UPDATE

V

DD1

V

I

(DATA IN)

V

DD1

GND

1

V

DD2

GND

2

V

O

(DATA OUT)

GND

2

ADuM1100

NOTES

1. FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION,
DC CORRECTNESS, AND MAGNETIC FIEL D IMMUNITY S E CTION.

8

7

6

5

1

2

3

4

02462-001

FEATURES

High data rate: dc to 100 Mbps (NRZ)
Compatible with 3.3 V and 5.0 V operation/level translation
125°C maximum operating temperature
Low power operation

5 V operation

1.0 mA maximum @ 1 Mbps

4.5 mA maximum @ 25 Mbps

16.8 mA maximum @ 100 Mbps

3.3 V operation

0.4 mA maximum @ 1 Mbps

3.5 mA maximum @ 25 Mbps

7.1 mA maximum @ 50 Mbps
8-lead SOIC_N package (RoHS compliant version available)
High common-mode transient immunity: >25 kV/μs

Safety and regulatory approvals

UL recognized

2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V

= 560 V peak

IORM

APPLICATIONS

Digital field bus isolation
Opto-isolator replacement
Computer peripheral interface
Microprocessor system interface
General instrumentation and data acquisition applications

GENERAL DESCRIPTION

The ADuM11001 is a digital isolator based on Analog Devices
Inc., iCoupler® technology. Combining high speed CMOS and
monolithic air core transformer technology, this isolation
component provides outstanding performance characteristics
superior to alternatives, such as optocoupler devices.

Configured as a pin-compatible replacement for existing high
speed optocouplers, the ADuM1100 supports data rates as high
as 25 Mbps and 100 Mbps.

The ADuM1100 operates with a voltage supply ranging from

3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge
asymmetry of <2 ns, and is compatible with temperatures up
to 125°C. It operates at very low power, less than 0.9 mA of
quiescent current (sum of both sides), and a dynamic current
of less than 160 μA per Mbps of data rate. Unlike other optocoupler
alternatives, the ADuM1100 provides dc correctness with a
patented refresh feature that continuously updates the output
signal.

The ADuM1100 is offered in three grades. The ADuM1100AR
and ADuM1100BR can operate up to a maximum temperature
of 105°C and support data rates up to 25 Mbps and 100 Mbps,
respectively. The ADuM1100UR can operate up to a maximum
temperature of 125°C and supports data rates up to 100 Mbps.

1

Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578; 6,873,065; 7,075,329.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Device s.

FUNCTIONAL BLOCK DIAGRAM

ure 1.

Fig

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2015 Analog Devices, Inc. All rights reserved.

ADuM1100 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Electrical Specifications—5 V Operation ................................. 4

Electrical Specifications—3.3 V Operation .............................. 6

Electrical Specifications—Mixed 5 V/3 V or 3 V/5 V

Operation ....................................................................................... 8

Package Characteristics ............................................................. 10

Regulatory Information ............................................................. 10

Insulation and Safety-Related Specifications .......................... 10

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

Insulation Characteristics .......................................................... 11

Recommended Operating Conditions .................................... 11

Absolute Maximum Ratings ......................................................... 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions ........................... 13

Typical Performance Characteristics ........................................... 14

Application Information ................................................................ 16

PC Board Layout ........................................................................ 16

Propagation Delay-Related Parameters ................................... 16

Method of Operation, DC Correctness, and Magnetic

Field Immunity ........................................................................... 17

Power Consumption .................................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. K | Page 2 of 20

Data Sheet ADuM1100

REVISION HISTORY

7/15—Rev. J to Rev. K

Changes to Table 5 and Table 6 ............................................................. 10

4/15—Rev. I to Rev. J

Changes to Logic Low Output Voltage Parameter, Tes t

Conditions, Ta b l e 2 ..................................................................................... 6

3/12—Rev. H to Rev. I

Created Hyperlink for Safety and Regulatory Approvals

Entry in Features Section ................................................................. 1

Change to PC Board Layout Section ............................................ 16

3/11—Rev. G to Rev. H

Changes to Data Sheet Title ............................................................. 1

Changes to Ordering Guide ........................................................... 18

6/07—Rev. F to Rev. G

Updated VDE Certification Throughout ....................................... 1

Changes to Features and Endnote 1 ................................................ 1

Changes to Table 5 and Table 6 ....................................................... 9

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 18

3/06—Rev. E to Rev. F

Updated Format.................................................................. Universal

Added Note 1 ..................................................................................... 1

Changes to Table 1 ............................................................................ 4

Changes to Table 2 ............................................................................ 6

Changes to Table 3 ............................................................................ 8

Added Tabl e 11 ................................................................................ 13

Inserted Power Consumption Section.......................................... 18

10/03—Rev. D to Rev. E

Changes to Product Name, Features, and General Description . 1

Changes to Regulatory Information ............................................... 6

Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics ................................................................................... 6

Changes to Absolute Maximum Ratings ........................................ 7

Changes to Recommended Operating Conditions ....................... 7

Changes to Ordering Guide ............................................................. 8

6/03—Rev. C to Rev. D

Changed DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics ................................................................................... 6

Updated Ordering Guide ................................................................. 8

Updated Outline Dimensions ........................................................ 13

4/03—Rev. B to Rev. C

Changes to Features and Patent Note ............................................. 1

Changes to Regulatory Information ............................................... 6

Changes to Insulation Characteristics Section .............................. 6

Changes to Absolute Maximum Ratings........................................ 7

Changes to Package Branding ......................................................... 8

Changes to Method of Operation, DC Correctness, and

Magnetic Field Immunity Section ................................................ 11

Replaced Figure 9 ............................................................................ 12

1/03—Rev. A to Rev. B

Added ADuM1100UR Grade ........................................... Universal

Changed ADuM1100AR/ADuM1100BR to

ADuM1100 ......................................................................... Universal

Changes to Features and General Description .............................. 1

Changes to Specifications................................................................. 2

Added Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V

Operation Table ................................................................................. 4

Updated Regulatory Information ................................................... 6

Changes to VDE 0884 Insulation Characteristics ........................ 6

Changes to Absolute Maximum Ratings........................................ 7

Changes to Package Branding ......................................................... 8

Updated TPC 3 to TPC 8 ................................................................. 9

Deleted iCoupler in Field Bus Networks Section ....................... 11

Changes to Figure 8 ........................................................................ 12

Added Figure 9 and Related Text .................................................. 12

11/02—Rev. 0 to Rev. A

Edits to Features ................................................................................ 1

Edits to Regulatory Information ..................................................... 4

Edits to VDE 0884 Insulation Characteristics ............................... 5

Added Revision History ................................................................. 12

Updated Outline Dimensions........................................................ 12

Rev. K | Page 3 of 20

ADuM1100 Data Sheet

Input Supply Current

I

0.3

0.8

mA

VI = 0 V or V

Logic High Output Voltage

VOH

V

− 0.1

5.0 V

IO = −20 μA, VI = VIH

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V
apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

DD1 (Q)

Output Supply Current I
Input Supply Current (25 Mbps)

0.01 0.06 mA VI = 0 V or V

DD2 (Q)

I

2.2 3.5 mA 12.5 MHz logic signal frequency

DD1 (25)

(See Figure 5)

Output Supply Current1 (25 Mbps)

I

0.5 1.0 mA 12.5 MHz logic signal frequency

DD2 (25)

(See Figure 6)

Input Supply Current (100 Mbps)

I

9.0 14 mA 50 MHz logic signal frequency,

DD1 (100)

(See Figure 5)

Output Supply Current1 (100 Mbps)

I

2.0 2.8 mA 50 MHz logic signal frequency,

DD2 (100)

(See Figure 6)

Input Current II −10 +0.01 +10 µA 0 V ≤ VIN ≤ V

V
Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL

0.03 0.1 V IO = 400 μA, VI = VIL

0.3 0.8 V IO = 4 mA, VI = VIL

SWITCHING SPECIFICATIONS

For ADuM1100AR

Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels

For ADuM1100BR/ADuM1100UR

Minimum Pulse Width2 PW 6.7 10 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 100 150 Mbps CL = 15 pF, CMOS signal levels

For All Grades

Propagation Delay Time to Logic Low

Propagation Delay Time to Logic High

Pulse Width Distortion |t

Output

Output

4, 5

(See Figure 7)

4, 5

(See Figure 7)

PLH

− t

|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

PHL

10.5 18 ns CL = 15 pF, CMOS signal levels

t

PHL

10.5 18 ns CL = 15 pF, CMOS signal levels

t

PLH

Change vs. Temperature6 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew

(Equal Temperature)

5, 7

Propagation Delay Skew

(Equal Temperature, Supplies)

5, 7

8 ns CL = 15 pF, CMOS signal levels

t

PSK1

6 ns CL = 15 pF, CMOS signal levels

t

PSK2

Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity

at Logic Low/High Output

8

Refresh Rate f
Input Dynamic Supply Current9 I
Output Dynamic Supply Current9 I

|,

|CM

L

|CM

|

H

r

0.09 mA/Mbps

DDI (D)

0.02 mA/Mbps

DDO (D)

≤ 5.5 V, 4.5 V ≤ V

DD1

≤ 5.5 V. All minimum/maximum specifications

DD2

A

ADuM1100BR/ADuM1100UR only

ADuM1100BR/ADuM1100UR only

DD2

− 0.8 4.6 V IO = −4 mA, VI = VIH

DD2

25 35 kV/µs V

= 0 V or V

I

transient magnitude = 800 V

1.2 Mbps

= 25°C, V

DD1

DD1

DD1

, VCM = 1000 V,

DD1

DD1

= V

DD2

= 5 V.

Rev. K | Page 4 of 20

Data Sheet ADuM1100

1

Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See

the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.

2

The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3

The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4

t

is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. t

PHL

rising edge of the V

5

Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width

signal to the 50% level of the rising edge of the VO signal.

I

distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the
impact of given input rise/fall times on these parameters.

6

Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.

7

t

is the magnitude of the worst-case difference in t

PSK1

recommended operating conditions. t
temperature, supply voltages, and output load within the recommended operating conditions.

8

CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

that can be sustained while maintaining V
over which the common mode is slewed.

9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on

is the magnitude of the worst-case difference in t

PSK2

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range

O

and/or t

PHL

that is measured between units at the same operating temperature and output load within the

PLH

and/or t

PHL

that is measured between units at the same operating

PLH

. CML is the maximum common-mode voltage slew rate

DD2

supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.

is measured from the 50% level of the

PLH

Rev. K | Page 5 of 20

ADuM1100 Data Sheet

For ADuM1100AR

High Output

(See Figure 8)

Pulse Width Distortion |t

− t

|5

PWD

0.5

3

ns

CL = 15 pF, CMOS signal levels

Output Rise/Fall Time

tR, tF 3 ns

CL = 15 pF, CMOS signal levels

ELECTRICAL SPECIFICATIONS—3.3 V OPERATION

All voltages are relative to their respective ground. 3.0 V ≤ V
over the entire recommended operation range, unless otherwise noted. All typical specifications are at T

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current I
Output Supply Current I
Input Supply Current (25 Mbps)

0.1 0.3 mA VI = 0 V or V

DD1 (Q)

0.005 0.04 mA VI = 0 V or V

DD2 (Q)

I

2.0 2.8 mA 12.5 MHz logic signal frequency

DD1 (25)

(See Figure 5)

Output Supply Current1 (25 Mbps)

I

0.3 0.7 mA 12.5 MHz logic signal frequency

DD2 (25)

(See Figure 6)

Input Supply Current (50 Mbps)

I

4.0 6.0 mA 25 MHz logic signal frequency,

DD1 (50)

(See Figure 5)

Output Supply Current1 (50 Mbps)

I

1.2 1.6 mA 25 MHz logic signal frequency,

DD2 (50)

(See Figure 6)
Input Current II −10 +0.01 +10 µA 0 V ≤ VIN ≤ V
Logic High Output Voltage VOH V
V
Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL

0.04 0.1 V IO = 400 μA, VI = VIL

0.3 0.4 V IO = 2.5 mA, VI = VIL

SWITCHING SPECIFICATIONS

≤ 3.6 V, 3.0 V ≤ V

DD1

≤ 3.6 V. All minimum/maximum specifications apply

DD2

= 25°C, V

A

DD1

DD1

ADuM1100BR/ADuM1100UR only

ADuM1100BR/ADuM1100UR only

DD1

− 0.1 3.3 V IO = −20 μA, VI = VIH

DD2

− 0.5 3.0 V IO = −2.5 mA, VI = VIH

DD2

DD1

= V

= 3.3 V.

DD2

Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels
For ADuM1100BR/ADuM1100UR

Minimum Pulse Width2 PW 10 20 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate3 50 100 Mbps CL = 15 pF, CMOS signal levels
For All Grades

Propagation Delay Time to Logic Low

Propagation Delay Time to Logic

Output

4, 5

(See Figure 8)

4, 5

PLH

PHL

14.5 28 ns CL = 15 pF, CMOS signal levels

t

PHL

t

15.0 28 ns CL = 15 pF, CMOS signal levels

PLH

Change vs. Temperature6 10 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew

(Equal Temperature)

Propagation Delay Skew

(Equal Temperature, Supplies)

Common-Mode Transient Immunity

at Logic Low/High Output

5, 7

5, 7

8

Refresh Rate f

Input Dynamic Supply Current9 I

Output Dynamic Supply Current9 I

15 ns CL = 15 pF, CMOS signal levels

t

PSK1

12 ns CL = 15 pF, CMOS signal levels

t

PSK2

|,

|CM
|CM

r

DDI (D)

DDO (D)

L

H

25 35 kV/µs V

|

1.1 Mbps

0.08 mA/Mbps

0.04 mA/Mbps

= 0 V or V

I

, VCM = 1000 V,

DD1

transient magnitude = 800 V

Rev. K | Page 6 of 20