ANALOG DEVICES ADuC842, ADuC843 Service Manual
Instruction Set
Data Transfer Operations
MOV A,Rn 1 1
MOV A,@Ri 1 2
MOV A,direct 2 2
MOV A,#data 2 2
MOV Rn,A 1 1
MOV Rn,direct 2 2
MOV Rn,#data 2 2
MOV direct,A 2 2
MOV direct,Rn 2 2
MOV direct,@Ri 2 2
MOV direct,direct 3 3
MOV direct,#data 3 3
MOV @Ri,A 1 2
MOV @Ri,direct 2 2
MOV @Ri,#data 2 2
MOV DPTR,#data16 3 3
MOVC A,@A+DPTR move from 1 4
MOVC A,@A+PC code memory 1 4
MOVX A,@Ri 1 4
MOVX A,@DPTR move to/from 1 4
MOVX @Ri,A data memory 1 4
MOVX @DPTR,A 1 4
PUSH direct push onto stack 2 2
POP direct pop from stack 2 2
XCH A,Rn 1 1
XCH A,@Ri exchange bytes 1 2
XCH A,direct 2 2
XCHD A,@Ri exchg low digits 1 2
move
Boolean Variable Manipulation
CLR C 1 1
CLR bit 2 2
SETB C 1 1
SETB bit 2 2
CPL C 1 1
CPL bit 2 2
ANL C,bit AND bit with C 2 2
ANL C,/bit AND (NOTbit) with C 2 2
ORL C,bit OR bit with C 2 2
ORL C,/bit OR (NOTbit) with C 2 2
MOV C,bit 2 2
MOV bit,C 2 2
clear bit to zero
set bit to one
complement bit
move bit to bit
Program Branching
ACALL addr11 2 3
LCALL addr16 3 4
RET return from sub. 1 4
RETI return from int. 1 4
AJMP addr11 2 3
LJMP addr16 3 4
SJMP rel 2 3
JMP @A+DPTR 1 3
JC rel jump if C set 2 3
JNC rel jmp if C not set 2 3
JB bit,rel jump if bit set 3 4
JNB bit,rel jmp if bit not set 3 4
JBC bit,rel jmp&clear if set 3 4
JZ rel jump if A = 0 2 3
JNZ rel jump if A not 0 2 3
CJNE A,direct,rel 3 4
CJNE A,#data,rel 3 4
CJNE Rn,#data,rel 3 4
CJNE @Ri,#data,rel 3 4
DJNZ Rn,rel decrement and 2 3
DJNZ direct, rel jump if not zero 3 4
NOP no operation 1 1
call subroutine
jump
compare and
jump if not
equal
Instructions That Affect Flags
ADD A,x C = carry out of bit 7
AC = carry out of bit 3
OV = carry out of bit 6, but not 7
ADDC A,x C = carry out of bit 7
AC = carry out of bit 3
OV = carry out of bit 6, but not 7
SUBB A,x C = borrow into bit 7
AC = borrow into bit 3
OV = borrow into bit 6, but not 7
MUL AB C = 0
OV = (result>255)
DIV AB C = 0
OV = divide by zero
bytes
bytes
bytes
Arithmetic Operations
OSC
periods
ADD A,Rn 1 1
ADD A,@Ri 1 2
ADD A,direct 2 2
ADD A,#data 2 2
ADDC A,Rn 1 1
ADDC A,@Ri 1 2
ADDC A,direct 2 2
ADDC A,#data 2 2
SUBB A,Rn 1 1
SUBB A,@Ri subtract from A 1 2
SUBB A,direct with borrow 2 2
SUBB A,#data 2 2
INC A 1 1
INC Rn 1 1
INC @Ri increment 1 2
INC direct 2 2
INC DPTR
DEC A 1 1
DEC Rn 1 1
DEC @Ri 1 2
DEC direct 2 2
MUL AB multiply A by B 1 9
DIV AB divide A by B 1 9
DA A decimal adjust 1 2
add source to A
add with carry
* 13
decrement
* INC DPTR increments the 24bit value DPP/DPH/DPL
Logical Operations
ANL A,Rn 1 1
ANL A,@Ri 1 2
OSC
ANL A,direct 2 2
periods
ANL A,#data 2 2
ANL direct,A 2 2
ANL direct,#data 3 3
ORL A,Rn 1 1
ORL A,@Ri 1 2
ORL A,direct 2 2
ORL A,#data 2 2
ORL direct,A 2 2
ORL direct,#data 3 3
XRL A,Rn 1 1
XRL A,@Ri 1 2
XRL A,direct 2 2
XRL A,#data 2 2
XRL direct,A 2 2
OSC
periods
XRL direct,#data 3 3
CLR A clear A to zero 1 1
CPL A complement A 1 1
RL A rotate A left 1 1
RLC A ...through C 1 1
RR A rotate A right 1 1
RRC A ...through C 1 1
SWAP A swap nibbles 1 1
logical AND
logical OR
logical XOR
Legend
Rn register addressing using R0-R7
@Ri indirect addressing using R0 or R1
direct 8bit internal address (00h-FFh)
#data 8bit constant included in instruction
#data16 16bit constant included in instruction
bit 8bit direct address of bit
rel signed 8bit offset
addr11 11bit address in current 2K page
addr16 16bit address
x any of: Rn, @Ri, direct, #data
DA A C = C or (x>100)
RRC A C = ACC.7
RLC A C = ACC.0
SETB C C = 1
CLR C C = 0
ANL C,bit C = C and bit
ANL C,/bit C = C and NOTbit
ORL C,bit C = C or bit
ORL C,/bit C = C or NOTbit
MOV C,bit C = bit
CJNE x,y,rel C = (x<y)
bytes
bytes
OSC
periods
OSC
periods
Pin Functions
MQFP
CSP
1 56 P1.0 / ADC0 / T2
2 1 P1.1 / ADC1 / T2EX
3 2 P1.2 / ADC2
4 3 P1.3 / ADC3
54,5AV
DD
6 6,7,8 AGND
79CREF
810VREF
9 11 DAC0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
545556
52
53
pin 1 identifier
ADuC842
56pin CSP
TOP VIEW
(not to scale)
15
434445464748495051
139
42
2
41
3
40
4
39
38
5
37
6
36
35
7
34
8
33
32
9
31
10
30
11
29
12
2625242322212019181716
28
27
13
pin 1 identifier
ADuC842
52pin MQFP
TOP VIEW
(not to scale)
10 12 DAC1
11 13 P1.4 / ADC4
12 14 P1.5 / ADC5 / SS
13 15 P1.6 / ADC6
14 16 P1.7 / ADC7
15 17 RESET
16 18 P3.0 / RxD
17 19 P3.1 / TxD
18 20 P3.2 / INT0
19 21 P3.3/INT1/MISO/PWM1
20 22 DVDD
21 23 DGND
P3.4 / T0 / PWMC /
22 24
PWM0 / EXTCLK
23 25 P3.5 / T1 / CONVST
24 26 P3.6 / WR
25 27 P3.7 / RD
26 28 SCLOCK
MQFP
CSP
27 29 SDATA / MOSI
28 30 P2.0 / A8 / A16
29 31 P2.1 / A9 / A17
30 32 P2.2 / A10 / A18
31 33 P2.3 / A11 / A19
32 34 XTAL1 (in)
33 35 XTAL2 (out)
DD
34 36 DV
35 37,38 DGND
36 39 P2.4 / A12 / A20
37 40 P2.5 / A13 / A21
38 41 P2.6/A14/A22/PWM0
39 42 P2.7/A15/A23/PWM1
MQFP
CSP
40 43 EA
41 44 PSEN
42 45 ALE
43 46 P0.0 / AD0
44 47 P0.1 / AD1
45 48 P0.2 / AD2
46 49 P0.3 / AD3
47 50 DGND
48 51 DVDD
49 52 P0.4 / AD4
50 53 P0.5 / AD5
51 54 P0.6 / AD6
52 55 P0.7 / AD7
Code Memory Space Options
FFFFh
F800h
F7FFh
0000h
62 32 8
(NOP instructions)
internal
code space
62K bytes
Flash/EE
FFFFh
8000h
7FFFh
0000h
(NOP instructions)
internal
code space
32K bytes
Flash/EE
FFFFh
2000h
1FFFh
0000h
(NOP instructions)
internal
code space
8K bytes
Flash/EE
Interrupt Vector Addresses
Interrupt Bit Interrupt Name
PSMCON.5 Power Supply Monitor Interrupt 43h 1
WDS WatchDog Timer Interrupt 5Bh 2
IE0 External Interrupt 0 03h 3
ADCI End of ADC Conversion Interrupt 33h 4
TF0 Timer0 Overflow Interrupt 0Bh 5
IE1 External Interrupt 1 13h 6
TF1 Timer1 Overflow Interrupt 1Bh 7
ISPI/I2CI SPI/I
2
C Interrupt 3Bh 8
RI/TI UART Interrupt 23h 9
TF2/EXF2 Timer2 Interrupt 2Bh 10
TIMECON.2 Time Interval Counter Interrupt 53h 11
© 2003 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the
property of their respective companies.
Purchase of licensed I2C components of Analog
Devices or one of its sublicensed Associated
Companies conveys a license for the purchaser
under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the
system conforms to the I2C Standard Specification
as defined by Philips.
Printed in the U.S.A. G03602-4-12/03(0)
Vector
Address
40414243444546474849505152
26252423222120191817161514
Relative
Priority
P3.7 (RD)
P3.6 (WR)
P3.7
P3.6
25242322191817163938373631302928141312
PWM
16bit
counter
timers
time
interval
counter
OSC &
PLL
32
XTAL1
BUF
BUF
33
XTAL2
®
DAC0
9
DAC1
10
38 PWM0
39 PWM1
22
T0
23
T1
1
T2
2
T2EX
18
INT0
19
INT1
38
ADuC842/843 MicroConverter
37
36
35
34
33
32
31
30
29
28
27
hardware
CONVST
Quick Reference Guide
FUNCTIONAL
BLOCK
DIAGRAM
P1.5 (ADC5 / SS)
P1.4 (ADC4)
P1.3 (ADC3)
P1.2 (ADC2)
P1.1 (ADC1 / T2EX)
P1.0 (ADC0 / T2)
P0.7 (AD7)
P0.6 (AD6)
P0.5 (AD5)
P0.4 (AD4)
P0.3 (AD3)
P0.2 (AD2)
P0.1 (AD1)
P0.0 (AD0)
P0.1
P0.0
43
23
1
ADC0
2
ADC1
3
ADC2
4
ADC3
ADC4
ADC5
ADC6
ADC7
V
C
AIN
11
MUX
12
13
14
TEMP
(-3 mV/oC)
sensor
2.5V
bandgap
reference
8
REF
7
REF
5
6
2034354721
DD
AV
AGND
* pin numbers refer to MQFP package
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
52515049464544
T/H
12bit ADC
BUF
POR
48
DD
DV
DGND
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
432
1
11
ADuC842/ADuC843
calibration
4K x 8
data
Flash/EE
62K x 8
program
Flash/EE
baudrate timer
downloader
debugger
asynchronous
serial port
(
UART
16
15RESET
RxD
P1.7 (ADC7)
P1.6 (ADC6)
P1.7
P1.6
ADC
control
&
)
17
TxD
P2.1 (A9 / A17)
P2.0 (A8 / A16)
P2.2 (A10 / A18)
P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.1
P2.0
P2.2
P2.3
P2.4
1-clock
8052
MCU
core
emulator
single-pin
424140
EA
ALE
PSEN
P3.3 (INT1 / MISO / PWM1)
P3.2 (INT0)
P3.1 (TxD)
P3.0 (RxD)
P2.5 (A13 / A21)
P2.6 (A14 / A22 / PWM0)
P2.7 (A15 / A23 / PWM1)
P3.3
P3.2
P3.1
P3.0
P2.5
P2.6
P2.7
DACs on ADuC842 only
DAC0
DAC
control
DAC1
2K x 8
user XRAM
256 x 8
user RAM
watchdog
timer
power supply
monitor
synchronous
serial interfaces
2
(SPI & I
C)
12
262719
SS
MISO
SCLOCK
SDATA / MOSI
P3.5 (T1 / CONVST)
P3.4 (T0/PWMC/PWM0/EXTCLK)
P3.5
P3.4
A Precision Analog Flash MCU
The ADuC842/ADuC843 is:
ADC:
12bit, 5µs, 8channel, self calibrating
0.5LSB INL & 70dB SNR
DAC (ADuC842 only):
dual, 12bit, 15µs, voltage output
<1LSB DNL
Flash/EEPROM:
62K bytes Flash/EE program memory
4K bytes Flash/EE data memory
Microcontroller:
single-cycle 8052, up to 16.8MIPS
32 I/O lines, programmable PLL clock
(131KHz to 16.8MHz from 32KHz crystal)
Embedded Tools Support:
on-chip download/debug & single-pin emulation functions
Other on-chip features:
temperature monitor, power supply monitor, watchdog
timer, flexible serial interface ports, voltage reference,
time interval counter, dual 8/16bit PWM, power-on-reset
REV. 0
Data Memory: RAM, SFRs, user Flash/EE (all read/write)
Lower RAM
decimal
address
HEX
address
127
7Fh
...
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
...
30h
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh R7
1Eh R6
1Dh R5
1Ch R4
1Bh R3
1Ah R2
19h R1
18h R0
17h R7
16h R6
15h R5
14h R4
13h R3
12h R2
11h R1
10h R0
0Fh R7
0Eh R6
0Dh R5
0Ch R4
0Bh R3
0Ah R2
09h R1
08h R0
07h R7
06h R6
05h R5
04h R4
03h R3
02h R2
01h R1
00h R0
General Purpose
Area
Bit Addressable
Area
Register Bank 3
Register Bank 2Register Bank 1Register Bank 0
lower RAM
details
ss
re
B
S
dd
M
a
7Fh 7Eh 7Dh 7Ch 7Bh 7Ah 79h 78h
(bit addresses)
77h 76h 75h 74h 73h 72h 71h 70h
6Fh 6Eh 6Dh 6Ch 6Bh 6Ah 69h 68h
67h 66h 65h 64h 63h 62h 61h 60h
5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h
57h 56h 55h 54h 53h 52h 51h 50h
4Fh 4Eh 4Dh 4Ch 4Bh 4Ah 49h 48h
47h 46h 45h 44h 43h 42h 41h 40h
3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h
37h 36h 35h 34h 33h 32h 31h 30h
2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h
27h 26h 25h 24h 23h 22g 21h 20h
1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h
17h 16h 15h 14h 13h 12h 11g 10h
0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h
07h 06h 05h 04h 03h 02h 01h 00h
Flash/EE
3FFh
000h
data space
( page 1023 )
4K bytes
(1K pages)
data
Flash/EE
(accessible
through
SFRs)
( page 0 )
extended RAM space
FFFFFFh
7FFh
RAM & SFRs
000h
CFG842.0=1
internal
data
memory
2K bytes
FFh
00h
128 bytes
upper RAM
(indirect
addressing
only)
128 bytes
lower RAM
(direct or
indirect
addressing)
SFRs
(direct
addressing
only)
SFR details
XRAM
LSBaddress
CFG842.0=0
external
data
memory
(16M bytes
addressable)
SFR Map
SPIDAT
(reserved)
(reserved)
(reserved)
DACCON
FDh 04h
ADCCON3
DAC1H
FCh 00h
ADCGAINH
DAC1L
FBh 00h
ADCGAINL
DAC0H
FAh 00h
ADCOFSH
DAC0L
ADCOFSL
F9h 00h
SPICON
F8h 04hBF0h 00h
SPR0
F8h 0
SPR1
F9h 0
CPHA
FAh 1
CPOL
FBh 0
SPIM
FCh 0
SPE
FDh 0
WCOL
FEh 0
ISPI
FFh 0
MAP KEY
F7h 00h
F5h 00h
F4h *00h
F3h *00h
F2h *20h
F1h *00h
F0h 0
F1h 0
F2h 0
F3h 0
I2CID0I2CID1I2CGCI2CSI
F4h 0
F5h 0
F6h 0
F7h 0
(reserved)
EFh 40h
ADCCON1
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
ACC
I2CCON
E8h 00h
E0h 00h
I2CI
E8h 0
E0h 0
I2CTX
E9h 0
E1h 0
I2CRS
EAh 0
E2h 0
I2CM
EBh 0
E3h 0
MDIMCOMDEMDO
ECh 0
E4h 0
EDh 0
E5h 0
EEh 0
E6h 0
EFh 0
E7h 0
mnemonic
address
reset value
PLLCON
PSMCON
DFh DEh
(reserved)
(reserved)
(reserved)
(reserved)
DMAP
(reserved)
DMAH
(reserved)
DMAL
DAh 00h
ADCDATAH
(reserved)
D9h 00h
ADCDATAL
PSW
D8h 00h
ADCCON2
CS0
D8h 0PD0h 0
CS1
D9h 0F1D1h 0
CS2
DAh 0OVD2h 0
CS3
RS0
DBh 0
RS1
DCh 0
SCONV
DDh 0F0D5h 0
CCONV
DMA
DEh 0ACD6h 0
ADCI
DFh 0CYD7h 0
EADRH
(reserved)
D7h 53h
EADRL
(reserved)
TH2
(reserved)
CDh 00h
TL2
(reserved)
D4h 00h
CCh 00h
(reserved)(reserved)
RCAP2H
D3h 00h
CBh 00h
CHIPID
RCAP2L
D2h 00h
CAh 00h
(reserved)
T2CON
WDCON
D0h 00h
C8h 00h
CAP2
WDWR
C8h 0
WDE
CNT2
C9h 0
TR2
WDS
CAh 0
WDIR
EXEN2
D3h 0
CBh 0
PRE0
TCLK
D4h 0
CCh 0
PRE1
RCLK
CDh 0
EXF2
PRE2
CEh 0
TF2
PRE3
CFh 0
these bits this byte
SPR0
SPR1
F8h 0
F9h 0
* calibration coefficients are preconfigured at power-up to factory calibrated values
SPH
CFG842
BFh 00h
BEh 00h
BDh 00h
BCh 00h
B9h 00h
B7h 00h
(not used)
(not used)
PWM1H
B4h 00h
PWM1L
B3h 00h
PWM0H
B2h 00h
PWM0L
B1h 00h
CFG843
AFh 00h
PWMCON
AEh 00h
(reserved) (reserved) (reserved) (reserved)
IEIP2
A9h A0h
C7h 00h
C6h 00h
C2h AXh
ED ATA4
ED ATA3
ED ATA2
ED ATA1
(reserved)(reserved)
ECON
C0h 10hIPB8h 00hP3B0h FFhIEA8h 00hP2A0h FFh
PX0
C0h 0
PT0
C1h 0
PX1
C2h 0
PT1
C3h 0
C4h 1PSBCh 0T0B4h 1ESACh 0
PT2
C5h 0
PADC
C6h 0
C7h 0
RXD
B8h 0
B0h 1
TXD
B9h 0
B1h 1
INT0
BAh 0
B2h 1
INT1
BBh 0
B3h 1
BDh 0T1B5h 1
BEh 0WRB6h 1
BFh 0RDB7h 1EAAFh 0
EX0
A8h 0
ET0
A9h 0
EX1
AAh 0
ET1
ABh 0
ET2
ADh 0
EADC
AEh 0
are contained in
SPICON
F8h 04h
DPCON
(not used)
A7h 00h
T3CON
INTVAL
A6h 00h
T3FD
HOUR
A5h 00h
MIN
(not used)
A4h 00h
SEC
I2CADD
A3h 00h
I2CDAT
HTHSEC
A2h 00h
SBUF
TIMECON
A1h 00h
SCON
A0h 1RI98h 0T290h 1
A1h 1TI99h 0
RB8
A2h 1
9Ah 0
TB8
A3h 1
9Bh 0
REN
A4h 1
9Ch 0
SM2
A5h 1
9Dh 0
SM1
A6h 1
9Eh 0
SM0
A7h 1
9Fh 0
mnemonic
reset value
address
(not used)
(not used)
9Eh 00h
(not used)
9Dh 00h
(not used)
I2CADD3
9Bh 55h
93h 00h
I2CADD2
9Ah 00h
92h 00h
I2CADD1
99h 00h
91h 00h
98h 00hP190h FFh
T2EX
91h 1
92h 1
93h 1
94h 1
95h 1
96h 1
97h 1
(reserved) (reserved)
TH1
8Dh 00h
TH0
8Ch 00h
TL1
8Bh 00h
TL0
8Ah 00h
TMOD
89h 00hSP81h 07h
TCON
88h 00hP080h FFh
IT0
88h 0
IE0
89h 0
IT1
8Ah 0
IE1
8Bh 0
TR0
8Ch 0
TF0
8Dh 0
TR1
8Eh 0
TF1
8Fh 0
PCON
87h 00h
(reserved) (reserved)
DPP
84h 00h
DPH
83h 00h
DPL
82h 00h
80h 1
81h 1
82h 1
83h 1
84h 1
85h 1
86h 1
87h 1
ADCCON1
ADCCON1.7 ADC mode (0=off, 1=on)
ADCCON1.6 external Vref select bit (0=on-chip Vref)
ADCCON1.5 conversion time = 16 / ADCclk
ADCCON1.4 ADCclk = 16,777,216Hz / [32,4,8,2]
ADCCON1.3 acquisition time select bits
ADCCON1.2 acq time = [1,2,3,4] / ADCclk
ADCCON1.1 Timer2 convert enable
ADCCON1.0 external CONVST enable
ADCCON2
ADCI ADC interrupt flag
DMA DMA mode enable
CCONV continuous conversion enable bit
SCONV single conversion start bit
CS3 input channel select bits:
CS2 0 - 7 = ADC0 - ADC7
CS1 8 = temperature sensor
CS0 9=DAC0, A=DAC1, B=AGND, C=VREF
ADCCON3
ADCCON3.7 busy indicator flag (0=ADC not active)
ADCCON3.6 (this bit must contain zero)
ADCCON3.5 number of averages selection bits:
ADCCON3.4 [15,1,31,63]
ADCCON3.3 (this bit must contain zero)
ADCCON3.2 (this bit must contain one when calibrating)
ADCCON3.1 cal type select (0=offset, 1=gain)
ADCCON3.0 start calibration bit, cleared by hardware
ADCDATAH
ADCDATAL
DMAP,DMAH,DMAL
ADCGAINH
ADCGAINL
ADCOFSH
ADCOFSL
DACCON
DACCON.7 ModeSelect (0=12bit, 1=8bit)
DACCON.6 DAC1 RangeSelect (0=V
DACCON.5 DAC0 RangeSelect (0=V
DACCON.4 Clear DAC1 (0=0V, 1=normal operation)
DACCON.3 Clear DAC0 (0=0V, 1=normal operation)
DACCON.2 SynchronousUpdate (1=asynchronous)
DACCON.1 PowerDown DAC1 (0=off, 1=on)
DACCON.0 PowerDown DAC0 (0=off, 1=on)
DAC1H,DAC1L
DAC0H,DAC0L
PLLCON
PLLCON.7 oscillator powerdown control bit (0=XTAL on)
PLLCON.6 PLL lock indicator flag (0=out of lock)
PLLCON.5 (this bit must contain zero)
PLLCON.4 (this bit must contain zero)
PLLCON.3 fast interrupt control bit (0=normal)
PLLCON.2 3-bit clock divider value, CD (default=3):
PLLCON.1
PLLCON.0
TIMECON
TIMECON.6 24-hour mode select (0=0..255hour, 1=0..23hour)
TIMECON.5 INTVAL timebase select bits
TIMECON.4 [128th sec, seconds, minutes, hours]
TIMECON.3 single time interval control bit (0=reload&restart)
TIMECON.2 time interval interrupt bit, TII
TIMECON.1 time interval enable bit (0=disable&clear)
TIMECON.0 time clock enable bit (0=disable)
INTVAL
HTHSEC
SEC
MIN
HOUR
ECON
EADRH,EADRL
EDATA 1,ED ATA2,E DATA3 ,EDATA4
SPICON
ISPI SPI interrupt (set by hardware at end of SPI transfer)
WCOL write collision error flag
SPE SPI enable (0=I
SPIM master mode select (0=slave)
CPOL clock polarity select (0=SCLK idles low)
CPHA clock phase select (0=leading edge latch)
SPR1 SPI bitrate select bits
SPR0 bitrate = F
SPIDAT
I2CCON
I2CSI slave mode stop interrupt enable bit (0=disable)
I2CGC slave mode general call status flag
I2CID1 slave mode interrupt decode bits
I2CID0 [start, repeated-start, data, stop]
I2CM master mode select bit (0=slave mode)
I2CRS serial port reset
I2CTX transmission direction status (0=RX,1=TX)
I2CI serial interface interrupt
I2CCON
MDO master mode SDATA output bit
MDE master mode SDATA output enable (0=disable)
MCO master mode SCLK output bit
MDI master mode SDATA input bit
I2CM master mode select bit (0=slave mode)
I2CADD
I2CADD1,I2CADD2,I2CADD3
I2CDAT
PWMCON
PWMCON.7 disable P2.6/P3.4 PWM output (0=enable)
PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res.,
PWMCON.5 2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,
PWMCON.4 5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)]
PWMCON.3 PWM clock divide bits
PWMCON.2 PWM counter = clock / [1,4,16,64]
PWMCON.1 PWM clock source bits [0=F
PWMCON.0 2=T0 ext.int.rate, 3=F
PWM0H,PWM0L
PWM1H,PWM1L
DPCON
DPCON.6 data pointer auto-toggle enable (0=disable)
DPCON.5 shadow data pointer mode control bits
DPCON.4 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
DPCON.3 main data pointer mode control bits
DPCON.2 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
DPCON.1 (not implemented to allow INC DPCON toggling)
DPCON.0 data pointer select [0=main, 1=shadow]
T3CON
T3CON.7 Timer 3 baud rate enable (0=disable)
T3CON.2 binary divide factor (DIV)
T3CON.1 DIV = log[F
T3CON.0 (rounded down)
ADC Control register #1
ADC Control register #2
ADC Control register #3
ADC Data registers
DMA address pointer
ADC Gain
calibration coefficients
ADC Offset
calibration coefficients
DAC Control register
DAC1 data registers
DAC0 data registers
PLL Control register
= 16,777,216Hz / 2
F
CORE
Time Interval Counter Control Register
TIC Interval Register
TIC Elapsed 128th Second Register
TIC Elapsed Seconds Register
TIC Elapsed Minutes Register
TIC Elapsed Hours Register
Data Flash/EE comand register
01h READ page
02h PROGRAM page
04h VERIFY page
05h ERASE page
06h ERASE ALL
Data Flash/EE address registers
Data Flash/EE data registers
SPI Control register
2
C enable, 1=SPI enable)
/ [2,4,8,16] (slave: SPR0=SS)
CORE
SPI Data register
I2C Control register (in slave mode)
I2C Control register (in master mode)
I2C slave Address register
I2C secondary slave Address registers
I2C Data register
PWM Control register
PWM0 data registers
PWM1 data registers
Data Pointer Control register
Timer 3 Control register
82h PROGRAM byte
0Fh EXIT ULOAD mode
F0h ENTER ULOAD mode
(all others reserved)
VCO
/(16·baudrate)] / log2
CORE
, 1=VDD)
REF
, 1=VDD)
REF
XTAL
(16.777MHz)]
CD
/15, 1=F
XTAL
T3FD
CHIPID
CFG842/CFG843
CFG842.7 extended stack-pointer enable (0=disable)
CFG842.6 PWM pins select (0=P2.6/P2.7,1=P3.4/P3.3)
CFG842.5 DAC output buffer bypass (0=buffer enabled)
CFG842.4 external clock select (0=internal clock)
CFG842.3 (this bit must contain 0)
CFG842.2 (this bit must contain 0)
CFG842.1 select SPI pins (0=default, 1=P3.3/P3.4/P3.5)
CFG842.0 internal XRAM select (0=external XRAM)
WDCON
PRE3 watchdog timeout selection bits
PRE2 0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms
PRE1 8=0ms (immediate reset)
PRE0 >8=reserved
WDIR watchdog interrupt response bit
WDS watchdog status flag (1 indicates watchdog timeout)
WDE watchdog enable control (0=disabled)
WDWR watchdog write enable bit (set to enable write)
PSMCON
PSMCON.6 PSM status bit (1=normal / 0=fault)
PSMCON.5 PSM interrupt bit
PSMCON.4 trip point select bits
PSMCON.3 [(reserved), 3.08V, 2.93V, (reserved)]
PSMCON.2 (this bit must contain zero)
PSMCON.1 (reserved)
PSMCON.0 PSM powerdown control (1=on / 0=off)
SP
SPH
IE
EA enable interrupts (0=all interrupts disabled)
EADC enable ADCI (ADC interrupt)
ET2 enable TF2/EXF2 (Timer2 overflow interrupt)
ES enable RI/TI (serial port interrupt)
ET1 enable TF1 (Timer1 overflow interrupt)
EX1 enable IE1 (external interrupt 1)
ET0 enable TF0 (Timer0 overflow interrupt)
EX0 enable IE0 (external interrupt 0)
IEIP2
IEIP2.6 priority of TII interrupt (time interval)
IEIP2.5 priority of PSMI interrupt (power supply monitor)
IEIP2.4 priority of ISPI interrupt (serial interface)
IEIP2.3 (this bit must contain zero)
IEIP2.2 enable TII interrupt (time interval)
IEIP2.1 enable PSMI (power supply monitor interrupt)
IEIP2.0 enable ISPI interrupt (serial interface)
IP
PADC priority of ADCI (ADC interrupt)
PT2 priority of TF2/EXF2 (Timer2 overflow interrupt)
PS priority of RI/TI (serial port interrupt)
PT1 priority of TF1 (Timer1 overflow interrupt)
PX1 priority of IE1 (external interrupt 1)
PT0 priority of TF0 (Timer0 overflow interrupt)
PX0 priority of IE0 (external interrupt 0)
TMOD
TMOD.3/.7 gate control bit (0=ignore INTx)
TMOD.2/.6 counter/timer select bit (0=timer)
TMOD.1/.5 timer mode selecton bits
TMOD.0/.4 [13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TCON
TF1 Timer1 overflow flag (auto cleared on vector to ISR)
TR1 Timer1 run control (0=off, 1=run)
TF0 Timer0 overflow flag (auto cleared on vector to ISR)
TR0 Timer0 run control (0=off, 1=run)
IE1 external INT1 flag (auto cleared on vector to ISR)
IT1 IE1 type (0=level trig, 1=edge trig)
IE0 external INT0 flag (auto cleared on vector to ISR)
IT0 IE0 type (0=level trig, 1=edge trig)
TH0,TL0
TH1,TL1
T2CON
TF2 overflow flag
EXF2 external flag
RCLK receive clock enable (0=Timer1 used for RxD clk)
TCLK transmit clock enable (0=Timer1 used for TxD clk)
EXEN2 external enable (0=ignore T2EX, 1=cap/rld on T2EX)
TR2 run control (0=stop, 1=run)
CNT2 timer/counter select (0=timer, 1=counter)
CAP2 capture/reload select (0=reload, 1=capture)
TH2,TL2
RCAP2H,RCAP2L
P0
P1
T2EX timer/counter 2 capture/reload trigger
T2 timer/counter 2 external input
P2
P3
RD external data memory read strobe
WR external data memory write strobe
T1 timer/counter 1 external input
T0 timer/counter 0 external input
INT1 external interrupt 1
INT0 external interrupt 0
TxD serial port transmit data line
RxD serial port receive data line
SCON
SM0 UART mode control bits baud rate:
SM1 00 - 8bit shift register - F
SM2 in modes 2&3, enables multiprocessor communication
REN receive enable control bit
TB8 in modes 2&3, 9th bit transmitted
RB8 in modes 2&3, 9th bit received
TI transmit interrupt flag
RI receive interrupt flag
SBUF
PCON
PCON.7 double baud rate control
PCON.4 ALE disable (0=normal, 1=forces ALE high)
PCON.3 general purpose flag
PCON.2 general purpose flag
PCON.1 power-down control bit (recoverable with hard reset)
PCON.0 idle-mode control (recoverable with enabled interrupt)
PSW
,
CY carry flag
AC auxiliary carry flag
F0 general purpose flag 0
RS1 register bank select control bits
RS0 active register bank = [0,1,2,3]
OV overflow flag
F1 general purpose flag 1
P parity of ACC
DPP
DPH,DPL (DPTR)
ACC
B
Timer 3 Fractional Divider register
T3FD = (2·F
01 - 8bit UART - variable
10 - 9bit UART - F
11 - 9bit UART - variable
) / (baudrate·2
CORE
Chip ID Register
Interrupt Enable register #1
Interrupt Enable/Priority register #2
Interrupt Priority register
Timer Mode register
Timer Control register
Port0 register
Port1 register (analog & digital inputs)
Port2 register
Port3 register
Serial communications Control register
Serial port Buffer register
Power Control register
Program Status Word
Accumulator
auxiliary math register
(AX hex = ADuC842/843)
ADuC84x Config. Register
Watchdog Timer control register
Power Supply Monitor control register
Stack Pointer
Stack Pointer High byte
Timer0 registers
Timer1 registers
Timer2 Control register
Timer2 register
Timer2 Reload/Capture
(also A0-A7 & D0-D7)
(also A8-A15 & A16-A23)
CORE
CORE
Data Pointer Page
Data Pointer
/12
/64(x2)
(DIV-1)
) - 64
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