ANALOG DEVICES ADuC841, ADuC842, ADuC843 Service Manual

MicroConverter® Multichannel 12-Bit ADC with

Anomaly Sheet for Silicon Rev. E

This anomaly list represents the known bugs, anomalies, and workarounds for the ADuC841, ADuC842, and ADuC843 MicroConverter
products. The anomalies listed apply to all ADuC841/ADuC842/ADuC843 packaged material branded as follows:

First(CSP) /Second (PQFP) Line ADuC841 or ADuC842 or ADuC843
Third (CSP) / Fourth Line (PQFP) E20

Analog Devices, Inc. is committed, through future silicon revisions, to continuously improving silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems implementing the recommended
workarounds outlined here.

Embedded 62 kB Flash and Single-Cycle MCU

ADuC841/ADuC842/ADuC843

ADuC841/ADuC842/ADuC843 SILICON REVISION HISTORY

Silicon
Revision
Identifier

E 0 All silicon branded

E 0 All silicon branded

Kernel
Revision
Identifier

Chip Marking Silicon Status

Release Rev. 0 8
ADUC841BS or ADuC841BCP
ADuC842BS or ADuC842BCP
ADuC843BS or ADuC843BCP
Third/Fourth Line: E20

Release Rev. A 11
ADUC841BS or ADuC841BCP
ADuC842BS or ADuC842BCP
ADuC843BS or ADuC843BCP
Third/Fourth Line: E20

Anomaly Sheet

No. of Reported Anomalies

Rev. A

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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADuC841/ADuC842/ADuC843

ANOMALIES

1. Mode 0 UART Operation [er001]

Background: UART Mode 0 allows the UART to function in an 8-bit shift register mode.
Issue: UART Mode 0 is nonfunctional on the ADuC841/ADuC842/ADuC843.
Workaround: None.
Related Issues: None.

2. Use of the Extended Stack Pointer [er002]

Background: The extended stack pointer allows the stack to overflow into internal XRAM.
Issue:

Work around:

Related Issues: None.

3. Use of I2C in Slave Mode with Stop Interrupt Enabled [er003]

Background:

Issue A:

Workaround A: When a stop interrupt is detected, the user should reset the I
Issue B:

Workaround B:

Related Issues: er004: Use of I

4. Use Of I2C in Slave Mode with Stop Interrupt Disabled [er004]

Background:

Issue:

Workaround: None.
Related Issues: None.

5. I2C Data Transfer [er005]

Background: The I2CDAT register is used to read or write data to the I2C bus. The I2CDAT register has an SFR address of 0x9A.
Issue A: During an I2C transfer if a user accesses the RAM address 0x9A the contents of the I2CDAT SFR can be modified.
Workaround A:

Issue B:

Workaround B:

Issue C:

Workaround C: If a second START+matching address is issued following a NACK, this is detected correctly.
Related Issues: None.

A PUSH onto the extended stack when it is the first instruction within a subroutine results in the return address being
overwritten.

For Assembly code, insert a NOP as the first instruction in any subroutine.
For C code, there is currently no workaround.

2

In slave mode, the I
condition. The I

C interface can be configured to generate an interrupt due to a start, repeated start, data, or stop

2

C interrupt decode bits (I2CID0 and I2CID1) in I2CCON indicate the source of the interrupt. If the stop

interrupt is enabled via the I2CSI bit, an interrupt is generated when the slave receives a stop condition.

2

C interrupt service routine, if the I2CI bit or I2CDAT register is accessed during a stop interrupt, the I2C bus will

In the I
fail to respond to further I

When the stop interrupt is enabled, on occasion the I
DATA interrupt occurred when the source was in fact a stop interrupt. If this happens the user may try to clear I2CI or
read I2CDAT, resulting in the bus failing to respond to further I

2

C communication.

2

2

C bus by using the I2CRS bit.

C interrupt decode bits indicate that a start, repeated start, or

2

C communication.

Tie the SCLOCK pin to an I/O pin; This allows the state of SCLOCK to be read. SCLOCK is high only during an interrupt if
the source is a stop interrupt.

2

C in slave mode with stop interrupt disabled.

2

In slave mode, the I
condition. The I

Once one repeated start is detected by the I

C interface can be configured to generate an interrupt due to a start, repeated start, data, or stop

2

C interrupt decode bits (I2CID0 and I2CID1) in I2CCON indicate the source of the interrupt.

2

C interface, all subsequent start conditions are detected as a repeated

start even if a stop bit has been received between data transfers.

For Assembly code: Do not use memory location 0x9A
For C code: Assign a dummy variable to location 0x9A using the following code:
idata unsigned int ui32Dummy[2] _at_ 0x9A;

2

During an I

C transfer, if a user executes either of the following instructions, the contents of the I2CDAT SFR can be

modified.

MOV dest,#9AH
SUBB A,R2

To prevent code from changing the contents of the I2CDAT SFR make sure that neither of these instructions are
executed during an I

A small percentage (<3%) of I

2

C transfer.

2

C stop conditions received by a slave cause the I2C bus to enter a state where the

subsequent START+matching address is not acknowledged.

Rev. A | Page 2 of 4