MicroConverter® Multichannel 12-Bit ADC with
Anomaly Sheet for Silicon Rev. E
This anomaly list represents the known bugs, anomalies, and workarounds for the ADuC841, ADuC842, and ADuC843 MicroConverter
products. The anomalies listed apply to all ADuC841/ADuC842/ADuC843 packaged material branded as follows:
First(CSP) /Second (PQFP) Line ADuC841 or ADuC842 or ADuC843
Third (CSP) / Fourth Line (PQFP) E20
Analog Devices, Inc. is committed, through future silicon revisions, to continuously improving silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems implementing the recommended
workarounds outlined here.
Embedded 62 kB Flash and Single-Cycle MCU
ADuC841/ADuC842/ADuC843
ADuC841/ADuC842/ADuC843 SILICON REVISION HISTORY
Silicon
Revision
Identifier
E 0 All silicon branded
E 0 All silicon branded
Kernel
Revision
Identifier
Chip Marking Silicon Status
Release Rev. 0 8
ADUC841BS or ADuC841BCP
ADuC842BS or ADuC842BCP
ADuC843BS or ADuC843BCP
Third/Fourth Line: E20
Release Rev. A 11
ADUC841BS or ADuC841BCP
ADuC842BS or ADuC842BCP
ADuC843BS or ADuC843BCP
Third/Fourth Line: E20
Anomaly Sheet
No. of Reported Anomalies
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
ADuC841/ADuC842/ADuC843
ANOMALIES
1. Mode 0 UART Operation [er001]
Background: UART Mode 0 allows the UART to function in an 8-bit shift register mode.
Issue: UART Mode 0 is nonfunctional on the ADuC841/ADuC842/ADuC843.
Workaround: None.
Related Issues: None.
2. Use of the Extended Stack Pointer [er002]
Background: The extended stack pointer allows the stack to overflow into internal XRAM.
Issue:
Work around:
Related Issues: None.
3. Use of I2C in Slave Mode with Stop Interrupt Enabled [er003]
Background:
Issue A:
Workaround A: When a stop interrupt is detected, the user should reset the I
Issue B:
Workaround B:
Related Issues: er004: Use of I
4. Use Of I2C in Slave Mode with Stop Interrupt Disabled [er004]
Background:
Issue:
Workaround: None.
Related Issues: None.
5. I2C Data Transfer [er005]
Background: The I2CDAT register is used to read or write data to the I2C bus. The I2CDAT register has an SFR address of 0x9A.
Issue A: During an I2C transfer if a user accesses the RAM address 0x9A the contents of the I2CDAT SFR can be modified.
Workaround A:
Issue B:
Workaround B:
Issue C:
Workaround C: If a second START+matching address is issued following a NACK, this is detected correctly.
Related Issues: None.
A PUSH onto the extended stack when it is the first instruction within a subroutine results in the return address being
overwritten.
For Assembly code, insert a NOP as the first instruction in any subroutine.
For C code, there is currently no workaround.
2
In slave mode, the I
condition. The I
C interface can be configured to generate an interrupt due to a start, repeated start, data, or stop
2
C interrupt decode bits (I2CID0 and I2CID1) in I2CCON indicate the source of the interrupt. If the stop
interrupt is enabled via the I2CSI bit, an interrupt is generated when the slave receives a stop condition.
2
C interrupt service routine, if the I2CI bit or I2CDAT register is accessed during a stop interrupt, the I2C bus will
In the I
fail to respond to further I
When the stop interrupt is enabled, on occasion the I
DATA interrupt occurred when the source was in fact a stop interrupt. If this happens the user may try to clear I2CI or
read I2CDAT, resulting in the bus failing to respond to further I
2
C communication.
2
2
C bus by using the I2CRS bit.
C interrupt decode bits indicate that a start, repeated start, or
2
C communication.
Tie the SCLOCK pin to an I/O pin; This allows the state of SCLOCK to be read. SCLOCK is high only during an interrupt if
the source is a stop interrupt.
2
C in slave mode with stop interrupt disabled.
2
In slave mode, the I
condition. The I
Once one repeated start is detected by the I
C interface can be configured to generate an interrupt due to a start, repeated start, data, or stop
2
C interrupt decode bits (I2CID0 and I2CID1) in I2CCON indicate the source of the interrupt.
2
C interface, all subsequent start conditions are detected as a repeated
start even if a stop bit has been received between data transfers.
For Assembly code: Do not use memory location 0x9A
For C code: Assign a dummy variable to location 0x9A using the following code:
idata unsigned int ui32Dummy[2] _at_ 0x9A;
2
During an I
C transfer, if a user executes either of the following instructions, the contents of the I2CDAT SFR can be
modified.
MOV dest,#9AH
SUBB A,R2
To prevent code from changing the contents of the I2CDAT SFR make sure that neither of these instructions are
executed during an I
A small percentage (<3%) of I
2
C transfer.
2
C stop conditions received by a slave cause the I2C bus to enter a state where the
subsequent START+matching address is not acknowledged.
Rev. A | Page 2 of 4
ADuC841/ADuC842/ADuC843
6. SPI Interface [er006]
Background:
Issue A:
Workaround A: None.
Issue B: When the ADuC841/ADuC842/ADuC843 is set up as an SPI slave, the device may receive or transmit bytes incorrectly.
Workaround B:
Related Issues: None.
7. Interrupts During Reading/Writing to Data FLASH/EE [er007]
Background: There are 4 kB of DATAFLASH/EE that can be used for nonvolatile data storage.
Issue:
Workaround: Disable all interrupts prior to a read or write operation. This can be done by setting the EA bit to 0.
Related Issues: None.
8. PWM Operation [er008]
Background: The PWM output rate is determined by the PWMxH and PWMxL registers for the PWM0 and PWM1 outputs.
Issue: Modifying RAM Address 0x2E causes the PWM timer to be reset.
Workaround: For Assembly code: Do not use memory location 0x2E.
Related Issues: None.
9. Watchdog Timer [er009]
Background:
Issue:
Work around:
Related Issues: None.
The SPI can either be used on the standard pins or can be moved to P3.3, P3.4, and P3.5 by setting the MSPI bit in
CFG841/CFG842. When the MSPI bit is set, P3.3 should be MISO, P3.4 MOSI, and P3.5 SCLOCK.
By setting the MSPI bit, the P3.3, P3.4, and P3.5 have the following configuration:
P3.3 = MISO, P3.4 = SCLOCK, P3.5 = MOSI
Incorporate checksums into all communication with the ADuC841/ADuC842/ADuC843 slave. This allows the master
devices to retransmit if an error occurs.
If an interrupt occurs during a DATAFLASH/EE read or write operation, code execution following the ISR may resume at
a random program memory address.
For C code: Assign a dummy variable to location 0x2E using the following code:
idata unsigned int ui32Dummy[2] _at_ 0x2E;
The ADuC841, ADuC842, and ADuC843 incorporate a Watchdog Timer. The purpose of the WDT is to ensure the part is
never stuck in an endless loop by generating either a hardware reset or an interrupt event that vectors to the WDT ISR.
If the WDT generates an interrupt as opposed to a hardware reset, and if the ISR subsequently sets up the WDT to time
out to a hardware reset, the reset is ignored.
Ensure that a double write to the WDCON is executed inside the ISR with the first write being a reset of the WDT. For
example:
void isr_wdt( void ) interrupt 11
{
WDWR = 1; // This first WDT write is required to get the WDT to work inside the ISR.
WDCON = 0x60;// Reset WDT.
WDWR = 1; // Now set the WDT to the required 1s timeout
WDCON = 0x62;// select reset after 1000mS
while(1);
}
void main(void)
{
EA = 0;
WDWR = 1; // Allow write to WDCON
WDCON = 0x6A; // timeout=1000mS, WDT enable, WDT ISR Interrupt
while (1);
}
Rev. A | Page 3 of 4
ADuC841/ADuC842/ADuC843
10. Level Triggered Interrupt Operation [er010]
Background:
Issue:
Work around:
Related Issues: None.
11. Stack Pointer in ULOAD Mode [er011]
Background: When starting user code, the stack pointer should, by default, be initialized to Address 0x07.
Issue: In ULOAD mode, the stack pointer defaults to 0x03 causing conflict between RAM locations R4 to R7 and the stack.
Work around:
Related Issues: None.
ADuC841/ADuC842/ADuC843 SILICON ANOMALIES
Anomaly No. Description Status
er001 Mode 0 UART Operation Pending
er002 Use of the Extended Stack Pointer Pending
er003 Use of I2C in Slave Mode with Stop Interrupt Enabled Pending
er004 Use Of I2C in Slave Mode with Stop Interrupt Disabled Pending
er005 I2C Data Transfer Pending
er006 SPI Interface Pending
er007 Interrupts During Reading/Writing to Data FLASH/EE Pending
er008 PWM Operation Pending
er009 Watchdog Timer Pending
er010 Level Triggered Interrupt Operation Pending
er011 Stack Pointer in ULOAD Mode Pending
Purchase of licensed I
Rights to use these components in an I
The ADuC841/ADuC842/ADuC843 incorporate two external interrupt sources (INT0 and INT1) that can be configured to
respond to either an edge event or a level event.
If an interrupt occurs on the INT0 or INT1 pins and is then removed within one core instruction cycle, the interrupt vector
address that is generated may be incorrect resulting in a vector to 0x0000. This effectively restarts code execution.
To ensure that this does not occur the level triggered interrupt source must be kept low for a minimum of 9 core clock
cycles.
Manually change, in code, the stack pointer address to 0x07 or to the address that is required upon entry to ULOAD
mode, that is,
MOV SP, #07H
or
SP = 0x07;
2
C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
2
C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
S03260–0–7/04(A)
Rev. A | Page 4 of 4
Loading...