Analog Devices ADUC834BS Datasheet

PRELIMINAR Y TECHNICAL D A T A

MicroConverter®, Dual 16-/24- Bit ADCs

a

with Embedded 62KB FLASH MCU

Preliminary Technical Data ADuC834

FEATURES
High Resolution Sigma-Delta ADCs

Two Independent ADCs (16- and 24-Bit Resolution)
24-Bit No Missing Codes, Primary ADC
13-Bit p-p Resolution @ 20 Hz, 20 mV Range
18-Bit p-p Resolution @ 20 Hz, 2.56 V Range

Memory

AIN1
AIN2

62Kbytes On-Chip Flash/EE Program Memory
4 KBytes On-Chip Flash/EE Data Memory
Flash/EE, 100 Yr Retention, 100 Kcycles Endurance
In Circuit Serial Download

AIN3
AIN4
AIN5

High Speed User Bootload (5s Download)
2304 Bytes On-Chip Data RAM

8051 Based Core

8051-Compatible Instruction Set (12.58 MHz Max)
32 kHz External Crystal, On-Chip Programmable PLL
11 Interrupt Sources, Two Priority Levels
Dual Data Pointer
Extended 11-bit Stack Pointer

On-Chip Peripherals

12-Bit Voltage Output DAC
Dual 16-Bit

Σ∆Σ∆

Σ∆ DACs/PWMs

Σ∆Σ∆

On-Chip Temperature Sensor
Dual Excitation Current Sources
Time Interval Counter (Real Time Clock/WakeUp Cct)
UART and SPI

®

Serial I/O
Timer 3 for high speed UART baud rates (incl 115,200)
Watchdog Timer (WDT), Power Supply Monitor (PSM)

Power

Specified for 3 V and 5 V Operation
Normal: 3 mA @ 3 V (Core CLK = 1.5 MHz)
Power-Down: 20µA max with wake-up cct running

GENERAL DESCRIPTION

The ADuC834 is a complete smart transducer front-end, inte­grating two high-resolution sigma delta ADCs, an 8-bit MCU,
and program/data Flash/EE Memory on a single chip.

The two independent ADCs (Primary and Auxiliary) include a
temperature sensor and a PGA (allowing direct measurement of
low-level signals). The ADCs with on-chip digital filtering and
programmable output data rates are intended for the measure­ment of wide dynamic range, low frequency signals, such as those
in weigh scale, strain-gauge, pressure transducer, or temperature
measurement applications.

The device operates from a 32 kHz crystal with an on-chip PLL
generating a high-frequency clock of 12.58 MHz. This clock is,
routed through a programmable clock divider from which the
MCU core clock operating frequency is generated. The micro­controller core is an 8052 and therefore 8051 instruction set
compatible with 12 core clock periods per machine cycle.

FUNCTIONAL BLOCK DIAGRAM

AVDD

12-BIT

DAC

16-BIT

Σ∆

DAC

16-BIT

Σ∆

DAC

16-BIT

PWM

16-BIT

PWM

PERIPHERALS

2304 BYTES USER R A M

POWER SUPPLY MON

WATCHDOG TIMER

UART AND SP I

SERIAL I/O

CURRE NT

SOURCE

BUF

MUX

IEX C 1
IEX C 2

DAC

PWM0

PWM1

AVDD

MUX

MUX

TEMP

SENSOR

INTERNAL
BANDGAP

VREF

EXTERNAL

VREF

DETEC T

REFIN+REFIN›

ADuC834

BUF

AGND

PROG.
CLOCK

DIVIDER

OSC

PLL

PGA

AUXILIARY

16-BIT Σ∆ ADC

&

XTAL2XTAL1

PRIMARY

Σ∆

ADC

24-BIT

8051-BASED MCU WITH ADDITIONAL

62 KBYTES FLASH/EE PROGRAM MEMORY

4 KBYTES FLASH/EE DATA MEMORY

3 × 16 BIT TIMERS

×

REAL TIME CLOCK

1

4 × PARALLE L

PORTS

62 Kbytes of nonvolatile Flash/EE program memory are provided
on-chip. 4 Kbytes of nonvolatile Flash/EE data memory, 256 bytes
RAM and 2 KBytes of extended RAM are also integrated on-chip.
The program memory can be configured as data memory in
datalogging applications.

The ADuC834 also incorporates additional analog functionality
with a 12-bit DAC, dual current sources, power supply monitor,
and a bandgap reference. On-chip digital peripherals include two
16-bit Σ∆ DACs/PWM, watchdog timer, real time clock (time
interval counter), four timers/counters, and two serial I/O ports
(UART and SPI).

On-chip factory firmware supports in-circuit serial download (via
UART), as well as single-pin emulation mode via the EA pin. A
functional block diagram of the ADuC834 is shown above with a
more detailed block diagram shown in figure 11 (page 18).

The part operates from a 3V or a 5V supply. When operating from
3V the power dissipation for the part is below 10mW. The
ADuC834 is housed in a 52-lead MQFP package.

APPLICATIONS
Intelligent Sensors (IEEE1451.2-Compatible)
Weigh Scales
Portable Instrumentation
Pressure Transducers
4–20 mA Transmitters

REV. PrC (12 March 2002)

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

MicroConverter is a registered trademark of Analog Devices, Inc.
SPI is a registered trademark of Motorola Inc.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADuC834

PRELIMINAR Y TECHNICAL D A T A

TABLE OF CONTENTS

OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 8

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 18

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . 21

SPECIAL FUNCTION REGISTERS (SFRS) . . . . . . . . . . 22

Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . 23

Power Control (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . 23

ADuC834 Configuration SFR (CFG834) . . . . . . . . . . . . 23

Complete SFR Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PRIMARY AND AUXILIARY ADCs . . . . . . . . . . . . . . . . 25

ADCSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ADCMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

ADC0CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ADC1CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ADC0H/M/L / ADC1H/L . . . . . . . . . . . . . . . . . . . . . . . . 28

OF0H/M/L / OF1H/L . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

GN0H/M/L / GN1H/L . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

ICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PRIMARY AND AUX ADC NOISE PERFORMANCE . . 30
PRIMARY AND AUXILIARY ADC DESCRIPTION . . . 31

Primary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Primary and Auxiliary ADC Inputs . . . . . . . . . . . . . . . . . 33

Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 33

Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

NONVOLATILE FLASH/EE MEMORY . . . . . . . . . . . . . 37

Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . 37

Flash/EE Memory and the ADuC834 . . . . . . . . . . . . . . . 37

ADuC834 Flash/EE Memory Reliability . . . . . . . . . . . . . 37

USING THE FLASH/EE PROGRAM MEMORY . . . . . . 38

Serial/Parallel Downloading . . . . . . . . . . . . . . . . . . . . . . . 38

User Download Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Flash/EE Program Memory Security . . . . . . . . . . . . . . . . 38

USING THE FLASH/EE DATA MEMORY . . . . . . . . . . . 39

ECON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Programming the Flash/EE Data Memory . . . . . . . . . . . 40

FLASH/EE MEMORY TIMING . . . . . . . . . . . . . . . . . . . . 40

DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DACCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Using the DAC Converter . . . . . . . . . . . . . . . . . . . . . . . . 41

PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

PWMCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

ON-CHIP PLL (PLLCON) . . . . . . . . . . . . . . . . . . . . . . . . 46

TIME INTERVAL COUNTER (TIMECON) . . . . . . . . . . 47

WATCHDOG TIMER (WDCON) . . . . . . . . . . . . . . . . . . 49

POWER SUPPLY MONITOR (PSMCON) . . . . . . . . . . . 50

SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . 51

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

SPICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Using the SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 52

DUAL DATA POINTER (DPCON) . . . . . . . . . . . . . . . . . 53

8051-COMPATIBLE PERIPHERALS . . . . . . . . . . . . . . . . 54

Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Additional High Current Digital Output Pins . . . . . . . . . 54

TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . 55

TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timer/Counter 0/1 Modes of Operation . . . . . . . . . . . 57

Timer 2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . 58

T2CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 61

Baud Rate Generation using Timer 1 and Timer 2 . . . 62

Baud Rate Generation using Timer 3 . . . . . . . . . . . . . 63

INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

HARDWARE DESIGN CONSIDERATIONS . . . . . . . . . . 66

External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . 66

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . 67

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Grounding and Board Layout Recommendations . . . . . . 68

System Self-Identification . . . . . . . . . . . . . . . . . . . . . . . . 68

Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

OTHER HARDWARE CONSIDERATIONS . . . . . . . . . . 69

In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . 69

Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . 69

Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . 69

Enhanced-Hooks Emulation Mode . . . . . . . . . . . . . . . . . 69

Typical System Configuration . . . . . . . . . . . . . . . . . . . . . 69

QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . . 71

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 72

–2–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V,

1

SPECIFICATIONS

Parameter ADuC834BS Test Conditions/Comments Unit

ADC SPECIFICATIONS

Conversion Rate 5.4 On Both Channels Hz min
Primary ADC

No Missing Codes
Resolution 13 Range = ±20 mV, 20 Hz Update Rate Bits p-p typ

Output Noise See Table X and XI Output Noise Varies with Selected

Integral Nonlinearity ±15 1 LSB
Offset Error
Offset Error Drift ±10 nV/°C typ
Full-Scale Error
Gain Error Drift
ADC Range Matching ±2 AIN = 18 mV µV typ
Power Supply Rejection (PSR) 113 AIN = 7.8 mV, Range = ±20 mV dBs typ

Common-Mode DC Rejection

On AIN 95 At DC, AIN = 7.8 mV, Range = ±20 mV dBs min
On AIN 113 At DC, AIN = 1 V, Range = ±2.56 V dBs typ
On REFIN 125 At DC, AIN = 1 V, Range = ±2.56 V dBs typ

Common-Mode 50 Hz/60 Hz Rejection

On AIN 95 50 Hz/60 Hz ±1 Hz, AIN = 7.8 mV, dBs min

On REFIN 90 50 Hz/60 Hz ±1 Hz, AIN = 1 V, dBs min

Normal Mode 50 Hz/60 Hz Rejection

On AIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs min
On REFIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs min

Auxiliary ADC

No Missing Codes
Resolution 16 Range = ±2.5 V, 20 Hz Update Rate Bits p-p typ
Output Noise See Table XII in Output Noise Varies with Selected

Integral Nonlinearity ±1 5 ppm of FSR max
Offset Error
Offset Error Drift 1 µV/°C typ
Full-Scale Error
Gain Error Drift

Power Supply Rejection (PSR) 80 AIN = 1 V, 20 Hz Update Rate dBs min

Normal Mode 50 Hz/60 Hz Rejection

On AIN 60 50 Hz/60 Hz ±1 Hz dBs min
On REFIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs min

DAC PERFORMANCE

DC Specifications

Resolution 12 Bits
Relative Accuracy ±3 LSB typ
Differential Nonlinearity –1 Guaranteed 12-Bit Monotonic LSB max
Offset Error ±50 mV max
Gain Error

8

AC Specifications

Voltage Output Settling Time 15 Settling Time to 1 LSB of Final Value µs typ
Digital-to-Analog Glitch Energy 10 1 LSB Change at Major Carry nVs typ

2

3

4

5

2

3

6

5

7

2, 7

REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz
Crystal; all specifications T

MIN

to T

unless otherwise noted.)

MAX

105 Programmable in 0.732 ms Increments Hz max
24 20 Hz Update Rate Bits min
18 Range = ±2.56 V, 20 Hz Update Rate Bits p-p typ
in ADuC834 ADC Update Rate and Gain Range

Description (pg 30)
±3 µV typ

16

±10 µV typ
±0.5 ppm/°C typ

80 AIN = 1 V, Range = ±2.56 V dBs min

2

20 Hz Update Rate
Range = ±20 mV

90 50 Hz/60 Hz ±1 Hz, AIN = 1 V , dBs min

Range = ±2.56 V

2

Range = ±2.56 V

16 Bits min

ADuC834 ADC Update Rate
Description (pg 30)

–2 LSB typ
–2.5 LSB typ

±0.5 ppm/°C typ

2

±1 AVDD Range % max
±1 V

Range % typ

REF

ADuC834

ppm of FSR max

REV. PrC (12 March 2002)

–3–

PRELIMINAR Y TECHNICAL D A TA

ADuC834–SPECIFICATIONS

1

Parameter ADuC834BS Test Conditions/Comments Unit

INTERNAL REFERENCE

ADC Reference

Reference Voltage 1.25 ± 1% Initial Tolerance @ 25°C, V
Power Supply Rejection 45 dBs typ
Reference Tempco 100 ppm/°C typ

DAC Reference

Reference Voltage 2.5 ± 1% Initial Tolerance @ 25°C, V
Power Supply Rejection 50 dBs typ
Reference Tempco ±100 ppm/°C typ

ANALOG INPUTS/REFERENCE INPUTS

Primary ADC

Differential Input Voltage Ranges

9, 10

External Reference Voltage = 2.5 V
RN2, RN1, RN0 of ADC0CON Set to

Bipolar Mode (ADC0CON3 = 0) ±20 0 0 0 (Unipolar Mode 0 to 20 mV) m V

±40 0 0 1 (Unipolar Mode 0 to 40 mV) m V
±80 0 1 0 (Unipolar Mode 0 to 80 mV) m V
±160 0 1 1 (Unipolar Mode 0 to 160 mV) m V
±320 1 0 0 (Unipolar Mode 0 to 320 mV) m V
±640 1 0 1 (Unipolar Mode 0 to 640 mV) m V
±1.28 1 1 0 (Unipolar Mode 0 to 1.28 V) V
±2.56 1 1 1 (Unipolar Mode 0 to 2.56 V) V
±1 nA max

Analog Input Current

2

Analog Input Current Drift ±5 pA/°C typ
Absolute AIN Voltage Limits AGND + 100 mV V min

– 100 mV V max

AV

Auxiliary ADC

Input Voltage Range

9, 10

DD

0 to V

REF

Unipolar Mode, for Bipolar Mode V

See Note 11
Average Analog Input Current 125 Input Current Will Vary with Input nA/V typ
Average Analog Input Current Drift
Absolute AIN Voltage Limits

External Reference Inputs

REFIN(+) to REFIN(–) Range

2

11

2

±2 Voltage on the Unbuffered Auxiliary ADC pA/V/°C typ
AGND – 30 mV V min
AV

+ 30 mV V max

DD

1V min
AV

DD

Average Reference Input Current 1 Both ADCs Enabled µA/V typ
Average Reference Input Current Drift ±0.1 nA/V/°C typ
‘NO Ext. REF’ Trigger Voltage 0. 3 NOXREF Bit Active if V

0.65 NOXREF Bit Inactive if V

ADC SYSTEM CALIBRATION

Full-Scale Calibration Limit +1.05 × FS V max
Zero-Scale Calibration Limit –1.05 × FS V min
Input Span 0.8 × FS V min

2.1 × FS V max

ANALOG (DAC) OUTPUTS

Voltage Range 0 to V

0 to AV

REF

DD

DACRN = 0 in DACCON SFR V typ

DACRN = 1 in DACCON SFR V typ

Resistive Load 10 From DAC Output to AGND Ω typ
Capacitive Load 100 From DAC Output to AGND pF typ
Output Impedance 0.5 Ω typ
I

SINK

50 µA typ

TEMPERATURE SENSOR

Accuracy ±2 °C typ
Thermal Impedance (θJA) 90 °C/Ω typ

= 5 V V min/max

DD

= 5 V V min/max

DD

< 0.3 V V min

REF

> 0.65 V V max

REF

V max

–4–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

Parameter ADuC834BS Test Conditions/Comments Unit

TRANSDUCER BURNOUT CURRENT SOURCES

AIN+ Current –100 AIN+ is the Selected Positive Input to nA typ

the Primary ADC

AIN– Current +100 AIN– is the Selected Negative Input to nA typ

the Auxiliary ADC
Initial Tolerance @ 25°C ±10 % typ
Drift 0.03 %/°C typ

EXCITATION CURRENT SOURCES

Output Current –200 Available from Each Current Source µA typ

Initial Tolerance @ 25°C ±10 % typ
Drift 200 ppm/°C typ
Initial Current Matching @ 25°C ± 1 Matching Between Both Current Sources % typ
Drift Matching 20 ppm/°C typ
Line Regulation (AV

)1 AV

DD

Load Regulation 0.1 µA/V typ
Output Compliance AV

– 0.6 V max

DD

AGND Min

LOGIC INPUTS

All Inputs Except SCLOCK, RESET,

and XTAL1

, Input Low Voltage 0.8 DVDD = 5 V V max

V

INL

0.4 DV

, Input High Voltage 2.0 V min

V

INH

SCLOCK and RESET Only

(Schmitt-Triggered Inputs)

V

T+

2

1.3/3 DVDD = 5 V V min/V max

0.95/2.5 DV

V

T–

0.8/1.4 DVDD = 5 V V min/V max

0.4/1.1 DV

V

T+

– V

T–

0.3/0.85 DVDD = 5 V V min/V max

0.3/0.85 DV

Input Currents

Port 0, P1.2–P1.7, EA ±10 V

SCLOCK, MOSI, MISO, SS

12

–10 min, –40 max VIN = 0 V, DVDD = 5 V, Internal Pull-Up µA min/µA ma x
±10 V

RESET ±10 V

35 min, 105 max V

P1.0, P1.1, Ports 2 and 3 ±1 0 V

–180 V
–660 µA max
–20 V
–75 µA max

Input Capacitance 5 All Digital Inputs pF typ

CRYSTAL OSCILLATOR (XTAL1 AND XTAL2)

Logic Inputs, XTAL1 Only

V

, Input Low Voltage 0.8 DVDD = 5 V V max

INL

0.4 DV

V

, Input High Voltage 3.5 DVDD = 5 V V min

INH

2.5 DV
XTAL1 Input Capacitance 18 pF typ
XTAL2 Output Capacitance 18 pF typ

= 5 V + 5% µA/V typ

DD

= 3 V V max

DD

= 3 V V min/V max

DD

= 3 V V min/V max

DD

= 3 V V min/V max

DD

= 0 V or V

IN

= VDD, DVDD = 5 V µA max

IN

= 0 V, DVDD = 5 V µA max

IN

= VDD, DVDD = 5 V, µA min/µA max

IN

DD

µA max

Internal Pull-Down

= VDD, DVDD = 5 V µA max

IN

= 2 V, DVDD = 5 V µA min

IN

= 450 mV, DVDD = 5 V µA min

IN

= 3 V V max

DD

= 3 V V min

DD

REV. PrC (12 March 2002)

–5–

PRELIMINAR Y TECHNICAL D A TA

ADuC834–SPECIFICATIONS

1

Parameter ADuC834BS Test Conditions/Comments Unit

LOGIC OUTPUTS (Not Including XTAL2)

VOH, Output High Voltage 2.4 VDD = 5 V, I
V

, Output Low Voltage

OL

13

Floating State Leakage Current ± 10 µA max
Floating State Output Capacitance 5 pF typ

POWER SUPPLY MONITOR (PSM)

AVDD Trip Point Selection Range 2.63 Four Trip Points Selectable in This Range V mi n

Power Supply Trip Point Accuracy ±3.5 % max

AV

DD

DV

Trip Point Selection Range 2.63 Four Trip Points Selectable in This Range V m in

DD

DVDD Power Supply Trip Point Accuracy ±3.5 % max

WATCHDOG TIMER (WDT)

Timeout Period 0 Nine Timeout Periods in This Range ms min

MCU CORE CLOCK RATE Clock Rate Generated via On-Chip PLL

MCU Clock Rate

2

START-UP TIME

At Power-On 300 ms typ
From Idle Mode 1 ms typ
From Power-Down Mode

Oscillator Running OSC_PD Bit = 0 in PLLCON SFR

Wakeup with INT0 Interrupt 1 ms typ
Wakeup with SPI Interrupt 1 ms typ
Wakeup with TIC Interrupt 1 ms typ
Wakeup with External RESET 3.4 ms typ

Oscillator Powered Down OSC_PD Bit = 1 in PLLCON SFR

Wakeup with External RESET 0.9 sec typ

After External RESET in Normal Mode 3.3 ms typ
After WDT Reset in Normal Mode 3.3 Controlled via WDCON SFR ms typ

FLASH/EE MEMORY RELIABILITY CHARACTERISTICS

Endurance
Data Retention

15

16

POWER REQUIREMENTS DV

Power Supply Voltages

, 3 V Nominal Operation 2.7 V min

AV

DD

AV

, 5 V Nominal Operation 4.75 V min

DD

, 3 V Nominal Operation 2.7 V min

DV

DD

, 5 V Nominal Operation 4.75 V min

DV

DD

2

= 80 µA V min

2.4 V

0.4 I

= 3 V, I

DD

= 8 mA, SCLOCK/D0, V max

SINK

SOURCE

= 20 µA V min

SOURCE

MOSI/D1

0.4 I

0.4 I

= 10 mA, P1.0 and P1.1 V max

SINK

= 1.6 mA, All Other Outputs V max

SINK

4.63 Programmed via TPA1–0 in PSMCON V max

4.63 Programmed via TPD1–0 in PSMCON V max

2000 Programmed via PRE3–0 in WDCON ms max

98.3 Programmable via CD2–0 Bits in kHz min
PLLCON SFR

12.58 MHz max

14

100,000 Cycles min
100 Years min

and AVDD Can Be Set

DD

Independently

3.6 V max

5.25 V max

3.6 V max

5.25 V max

–6–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

Parameter ADuC834BS Test Conditions/Comments Unit

POWER REQUIREMENTS (continued)

Power Supply Currents Normal Mode

DVDD Current 4 DVDD = 4.75 V to 5.25 V, Core CLK = 1.57 MHz mA max

Current 170 AVDD = 5.25 V, Core CLK = 1.57 MHz µA max

AV

DD

DV

Current 15 DVDD = 4.75 V to 5.25 V, Core CLK = 12.58 MH z mA max

DD

Current 170 AVDD = 5.25 V, Core CLK = 12.58 MHz µA max

AV

DD

Power Supply Currents Idle Mode

DVDD Current 1.2 DVDD = 4.75 V to 5.25 V, Core CLK = 1.57 MHz mA max
AV

Current 140 Measured @ AVDD = 5.25 V, Core CLK = 1.57 MHz µA typ

DD

DV

Current 2 DVDD = 4.75 V to 5.25 V, Core CLK = 12.58 MH z mA typ

DD

AV

Current 140 Measured at AVDD = 5.25 V, Core CLK = 12.58 MHz µA typ

DD

Power Supply Currents Power-Down Mode

Current 50 DVDD = 4.75 V to 5.25 V, Osc. On, TIC On µA max

DV

DD

AV

Current 1 Measured at AVDD = 5.25 V, Osc. On or Osc. Off µA max

DD

Current 20 DVDD = 4.75 V to 5.25 V, Osc. Off µA max

DV

DD

Typical Additional Power Supply Currents Core CLK = 1.57 MHz, AV

and DIDD)

(AI

DD

PSM Peripheral 50 µA typ
Primary ADC 1 mA typ
Auxiliary ADC 500 µA typ
DAC 150 µA typ
Dual Current Sources 400 µA typ

NOTES

1

Temperature Range –40°C to +85°C.

2

These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.

3

System Zero-Scale Calibration can remove this error.

4

The primary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of 10 µV. If user power supply or temperature conditions
are significantly different than these, an Internal Full-Scale Calibration will restore this error to 10 µV. A system zero-scale and full-scale calibration will remove
this error altogether.

5

Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.

6

The auxiliary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration
will remove this error altogether.

7

DAC linearity and AC Specifications are calculated using:

reduced code range of 48 to 4095, 0 to V
reduced code range of 48 to 3995, 0 to VDD.

8

Gain Error is a measure of the span error of the DAC.

9

In general terms, the bipolar input voltage range to the primary ADC is given by Range

V

= REFIN(+) to REFIN(–) voltage and V

REF

RN = decimal equivalent of RN2, RN1, RN0,
e.g., V
In unipolar mode the effective range is 0 V to 1.28 V in our example.

10

1.25 V is used as the reference voltage to the ADC when internal V

11

In bipolar mode, the Auxiliary ADC can only be driven to a minimum of A
bipolar range is still –V

12

Pins configured in SPI mode, pins configured as digital inputs during this test.

13

Pins configured in High Current Output mode only.

14

Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.

15

Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C and +85°C, typical endurance at 25°C is 700
Kcycles.

16

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of

0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet.

17

Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:

Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.

18

DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.

Specifications subject to change without notice

= 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the Range

REF

to +V

REF

Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in

PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in
PLLCON SFR.

; however, the negative voltage is limited to –30 mV.

REF

17, 18

2.1 DV

8DV

17, 18

750 DV

1DV

17, 18

20 DV

5DV

,

REF

= 1.25 V when internal ADC V

REF

= ±1.28 V.

ADC

REF

= 2.7 V to 3.6 V, Core CLK = 1.57 MH z mA max

DD

= 2.7 V to 3.6 V, Core CLK = 12.58 MH z mA max

DD

= 2.7 V to 3.6 V, Core CLK = 1.57 MH z µA typ

DD

= 2.7 V to 3.6 V, Core CLK = 12.58 MH z mA typ

DD

Core CLK = 1.57 MHz or 12.58 MHz

= 2.7 V to 3.6 V, Osc. On, TIC On µA max

DD

= 2.7 V to 3.6 V, Osc. Off µA typ

DD

= ±(V

ADC

is selected.

REF

is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON respectively.

– 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The

GND

2RN)/125, where:

REF

= DVDD = 5 V

DD

REV. PrC (12 March 2002)

–7–

ADuC834

PRELIMINAR Y TECHNICAL D A T A

(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all
specifications T

MIN

to T

unless otherwise noted.)

MAX

TIMING SPECIFICATIONS

1, 2, 3

32.768 kHz External Crystal

Parameter Min Typ Max Unit Figure

CLOCK INPUT (External Clock Driven XTAL1)

t

CK

t

CKL

t

CKH

t

CKR

t

CKF

1/t

CORE

t

CORE

t

CYC

NOTES

1

AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at VIH min for a Logic 1, and VIL max
for a Logic 0 as shown in Figure 2.

2

For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded VOH/VOL level occurs as shown in Figure 2.

3

C

for Port0, ALE, PSEN outputs = 100 pF; C

LOAD

4

ADuC834 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a Stable 12.583 MHz internal clock for the
system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.

5

This number is measured at the default Core_Clk operating frequency of 1.57 MHz.

6

ADuC834 Machine Cycle Time is nominally defined as 12/Core_CLK.

XTAL1 Period 30.52 µs 1
XTAL1 Width Low 15.16 µs 1
XTAL1 Width High 15.16 µs 1
XTAL1 Rise Time 20 ns 1
XTAL1 Fall Time 20 ns 1
ADuC834 Core Clock Frequency
ADuC834 Core Clock Period
ADuC834 Machine Cycle Time

LOAD

4

5

6

0.098 12.58 MHz

0.636 µs

0.95 7.6 122.45 µs

for all other outputs = 80 pF unless otherwise noted.

t

CHK

t

CKR

DVDD › 0.5 V

0.45V

t

CKL

t

CK

Figure 1. XTAL1 Input

+ 0.9V

0.2DV

DD

TEST POINTS

0.2DVDD › 0.1V

V

LOAD

V

LOAD

LOAD

+ 0.1V

› 0.1V

V

Figure 2. Timing Waveform Characteristics

t

TIMING

REFEREN CE

POINTS

CKF

V

V

LOAD

LOAD

› 0.1V

+ 0.1V

V

LOAD

–8–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

12.58 MHz Core_Clk Variable Core_Clk

Parameter Min Max Min Max Unit Figure

EXTERNAL PROGRAM MEMORY

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

AVIV

t

PLAZ

t

PHAX

ALE Pulsewidth 119 2t
Address Valid to ALE Low 39 t
Address Hold after ALE Low 49 t
ALE Low to Valid Instruction In 218 4t
ALE Low to PSEN Low 49 t

PSEN Pulsewidth 193 3t
PSEN Low to Valid Instruction In 133 3t

– 40 ns 3

CORE

– 40 ns 3

CORE

– 30 ns 3

CORE

– 30 ns 3

CORE

– 45 ns 3

CORE

– 100 ns 3

CORE

– 105 ns 3

CORE

Input Instruction Hold after PSEN 00 ns3
Input Instruction Float after PSEN 54 t
Address to Valid Instruction In 292 5t

– 25 ns 3

CORE

– 105 ns 3

CORE

PSEN Low to Address Float 25 25 ns 3
Address Hold after PSEN High 0 0 ns 3

CORE_C LK

ALE (O)

PSEN

(O)

PORT 0 (I/O)

PORT 2 (O)

t

LHLL

PLAZ

PCH

t

PLPH

t

LLIV

t

PLIV

t

PXIX

INSTRUCTION

(IN)

t

AVLL

PCL

(OUT )

t

LLPL

t

LLAX

t

t

AVIV

Figure 3. External Program Memory Read Cycle

t

PXIZ

t

PHAX

REV. PrC (12 March 2002)

–9–

PRELIMINAR Y TECHNICAL D A T A

ADuC834

12.58 MHz Core_Clk Variable Core_Clk

Parameter Min Max Min Max Unit Figure

EXTERNAL DATA MEMORY READ CYCLE

t

RLRH

t

AVLL

t

LLAX

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

RLAZ

t

WHLH

RD Pulsewidth 377 6t
Address Valid after ALE Low 39 t
Address Hold after ALE Low 44 t
RD Low to Valid Data In 232 5t

– 100 ns 4

CORE

– 40 ns 4

CORE

– 35 ns 4

CORE

– 165 ns 4

CORE

Data and Address Hold after RD 00 ns4
Data Float after RD 89 2t
ALE Low to Valid Data In 486 8t
Address to Valid Data In 550 9t
ALE Low to RD Low 188 288 3t
Address Valid to RD Low 188 4t

– 50 3t

CORE

– 130 ns 4

CORE

– 70 ns 4

CORE

– 150 ns 4

CORE

– 165 ns 4

CORE

+ 50 ns 4

CORE

RD Low to Address Float 0 0 ns 4
RD High to ALE High 39 119 t

CORE_CLK

– 40 t

CORE

+ 40 ns 4

CORE

ALE (O)

PSEN

(O)

RD

(O)

POR T 0 (I/O)

PORT 2 (O)

t

LLDV

t

AVLL

A0 › A7

(OUT )

t

A16

AVDV

› A23

t

LLAX

t

AVWL

t

LLWL

t

RLAZ

t

RLDV

A8

› A15

t

RLRH

t

RHDX

DATA (IN)

Figure 4. External Data Memory Read Cycle

t

WHLH

t

RHDZ

–10–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

12.58 MHz Core_Clk Variable Core_Clk

Parameter Min Max Min Max Unit Figure

EXTERNAL DATA MEMORY WRITE CYCLE

t

WLWH

t

AVLL

t

LLAX

t

LLWL

t

AVWL

t

QVWX

t

QVWH

t

WHQX

t

WHLH

WR Pulsewidth 377 6t
Address Valid after ALE Low 39 t
Address Hold after ALE Low 44 t
ALE Low to WR Low 188 288 3t
Address Valid to WR Low 188 4t
Data Valid to WR Transition 29 t
Data Setup before WR 406 7t
Data and Address Hold after WR 29 t
WR High to ALE High 39 119 t

CORE_CLK

– 100 ns 5

CORE

– 40 ns 5

CORE

– 35 ns 5

CORE

– 50 3t

CORE

– 130 ns 5

CORE

– 50 ns 5

CORE

– 150 ns 5

CORE

– 50 ns 5

CORE

– 40 t

CORE

+ 50 ns 5

CORE

+ 40 ns 5

CORE

ALE (O)

PSEN

(O)

WR

(O)

PORT 0 (O)

PORT 2 (O)

t

QVWX

t

QVWH

DATA

t

WLWH

t

LLWL

t

AVWL

t

t

AVLL

LLAX

A0 › A7

A16 › A23 A8 › A15

Figure 5. External Data Memory Write Cycle

t

WHLH

t

WHQX

REV. PrC (12 March 2002)

–11–

PRELIMINAR Y TECHNICAL D A T A

ADuC834

12.58 MHz Core_Clk Variable Core_Clk

Parameter Min Typ Max Min Typ Max Unit Figure

UART TIMING (Shift Register Mode)

t

XLXL

t

QVXH

t

DVXH

t

XHDX

t

XHQX

Serial Port Clock Cycle Time 0.95 12t
Output Data Setup to Clock 662 10t
Input Data Setup to Clock 292 2t

– 133 ns 6

CORE

+ 133 ns 6

CORE

CORE

µs 6

Input Data Hold after Clock 0 0 ns 6
Output Data Hold after Clock 42 2t

ALE (O)

– 117 ns 6

CORE

t

XLXL

(OUTPUT CLOCK)

(OUTP U T D A TA )

TXD

RXD

RXD

(INPUT DATA)

01

MSB

67

t

QVXH

BIT 6MSB

t

DVXH

BIT 6 BIT 1 LSB

t

XHQX

t

XHDX

BIT 1

Figure 6. UART Timing in Shift Register Mode

SET RI

OR

SET TI

–12–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

Parameter Min Typ Max Unit Figure

SPI MASTER MODE TIMING (CPHA = 1)

t

SL

t

SH

t

DAV

t

DSU

t

DHD

t

DF

t

DR

t

SR

t

SF

NOTE
*Characterized under the following conditions:

a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.

SCLOCK Low Pulsewidth* 630 ns 7
SCLOCK High Pulsewidth* 630 ns 7
Data Output Valid after SCLOCK Edge 50 ns 7
Data Input Setup Time before SCLOCK Edge 100 n s 7
Data Input Hold Time after SCLOCK Edge 100 ns 7
Data Output Fall Time 10 25 ns 7
Data Output Rise Time 10 25 ns 7
SCLOCK Rise Time 10 25 ns 7
SCLOCK Fall Time 10 25 ns 7

SCLOCK

(CPOL = 0)

SCLOCK

(CPOL = 1)

t

SH

t

SL

t

SR

t

SF

MOSI

MISO

t

DAV

t

DSU

MSB IN

t

DHD

t

DF

t

DR

BITS 6 › 1

BITS 6 › 1

Figure 7. SPI Master Mode Timing (CPHA = 1)

LSBMSB

LSB IN

REV. PrC (12 March 2002)

–13–

PRELIMINAR Y TECHNICAL D A T A

ADuC834

Parameter Min Typ Max Unit Figure

SPI MASTER MODE TIMING (CPHA = 0)

t

SL

t

SH

t

DAV

t

DOSU

t

DSU

t

DHD

t

DF

t

DR

t

SR

t

SF

NOTE
*Characterized under the following conditions:

a. Core clock divider bits CD2, CD1 and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.

SCLOCK Low Pulsewidth* 630 ns 8
SCLOCK High Pulsewidth* 630 ns 8
Data Output Valid after SCLOCK Edge 50 ns 8
Data Output Setup before SCLOCK Edge 150 ns 8
Data Input Setup Time before SCLOCK Edge 100 n s 8
Data Input Hold Time after SCLOCK Edge 100 ns 8
Data Output Fall Time 10 25 ns 8
Data Output Rise Time 10 25 ns 8
SCLOCK Rise Time 10 25 ns 8
SCLOCK Fall Time 10 25 ns 8

SCLOCK

(CPOL = 0)

SCLOCK

(CPOL = 1)

t

SH

t

SL

t

SR

t

SF

MOSI

MISO

t

DAV

t

DOSU

t

DSU

MSB IN

t

DF

MSB LSB

t

DHD

t

DR

BITS 6 › 1

Figure 8. SPI Master Mode Timing (CPHA = 0)

LSB INBITS 6 › 1

–14–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

Parameter Min Typ Max Unit Figure

SPI SLAVE MODE TIMING (CPHA = 1)

t

SS

t

SL

t

SH

t

DAV

t

DSU

t

DHD

t

DF

t

DR

t

SR

t

SF

t

SFS

SS to SCLOCK Edge 0 ns 9
SCLOCK Low Pulsewidth 330 ns 9
SCLOCK High Pulsewidth 330 ns 9
Data Output Valid after SCLOCK Edge 50 ns 9
Data Input Setup Time before SCLOCK Edge 100 n s 9
Data Input Hold Time after SCLOCK Edge 100 ns 9
Data Output Fall Time 10 25 ns 9
Data Output Rise Time 10 25 ns 9
SCLOCK Rise Time 10 25 ns 9
SCLOCK Fall Time 10 25 ns 9
SS High after SCLOCK Edge 0 ns 9

SS

SCLOCK

(CPOL = 0)

SCLOCK

(CPOL = 1)

MISO

MOSI

t

SS

t

DF

MSB IN

MSB

t

DHD

t

SL

t

DF

t

DR

BITS 6

t

SH

t

DAV

t

DSU

Figure 9. SPI Slave Mode Timing (CPHA = 1)

t

SFS

t

SR

›

1

BITS 6

›

1LSB IN

LSB

t

SF

REV. PrC (12 March 2002)

–15–

PRELIMINAR Y TECHNICAL D A T A

ADuC834

Parameter Min Typ Max Unit Figure

SPI SLAVE MODE TIMING (CPHA = 0)

t

SS

t

SL

t

SH

t

DAV

t

DSU

t

DHD

t

DF

t

DR

t

SR

t

SF

t

SSR

t

DOSS

t

SFS

SS to SCLOCK Edge 0 ns 10
SCLOCK Low Pulsewidth 330 ns 10
SCLOCK High Pulsewidth 330 ns 10
Data Output Valid after SCLOCK Edge 50 ns 10
Data Input Setup Time before SCLOCK Edge 100 n s 10
Data Input Hold Time after SCLOCK Edge 100 ns 10
Data Output Fall Time 10 25 ns 10
Data Output Rise Time 10 25 ns 10
SCLOCK Rise Time 10 25 ns 10
SCLOCK Fall Time 10 25 ns 10
SS to SCLOCK Edge 50 ns 10
Data Output Valid after SS Edge 20 ns 10
SS High after SCLOCK Edge 0 ns 10

SS

SCLOCK

(CPOL = 0)

SCLOCK

(CPOL = 1)

MISO

MOSI

t

DOSS

t

SS

t

DSU

MSB IN

MSB

t

DHD

t

SH

t

t

SL

t

DAV

DF

t

DR

BITS 6 › 1

BITS 6 › 1

Figure 10. SPI Slave Mode Timing (CPHA = 0)

t

SR

LSB IN

LSB

t

SFS

t

SF

–16–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

1

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

DD

AGND to DGND
AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V

DD

Analog Input Voltage to AGND
Reference Input Voltage to AGND . . –0.3 V to AV

2

. . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

3

. . . –0.3 V to AVDD +0.3 V

+0.3 V

DD

AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . . . . 30 mA

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV

+0.3 V

DD

+0.3 V

DD

Operating Temperature Range . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 53.2°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

AGND and DGND are shorted internally on the ADuC834.

3

Applies to P1.2 to P1.7 pins operating in analog or digital input modes.

PIN CONFIGURATION

52-Lead MQFP

ORDERING GUIDE

Model Temperature Package Package

Range Description Option

ADuC834BS –40°C to +85°C 52-Lead Plastic Quad Flatpack S-52

QuickStart Development System Description
Model

EVAL-ADUC834QS Development System for the ADuC834 MicroConverter, Containing:

Evaluation Board
Serial Port Cable
Windows

®

Serial Downloader (WSD)
Windows Debugger/Emulator (with C source DeBug)
Windows ADuC834 Simulator (ADSIM)
Windows ADC Analysis Software Program (WASP)
8051 Assembler (Metalink)
Example Code
Documentation

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

34

the ADuC8

features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Windows is a registered trademark of Microsoft Corporation.

REV. PrC (12 March 2002)

–17–

PRELIMINAR Y TECHNICAL D A T A

ADuC834

ADuC834 DETAILED BLOCK DIAGRAM

AIN1
AIN2

AIN3

AIN4
AIN5

REFIN
REFIN

IEXC 1

IEXC 2

)

0)

1)

P0.0 (AD

P0.1 (AD

43

44

4)

5)

6)

2)

3)

P0.2 (AD

P0.3 (AD

P0.4 (AD

45

46

49

7)

P0.5 (AD

P0.6 (AD

P0.7 (AD

P1.0 (T 2)

50

51

52

P1.1 (T2EX)3P1.2 (DAC/IEXC 1)

1

2

P1.3 (AIN5/IEXC 2)

4 9

P1.4 (AI N1 )10P1.5 (AI N2 )11P1.6 (AI N3 )12P1.7 (

4/DAC
AIN

ADuC834

AIN

MUX

AIN

MUX

TEMP

SENSOR

ⴙⴙⴙⴙ

ⴚⴚⴚⴚ

A

200

␮␮␮␮

CURRENT

SOURCE

MUX

5

DD

AV

6

D

AGN

BANDGAP

REFEREN CE

200

34 47

20

DD

DV

DVDDDV

V

DETECT

A

␮␮␮␮

48

PGA

BUF

AUXILIARY ADC

16-BIT

ADC

⌺⌬

⌺⌬

⌺⌬⌺⌬

REF

POR

21

35

D

D

DD

DGN

DGN

PRIMARY ADC

24-BIT

ADC

⌺⌬

⌺⌬

⌺⌬⌺⌬

ADC CONTR OL

CALIBRATION

62 KBYTES PROGRAM
FLASH/EE INCLUDING

USER DOWNLOAD MODE

4 KBYTES DATA

FLASH/EE

2 KBytes USER XRAM

2 X DATA POINTERS

11-BIT S T A C K P O INTER

UART

SERIAL PORT

16

15

D

DGN

RESET

17

RXD

AND

DOWNLO ADE R

DEBUGG ER

TXD

CONTROL

CALIBRATION

UART

TIMER

28

ADC

AND

)
8
1
A

/

A17)

0

8
A

P2.0 (

1/A19)

1

1

1

1

A

A

P2.1 (A9 /

29

P2.4 (

P2.2 (

P2.3 (A1

30

31

36

8052

MCU

CORE

EMULATO R

SINGLE-PIN

40EA41

N

ALE

PSE

A

A

P2.5 (

P2.6 (

38

37

39

DAC

CONTROL

PWM

CONTROL

256 BYTES USER

POWER SUPPLY

SPI SERIAL

INTE R F AC E

26

0
/D

SCLOCK

1
A

P2.7 (

RAM

WATCHDOG

TIMER

MONITOR

27

D1

/

MOSI

)

INT 0

P3.0 (RXD)

P3.1 (TXD)18P3.2 (

16

17

19

12-BIT

VOLTAGE

OUTPUT DAC

16-BIT

SD DAC

16-BIT

SD DAC

16-BIT

PWM

16-BIT

PWM

PROG. CLOCK

TIME INTERVAL

COUNTE R

(WAKEUP CCT)

14

13

SS

MISO

)

INT 1

P3.4 (T 0)23P3.5 (T1)24P3.6 (

P3.3 (

22

MUX

16-BIT

COUNTE R

TIMERS

DIVIDER

OSC

3242

XTAL1

BUF

PLL

33

)

WR

XTAL2

)

RD

P3.7 (

25

DAC

3

PWM0

1

2

PWM1

22

T0

23

T1

1

T2

2

T2EX

INT 0

18

19

INT 1

* SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADUC834 OVER THE ADUC824

Figure 11. ADuC834 Detailed Block Diagram

ADuC834 PIN BY PIN FUNCTION DESCRIPTION

Pin No. Mnemonic Type* Description

1, 2 P1.0/P1.1 I/O P1.0 and P1.1 can function as a digital inputs or digital outputs and have a

pull-up configuration as described below for Port 3. P1.0 and P1.1 have an
increased current drive sink capability of 10 mA.

P1.0/T2/PWM0 I/O P1.0 and P1.1 also have various secondary functions as described below.

P1.0 can also be used to provide a clock input to Timer 2. When Enabled, counter
2 is incremented in response to a negative transition on the T2 input pin.
If the PWM is enabled then the PWM0 output will appear at this pin.

P1.1/T2EX/PWM1 I/O P1.1 can also be used to provide a control input to Timer 2. When Enabled, a

negative transition on the T2EX input pin will cause a Timer 2 capture or reload
event.
If the PWM is enabled then the PWM1 output will appear at this pin.

–18–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

Pin No. Mnemonic Type* Description

3-4, 9-12 P1.2-P1.7 I Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital

input for which ‘0’ must be written to the port bit. As a digital input, these pins
must be driven high or low externally.
These pins also have the following analog functionality:

P1.2/DAC/IEXC1 I/O The voltage output from the DAC or one or both current sources (20 0 µ A o r 2 x

200 µA ) can be configured to appear at this pin.
P1.3/AIN5/IEXC2 I/O Auxiliary ADC Input or one or both current sources can be configured at this pin.
P1.4/AIN1 I Primary ADC, Positive Analog Input
P1.5/AIN2 I Primary ADC, Negative Analog Input
P1.6/AIN3 I Auxiliary ADC Input or muxed Primary ADC, Positive Analog Input
P1.7/AIN4/DAC I/O Auxiliary ADC Input or muxed Primary ADC, Negative Analog Input. The voltage

output from the DAC can also be configured to appear at this pin.

5AV
6 AGND S Analog Ground. Ground reference pin for the analog circuitry.

7 REFIN(–) I Reference input, negative terminal.
8 REFIN(+) I Reference input, positive terminal.

13 SS I Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.
14 MISO I/O Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this

15 RESET I Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is

16–19, P3.0–P3.7 I/O P3.0–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins
22-25 that have 1s written to them are pulled high by the internal pull-up resistors, and

DD

P3.0/RXD I/O Receiver Data for UART serial Port
P3.1/TXD I/O Transmitter Data for UART serial Port
P3.2/INT0 I/O External Interrupt 0. This pin can also be used as a gate control input to Timer0.
P3.3/INT1 I/O External Interrupt 1. This pin can also be used as a gate control input to Timer1.
P3.4/T0 I/O Timer/Counter 0 External Input
P3.5/T1 I/O Timer/Counter 1 External Input
P3.6/WR I/O External Data Memory Write Strobe. Latches the data byte from Port 0 into an

P3.7/RD I/O External Data Memory Read Strobe. Enables the data from an external data

S Analog Supply Voltage, 3 V or 5 V

input pin.

running resets the device. There is an internal weak pull-down and a Schmitt

trigger input stage on this pin.

in that state can be used as inputs. As inputs, Port 3 pins being pulled externally

low will source current because of the internal pull-up resistors. When driving a

0-to-1 output transition, a strong pull-up is active for two core clock periods of

the instruction cycle.

Port 3 pins also have various secondary functions described below.

external data memory.

memory to Port 0.

20, 34, 48 DV
21, 35, 47 DGND S Digital ground, ground reference point for the digital circuitry.

26 SCLOCK/D0 I/O Serial interface clock for the SPI interface. As an input this pin i s a Schmitt

27 MOSI/D1 I/O Serial master output/slave input data for the SPI interface. A weak internal

REV. PrC (12 March 2002)

DD

S Digital supply, 3 V or 5 V.

triggered input and a weak internal pull-up is present on this pin unless it is

outputting logic low.

This pin can also be controlled directly in software as a digital output pin.

pull-up is present on this pin unless it is outputting logic low.

This pin can also be controlled directly in software as a digital output pin.

–19–

PRELIMINAR Y TECHNICAL D A T A

ADuC834

Pin No. Mnemonic Type* Description

28–31 P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s
36-39 (A8–A15) written to them are pulled high by the internal pull-up resistors, and in that state can

(A16–A23) be used as inputs. As inputs, Port 2 pins being pulled externally low will source current

because of the internal pull-up resistors.
Port 2 emits the high order address bytes during fetches from external program
memory and middle and high order address bytes during accesses to the 24-bit
external data memory space.

32 XTAL1 I Input to the crystal oscillator inverter.
33 XTAL2 O Output from the crystal oscillator inverter. (see page 68 for description)

40 EA I/O External Access Enable, Logic Input. When held high, this input enables the device

to fetch code from internal program memory locations 0000h to F800h. When held
low this input enables the device to fetch all instructions from external program
memory. To determine the mode of code execution, i.e., internal or external, the
EA pin is sampled at the end of an external RESET assertion or as part of a device
power cycle.
EA may also be used as an external emulation I/O pin and therefore the voltage
level at this pin must not be changed during normal mode operation as it may
cause an emulation interrupt that will halt code execution.

41 PSEN O Program Store Enable, Logic Output. This output is a control signal that enables

the external program memory to the bus during external fetch operations. It is
active every six oscillator periods except during external data memory accesses.
This pin remains high during internal program execution.
PSEN can also be used to enable serial download mode when pulled low through a
resistor at the end of an external RESET assertion or as part of a device power cycle.

42 ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and

page byte for 24-bit data address space accesses) of the address to external memory
during external code or data memory access cycles. It is activated every six oscillator
periods except during an external data memory access. It can be disabled by setting
the PCON.4 bit in the PCON SFR.

43–46 P0.0–P0.7 I/O P0.0–P0.7, these pins are part of Port0 which is an 8-bit open-drain bidirectional
49–52 (AD0–AD3) I/O port. Port 0 pins that have 1s written to them float and in that state can be used

(AD4–AD7) as high impedance inputs. An external pull-up resistor will be required on P0

outputs to force a valid logic high level externally. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program or data memory.
In this application it uses strong internal pull-ups when emitting 1s.

*I = Input, O = Output, S = Supply.
NOTES

1. In the following descriptions, SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated.

2. In the following descriptions, SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC834 hardware unless otherwise stated.

3. User software should not write 1s to reserved or unimplemented bits as they may be used in future products.

–20–

(12 March 2002) REV. PrC

PRELIMINAR Y TECHNICAL D A T A

ADuC834

MEMORY ORGANIZATION

The ADuC834 contains 4 different memory blocks namely:

- 62kBytes of On-Chip Flash/EE Program Memory

- 4kBytes of On-Chip Flash/EE Data Memory

- 256 Bytes of General Purpose RAM

- 2kBytes of Internal XRAM

(1) Flash/EE Program Memory

The ADuC834 provides 62kBytes of Flash/EE program
memory to run user code. The user can choose to run code
from this internal memory or run code from an external pro­gram memory.
If the user applies power or resets the device while the EA pin
is pulled low, the part will execute code from the external pro­gram space, otherwise the part defaults to code execution
from i ts internal 62kBytes of Flash/EE program memory. Un­like the ADuC824, where code execution can overflow from the
internal code space to external code space once the PC be­comes greater than 1FFFh, the ADuC834 does not support the
rollover from F7FFh in internal code space to F800h in exter­nal code space. Instead the 2048 bytes between F800h and
FFFFh will appear as NOP instructions to user code.
This internal code space can be downloaded via the UART
serial port while the device is in-circuit.
56kBytes of the program memory can be repogrammed during
runtime hence the code space can be upgraded in the field
using a user defined protocol or it can be used as a data
memory. This will be discussed in more detail in the Flash/EE
Memory section of the datasheet.

(2) Flash/EE Data Memory

4kBytes of Flash/EE Data Memory are available to the user
an d c a n b e accessed indirectly via a group of control registers
mapped into the Special Function Register (SFR) area. Access
to the Flash/EE Data memory is discussed in detail later as part
of the Flash/EE memory section in this data sheet.

if one is going to use more than one register bank, the stack
pointer should be initialized to an area of RAM not used for data
storage.

7FH

GENERAL-PURPOSE
AREA

30H

BANKS

SELECTED

VIA

BITS IN PSW

20H

11

18H

10

10H

01

08H

00

00H

2FH

BIT-ADDRESSABLE
(BIT ADDRESSES)

1FH

17H

FOUR BANKS OF EIGHT
REGISTERS

0FH

R0 R7

07H

RESET VALUE OF
STACK POINTER

Figure 12. Lower 128 Bytes of Internal Data Memory

The ADuC834 contains 2048 bytes of internal XRAM, 1792
bytes of which can be configured to be used as an extended 11­bit stack pointer.
By default the stack will operate exactly like an 8052 in that it
will rollover from FFh to 00h in the general purpose RAM. On
the ADuC834 however it is possible (by setting CFG834.7) to
enable the 11-bit extended stack pointer. In this case the stack
will rollover from FFh in RAM to 0100h in XRAM.
The 11-bit stack pointer is visable in the SP and SPH SFRs.
The SP SFR is located at 81h as with a standard 8052. The
SPH SFR is located at B7h. The 3 LSBs of this SFR contain
the 3 extra bits necessary to extend the 8-bit stack pointer into
an 11-bit stack pointer.

(3) General Purpose RAM

The general purpose RAM is divided into two seperate memo­ries, namely the upper and the lower 128 bytes of RAM. The
lower 128 bytes of RAM can be accessed through direct or
indirect addressing while the upper 128 bytes of RAM can
only be accessed through indirect addressing as it shares the
same address space as the SFR space which can only be ac­cessed through direct addressing.
The lower 128 bytes of internal data memory are mapped as
shown in Figure 12. The lowest 32 bytes are grouped into
four banks of eight registers addressed as R0 through R7. The
next 16 bytes (128 bits), locations 20Hex through 2FHex
above the register banks, form a block of directly addressable
bit locations at bit addresses 00H through 7FH. The stack can
be located anywhere in the internal memory address space, and
the stack depth can be expanded up to 2048 bytes.
Reset initializes the stack pointer to location 07 hex and incre­ments it once before loading the stack to start from locations 08
hex which is also the first register (R0) of register bank 1. Thus,

REV. PrC (12 March 2002)

–21–

07FFH

UPPER 1792

BYTES OF

ON-CHIP XRAM

(DATA +STACK

FOR EXSP=1,

DATA ONLY

100H

00H

FOR EXSP=0)

LOWER 256

BYTES OF

ON-CHIP XRAM

(DATA ONLY)

CFG834.7 = 0

FFH

256 BYTES OF

ON-CHIP DATA

(DATA + STACK)

00H

CFG834.7 = 1

RAM

Figure 13. Extended Stack Pointer Operation

ADuC834

PRELIMINAR Y TECHNICAL D A T A

External Data Memory (External XRAM)

Just like a standard 8051 compatible core the ADuC834 can
access external data memory using a MOVX instruction. The
MOVX instruction automatically outputs the various control
strobes required to access the data memory.
The ADuC834 however, can access up to 16MBytes of extrenal
data memory. This is an enhancement of the 64kBytes external
data memory space available on a standard 8051 compatible
core.
The external data memory is discussed in more detail in the
ADuC834 Hardware Design Considerations section.

Internal XRAM

2kBytes of on-chip data memory exist on the ADuC834. This
memory although on-chip is also accessed via the MOVX in­struction. The 2kBytes of internal XRAM are mapped into the
bottom 2kBytes of the external address space if the CFG834.0
bit is set, otherwise access to the external data memory will
occur just like a standard 8051.

Even with the CFG834.0 bit set access to the external XRAM
will occur once the 24 bit DPTR is greater than 0007FFH.

When accessing the internal XRAM the P0, P2 port pins as well
as the RD and WR strobes will not be output as per a standard
8051 MOVX instruction. This allows the user to use these port
pins as standard I/O.

FFFFFFH

FFFFFFH

SPECIAL FUNCTION REGISTERS (SFRs)

The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on chip periph­erals. A block diagram showing the programming model of the
ADuC834 via the SFR area is shown in Figure 15.
All registers except the Program Counter (PC) and the four
general-purpose register banks, reside in the SFR area. The
SFR registers include control, configuration, and data regis­ters that provide an interface between the CPU and all on-chip
peripherals.

62 KBYTE ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE FLASH/EE

PROGRAM MEMORY

8051-

COMPAT IBLE

CORE

256 BYTES RAM

2K XRAM

128-BYTE

SPECIAL
FUNCTION
REGISTER

AREA

4 KBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLAT ILE

FLASH/EE DATA

MEMORY

DUAL

SIGMA-DELTA

ADCs

OTHER ON-CHIP

PERIPHERALS
TEMP SENSOR

CURRENT SOU RCES

12-BIT D A C

SERIAL I/O
WDT, PSM

TIC, PLL

EXTERNAL

MEMORY

ADDRESS

2 KBYTES

ON-CHIP

CFG834.0=1

000000H

EXTERNAL

DATA

MEMORY

SPACE
(24-BIT

ADDRESS

SPACE)

CFG834.0=0

000800H
0007FFH

000000H

Figure 14. Internal and External XRAM

DATA

SPACE
(24-BIT

SPACE)

XRAM

Figure 15. Programming Model

Accumulator SFR (ACC)

ACC is the Accumulator register and is used for math opera­tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the Accumulator as
A.

B SFR (B)

The B register is used with the ACC for multiplication and
division operations. For other instructions it can be treated
as a general-purpose scratchpad register.

Stack Pointer (SP and SPH)

The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the ‘top of the stack.’ The SP register
is incremented before data is stored during PUSH and CALL
executions. While the Stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
As mentioned earlier the ADuC834 offers an extended 11-bit
stack pointer. The 3 extra bits to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7h.

–22–

(12 March 2002) REV. PrC