ANALOG DEVICES ADUC832 Service Manual

MicroConverter, 12-Bit ADCs and DACs

FEATURES

ANALOG I/O

8-channel, 247 kSPS, 12-Bit ADC

DC performance: ±1 LSB INL

AC performance: 71 dB SNR DMA controller for high speed ADC-to-RAM capture 2 12-bit (monotonic) voltage output DACs Dual output PWM/Σ-∆ DACs On-chip temperature sensor function: ±3°C On-chip voltage reference

Memory

62 kB on-chip Flash/EE program memory 4 kB on-chip Flash/EE data memory Flash/EE, 100 Yr retention, 100,000 cycles of endurance 2304 bytes on-chip data RAM

8051-based core

8051-compatible instruction set (16 MHz maximum) 32 kHz external crystal, on-chip programmable PLL 12 interrupt sources, 2 priority levels Dual data pointer Extended 11-bit stack pointer

On-chip peripherals

Time interval counter (TIC)

2

UART, I Watchdog timer (WDT), power supply monitor (PSM)

Power

Specified for 3 V and 5 V operation Normal, idle, and power-down modes Power-down: 25 µA @ 3 V with wake-up timer running

APPLICATIONS

Optical networking—laser power control Base station systems Precision instrumentation, smart sensors Transient capture systems DAS and communications systems Upgrade to ADuC812 systems; runs from 32 kHz External crystal with on-chip PLL. Also available: ADuC831 pin-compatible upgrade to

existing ADuC812 systems that require additional code or data memory; runs from 1 MHz to 16 MHz

External crystal

C, and SPI Serial I/O

with Embedded 62 kB Flash MCU

ADuC832

FUNCTIONAL BLOCK DIAGRAM

ADuC832

ADC0 ADC1

ADC5 ADC6 ADC7

TEMP

SENSOR

INTERNAL BAND GAP

VREF

MUX

V

T/H

REF

PLL

OSC

XTAL2XTAL1

12-BIT ADC

HARDWARE

CALIBRATON

8051-BASED MCU WITH ADDITIONAL

62 kB FLASH/EE PROGRAM MEMORY

4 kB FLASH/EE DATA ME M O RY

3 × 16-BIT TIM ERS

1 × REAL-TI M E CL O CK

4 ×PARALLEL

PORTS

Figure 1.

GENERAL DESCRIPTION

The ADuC832 is a complete, smart transducer front end, integrating a high performance self-calibrating multichannel 12-bit ADC, dual 12-bit DACs, and programmable 8-bit MCU on a single chip.

The device operates from a 32 kHz crystal with an on-chip PLL, generating a high frequency clock of 16.78 MHz. This clock is, in turn, routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an 8052 and is therefore 8051 instruction set compatible with 12 core clock periods per machine cycle. 62 kB of nonvolatile Flash/EE program memory are provided on chip. There are also 4 kB of nonvolatile Flash/EE data memory, 256 bytes of RAM, and 2 kB of extended RAM integrated on chip.

The ADuC832 also incorporates additional analog functionality with two 12-bit DACs, a power supply monitor, and a band gap reference. On-chip digital peripherals include two 16-bit Σ- DACs, a dual-output 16-bit PWM, a watchdog timer, time interval counter, three timers/counters, Timer 3 for baud rate generation, and serial I/O ports (SPI, I

12-BIT

DAC

12-BIT

DAC

16-BIT

Σ-Δ DAC

16-BIT

Σ-Δ DAC

16-BIT

PWM

16-BIT

PWM

PERIPHERALS

2304 BYTES USER RAM

POWER SUPPLY MO N

WATCHDOG TIMER

UART, I

SERIAL I/ O

2

C®, and UART).

BUF

2

C, AND SPI

MUX

DAC0

DAC1

PWM0

PWM1

2987-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADuC832

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to Figure 1 .......................................................................... 1

Changed 16.77 MHz to 16.78 MHz Throughout ......................... 1

Changes to Reference Input/Output, Output Voltage Parameter,

Endnote 19, and Endnote 20, Table 1 ............................................ 9

Moved Timing Specifications Section ......................................... 10

Changes to Figure 3 ........................................................................ 10

Changes to Table 3 .......................................................................... 11

Changes to Table 4 .......................................................................... 12

Changes to Table 5 .......................................................................... 13

Changes to Table 11 ........................................................................ 19

Changes to Figure 15 and Table 13 ............................................... 21

Changes to Figure 16, Figure 17, Figure 20, and Figure 21 ....... 26

Added Explanation of Typical Performance Plots Section ....... 30

Changes to Flash/EE Program Memory, Flash/EE Data

Memory, and General-Purpose RAM Sections .......................... 31

Changes to Figure 36 ...................................................................... 34

Changes to Figure 39 and Figure 40 ............................................. 39

Changes to Table 20 ........................................................................ 40

Changes to A Typical DMA Mode Configuration Example

Section .............................................................................................. 41

Changed 16.777216 MHz to 16.78 MHz Throughout ............... 41

Changes to Table 21 ........................................................................ 48

Changes to Using the DAC Section and Figure 52 .................... 52

Changes to Figure 54 Caption ...................................................... 53

Changes to Figure 56 ...................................................................... 55

Changed 16.77 MHz to 16.78 MHz ............................................. 56

Changes to Figure 60 ...................................................................... 57

Changes to Table 31 ....................................................................... 63

Deleted Figure 65 and Figure 66; Renumbered Sequentially ... 66

Deleted ASPIRE—IDE Section..................................................... 66

Deleted Figure 67 ............................................................................ 67

Changes to Table 34 ....................................................................... 67

Changes to Figure 68, Figure 69, Figure 70, and Table 35 ........ 68

Changes to Figure 84 ...................................................................... 78

Changes to External Memory Interface Section ........................ 82

Changes to Power Supplies Section ............................................. 83

Changes to Table 50 ....................................................................... 84

Changes to Figure 94 ...................................................................... 86

Changes to Single-Pin Emulation Mode Section ....................... 87

Changes to QuickStart Development System Section and

QuickStart Plus Development System Section ........................... 88

Updated Outline Dimensions ....................................................... 89

Changes to Ordering Guide .......................................................... 89

11/02—Revision 0: Initial Version

Rev. A | Page 4 of 92

ADuC832

On-chip factory firmware supports in-circuit serial download and debug modes (via UART) as well as single-pin emulation mode via the

EA

pin. The ADuC832 is supported by QuickStart™ and QuickStart Plus development systems featuring low cost software and hardware development tools. A functional block

diagram of the ADuC832 is shown in with a more detailed block diagram shown in .

The part is specified for 3 V and 5 V operation over the extended industrial temperature range and is available in a 52-lead metric quad flat package (MQFP) and a 56-lead lead frame chip scale package (LFCSP).

Figure 1

Figure 2

PWM

TIMER

DATA/MOSI

2

C )

MISO

12-BIT

VOLTAGE

OUTPUT DAC

12-BIT

VOLTAGE

OUTPUT DAC

16-BIT

Σ-Δ DAC

16-BIT

Σ-Δ DAC

16-BIT PWM

16-BIT

COUNTER

TIMERS

PROG. CLOCK

DIVIDER

TIME INTERVAL

COUNTER

(WAKEUP C CT)

SS

MUX

PLL

OSC

XTAL1

DAC0

DAC1

PWM0

PWM1

T0 T1 T2 T2EX

INT0 INT1

XTAL2

2987-004

ADC0 ADC1

ADC6 ADC7

V

REF

C

REF

ADuC832

TEMP

SENSOR

BAND GAP

REFERENCE

DD

AV

AGND

MUX

DDDVDDDVDD

DV

BUF

T/H

DGND

FLASH/EE INCLUDING

USER DOWNLO AD M ODE

2 × DATA POINTERS

11-BIT STACK PO I N T ER

POR

DGND

RESET

12-BIT

ADC

62 kB PROGRAM

4 kB DATA FLASH/EE

2 kB USER XRAM

DOWNLOADER

DEBUGGER

ASYNCHRONOUS

SERIAL PORT

(UART)

TxD

RxD

ADC

CONTROL

AND

CALIBRATION

CORE

UART

TIMER

ALE

8052 MCU

PSEN

SINGLE-PIN

EMULATOR

EA

CONTROL

DAC

CONTROL

256 BYTES USER RAM

WATCHDOG

POWER SUPPLY

MONITOR

SYNCHRONOUS

SERIAL INT E RFACE

(SPI OR I

SCLOCK

Figure 2. ADuC832 Block Diagram (Shaded Areas are Features Not Present on the ADuC812)

Rev. A | Page 5 of 92

ADuC832

SPECIFICATIONS

AVDD = DVDD = 2.7 V to 3.3 V or 4.5 V to 5.5 V; V unless otherwise noted.

= 2.5 V internal reference, f

REF

= 16.78 MHz; all specifications TA = T

CORE

MIN

to T

MAX

,

Table 1.

Parameter

ADC CHANNEL SPECIFICATIONS

DC Accuracy

Calibrated Endpoint Errors

Dynamic Performance fIN = 10 kHz sine wave, fS = 147 kHz

Analog Input

Temperature Sensor

±1.5 ±1.5 °C typ External 2.5 V V DAC CHANNEL SPECIFICATIONS, INTERNAL BUFFER

ENABLED DC Accuracy10

Analog Outputs

DAC AC Characteristics

1

2, 3

VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

f

= 147 kHz, see Figure 16 to Figure 21 at

S

other f

S

Resolution 12 12 Bits Integral Nonlinearity ±1 ±1 LSB max For 2.5 V internal reference ±0.3 ±0.3 LSB typ Differential Nonlinearity ±0.9 ±0.9 LSB max 2.5 V internal reference ±0.25 ±0.25 LSB typ Integral Nonlinearity Differential Nonlinearity

4

+1.5/−0.9 +1.5/−0.9 LSB max 1 V external reference

±1.5 ±1.5 LSB max 1 V external reference

Code Distribution 1 1 LSB typ ADC input is a dc voltage

5, 6

Offset Error ±4 ±4 LSB max Offset Error Match ±1 ±1 LSB typ Gain Error ±2 ±3 LSB max Gain Error Match −85 −85 dB typ

Signal-to-Noise Ratio (SNR)

7

71 71 dB typ Total Harmonic Distortion (THD) −85 −85 dB typ Peak Harmonic or Spurious Noise −85 −85 dB typ Channel-to-Channel Crosstalk

Input Voltage Ranges 0 to V

8

−80 −80 dB typ

0 to V

REF

V

REF

Leakage Current ±1 ±1 A max Input Capacitance 32 32 pF typ

9

Voltage Output at 25°C 650 650 mV typ Voltage TC −2.0 −2.0 mV/°C typ Accuracy ±3 ±3 °C typ Internal 2.5 V V

DAC load to AGND, R

REF

= 10 kΩ, CL = 100 pF

L

Resolution 12 12 Bits Relative Accuracy ±3 ±3 LSB typ Differential Nonlinearity11 −1 −1 LSB max Guaranteed 12-bit monotonic ±1/2 ±1/2 LSB typ Offset Error ±50 ±50 mV max

V

REF

range Gain Error ±1 ±1 % max AVDD range ±1 ±1 % typ V

range

REF

Gain Error Mismatch 0.5 0.5 % typ % of full scale on DAC1

Voltage Range 0 0 to V Voltage Range 1 0 to VDD 0 to VDD V typ DAC V

0 to V

REF

V typ DAC V

REF

= 2.5 V

REF

= VDD

REF

Output Impedance 0.5 0.5 Ω typ

Voltage Output Settling Time 15 15 s typ Full-scale settling time to within ½ LSB of final

value

Digital-to-Analog Glitch Energy 10 10 nV sec typ 1 LSB change at major carry

Rev. A | Page 6 of 92

ADuC832

Parameter

DAC CHANNEL SPECIFICATIONS

DISABLED DC Accuracy

1

12, 13

10

, INTERNAL BUFFER

VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

Resolution 12 12 Bits Relative Accuracy ±3 ±3 LSB typ Differential Nonlinearity11 −1 −1 LSB max Guaranteed 12-bit monotonic ±1/2 ±1/2 LSB typ Offset Error ±5 ±5 mV max V Gain Error −0.3 −0.3 % typ V

range

REF

range

REF

Gain Error Mismatch4 0.5 0.5 % max % of full scale on DAC1

Analog outputs

Voltage Range 0 0 to V

0 to V

REF

V typ DAC V

REF

= 2.5 V

REF

REFERENCE INPUT/OUTPUT

Reference Output

Output Voltage (V Accuracy ±2.5 ±2.5 % max Of V

14

) 2.5 2.5 V typ

REF

measured at the C

REF

pin Power Supply Rejection 47 47 dB typ Reference Temperature Coefficient ±100 ±100 ppm/°C

typ

Internal V

External Reference Input

Voltage Range (V V

Power-On Time 80 80 ms typ

REF

15

4

)

0.1 0.1 V min

REF

V

DD

V max

DD

and C

REF

pins shorted

REF

Input Impedance 20 20 kΩ typ Input Leakage 1 1 A max Internal band gap deselected via

ADCCON1[6]

POWER SUPPLY MONITOR (PSM)

DVDD Trip Point Selection Range 2.63 V min Four trip points selectable in this range

4.37 V max programmed via TPD1 and TPD0 in PSMCON

DVDD Power Supply Trip Point Accuracy ±3.5 % max

WATCHDOG TIMER (WDT)4

Timeout Period 0 0 ms min Nine timeout periods 2000 2000 ms max Selectable in this range FLASH/EE MEMORY RELIABILITY CHARACTERISTICS

Endurance

Data Retention

17

18

16

100,000 100,000 Cycles min 100 100 Years min

DIGITAL INPUTS

Input High Voltage (V

Input Low Voltage (V

Input Leakage Current (Port 0, EA)

)4 2.4 2 V min

INH

)4 0.8 0.4 V max

INL

±10 ±10 A max V

= 0 V or VDD

IN

±1 ±1 A typ VIN = 0 V or VDD

Logic 1 Input Current (All Digital Inputs)

±10 ±10 A max VIN = VDD ±1 ±1 A typ VIN = VDD Logic 0 Input Current (Port 1, Port 2, and Port 3) −75 −25 A max

−40 −15 A typ VIL = 450 mV Logic 1-to-Logic 0 Transition Current (Port 2, Port 3) −660 −250 A max VIL = 2 V

−400 −140 A typ VIL = 2 V

Rev. A | Page 7 of 92

ADuC832

Parameter

1

VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

SCLOCK and RESET ONLY4

(Schmitt-Triggered Inputs)

VT+ 1.3 0.95 V min

3.0 2.5 V max VT− 0.8 0.4 V min

1.4 1.1 V max VT+ − VT− 0.3 0.3 V min

0.85 0.85 V max CRYSTAL OSCILLATOR

Logic Inputs, XTAL1 Only

V

, Input Low Voltage 0.8 0.4 V typ

INL

V

, Input High Voltage 3.5 2.5 V typ

INH

XTAL1 Input Capacitance 18 18 pF typ

XTAL2 Output Capacitance 18 18 pF typ MCU CLOCK RATE 16.78 16.78 MHz max Programmable via PLLCON[2:0] DIGITAL OUTPUTS

Output High Voltage (VOH) 2.4 V min VDD = 4.5 V to 5.5 V

4.0 V typ I

SOURCE

= 80 A

2.4 V min VDD = 2.7 V to 3.3 V

2.6 V typ I

SOURCE

= 20 A

Output Low Voltage (VOL)

ALE, Port 0 and Port 2 0.4 0.4 V max I

0.2 0.2 V typ I

Port 3 0.4 0.4 V max I

SCLOCK/SDATA 0.4 0.4 V max I

Floating State Leakage Current

4

±10 ±10 A max

= 1.6 mA

SINK

= 1.6 mA

SINK

= 4 mA

SINK

= 8 mA, I2C enabled

SINK

±1 ±1 A typ

Floating State Output Capacitance 10 10 pF typ START-UP TIME At any Core_CLK

At Power-On 500 500 ms typ From Idle Mode 100 100 s typ From Power-Down Mode

Wakeup with

INT0

Interrupt

150 400 s typ

Wakeup with SPI/I2C Interrupt 150 400 s typ

Wakeup with External Reset 150 400 s typ

After External Reset in Normal Mode 30 30 ms typ

After WDT Reset in Normal Mode 3 3 ms typ Controlled via WDCON SFR POWER REQUIREMENTS

19, 20

Power Supply Voltages

AVDD/DVDD − AGND 2.7 V min AVDD/DVDD = 3 V nom

3.3 V max

4.5 V min AVDD/DVDD = 5 V nom

5.5 V max Power Supply Currents Normal Mode

DVDD Current

4

6 3 mA max Core_CLK = 2.097 MHz

AVDD Current 1.7 1.7 mA max Core_CLK = 2.097 MHz

DVDD Current 23 12 mA max Core_CLK = 16.78 MHz 20 10 mA typ Core_CLK = 16.78 MHz

AVDD Current 1.7 1.7 mA max Core_CLK = 16.78 MHz

Power Supply Currents Idle Mode

DVDD Current 4 2 mA typ Core_CLK = 2.097 MHz

AVDD Current 0.14 0.14 mA typ Core_CLK = 2.097 MHz

DVDD Current4 10 5 mA max Core_CLK = 16.78 MHz 9 4 mA typ Core_CLK = 16.78 MHz

AVDD Current 0.14 0.14 mA typ Core_CLK = 16.78 MHz

Rev. A | Page 8 of 92

ADuC832

Parameter

1

VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

Power Supply Currents Power-Down Mode Core_CLK = 2.097 MHz or 16.78 MHz

DVDD Current

4

80 25 A max Oscillator on

38 14 A typ AVDD Current 2 1 A typ

DVDD Current 35 20 A max Oscillator off 25 12 A typ Typical Additional Power Supply Currents AVDD = DVDD = 5 V

PSM Peripheral 50 A typ

ADC 1.5 mA typ

DAC 150 A typ

1

Temperature range: −40°C to +125°C.

2

ADC linearity is guaranteed during normal MicroConverter core operation.

3

ADC LSB size = V

4

Not production tested, but are guaranteed by design and/or characterization data on production release.

5

Offset error, gain error, offset error match, and gain error match are measured after factory calibration.

6

Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these

specifications.

7

SNR calculation includes distortion and noise components.

8

Channel-to-channel crosstalk is measured on adjacent channels.

9

The temperature sensor gives a measure of the die temperature directly; air temperature can be inferred from this result.

10

DAC linearity is calculated using:

Reduced code range of 100 to 4095, 0 V to V Reduced code range of 100 to 3945, 0 V to VDD range. DAC output load = 10 kΩ and 100 pF.

11

DAC differential nonlinearity specified on 0 V to V

12

DAC specification for output impedance in the unbuffered case depends on DAC code.

13

DAC specifications for I unbuffered mode tested with OP270 external buffer, which has a low input leakage current.

14

Measured with V capacitor chosen for both the V

15

When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1[6] bit. In this mode, the V need to be shorted together for correct operation.

16

Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.

17

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 700,000 cycles.

18

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22 Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature as shown in Figure 48 in the ADuC832 Flash/EE Memory Reliability section.

19

Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions:

/212, that is, for internal V

REF

, voltage output settling time, and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in

SINK

and C

REF

pins decoupled with 0.1 µF capacitors to ground. Power-up time for the internal reference is determined by the value of the decoupling

REF

and C

REF

= 2.5 V, 1 LSB = 610 µV and for external V

REF

range.

REF

and 0 V to VDD ranges.

REF

pins.

REF

= 1 V, 1 LSB = 244 µV.

REF

and C

REF

Normal mode: RESET = 0.4 V, digital I/O pins = open circuit, Core_CLK changed via the CD bits in PLLCON[2:0], core executing internal software loop. Idle mode: RESET = 0.4 V, digital I/O pins = open circuit, Core_CLK changed via the CD bits in PLLCON, PCON[0] = 1, core execution suspended in idle mode. Power-down mode: RESET = 0.4 V, all Port 0 pins = 0.4 V, all other digital I/O and Port 1 pins are open circuit, Core_CLK changed via the CD bits in PLLCON, PCON[1] = 1, core execution suspended in power-down mode, oscillator turned on or off via OSC_PD bit (PLLCON[7]).

20

DVDD power supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.

pins

Rev. A | Page 9 of 92

ADuC832

V

TIMING SPECIFICATIONS

AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications T

Table 2. Clock Input (External Clock Applied on XTAL1)

32.768 kHz External Crystal

1, 2, 3

Parameter

Description Min Typ Max Unit

tCK XTAL1 period (see Figure 3) 30.52 s t

XTAL1 width low (see Figure 3) 15.16 s

CKL

t

XTAL1 width high (see Figure 3) 15.16 s

CKH

t

XTAL1 rise time (see Figure 3) 20 ns

CKR

t

XTAL1 fall time (see Figure 3) 20 ns

CKF

1/t

ADuC832 core clock frequency

CORE

t

ADuC832 core clock period

CORE

t

ADuC832 machine cycle time

CYC

1

AC inputs during testing are driven at DVDD − 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at VIH minimum for a Logic 1 and VIL maximum for

a Logic 0, as shown in Figure 4.

2

For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the

loaded VOH/VOL level occurs, as shown in Figure 4.

3

C

for all outputs = 80 pF, unless otherwise noted.

LOAD

4

The ADuC832 internal PLL locks onto a multiple (512 times) the external crystal frequency of 32.768 kHz to provide a stable 16.78 MHz internal clock for the system.

The core can operate at this frequency or at a binary submultiple called Core_CLK, selected via the PLLCON SFR.

5

This number is measured at the default Core_CLK operating frequency of 2.09 MHz.

6

ADuC832 machine cycle time is nominally defined as 12/Core_CLK.

4

5

6

0.131 16.78 MHz

0.476 s

0.72 5.7 91.55 s

t

CKH

t

CKR

MIN

to T

, unless otherwise noted.

MAX

t

CKL

t

CK

t

CKF

2987-086

Figure 3. XTAL1 Input

DVDD –0.5

0.45V

+ 0.9V

0.2DV

DD

TEST POINTS

– 0.1V

0.2DV

DD

V

LOAD

Figure 4. Timing Waveform Characteristics

V

LOAD

– 0.1V

+ 0.1V

TIMING

REFERENCE

POINTS

V

LOAD

– 0.1V

+ 0.1V

V

LOAD

2987-087

Rev. A | Page 10 of 92

ADuC832

Table 3. External Program Memory Read Cycle

16.78 MHz Core_CLK Variable Clock

Parameter1 Description

t

ALE pulse width 79 2tCK − 40 ns

LHLL

t

Address valid to ALE low 19 tCK − 40 ns

AVLL

t

Address hold after ALE low 29 tCK − 30 ns

LLAX

t

ALE low to valid instruction in 138 4tCK − 100 ns

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

Address to valid instruction in 193 5tCK − 105 ns

AVIV

t

PLAZ

t

PHAX

1

See Figure 5.

ALE low to PSEN

pulse width

PSEN

low to valid instruction in

PSEN Instruction in, hold after PSEN Instruction in, float after PSEN

low to address float

PSEN Address hold after PSEN

low

high

M

CLK

t

LHLL

Min Max Min Max Unit

29 t 133 3t 73 3t

− 30 ns

CK

− 45 ns

CK

− 105 ns

CK

0 0 ns 34 tCK − 25 ns

25 25 ns 0 0 ns

ALE (O )

PSEN (O)

PORT 0 (I/O)

PORT 2 (O)

t

AVLLtLLPL

t

PCL (OUT)

LLAX

t

AVIV

t

PLAZ

PCH

t

PLPH

t t

LLIV PLIV

t

PXIX

INSTRUCTION

(IN)

Figure 5. External Program Memory Read Cycle

t

PXIZ

t

PHAX

02987-088

Rev. A | Page 11 of 92

ADuC832

Table 4. External Data Memory Read Cycle

16.78 MHz Core_CLK Variable Clock Parameter1 Description Min Max Min Max Unit

t

RLRH

t

Address valid before ALE low 19 tCK − 40 ns

AVLL

t

Address hold after ALE low 24 tCK − 35 ns

LLAX

t

RLDV

t

RHDX

t

RHDZ

t

ALE low to valid data in 326 8tCK − 150 ns

LLDV

t

Address to valid data in 371 9tCK − 165 ns

AVDV

t

LLWL

t

AVW L

t

RLAZ

t

WHLH

1

See Figure 6.

pulse width

RD

low to valid data in

RD Data and address hold after RD Data float after RD

ALE low to RD Address valid to RD

low to address float

RD

high to ALE high

RD

low

M

CLK

257 6t

133 5t

− 100 ns

CK

− 165 ns

CK

0 0 ns 49 2tCK − 70 ns

128 228 3t 108 4t

− 50 3tCK +50 ns

CK

− 130 ns

CK

0 0 ns 19 257 t

− 40 6tCK − 100 ns

CK

ALE (O )

PSEN (O)

RD (O)

PORT 0 (I/O)

PORT 2 (O)

t

AVLL

t

LLDV

t

LLWL

t

AVDV

t

LLAX

AVWL

t

RLAZ

t

RLDV

A8 TO A15A16 TO A23

Figure 6. External Data Memory Read Cycle

t

RLRH

D0 TO D7 (IN)A0 TO A7 (OUT)

t

RHDX

t

WHLH

t

RHDZ

02987-089

Rev. A | Page 12 of 92

ADuC832

Table 5. External Data Memory Write Cycle

16.78 MHz Core_CLK Variable Clock

Parameter1 Description

t

WLWH

t

Address valid before ALE low 19 tCK − 40 ns

AVLL

t

Address hold after ALE low 24 tCK − 35 ns

LLAX

t

LLWL

t

AVW L

t

QVWX

t

QVWH

t

WHQX

t

WHLH

1

See Figure 7.

pulse width

WR

ALE low to WR Address valid to WR Data valid to WR Data setup before WR

low

Low

transition

Data and address hold after WR

high to ALE high

WR

M

CLK

ALE (O)

Min Max Min Max Unit

257 6t

128 228 3t 108 4t 9 t

− 100 ns

CK

− 50 3tCK +50 ns

CK

− 130 ns

CK

− 50 ns

CK

267 7tCK − 150 ns 9 t 19 257 t

− 50 ns

CK

− 40 6tCK − 100 ns

CK

t

WHLH

PSEN (O)

WR (O)

PORT 2 (O)

t

AVLL

t

LLWL

t

AVWL

t

LLAX

A0 TO A7

A16 TO A23

QVWX

DATA

A8 TO A15

Figure 7. External Data Memory Write Cycle

t

WLWH

t

QVWH

t

WHQX

02987-090

Rev. A | Page 13 of 92

ADuC832

Table 6. UART Timing (Shift Register Mode)

Parameter

t

XLXL

t

QVXH

t

DVXH

t

XHDX

t

XHQX

1

See Figure 8.

1

Description

Serial port clock cycle time 715 12tCK s

Output data setup to clock 463 10tCK − 133 ns Input data setup to clock 252 2tCK + 133 ns Input data hold after clock 0 0 ns Output data hold after clock 22 2tCK − 117 ns

ALE (O)

16.78 MHz Core_CLK Variable Clock

Min Typ Max Min Typ Max Unit

t

XLXL

(OUTPUT CLOCK)

(OUTPUT DATA)

TxD

RxD

(INPUT DATA)

MSB

6

BIT 1BIT 6

BIT 1

t

DVXH

t

QVXH

1

t

XHQX

t

XHDX

BIT 6

0

MSB

LSB

7

SET RI

OR

SET TI

LSB

2987-091

Figure 8. UART Timing in Shift Register Mode

Rev. A | Page 14 of 92

ADuC832

Table 7. I2C-Compatible Interface Timing

Parameter1 Description Min Max Unit

tL SCLOCK low pulse width 4.7 s tH SCLOCK high pulse width 4.0 s t

Start condition hold time 0.6 s

SHD

t

Data setup time 100 s

DSU

t

Data hold time 0.9 s

DHD

t

Setup time for repeated start 0.6 s

RSU

t

Stop condition setup time 0.6 s

PSU

t

Bus free time between a stop condition and a start condition 1.3 s

BUF

tR Rise time of both SCLOCK and SDATA 300 ns tF Fall time of both SCLOCK and SDATA 300 ns

2

t

Pulse width of spike suppressed 50 ns

SUP

1

See Figure 9.

2

Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.

t

SDATA (I/O)

BUF

MSB

LSB

t

SUP

t

R

MSBACK

SCLOCK (I)

t

PSU

PS

STOP

CONDITION

START

CONDITION

t

DSU

t

DHD

t

SHD

Figure 9. I

2–7

2

C Compatible Interface Timing

8

t

L

1

DSU

t

H

t

SUP

t

DHD

t

RSU

9

S(R)

REPEATED

START

t

F

t

R

1

t

F

02987-092

Rev. A | Page 15 of 92

ADuC832

Table 8. SPI Master Mode Timing (CPHA = 1)

Parameter1 Description Min Typ Max Unit

tSL SCLOCK low pulse width tSH SCLOCK high pulse width t

Data output valid after SCLOCK edge 50 ns

DAV

t

Data input setup time before SCLOCK edge 100 ns

DSU

t

Data input hold time after SCLOCK edge 100 ns

DHD

tDF Data output fall time 10 25 ns tDR Data output rise time 10 25 ns tSR SCLOCK rise time 10 25 ns tSF SCLOCK fall time 10 25 ns

1

See Figure 10.

2

Characterized under the following conditions:

a. Core clock divider bits (CD2, CD1, and CD0 bits in PLLCON SFR) set to 0, 1, and 1, respectively, that is, core clock frequency = 2.09 MHz b. SPI bit rate selection bits (SPR1 and SPR0 bits in SPICON SFR) set to 0 and 0, respectively.

SCLOCK (O)

(CPO L = 0)

SCLOCK (O)

(CPO L = 1)

MOSI (O)

2

476 ns

t

MSB

SL

t

DF

t

DR

BIT 6 TO 1

t

DAV

t

SH

476 ns

SR

t

SF

LSB

MISO (I)

t

DSU

MSB IN

t

DHD

BIT 6 TO 1

Figure 10. SPI Master Mode Timing (CPHA = 1)

LSB IN

2987-093

Rev. A | Page 16 of 92

ADuC832

Table 9. SPI Master Mode Timing (CPHA = 0)

Parameter

tSL SCLOCK low pulse width tSH SCLOCK high pulse width t

DAV

t

DOSU

t

DSU

t

DHD

tDF Data output fall time 10 25 ns tDR Data output rise time 10 25 ns tSR SCLOCK rise time 10 25 ns tSF SCLOCK fall time 10 25 ns

1

See Figure 11.

2

Characterized under the following conditions:

a. Core clock divider bits (CD2, CD1, and CD0 bits in PLLCON SFR) set to 0, 1, and 1, respectively, that is, core clock frequency = 2.09 MHz b. SPI bit rate selection bits (SPR1 and SPR0 bits in SPICON SFR) set to 0 and 0, respectively.

1

Description Min Typ Max Unit

2

476 ns

Data output valid after SCLOCK edge 50 ns

Data output setup before SCLOCK edge 150 ns

Data input setup time before SCLOCK edge 100 ns

Data input hold time after SCLOCK edge 100 ns

SCLOCK (O)

(CPOL = 0)

t

SL

t

DAV

t

DF

t

DR

t

SR

t

SF

SCLOCK (O)

(CPOL = 1)

t

DOSU

t

SH

MISO (O)

MOSI (I)

t

DSU

MSB IN

t

MSB

DHD

BIT 6 TO 1

Figure 11. SPI Master Mode Timing (CPHA = 0)

LSB IN

LSB

02987-094

Rev. A | Page 17 of 92

ADuC832

Table 10. SPI Slave Mode Timing (CPHA = 1)

Parameter

tSS tSL SCLOCK low pulse width 330 ns

tSH SCLOCK high pulse width 330 ns t

Data output valid after SCLOCK edge 50 ns

DAV

t

Data input setup time before SCLOCK edge 100 ns

DSU

t

DHD

tDF Data output fall time 10 25 ns tDR Data output rise time 10 25 ns tSR SCLOCK rise time 10 25 ns tSF SCLOCK fall time 10 25 ns t

SFS

1

See Figure 12.

1

Description Min Typ Max Unit

to SCLOCK edge

SS

0 ns

Data input hold time after SCLOCK edge 100 ns

0 ns

t

SFS

t

SR

t

SF

SS (I)

SCLOCK (I)

(CPOL = 0)

SCLOCK (I)

(CPOL = 1)

high after SCLOCK edge

SS

t

SS

t

SH

t

SL

MISO (O)

MOSI (I)

t

DAV

MSB IN

t

DSU

MSB

t

DHD

t

DF

t

DR

BITS 6 TO 1

LSB

LSB IN

02987-095

Figure 12. SPI Slave Mode Timing (CPHA = 1)

Rev. A | Page 18 of 92

ADuC832

S

Table 11. SPI Slave Mode Timing (CPHA = 0)

Parameter1 Description Min Typ Max Unit

tSS

to SCLOCK edge

SS tSL SCLOCK low pulse width 330 ns tSH SCLOCK high pulse width 330 ns t

Data output valid after SCLOCK edge 50 ns

DAV

t

Data input setup time before SCLOCK edge 100 ns

DSU

t

Data input hold time after SCLOCK edge 100 ns

DHD

tDF Data output fall time 10 25 ns tDR Data output rise time 10 25 ns tSR SCLOCK rise time 10 25 ns tSF SCLOCK fall time 10 25 ns t

DOSS

t

SFS

1

See Figure 13.

Data output valid after SS

high after SCLOCK edge

SS

edge

SS (I)

0 ns

20 ns 0 ns

t

SFS

t

SF

02987-096

CLOCK (I)

(CPOL = 0)

CLOCK (I)

(CPOL = 1)

MISO (O)

MOSI (I)

t

DOSS

t

SS

t

SH

MSB LSB

MSB IN

t

DSU

DHD

t

SL

t

DAV

t

DF

t

DR

BIT 6 TO BIT 1

t

SR

LSB IN

Figure 13. SPI Slave Mode Timing (CPHA = 0)

Rev. A | Page 19 of 92

ADuC832

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 12.

Parameter Rating

AVDD to DVDD −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V DVDD to DGND, AVDD to AGND −0.3 V to +7 V Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V V

to AGND −0.3 V to AVDD + 0.3 V

REF

Analog Inputs to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial

ADuC832BS −40°C to +125°C

Operating Temperature Range Industrial

ADuC832BCP −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance (ADuC832BS) 90°C/W θJA Thermal Impedance (ADuC832BCP) 52°C/W Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 20 of 92

ADuC832

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

DVDDDGND

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

ALE

PSEN

P1.0/ADC0/T2

P1.1/ADC1/T2EX

P1.2/ADC2 P1.3/ADC3

AV

AGND

C

REF

V

REF

DAC0 DAC1

P1.4/ADC4

P1.5/ADC5/SS

P1.6/ADC6

52

51 50 49 48 47 46 45 44 43 42 41 40

1

PIN 1 IDENTIFIER

2 3 4 5

DD

6 7 8

9 10 11 12 13

P1.7/ADC7

RESET

(Not to Scale)

P3.1/TxD

P3.0/RxD

ADuC832

TOP VIEW

DD

DV

P3.2/INT0

3.3/INT1/MISO/PWM1 P

DGND

WMC/PWM0/EXTCLK

P3.4/T0/P

EA

39

P2.7/PWM1/A15/A23

38

P2.6/PWM0/A14/A22

37

P2.5/A13/A21

36

P2.4/A12/A20

35

DGND

34

DV

DD

33

XTAL2

32

XTAL1

31

P2.3/A11/A19

30

P2.2/A10/A18

29

P2.1/A9/A17

28

P2.0/A8/A16

27

SDATA/MOSI

26252423222120191817161514

P3.7/RD

P3.6/WR

SCLOCK

P3.5/T1/CONVST

02987-002

NOTES

1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE SOLDERED

AV

DD

AV

DD

AGND

C

REF

V

REF

DAC0

TO THE PCB BUT ELECTRICALLY LEFT UNCONNECTED.

P1.0/ADC0/T2 56

1P1.1/ADC1/T2EX 2P1.2/ADC2 3P1.3/ADC3 4 5 6 7AGND 8AGND 9

10

11 12DAC1 13P1.4/ADC4 14P1.5/ADC5/SS

15

P1.6/ADC6

Figure 14. 52-Lead MQFP

DD

0.7/AD7 P0.6/AD6

P

54

55

PIN 1 INDICATOR

(Not to Scale)

16

17

RESET

P.7/ADC7

P0.4/AD4

P0.5/AD5

P0.3/AD3

DGND

DV

52

53

49

50

51

ADuC832

TOP VIEW

19

21

20

22

18

DD

DV

P3.1/TxD

P3.0/RxD

P3.2/INT0

P3.3/INT1/MISO/PWM1

0.2/AD2 ALE

P0.0/AD0

P0.1/AD1

P

PSEN 44

45

46

47

48

23

24

25

26

27

DGND

P3.7/RD

P3.6/WR

P3.5/T1/CONVST

P3.4/T0/PWMC/PWM0/EXTCLK

Figure 15. 56-Lead LFCSP

EA 43

28

SCLOCK

42 41 40 39 38 37 36 35 34 33 32 31 30 29

P2.7/PWM1/A15/A23 P2.6/PWM0/A14/A22 P2.5/A13/A21 P2.4/A12/A20 DGND DGND DV

DD

XTAL2 XTAL1 P2.3/A11/A19 P2.2/A10/A18 P2.1/A9/A17 P2.0/A8/A16 SDATA/MOSI

7-003 0298

Table 13. Pin Function Descriptions

Pin No. Mnemonic MQFP LFCSP Type Description

Exposed Paddle N/A 0 The LFCSP has an exposed paddle that must be soldered to the PCB but left

P1.0/ADC0/T2 1 56 I Input Port 1 (P1.0). Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults

I I

P1.1/ADC1/T2EX 2 1 I

I I

P1.2/ADC2 3 2 I

I P1.3/ADC3 4 3 I

I AV

5 4, 5 P Analog Positive Supply Voltage, 3 V or 5 V Nominal.

DD

AGND 6 6, 7, 8 G C

7 9 I/O Decoupling Input for On-Chip Reference. Connect 0.1 F between this pin and AGND.

REF

unconnected.

to analog input mode. To configure any Port 1 pin as a digital input, write a 0 to the Port 1 bit. Port 1 pins are multifunctional and share the following functionality.

Single-Ended Analog Input (ADC0). Channel selection is via ADCCON2 SFR. Timer/Counter 2 Digital Input (T2). When enabled, Counter 2 is incremented in

response to a 1-to-0 transition of the T2 input.

Input Port 1 (P1.1). Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults to analog input mode. To configure any Port 1 pin as a digital input, write a 0 to the Port 1 bit. Port 1 pins are multifunctional and share the following functionality.

Single-Ended Analog Input (ADC1). Channel selection is via ADCCON2 SFR. Digital Input (T2EX). Capture/Reload trigger for Counter 2; also functions as an

up/down control input for Counter 2. Input Port 1 (P1.2). Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults

to analog input mode. To configure any Port 1 pin as a digital input, write a 0 to the Port 1 bit. Port 1 pins are multifunctional and share the following functionality.

Single-Ended Analog Input (ADC2). Channel selection is via ADCCON2 SFR. Input Port 1 (P1.3). Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults

to analog input mode. To configure any Port 1 pin as a digital input, write a 0 to the Port 1 bit. Port 1 pins are multifunctional and share the following functionality.

Single-Ended Analog Input (ADC3). Channel selection is via ADCCON2 SFR.

Analog Ground. Ground reference point for the analog circuitry.

Rev. A | Page 21 of 92

ADuC832

Pin No. Mnemonic MQFP LFCSP Type Description

V

8 10 I/O Reference Input/Output. This pin is connected to the internal reference through a

REF

DAC0 9 11 O Voltage Output from DAC0. DAC1 10 12 O Voltage Output from DAC1. P1.4/ADC4 11 13 I Input Port 1 (P1.4). Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults

I Single-Ended Analog Input (ADC4). Channel selection is via ADCCON2 SFR. P1.5/ADC5/SS

I Single-Ended Analog Input (ADC5). Channel selection is via ADCCON2 SFR. I P1.6/ADC6 13 15 I Input Port 1 (P1.6). Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults

I Single-Ended Analog Input (ADC6). Channel selection is via ADCCON2 SFR. P1.7/ADC7 14 16 I

I Single-Ended Analog Input (ADC7). Channel selection is via ADCCON2 SFR. RESET 15 17 I Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is

P3.0/RxD 16 18 I/O Input/Output Port 3 (P3.0). Port 3 is a bidirectional port with internal pull-up resistors.

I Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial

P3.1/TxD 17 19 I/O Input/Output Port 3 (P3.1). Port 3 is a bidirectional port with internal pull-up resistors.

O Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial

INT0

P3.2/

I

P3.3/

I

I/O SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface (MISO). O PWM1 Voltage Output (PWM1). See the ADuC832 Configuration SFR (CFG832) section

DVDD 20, 34,

DGND 21, 35,

INT1

/MISO/PWM1

12 14 I Input Port 1 (P1.5). Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults

18 20 I Input/Output Port 3 (P3.2). Port 3 is a bidirectional port with internal pull-up resistors.

19 21 I Input/Output Port 3 (P3.3). Port 3 is a bidirectional port with internal pull-up resistors.

48

47

22, 36, 51

23, 37, 38, 50

P Digital Positive Supply Voltage, 3 V or 5 V Nominal.

G Digital Ground. Ground reference point for the digital circuitry.

series resistor and is the reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V, which appears at the pin. See the Voltage Reference Connections section on how to connect an external reference.

to analog input mode. To configure any Port 1 pin as a digital input, write a 0 to the Port 1 bit. Port 1 pins are multifunctional and share the following functionality.

to analog input mode. To configure any of these Port Pins as a digital input, write a 0 to the port bit. Port 1 pins are multifunction and share the following functionality.

Slave Select Input for the SPI Interface (

to analog input mode. To configure any Port 1 pin as a digital input, write a 0 to the Port 1 bit. Port 1 pins are multifunctional and share the following functionality.

SS

).

Input Port 1 (P1.7). Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults to Analog Input mode. To configure any Port 1 pin as a digital input, write a 0 to the Port 1 bit. Port 1 pins are multifunctional and share the following functionality.

running resets the device.

Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low sources current because of the internal pull-up resistors.

(UART) Port (RxD).

Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low sources current because of the internal pull-up resistors.

(UART) Port (TxD).

Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low sources current because of the internal pull-up resistors.

Interrupt 0 ( programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 0.

Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low sources current because of the internal pull-up resistors.

Interrupt 1 ( programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 1.

for further information.

INT0

). This programmable edge or level triggered interrupt input can be

INT1

). This programmable edge or level triggered interrupt input can be

Rev. A | Page 22 of 92

ADuC832

Pin No. Mnemonic MQFP LFCSP Type Description

P3.4/T0/PWMC/PWM0/EXTCLK 22 24 I/O Input/Output Port 3 (P3.4). Port 3 is a bidirectional port with internal pull-up resistors.

I Timer/Counter 0 Input (T0). I PWM Clock Input (PWMC). O PWM0 Voltage Output (PWM0). PWM outputs can be configured to uses

I Input for External Clock Signal (EXTCLK). This pin must be enabled via the CFG832

CONVST

P3.5/T1/

I Timer/Counter 1 Input (T1). I Active Low Convert Start Logic Input for the ADC Block When the External Convert

P3.6/WR

O

P3.7/RD

O SCLOCK 26 28 I/O Serial Clock Pin for I2C-Compatible or SPI Serial Interface Clock. SDATA/MOSI 27 29 I/O User Selectable, I2C-Compatible or SPI Data Input/Output Pin (SDATA).

I/O SPI Master Output/Slave Input Data I/O Pin for SPI Interface (MOSI). P2.0/A8/A16 28 30 I/O Input/Output Port 2 (P2.0). Port 2 is a bidirectional port with internal pull-up resistors.

I/O External Memory Addresses (A8/A16). Port 2 emits the high order address bytes

P2.1/A9/A17 29 31 I/O Input/Output Port 2 (P2.1). Port 2 is a bidirectional port with internal pull-up resistors.

I/O External Memory Addresses (A9/A17). Port 2 emits the high order address bytes

P2.2/A10/A18 30 32 I/O Input/Output Port 2 (P2.2). Port 2 is a bidirectional port with internal pull-up resistors.

I/O External Memory Addresses (A10/A18). Port 2 emits the high order address bytes

P2.3/A11/A19 31 33 I/O Input/Output Port 2 (P2.3). Port 2 is a bidirectional port with internal pull-up resistors.

I/O External Memory Addresses (A11/A19). Port 2 emits the high order address bytes

XTAL1 32 34 I Input to the Inverting Oscillator Amplifier.

23 25 I/O Input/Output Port 3 (P3.5). Port 3 is a bidirectional port with internal pull-up resistors.

24 26 I/O Input/Output Port 3 (P3.6). Port 3 is a bidirectional port with internal pull-up resistors.

25 27 O Input/Output Port 3 (P3.7). Port 3 is a bidirectional port with internal pull-up resistors.

Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low sources current because of the internal pull-up resistors.

Port 2.6 and Port 2.7, or Port 3.4 and Port 3.3.

register.

Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low sources current because of the internal pull-up resistors.

CONVST

Start Function is Enabled ( track-and-hold into its hold mode and starts conversion.

Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low sources current because of the internal pull-up resistors.

Write Control Signal, Logic Output ( external data memory.

Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low sources current because of the internal pull-up resistors.

Read Control Signal, Logic Output (

Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors.

during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors.

during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors.

during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors.

during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

Rev. A | Page 23 of 92

). A low-to-high transition on this input puts the

WR

). Latches the data byte from Port 0 into the

RD

). Enables the external data memory to Port 0.

ADuC832

Pin No. Mnemonic MQFP LFCSP Type Description

XTAL2 33 35 O Output of the Inverting Oscillator Amplifier. P2.4/A12/A20 36 39 I/O Input/Output Port 2 (P2.4). Port 2 is a bidirectional port with internal pull-up resistors.

I/O External Memory Addresses (A12/A20). Port 2 emits the high order address bytes

P2.5/A13/A21 37 40 I/O Input/Output Port 2 (P2.5). Port 2 is a bidirectional port with internal pull-up resistors.

I/O External Memory Addresses (A13/A21). Port 2 emits the high order address bytes

P2.6/PWM0/A14/A22 38 41 I/O Input/Output Port 2 (P2.6). Port 2 is a bidirectional port with internal pull-up resistors.

O PWM0 Voltage Output (PWM0). PWM outputs can be configured to use Port 2.6 and

I/O External Memory Addresses (A14/A22). Port 2 emits the high order address bytes

P2.7/PWM1/A15/A23 39 42 I/O Input/Output Port 2 (P2.7). Port 2 is a bidirectional port with internal pull-up resistors.

O PWM1 Voltage Output (PWM1). See the ADuC832 Configuration SFR (CFG832) section

I/O External Memory Addresses (A15/A23). Port 2 emits the high order address bytes

EA

PSEN

ALE 42 45 O Address Latch Enable, Logic Output. This output is used to latch the low byte (and

P0.0/AD0 43 46 I/O Input/Output Port 0 (P0.0). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0

I/O External Memory Address and Data (AD0). Port 0 is also the multiplexed low order

P0.1/AD1 44 47 I/O Input/Output Port 0 (P0.1). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0

I/O External Memory Address and Data (AD1). Port 0 is also the multiplexed low order

40 43 I External Access Enable, Logic Input. When held high, this input enables the device to

41 44 O Program Store Enable, Logic Output. This output is a control signal that enables the

Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors.

during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors.

during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors.

Port 2.7 or Port 3.4 and Port 3.3

during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low sources current because of the internal pull-up resistors.

for further information.

during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.

fetch code from internal program memory locations 0000H to 1FFFH. When held low, this input enables the device to fetch all instructions from external program memory. This pin should not be left floating.

external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. serial download mode when pulled low through a resistor on power-up or reset.

page byte for 24-bit address space accesses) of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access.

pins that have 1s written to them float and in that state can be used as high impedance inputs.

address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-ups when emitting 1s.

pins that have 1s written to them float and in that state can be used as high impedance inputs.

address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-ups when emitting 1s.

PSEN

can also be used to enable

Rev. A | Page 24 of 92

ADuC832

Pin No. Mnemonic MQFP LFCSP Type Description

P0.2/AD2 45 48 I/O Input/Output Port 0 (P0.2). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0

External Memory Address and Data (AD2). Port 0 is also the multiplexed low order

P0.3/AD3 46 49 I/O Input/Output Port 0 (P0.3). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0

I/O External Memory Address and Data (AD3). Port 0 is also the multiplexed low order

P0.4/AD4 49 52 I/O Input/Output Port 0 (P0.4). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0

I/O External Memory Address and Data (AD4). Port 0 is also the multiplexed low order

P0.5/AD5 50 53 I/O Input/Output Port 0 (P0.5). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0

I/O External Memory Address and Data (AD5). Port 0 is also the multiplexed low order

P0.6/AD6 51 54 I/O Input/Output Port 0 (P0.6). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0

I/O External Memory Address and Data (AD6). Port 0 is also the multiplexed low order

P0.7/AD7 52 56 I/O Input/Output Port 0 (P0.7). Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0

External Memory Address and Data (AD7). Port 0 is also the multiplexed low order