Analog Devices ADuC832 Datasheet

MicroConverter®, 12-Bit ADCs and DACs

with Embedded 62 kBytes Flash MCU

ADuC832

FEATURES
ANALOG I/O

8-Channel, 247 kSPS 12-Bit ADC

DC Performance: 1 LSB INL

AC Performance: 71 dB SNR
DMA Controller for High Speed ADC-to-RAM Capture
2 12-Bit (Monotonic) Voltage Output DACs
Dual Output PWM/- DACs
On-Chip Temperature Sensor Function 3C
On-Chip Voltage Reference

Memory

62 kBytes On-Chip Flash/EE Program Memory
4 kBytes On-Chip Flash/EE Data Memory
Flash/EE, 100 Yr Retention, 100 kCycles Endurance
2304 Bytes On-Chip Data RAM

8051-Based Core

8051 Compatible Instruction Set (16 MHz Max)
32 kHz Ext Crystal, On-Chip Programmable PLL
12 Interrupt Sources, 2 Priority Levels
Dual Data Pointer
Extended 11-Bit Stack Pointer

On-Chip Peripherals

Time Interval Counter (TIC)
UART, I

2C®

, and SPI® Serial I/O

Watchdog Timer (WDT), Power Supply Monitor (PSM)

Power

Specified for 3 V and 5 V Operation
Normal, Idle, and Power-Down Modes
Power-Down: 25 A @ 3 V with Wake-Up cct Running

APPLICATIONS
Optical Networking—Laser Power Control
Base Station Systems
Precision Instrumentation, Smart Sensors
Transient Capture Systems
DAS and Communications Systems

Upgrade to ADuC812 Systems. Runs from 32 kHz
External Crystal with On-Chip PLL.

Also Available: ADuC831 Pin Compatible Upgrade to
Existing ADuC812 Systems that Require Additional
Code or Data Memory. Runs from 1 MHz–16 MHz
External Crystal.

MicroConverter is a registered trademark and QuickStart is a trademark
of Analog Devices, Inc.
SPI is a registered trademark of Motorola, Inc.
I2C is a registered trademark of Philips Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

FUNCTIONAL BLOCK DIAGRAM

12-BIT

DAC

12-BIT

DAC

16-BIT

– DAC

16-BIT

– DAC

16-BIT

PWM

16-BIT

PWM

PERIPHERALS

2304 BYTES USER RAM

POWER SUPPLY MON

WATCHDOG TIMER

UART, I

SERIAL I/O

BUF

BUF

2

C, AND SPI

DAC

DAC

PWM0

MUX

PWM1

ADC0

ADC1

ADC5

ADC6
ADC7

MUX

TEMP

SENSOR

INTERNAL

BAND GAP

VREF

V

REF

ADuC832

T/H

PLL

OSC

12-BIT ADC

HARDWARE

CALIBRATON

8051-BASED MCU WITH ADDITIONAL

62 kBYTES FLASH/EE PROGRAM MEMORY

4 kBYTES FLASH/EE DATA MEMORY

3  16 BIT TIMERS

1  REAL TIME CLOCK

4 PARALLEL

PORTS

XTAL2XTAL1

GENERAL DESCRIPTION

The ADuC832 is a complete smart transducer front end, integrat­ing a high performance self-calibrating multichannel 12-bit ADC,
dual 12-bit DACs, and programmable 8-bit MCU on a single chip.

The device operates from a 32 kHz crystal with an on-chip PLL
generating a high frequency clock of 16.77 MHz. This clock is, in
turn, routed through a programmable clock divider from which
the MCU core clock operating frequency is generated. The micro­controller core is an 8052 and therefore 8051 instruction set
compatible with 12 core clock periods per machine cycle. 62 kBytes
of nonvolatile Flash/EE program memory are provided on-chip.
4 kBytes of nonvolatile Flash/EE data memory, 256 bytes RAM,
and 2 kBytes of extended RAM are also integrated on-chip.

The ADuC832 also incorporates additional analog functionality
with two 12-bit DACs, power supply monitor, and a band gap
reference. On-chip digital peripherals include two 16-bit -
DACs, dual output 16-bit PWM, watchdog timer, time interval
counter, three timers/counters, Timer 3 for baud rate generation,
and serial I/O ports (SPI, I

2

C, and UART)

On-chip factory firmware supports in-circuit serial download and
debug modes (via UART) as well as single-pin emulation mode
via the EA pin. The ADuC832 is supported by QuickStart™ and
QuickStart Plus development systems featuring low cost software
and hardware development tools. A functional block diagram of
the ADuC832 is shown above with a more detailed block diagram
shown in Figure 1.

The part is specified for 3 V and 5 V operation over the extended
industrial temperature range and is available in a 52-lead plastic
quad flatpack package and a 56-lead chip scale package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002. All rights reserved.

ADuC832

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . 7

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . 9

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

TYPICAL PERFORMANCE CHARACTERISTICS . . 11

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . 14

OVERVIEW OF MCU-RELATED SFRS . . . . . . . . . . 15

Accumulator SFR (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . 15

B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Stack Pointer SFR (SP AND SPH) . . . . . . . . . . . . . . . . . 15

Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program Status Word SFR (PSW) . . . . . . . . . . . . . . . . . . 16

Power Control SFR (PCON) . . . . . . . . . . . . . . . . . . . . . . 16

SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . 17

ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . 18

General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Typical Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ADCCON1 – (ADC Control SFR #1) . . . . . . . . . . . . . . 19

ADCCON2 – (ADC Control SFR #2) . . . . . . . . . . . . . . 20

ADCCON3 – (ADC Control SFR #3) . . . . . . . . . . . . . . 21

Driving the A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . 22

Voltage Reference Connections . . . . . . . . . . . . . . . . . . . . 23

Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

ADC DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Micro Operation during ADC DMA Mode . . . . . . . . . . . 25

ADC Offset and Gain Calibration Coefficients . . . . . . . . 25

Calibrating the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

NONVOLATILE FLASH MEMORY . . . . . . . . . . . . . . 27

Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . 27

Flash/EE Memory and the ADuC832 . . . . . . . . . . . . . . . 27

ADuC832 Flash/EE Memory Reliability . . . . . . . . . . . . . 27

Using the Flash/EE Program Memory . . . . . . . . . . . . . . . 28

ULOAD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Flash/EE Program Memory Security . . . . . . . . . . . . . . . . 28

Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . 29

ECON—Flash/EE Memory Control SFR . . . . . . . . . . . . 29

Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . 30

ADuC832 CONFIGURATION REGISTER (CFG832) . 31

USER INTERFACE TO OTHER ON-CHIP

ADuC832 PERIPHERALS . . . . . . . . . . . . . . . . . . . . . 32

Using the DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

On-Chip PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pulsewidth Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . 36

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . 39

2

C Compatible Interface . . . . . . . . . . . . . . . . . . . . . . . . . 41

I

Dual Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Timer Interval Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8052 COMPATIBLE ON-CHIP PERIPHERALS . . . . 48

Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

UART Serial Port Control Register . . . . . . . . . . . . . . . . . 56

UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . 57

UART Serial Port Baud Rate Generation . . . . . . . . . . . . 57

Timer 1 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . 58

Timer 2 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . 58

Timer 3 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . 59

Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

ADuC832 HARDWARE DESIGN CONSIDERATIONS . 61

Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . 62

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Grounding and Board Layout Recommendations . . . . . . 64

OTHER HARDWARE CONSIDERATIONS . . . . . . . . 65

In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . 65

Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . 66

Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . 66

Typical System Configuration . . . . . . . . . . . . . . . . . . . . . 66

DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . 66

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 67

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 77

REV. 0–2–

ADuC832

(AVDD = DV

1

SPECIFICATIONS

all specifications TA = T

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

DC ACCURACY

2, 3

Resolution 12 12 Bits
Integral Nonlinearity ±1 ±1LSB max 2.5 V Internal Reference

Differential Nonlinearity ±0.9 ±0.9 LSB max 2.5 V Internal Reference

Integral Nonlinearity
Differential Nonlinearity

4

4

Code Distribution 1 1 LSB typ ADC Input is a DC Voltage

CALIBRATED ENDPOINT ERRORS

5, 6

Offset Error ±4 ± 4LSB max
Offset Error Match ±1 ± 1LSB typ
Gain Error ±2 ± 3LSB max
Gain Error Match –85 –85 dB typ

DYNAMIC PERFORMANCE f

Signal-to-Noise Ratio (SNR)

7

Total Harmonic Distortion (THD) –85 –85 dB typ
Peak Harmonic or Spurious Noise –85 –85 dB typ
Channel-to-Channel Crosstalk

8

ANALOG INPUT

Input Voltage Ranges 0 to V
Leakage Current ±1 ± 1 µA max
Input Capacitance 32 32 pF typ

TEMPERATURE SENSOR

9

Voltage Output at 25°C 650 650 mV typ
Voltage TC –2.0 –2.0 mV/°C typ
Accuracy ±3 ± 3 °C typ Internal 2.5 V V

DAC CHANNEL SPECIFICATIONS DAC Load to AGND

Internal Buffer Enabled RL = 10 kΩ, CL = 100 pF

DC ACCURACY

10

Resolution 12 12 Bits
Relative Accuracy ±3 ± 3LSB typ
Differential Nonlinearity

11

Offset Error ±50 ± 50 mV max V
Gain Error ±1 ± 1% maxAV

Gain Error Mismatch 0.5 0.5 % typ % of Full-Scale on DAC1

ANALOG OUTPUTS

Voltage Range_0 0 to V
Voltage Range_1 0 to V
Output Impedance 0.5 0.5 Ω typ

DAC AC CHARACTERISTICS

Voltage Output Settling Time 15 15 µs typ Full-Scale Settling Time to

Digital-to-Analog Glitch Energy 10 10 nV sec typ 1 LSB Change at Major Carry

= 2.7 V to 3.3 V or 4.5 V to 5.5 V; V

DD

MIN

to T

, unless otherwise noted.)

MAX

= 2.5 V Internal Reference, F

REF

f

= 147 kHz, see Page 11 for

SAMPLE

=16.78 MHz;

CORE

Typical Performance at other f

±0.3 ±0.3 LSB typ

±0.25 ±0.25 LSB typ
±1.5 ±1.5 LSB max 1 V External Reference

+1.5/–0.9 +1.5/–0.9 LSB max 1 V External Reference

= 10 kHz Sine Wave

IN

= 147 kHz

f

SAMPLE

71 71 dB typ

–80 –80 dB typ

REF

0 to V

REF

±1.5 ±1.5 °C typ External 2.5 V V

V

REF

REF

–1 –1LSB max Guaranteed 12-Bit Monotonic
±1/2 ±1/2 LSB typ

Range

REF

Range

DD

±1 ± 1% typ V

REF

DD

0 to V
0 to V

REF

DD

V typ DAC V
V typ DAC V

REF

Range

REF

REF

= 2.5 V
= V

DD

within 1/2 LSB of Final Value

SAMPLE

REV. 0 –3–

ADuC832

SPECIFICATIONS

(continued)

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments

DAC CHANNEL SPECIFICATIONS

12, 13

Internal Buffer Disabled

DC ACCURACY

10

Resolution 12 12 Bits
Relative Accuracy ±3 ± 3LSB typ
Differential Nonlinearity

11

–1 –1LSB max Guaranteed 12-Bit Monotonic
±1/2 ±1/2 LSB typ

Offset Error ±5 ± 5 mV max V
Gain Error –0.3 –0.3 % typ V
Gain Error Mismatch

4

0.5 0.5 % max % of Full-Scale on DAC1

REF

REF

Range
Range

ANALOG OUTPUTS

Voltage Range_0 0 to V

REFERENCE INPUT/OUTPUT

REFERENCE OUTPUT
Output Voltage (V

14

) 2.5 2.5 V

REF

REF

Accuracy ±2.5 ±2.5 % max Of V

0 to V

REF

V typ DAC V

REF

= 2.5 V

REF

Measured at the C

REF

Power Supply Rejection 47 57 dB typ
Reference Temperature Coefficient ±100 ±100 ppm/°C typ
Internal V

EXTERNAL REFERENCE INPUT

Voltage Range (V

Power-On Time 80 80 ms typ

REF

15

4

REF

)

0.1 0.1 V min
V

DD

V

DD

V max

V

REF

and C

Pins Shorted

REF

Input Impedance 20 20 kΩ typ
Input Leakage 1 1 µA max Internal Band Gap Deselected via

ADCCON1.6

POWER SUPPLY MONITOR (PSM)

DVDD Trip Point Selection Range 2.63 V min Four Trip Points Selectable in

4.37 V max This Range Programmed via
TPD1–0 in PSMCON

DVDD Power Supply Trip Point Accuracy ±3.5 % max

WATCHDOG TIMER (WDT)

4

Timeout Period 0 0 ms min Nine Timeout Periods

2000 2000 ms max Selectable in this Range

FLASH/EE MEMORY RELIABILITY
CHARACTERISTICS

Endurance

17

Data Retention

DIGITAL INPUTS

Input High Voltage (V
Input Low Voltage (V
Input Leakage Current (Port 0, EA) ±10 ±10 µA max V

16

18

4

)

INH

4

)

INL

100,000 100,000 Cycles min
100 100 Years min

2.4 2 V min

0.8 0.4 V max

= 0 V or V

IN

±1 ± 1 µA typ VIN = 0 V or V

DD

DD

Logic 1 Input Current

(All Digital Inputs) ±10 ±10 µA max V

±1 ± 1 µA typ VIN = V

IN

= V

DD

DD

Logic 0 Input Current (Port 1, 2, 3) –75 –25 µA max

–40 –15 µA typ V

Logic 1–0 Transition Current (Port 2, 3) –660 –250 µA max V

= 450 mV

IL

= 2 V

IL

–400 –140 µA typ VIL = 2 V

Pin

REV. 0–4–

ADuC832

Parameter V

SCLOCK and RESET Only

4

= 5 V V

DD

= 3 V Unit Test Conditions/Comments

DD

(Schmitt-Triggered Inputs)

V

T+

1.3 0.95 V min

3.0 2.5 V max

V

T–

0.8 0.4 V min

1.4 1.1 V max

– V

V

T+

T–

0.3 0.3 V min

0.85 0.85 V max

CRYSTAL OSCILLATOR

Logic Inputs, XTAL1 Only

, Input Low Voltage 0.8 0.4 V typ

V

INL

, Input High Voltage 3.5 2.5 V typ

V

INH

XTAL1 Input Capacitance 18 18 pF typ
XTAL2 Output Capacitance 18 18 pF typ

MCU CLOCK RATE 16.78 16.78 MHz max Programmable via PLLCON

DIGITAL OUTPUTS

Output High Voltage (V

Output Low Voltage (V

ALE, Ports 0 and 2 0.4 0.4 V max I

Port 3 0.4 0.4 V max I
SCLOCK/SDATA 0.4 0.4 V max I

Floating State Leakage Current

) 2.4 V min VDD = 4.5 V to 5.5 V

OL

OH

)

4

4.0 V typ I

2.4 V min V

2.6 V typ I

0.2 0.2 V typ I

±10 ± 10 µA max

= 80 µA

SOURCE

= 2.7 V to 3.3 V

DD

= 20 µA

SOURCE

= 1.6 mA

SINK

= 1.6 mA

SINK

= 4 mA

SINK

= 8 mA, I2C Enabled

SINK

±1 ± 1 µA typ

Floating State Output Capacitance 10 10 pF typ

START UP TIME At any Core CLK

At Power-On 500 500 ms typ
From Idle Mode 100 100 µs typ
From Power-Down Mode

Wakeup with INT0 Interrupt 150 400 µs typ
Wakeup with SPI/I

2

C Interrupt 150 400 µs typ

Wakeup with External RESET 150 400 µs typ
After External RESET in Normal Mode 30 30 ms typ
After WDT Reset in Normal Mode 3 3 ms typ Controlled via WDCON SFR

REV. 0

–5–

ADuC832

SPECIFICATIONS

Parameter V

POWER REQUIREMENTS

(continued)

19, 20

= 5 V V

DD

= 3 V Unit Test Conditions/Comments

DD

Power Supply Voltages

/DV

AV

DD

– AGND 2.7 V min AVDD/DVDD = 3 V nom

DD

3.3 V max

4.5 V min AV

/DVDD = 5 V nom

DD

5.5 V max

Power Supply Currents Normal Mode

Current

DV

DD

Current 1.7 1.7 mA max Core CLK = 2.097 MHz

AV

DD

Current 23 12 mA max Core CLK = 16.78 MHz

DV

DD

4

63mA max Core CLK = 2.097 MHz

20 10 mA typ Core CLK = 16.78 MHz

Current 1.7 1.7 mA max Core CLK = 16.78 MHz

AV

DD

Power Supply Currents Idle Mode

Current 4 2 mA typ Core CLK = 2.097 MHz

DV

DD

Current 0.14 0.14 mA typ Core CLK = 2.097 MHz

AV
DV

DD

Current

DD

4

10 5 mA max Core CLK = 16.78 MHz
94mA typ Core CLK = 16.78 MHz

Current 0.14 0.14 mA typ Core CLK = 16.78 MHz

AV

DD

Power Supply Currents Power-Down Mode Core CLK = 2.097 MHz or 16.78 MHz

Current

DV

DD

4

80 25 µA max Osc. On
38 14 µA typ

Current 2 1 µA typ

AV

DD

Current 35 20 µA max Osc. Off

DV

DD

25 12 µA typ

Typical Additional Power Supply Currents AV

= DVDD = 5 V

DD

PSM Peripheral 50 µA typ
ADC 1.5 mA typ
DAC 150 µA typ

NOTES

1

Temperature Range –40ºC to +125ºC.

2

ADC linearity is guaranteed during normal MicroConverter core operation.

3

ADC LSB Size = V

4

These numbers are not production tested but are guaranteed by design and/or characterization data on production release.

5

Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.

6

Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these
specifications.

7

SNR calculation includes distortion and noise components.

8

Channel-to-channel crosstalk is measured on adjacent channels.

9

The Temperature Monitor will give a measure of the die temperature directly; air temperature can be inferred from this result.

10

DAC linearity is calculated using:

Reduced code range of 100 to 4095, 0 to V
Reduced code range of 100 to 3945, 0 to VDD range.
DAC Output Load = 10 kΩ and 100 pF.

11

DAC differential nonlinearity specified on 0 to V

12

DAC specification for output impedance in the unbuffered case depends on DAC code.

13

DAC specifications for I
unbuffered mode tested with OP270 external buffer, which has a low input leakage current.

14

Measured with V
decoupling capacitor chosen for both the V

15

When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the V
pins need to be shorted together for correct operation.

16

Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.

17

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40ºC, +25ºC, and +125ºC. Typical endurance at 25ºC is 700,000 cycles.

18

Retention lifetime equivalent at junction temperature (TJ) = 55ºC as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV
will derate with junction temperature as shown in Figure 18 in the Flash/EE Memory description section.

19

Power supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:

Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in

Power-Down Mode: Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed via CD bits in PLLCON,

20

DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.

Specifications subject to change without notice.

/212 i.e., for Internal V

REF

, voltage output settling time and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in

SINK

REF

and C

pins decoupled with 0.1 µF capacitors to ground. Power-up time for the internal reference will be determined by the value of the

REF

idle mode.

PCON.0 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR

= 2.5 V, 1 LSB = 610 µV and for External V

REF

range.

REF

and 0 to VDD ranges.

REF

REF

and C

REF

pins.

= 1 V, 1 LSB = 244 µV.

REF

REF

and C

REF

REV. 0–6–

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

to DGND, AVDD to AGND . . . . . . . . . . –0.3 V to +7 V

DV

DD

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV

to AGND . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

V

REF

+ 0.3 V

DD

+ 0.3 V

DD

Analog Inputs to AGND . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range Industrial

ADuC832BS . . . . . . . . . . . . . . . . . . . . . . .–40°C to +125°C

Operating Temperature Range Industrial

ADuC832BCP . . . . . . . . . . . . . . . . . . . . . . – 40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance (ADuC832BS) . . . . . . . . . . . . 90°C/W



JA

Thermal Impedance (ADuC832BCP) . . . . . . . . . . 52°C/W



JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ADuC832

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADuC832BS –40°C to +125°C 52-Lead Plastic Quad Flatpack S-52
ADuC832BCP –40°C to +85°C 56-Lead Chip Scale Package CP-56
EVAL-ADuC832QS QuickStart Development System
EVAL-ADuC832QSP

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADuC832 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

QuickStart Plus Development System

REV. 0

–7–

ADuC832

PIN CONFIGURATION

P1.0/ADC0/T2

P1.1/ADC1/T2EX

P1.2/ADC2

P1.3/ADC3

AV

AGND

C

REF

V

REF

DAC0
DAC1

P1.4/ADC4

P1.5/ADC5/SS

P1.6/ADC6

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

RESET

P3.0/RxD

DVDDDGND

TOP VIEW

(Not to Scale)

P3.1/TxD

P3.2/INT0

52 51 50 49 48 43 42 41 4047 4 6 45 44

1

PIN 1
IDENTIFIER

2

3

4

5

DD

6

ADuC832 52-LEAD PQFP

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

P1.7/ADC7

P3.3/INT1/MISO/PWM1

ADC0

ADC1

ADC6

...

...

MUX

ADC7

TEMP

SENSOR

BAND GAP

REFERENCE

V

REF

C

REF

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

ALE

PSEN

EA

DD

DV

DGND

P3.6/WR

P3.7/RD

SCLOCK

P3.5/T1/CONVST

P3.4/T0/PWMC/PWM0/EXTCLK

T/H

BUF

POR

39

P2.7/PWM1/A15/A23

38

P2.6/PWM0/A14/A22

37

P2.5/A13/A21

36

P2.4/A12/A20

35

DGND

34

DV

DD

33

XTAL2

32

XTAL1

31

P2.3/A11/A19

30

P2.2/A10/A18

29

P2.1/A9/A17

28

P2.0/A8/A16

27

SDATA/MOSI

12-BIT
ADC

62 kBYTES PROGRAM
FLASH/EE INCLUDING

USER DOWNLOAD MODE

4 kBYTES DATA

FLASH/EE

2 kBYTES USER XRAM

2 ⴛ DATA POINTERS

11-BIT STACK POINTER

DOWNLOADER

DEBUGGER

ASYNCHRONOUS

SERIAL PORT

(UART)

P1.1/ADC1/T2EX

P1.5/ADC5/SS

ADuC832

ADC

CONTROL

AND

CALIBRATION

UART

TIMER

P1.2/ADC2

P1.3/ADC3

AV
AV

AGND
AGND

AGND

C

REF

V

REF

DAC0

DAC1

P1.4/ADC4

8052

MCU

CORE

1
2

3

4

DD

5

DD

6

7
8

9

10

11

12

13
14

DAC

CONTROL

SERIAL INTERFACE

EMULATOR

SINGLE-PIN

DD

P0.4/AD4

P0.3/AD3

DV

P0.5/AD5

51

52

53

TOP VIEW

(Not to Scale)

20

P3.1/TxD

P3.0/RxD

P3.2/INT0

VOLTAGE

OUTPUT DAC

VOLTAGE

OUTPUT DAC

12-BIT

12-BIT

DGND

49

50

21222324252627

DV

P3.3/INT1/MISO/PWM1

16-BIT

⌺-⌬ DAC

16-BIT

⌺-⌬ DAC

16-BIT

P1.0/ADC0/T2

P0.7/AD7

P0.6/AD6

54

55

56

PIN 1
IDENTIFIER

ADuC832 56-LEAD CSP

1516171819

RESET

P.7/ADC7

P1.6/ADC6

PWM

CONTROL

16-BIT

256 BYTES
USER RAM

WATCHDOG

TIMER

POWER SUPPLY

MONITOR

TIME INTERVAL

COUNTER

(WAKEUP CCT)

SYNCHRONOUS

2

C )

(SPI OR I

P0.2/AD2

P0.1/AD1

P0.0/AD0

EA

ALE

PSEN

43

45

46

47

48

DD

DGND

44

42
41

40

39

38
37
36

35
34

33

32
31
30
29

28

P3.7/RD

P3.6/WR

SCLOCK

P3.5/T1/CONVST

P3.4/T0/PWMC/PWM0/EXTCLK

MUX

PWM

PWM

16-BIT

COUNTER

TIMERS

PROG. CLOCK

DIVIDER

PLL

OSC

P2.7/PWM1/A15/A23

P2.6/PWM0/A14/A22

P2.5/A13/A21

P2.4/A12/A20
DGND

DGND

DV

DD

XTAL2
XTAL1

P2.3/A11/A19

P2.2/A10/A18

P2.1/A9/A17

P2.0/A8/A16

SDATA/MOSI

DAC0

DAC1

PWM0

PWM1

T0

T1

T2

T2EX

INT0

INT1

DD

AV

AGND

DV

DDDVDDDVDD

DGND

DGND

DGND

RESET

RxD

TxD

ALE

EA

PSEN

SCLOCK

MISO

SS

XTAL1

XTAL2

SDATA/MOSI

Figure 1. ADuC832 Block Diagram (Shaded Areas are Features Not Present on the ADuC812)

REV. 0–8–

ADuC832

PIN FUNCTION DESCRIPTIONS

Mnemonic Type Function

DV

DD

AV

DD

C

REF

V

REF

AGND G Analog Ground. Ground reference point for the analog circuitry.
P1.0–P1.7 I Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults to Analog Input mode. To configure

ADC0–ADC7 I Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.
T2 I Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response to a

T2EX I Digital Input. Capture/Reload trigger for Counter 2; also functions as an Up/Down control input for

SS I Slave Select Input for the SPI Interface
SDATA I/O User Selectable, I
SCLOCK I/O Serial Clock Pin for I
MOSI I/O SPI Master Output/Slave Input Data I/O Pin for SPI Interface
MISO I/O SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface
DAC0 O Voltage Output from DAC0
DAC1 O Voltage Output from DAC1
RESET I Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the device.
P3.0–P3.7 I/O Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are

PWMC I PWM Clock Input
PWM0 O PWM0 Voltage Output. PWM outputs can be configured to uses ports 2.6 and 2.7 or 3.4 and 3.3
PWM1 O PWM1 Voltage Output. See CFG832 Register for further information.
RxD I/O Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port
TxD O Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port

INT0 I Interrupt 0, programmable edge or level triggered Interrupt input, can be programmed to one of two priority

INT1 I Interrupt 1, programmable edge or level triggered Interrupt input, can be programmed to one of two priority

T0 I Timer/Counter 0 Input
T1 I Timer/Counter 1 Input
CONVST I Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is enabled.

EXTCLK I Input for External Clock Signal; has to be enabled via CFG832 Register.

WR OWrite Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
RD ORead Control Signal, Logic Output. Enables the external data memory to Port 0.

XTAL2 O Output of the Inverting Oscillator Amplifier
XTAL1 I Input to the Inverting Oscillator Amplifier
DGND G Digital Ground. Ground reference point for the digital circuitry.
P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are

(A8–A15) pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2
(A16–A23) pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the

PDigital Positive Supply Voltage, 3 V or 5 V Nominal
PAnalog Positive Supply Voltage, 3 V or 5 V Nominal
I/O Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND.
I/O Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V, which
appears at the pin. See ADC section on how to connect an external reference.

any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share
the following functionality.

1-to-0 transition of the T2 input.

Counter 2.

2

C Compatible or SPI Data Input/Output Pin

2

C Compatible or SPI Serial Interface Clock

pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins
being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also
contain various secondary functions that are described below.

levels. This pin can also be used as a gate control input to Timer 0.

levels. This pin can also be used as a gate control input to Timer 1.

A low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion.

high order address bytes during fetches from external program memory and middle and high order address
bytes during accesses to the external 24-bit external data memory space.

REV. 0

–9–

ADuC832

PIN FUNCTION DESCRIPTIONS (continued)

Mnemonic Type Function

PSEN OProgram Store Enable, Logic Output. This output is a control signal that enables the external program

memory to the bus during external fetch operations. It is active every six oscillator periods except during
external data memory accesses. This pin remains high during internal program execution. PSEN can also be
used to enable serial download mode when pulled low through a resistor on power-up or RESET.

ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit

address space accesses) of the address into external memory during normal operation. It is activated every
six oscillator periods except during an external data memory access.

EA IExternal Access Enable, Logic Input. When held high, this input enables the device to fetch code from

internal program memory locations 0000H to 1FFFH. When held low, this input enables the device to fetch
all instructions from external program memory. This pin should not be left floating.

P0.7–P0.0 I/O Port 0 is an 8-Bit Open-Drain Bidirectional I/O Port. Port 0 pins that have 1s written to them float and in
(A0–A7) that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data

bus during accesses to external program or data memory. In this application it uses strong internal pull-ups
when emitting 1s.

TERMINOLOGY
ADC SPECIFICATIONS

Integral Nonlinearity

This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point
1/2 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.

Gain Error

This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has
been adjusted out.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental sig­nals up to half the sampling frequency (f

/2), excluding dc. The

S

ratio is dependent upon the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:

Signal to(Noise Distortion)= (6.02N + 1.76) dB+

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.

DAC SPECIFICATIONS
Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error.

Voltage Output Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV sec.

REV. 0–10–

Typical Performance Characteristics–ADuC832

The typical performance plots presented in this section illustrate
typical performance of the ADuC832 under various operating
conditions.

TPC 1 and TPC 2 show typical ADC Integral Nonlinearity
(INL) errors from ADC code 0 to code 4095 at 5 V and 3 V
supplies, respectively. The ADC is using its internal reference
(2.5 V) and operating at a sampling rate of 152 kHz and the
typically worst case errors in both plots are just less than 0.3 LSBs.

TPC 3 and TPC 4 show the variation in worst case positive
(WCP) INL and worst case negative (WCN) INL versus external
reference input voltage.

TPC 5 and TPC 6 show typical ADC differential nonlinearity
(DNL) errors from ADC code 0 to code 4095 at 5 V and 3 V
supplies, respectively. The ADC is using its internal reference
(2.5 V) and operating at a sampling rate of 152 kHz and the
typically worst case errors in both plots is just less than 0.2 LSBs.

TPC 7 and TPC 8 show the variation in worst case positive
(WCP) DNL and worst case negative (WCN) DNL versus
external reference input voltage.

TPC 9 shows a histogram plot of 10,000 ADC conversion results
on a dc input with V

= 5 V. The plot illustrates an excellent

DD

code distribution pointing to the low noise performance of the
on-chip precision ADC.

TPC 10 shows a histogram plot of 10,000 ADC conversion
results on a dc input for V

= 3 V. The plot again illustrates a

DD

very tight code distribution of 1 LSB with the majority of codes
appearing in one output pin.

TPC 11 and TPC 12 show typical FFT plots for the ADuC832.
These plots were generated using an external clock input. The
ADC is using its internal reference (2.5 V) sampling a full-scale,
10 kHz sine wave test tone input at a sampling rate of 149.79 kHz.
The resultant FFTs shown at 5 V and 3 V supplies illustrate an
excellent 100 dB noise floor, 71 dB Signal-to-Noise Ratio (SNR)
and THD greater than –80 dB.

TPC 13 and TPC 14 show typical dynamic performance versus
external reference voltages. Again, excellent ac performance can
be observed in both plots with some roll-off being observed as
V

falls below 1 V.

REF

TPC 15 shows typical dynamic performance versus sampling
frequency. SNR levels of 71 dBs are obtained across the sampling
range of the ADuC832.

TPC 16 shows the voltage output of the on-chip temperature
sensor versus temperature. Although the initial voltage output at
25ºC can vary from part to part, the resulting slope of –2 mV/ºC
is constant across all parts.

1.0

0.8

0.6

0.4

0.2

0

LSBs

–0.2

–0.4

–0.6

–0.8

–1.0

0 511

1023 2047 2559 3071

1535 3583

ADC CODES

TPC 1. Typical INL Error, VDD = 5 V

1.0

0.8

0.6

0.4

0.2

0

LSBs

–0.2

–0.4

–0.6

–0.8

–1.0

511 1023 1535 2047 2559

ADC CODES

AVDD / DVDD = 5V

f

= 152kHz

S

AVDD/DVDD = 3V

f

= 152kHz

S

3071 35830 4095

4095

1.2

1.0

0.8

0.6

0.4

0.2

WCP–INL – LSBs

0

–0.2

–0.4

–0.6

0.5 1.0 1.5 2.0 2.5 5.0
EXTERNAL REFERENCE – V

AVDD/DVDD = 5V

f

= 152kHz

S

WCP INL

WCN INL

TPC 3. Typical Worst Case INL Error vs. V

0.8

0.6

0.4

0.2

0

–0.2

WCP–INL – LSBs

–0.4

–0.6

–0.8

0.5 1.5 2.5
EXTERNAL REFERENCE – V

AVDD/DVDD = 3V

f

= 152kHz

S

WCP INL

WCN INL

, VDD = 5 V

REF

3.02.01.0

0.6

0.4

0.2

0

WCN–INL – LSBs

–0.2

–0.4

–0.6

0.8

0.6

0.4

0.2

0

–0.2

WCN–INL – LSBs

–0.4

–0.6

–0.8

REV. 0

TPC 2. Typical INL Error, VDD = 3 V

TPC 4. Typical Worst Case INL Error vs. V

–11–

, VDD = 3 V

REF

ADuC832

1.0

0.8

0.6

0.4

0.2

0

LSBs

–0.2

–0.4

–0.6

–0.8

–1.0

511 1023 1535 2047 2559

ADC CODES

TPC 5. Typical DNL Error, VDD = 5 V

1.0

0.8

0.6

0.4

0.2

0

LSBs

–0.2

–0.4

–0.6

–0.8

–1.0

511 1023 1535 2047 2559

ADC CODES

TPC 6. Typical DNL Error, VDD = 3 V

AVDD/DVDD = 5V

= 152kHz

f

S

3071 35830 4095

AVDD/DVDD = 3V

f

= 152kHz

S

3071 35830 4095

0.7

0.5

0.3

0.1

–0.1

WCP–DNL – LSBs

–0.3

–0.5

–0.7

0.5 1.0 1.5 2.0 2.5 3.0
EXTERNAL REFERENCE – V

AVDD/DVDD = 3V

f

= 152kHz

S

WCP DNL

WCN DNL

TPC 8. Typical Worst Case DNL Error vs. V

10000

8000

6000

4000

OCCURRENCE

2000

0

817 818 819 820 821

CODE

TPC 9. Code Histogram Plot, VDD = 5 V

, VDD = 3 V

REF

0.7

0.5

0.3

0.1

–0.1

WCN–DNL – LSBs

–0.3

–0.5

–0.7

0.6

0.4

0.2

0

WCP–DNL – LSBs

–0.2

–0.4

–0.6

0.5

1.0 2.0 2.5 5.0

1.5

EXTERNAL REFERENCE – V

AVDD / DVDD = 5V

f

= 152kHz

S

WCP DNL

WCN DNL

TPC 7. Typical Worst Case DNL Error vs. V

, VDD = 5 V

REF

0.6

0.4

0.2

0

–0.2

WCN–DNL – LSBs

–0.4

–0.6

10000

9000

8000

7000

6000

5000

4000

OCCURRENCE

3000

2000

1000

0

817 818 819 820 821

CODE

TPC 10. Code Histogram Plot, VDD = 3 V

REV. 0–12–

ADuC832

20

0

–20

–40

–60

dBs

–80

–100

–120

–140

–160

010

20 40 50 60

30 70

FREQUENCY – kHz

AVDD / DVDD = 5V

f

= 152kHz

S

f

= 9.910kHz

IN

SNR = 71.3dB
THD = –88.0dB
ENOB = 11.6

TPC 11. Dynamic Performance at VDD = 5 V

20

0

–20

–40

–60

dBs

–80

–100

–120

–140

–160

010

20 40 50 60

30 70

FREQUENCY – kHz

AVDD / DVDD = 3V

f

= 149.79kHz

S

f

= 9.910kHz

IN

SNR = 71.0dB
THD = –83.0dB
ENOB = 11.5

80

75

70

65

SNR – dBs

60

55

50

1.0 2.0 3.0

0.5 1.5 2.5
EXTERNAL REFERENCE – V

AVDD/DVDD = 3V

f

= 152kHz

S

SNR

TPC 14. Typical Dynamic Performance vs. V

80

78

76

74

72

70

68

SNR – dBs

66

64

62

60

65.476

92.262

119.05

145.83

FREQUENCY – kHz

AVDD / DVDD = 5V

172.62 199.41 226.19

–70

–75

–80

THD

–85

–90

–95

–100

, VDD = 3 V

REF

THD – dBs

TPC 12. Dynamic Performance at VDD = 3 V

80

75

70

65

SNR – dBs

60

55

50

1.0 2.0 2.5 5.0

0.5

1.5

EXTERNAL REFERENCE – V

AVDD / DVDD = 5V

f

= 152kHz

S

SNR

THD

TPC 13. Typical Dynamic Performance vs. V

–70

–75

–80

–85

–100

, VDD = 5 V

REF

–90

–95

THD – dBs

TPC 15. Typical Dynamic Performance vs.
Sampling Frequency

0.80

AVDD / DVDD = 3V

0.75

SLOPE = 2mV/C

0.70

0.65

0.60

0.55

VOLTAGE – V

0.50

0.45

0.40
–40

–20

TEMPERATURE – C

25 50 85

0

TPC 16. Typical Temperature Sensor Output vs.
Temperature

REV. 0

–13–

ADuC832

MEMORY ORGANIZATION

The ADuC832 contains four different memory blocks:

•

62 kBytes of On-Chip Flash/EE Program Memory

•

4 kBytes of On-Chip Flash/EE Data Memory

•

256 Bytes of General-Purpose RAM

•

2 kBytes of Internal XRAM

Flash/EE Program Memory

The ADuC832 provides 62 kBytes of Flash/EE program memory
to run user code. The user can choose to run code from this
internal memory or from an external program memory.

If the user applies power or resets the device while the EA pin is
pulled low, the part will execute code from the external program
space; otherwise the part defaults to code execution from its
internal 62 kBytes of Flash/EE program memory. Unlike the
ADuC812, where code execution can overflow from the internal
code space to external code space once the PC becomes greater
than 1FFFH, the ADuC832 does not support the rollover from
F7FFH in internal code space to F800H in external code space.
Instead the 2048 bytes between F800H and FFFFH will appear
as NOP instructions to user code.

This internal code space can be downloaded via the UART
serial port while the device is in-circuit. 56 kBytes of the program
memory can be reprogrammed during runtime; thus the code
space can be upgraded in the field using a user defined protocol
or it can be used as a data memory. This will be discussed in
more detail in the Flash/EE Memory section.

Flash/EE Data Memory

4 kBytes of Flash/EE data memory are available to the user
and can be accessed indirectly via a group of control registers
mapped into the Special Function Register (SFR) area. Access
to the Flash/EE data memory is discussed in detail later as part
of the Flash/EE Memory section.

General-Purpose RAM

The general-purpose RAM is divided into two separate memories,
namely the upper and the lower 128 bytes of RAM. The lower
128 bytes of RAM can be accessed through direct or indirect
addressing. The upper 128 bytes of RAM can only be accessed
through indirect addressing as it shares the same address space
as the SFR space, which can only be accessed through direct
addressing.

The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
16 bytes (128 bits), locations 20H through 2FH above the
register banks, form a block of directly addressable bit locations
at bit addresses 00H through 7FH. The stack can be located
anywhere in the internal memory address space, and the stack
depth can be expanded up to 2048 bytes.

Reset initializes the stack pointer to location 07H and increments
it once before loading the stack to start from locations 08H
which is also the first register (R0) of register bank 1. Thus, if one
is going to use more than one register bank, the stack pointer
should be initialized to an area of RAM not used for data storage.

7FH

GENERAL-PURPOSE
AREA

30H

BANKS

SELECTED

VIA

BITS IN PSW

20H

11

18H

10

10H

01

08H

00

00H

2FH

BIT-ADDRESSABLE
(BIT ADDRESSES)

1FH

17H

FOUR BANKS OF EIGHT
REGISTERS

0FH

R0 R7

07H

RESET VALUE OF
STACK POINTER

Figure 2. Lower 128 Bytes of Internal Data Memory

The ADuC832 contains 2048 bytes of internal XRAM, 1792 bytes
of which can be configured to be used as an extended 11-bit stack
pointer.

By default, the stack will operate exactly like an 8052 in that it
will roll over from FFH to 00H in the general-purpose RAM. On
the ADuC832, however, it is possible (by setting CFG832.7)
to enable the 11-bit extended stack pointer. In this case, the
stack will roll over from FFH in RAM to 0100H in XRAM.

The 11-bit stack pointer is visible in the SP and SPH SFRs.
The SP SFR is located at 81H as with a standard 8052. The
SPH SFR is located at B7H. The 3 LSBs of this SFR contain
the three extra bits necessary to extend the 8-bit stack pointer
into an 11-bit stack pointer.

07FFH

UPPER 1792

BYTES OF

ON-CHIP XRAM

(DATA + STACK

FOR EXSP = 1,

DATA ONLY

FOR EXSP = 0)

CFG832.7 = 0

FFH

00H

CFG832.7 = 1

256 BYTES OF

ON-CHIP DATA

RAM
(DATA +
STACK)

100H

00H

LOWER 256

BYTES OF

ON-CHIP XRAM

(DATA ONLY)

Figure 3. Extended Stack Pointer Operation

REV. 0–14–

ADuC832

External Data Memory (External XRAM)

Just like a standard 8051 compatible core, the ADuC832 can
access external data memory using a MOVX instruction. The
MOVX instruction automatically outputs the various control
strobes required to access the data memory.

The ADuC832, however, can access up to 16 MBytes of external
data memory. This is an enhancement of the 64 kBytes external
data memory space available on a standard 8051 compatible core.

The external data memory is discussed in more detail in the
ADuC832 Hardware Design Considerations section.

Internal XRAM

2 kBytes of on-chip data memory exist on the ADuC832. This
memory, although on-chip, is also accessed via the MOVX
instruction. The 2 kBytes of internal XRAM are mapped into the
bottom 2 kBytes of the external address space if the CFG832 bit
is set. Otherwise, access to the external data memory will occur
just like a standard 8051. When using the internal XRAM,
Ports 0 and 2 are free to be used as general-purpose I/O.

FFFFFFH

000000H

EXTERNAL

DATA

MEMORY

SPACE
(24-BIT

ADDRESS

SPACE)

CFG832.0 = 0

FFFFFFH

000800H

0007FFH

000000H

EXTERNAL

DATA

MEMORY

SPACE
(24-BIT

ADDRESS

SPACE)

2 kBYTES

ON-CHIP

XRAM

CFG832.0 = 1

Figure 4. Internal and External XRAM

SPECIAL FUNCTION REGISTERS (SFRs)

The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on chip periph­erals. A block diagram showing the programming model of the
ADuC832 via the SFR area is shown in Figure 5.

All registers, except the Program Counter (PC) and the four
general-purpose register banks, reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.

4-kBYTE

62-kBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

MEMORY

8051

COMPATIBLE

CORE

2304 BYTES

RAM

128-BYTE

SPECIAL
FUNCTION
REGISTER

AREA

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

8-CHANNEL

12-BIT ADC

OTHER ON-CHIP

PERIPHERALS

TEMPERATURE

SENSOR

2  12-BIT DACs

SERIAL I/O

WDT
PSM

TIC

PWM

Figure 5. Programming Model

Accumulator SFR (ACC)

ACC is the Accumulator register and is used for math operations
including addition, subtraction, integer multiplication and division,
and Boolean bit manipulations. The mnemonics for accumulator­specific instructions refer to the Accumulator as A.

B SFR (B)

The B register is used with the ACC for multiplication and divi­sion operations. For other instructions, it can be treated as a
general-purpose scratch pad register.

Stack Pointer (SP and SPH)

The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the top of the stack. The SP register is
incremented before data is stored during PUSH and CALL execu­tions. While the stack may reside anywhere in on-chip RAM, the
SP register is initialized to 07H after a reset. This causes the
stack to begin at location 08H.

As mentioned earlier, the ADuC832 offers an extended 11-bit
stack pointer. The three extra bits to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7H.

REV. 0

–15–

ADuC832

Data Pointer (DPTR)

The Data Pointer is made up of three 8-bit registers, named
DPP (page byte), DPH (high byte) and DPL (low byte). These
are used to provide memory addresses for internal and external
code access and external data access. It may be manipulated as
a 16-bit register (DPTR = DPH, DPL), although INC DPTR
instructions will automatically carry over to DPP, or as three
independent 8-bit registers (DPP, DPH, DPL).

The ADuC832 supports dual data pointers. Refer to the Dual
Data Pointer section.

Program Status Word (PSW)

The PSW SFR contains several bits reflecting the current status
of the CPU as detailed in Table I.

SFR Address D0H
Power-On Default Value 00H
Bit Addressable Yes

Table I. PSW SFR Bit Designations

Bit Name Description

7CYCarry Flag
6ACAuxiliary Carry Flag
5F0General-Purpose Flag
4 RS1 Register Bank Select Bits
3 RS0 RS1 RS0 Selected Bank

000
011
102

113
2OVOverflow Flag
1F1General-Purpose Flag
0P Parity Bit

Power Control SFR (PCON)

The PCON SFR contains bits for power-saving options and
general-purpose status flags as shown in Table II.

SFR Address 87H
Power-On Default Value 00H
Bit Addressable No

Table II. PCON SFR Bit Designations

Bit Name Description

7 SMOD Double UART Baud Rate
6 SERIPD I2C/SPI Power-Down Interrupt Enable
5 INT0PD INT0 Power-Down Interrupt Enable
4 ALEOFF Disable ALE Output
3 GF1 General-Purpose Flag Bit
2 GF0 General-Purpose Flag Bit
1PD Power-Down Mode Enable
0 IDL Idle Mode Enable

REV. 0–16–

ADuC832

SPECIAL FUNCTION REGISTERS

All registers except the program counter and the four general­purpose register banks reside in the special function register
(SFR) area. The SFR registers include control, configuration,
and data registers that provide an interface between the CPU
and other on-chip peripherals.

Figure 6 shows a full SFR memory map and SFR contents on
Reset. Unoccupied SFR locations are shown dark-shaded in

ISPI

WCOL

SPE

SPIM

CPOL

CPHA

FFH

0

FEH

0

FDH

0

FCH

0

FBH

0

F7H0F6H0F5H0F4H0F3H0F2H

MCO

RCLK

PRE1

PT2

T1

ET2

SM2

TF0

SCONV

DCH

0

0

D4H

TCLK

0

CCH

PRE0

0PSBCH

1

B4H

0

0

9CH

0

8CH

MDI I2CRS

CS3

DBH

0

0

RS1

RS0

0

D3H

0OVD2H

EXEN2

0

CBH

0

WDIR

1

C3H

0

PT1

0

BBH

0

T0

INT1

1

1

B3H

ET1

ABH 0

REN

TB8

0

0

9BH

TR0

IE1

0

0

8BH

EFH0EEH

0

E7H

ADCI

DFH

0

CY

D7H

0ACD6H

TF2

CFH

0

PRE3

C7H

0

PSI

BFH

0

RD

B7H

1

EA

AFH

0

A7H

11

SM0

9FH

0

97H196H195H194H193H192H

TF1

8FH

0

87H186H185H184H183H182H 81H180H

EDH0ECH0EBH0EAH

0

E6H0E5H0E4H0E3H0E2H E1H0E0H

DMA

CCONV

DEH

DDH

0

0F0D5H

EXF2

CEH

0

CDH

PRE2

C6H

0

C5H0C4H

PADC

BEH

0

BDH

WR

1

B6H

B5H

EADC

AEH

ADHESACH 0

0

A6H A5H1A4H1A3H1A2H A1H

SM1

0

9EH

9DH

TR1

0

8EH

8DH

MDE I2CM

MDO

FAH

DAH

CAH

C2H

BAH

B2H

AAH

9AH

8AH

CS2

TR2

WDS

PX1

INT0

EX1

RB8

IT1

SPR1

F9H

1

0

F1H0F0H

I2CTX

E9H0E8H

0

0

CS1

0

D9H

FI

0

D1H

CNT2

0

C9H

WDE

0

C1H

PT0

0

B9H

TxD

1

B1H

ET0

A9H 0

0

1

TI

99H

0

T2EX

91H

1

IE0

0

89H

1

0

F8H

D8H

0

0PD0H

0

C8H

WDWR

0

C0H

0

B8H

1

B0H

A8H

1

A0H

0RI98H

1T290H

0

88H

SPR0

I2CI

CS0

CAP2

PX0

RxD

EX0

IT0

BITS

0

BITS

0

BITS

0

BITS

0

BITS

0

BITS

0

BITS

0

BITS

0

BITS

0

BITS

1

BITS

0

BITS

1

BITS

0

BITS

1

BITS

0

BITS

1

SPICON

F8H

F0H 00H

I2CCON

E8H 00H

ACC

E0H 00H

ADCCON2

D8H 00H

PSW

D0H 00H

T2CON

C8H 00H

WDCON

C0H 10H

B8H 00H

P3

B0H FFH

A8H 00H

P2

A0H FFH

SCON

98H 00H

P1

90H FFH

TCON

88H 00H

P0

80H FFHSP81H 07H

the figure below (NOT USED). Unoccupied locations in the
SFR address space are not implemented i.e., no register exists
at this location. If an unoccupied location is read, an unspecified
value is returned. SFR locations reserved for on-chip testing are
shown lighter shaded below (RESERVED) and should not be
accessed by user software. Sixteen of the SFR locations are also
bit addressable and denoted by

'1'

in the figure below, i.e., the

bit addressable SFRs are those whose address ends in 0H or 8H.

1

04H

1

B

1

1

1

1

1

1

1

IP

1

1

IE

1

1

1, 2

1

1

DAC0L

F9H 00H

ADCOFSL

F1H 00H

ADCDATAL

D9H 00H

RESERVED

RESERVED

ECON

B9H 00H

PWM0L PWM0H

IEIP2

A9H A0H

TIMECON

A1H

SBUF

99H 00H

TMOD

89H 00H

DAC0H

FAH 00H

3

ADCOFSH

F2H 20H

DAC1L

FBH 00H

3

ADCGAINL

F3H 00H

DAC1H

FCH 00H

3

ADCGAINH

F4H 00H

ADC DATAH

DAH

00H

DMAL

D2H 00H

RCAP2L

CAH

CHIPID

C2H

RESERVED RESERVED

DMAH

D3H 00H

RCAP2H

00H

CBH 00H

RESERVED RESERVED

2XH

DMAP

D4H 00H

TL2

CCH 00H

EDATA1

BCH 00H

PWM1L PWM1H

B4H

B2H B3H

00H

00H

RESERVED RESERVED

HTHSEC

A2H A3H A4H

00H 00H 00H 00H

I2CDAT

9AH 00H

TL0

8AH 00H

DPL

82H 00H

00H

SEC

I2CADD

9BH 55H

TL1

8BH 00H

DPH

83H 00H

00H

RESERVED RESERVED

MIN

NOT USED

TH0

8CH 00H

DPP

84H 00H

DACCON

FDH 04H

3

ADCCON3

F5H 00H

RESERVEDRESERVEDRESERVEDRESERVEDRESERVED

RESERVEDRESERVEDRESERVEDRESERVEDRESERVED

RESERVEDRESERVEDRESERVED

RESERVEDRESERVED

CDH 00H

RESERVED

EDATA2

BDH 00H

TH2

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

EDARL

C6H 00H

EDATA3

BEH 00H

NOT USEDNOT USED

PWMCON

AEH

HOUR INTVAL

A5H

A6H A7H

00H 00H

T3FD T3CON

9DH 9EH00H 00H

NOT USEDNOT USEDNOT USEDNOT USEDNOT USED

8DH 00H

TH1

RESERVED RESERVED

NOT USED

RESERVEDRESERVED

00H

RESERVED

SPIDAT

F7H 00H

ADCCON1

EFH 00H

RESERVED

PSMCON

DFH

PLLCON

D7H 53H

RESERVED

EDARH

C7H 00H

EDATA4

BFH 00H

SPH

B7H

CFG832

AFH 00H

DPCON

NOT USED

NOT USED

PCON

87H 00H

DEH

00HB1H

00H

SFR MAP KEY:

MNEMONIC

SFR ADDRESS

DEFAULT VALUE

NOTES

1

SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.

2

THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE

PORT PINS, WRITE A “0” TO THE CORRESPONDING PORT 1 SFR BIT.

3

CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.

THESE BITS ARE CONTAINED IN THIS BYTE.

89H

IE0

IT0

0

88H

TCON

0

88H 00H

MNEMONIC

DEFAULT VALUE

SFR ADDRESS

Figure 6. Special Function Register Locations and Reset Values

REV. 0

–17–

ADuC832

ADC CIRCUIT INFORMATION
General Overview

The ADC conversion block incorporates a fast, 8-channel,
12-bit, single-supply ADC. This block provides the user with
multichannel mux, track/hold, on-chip reference, calibration
features, and ADC. All components in this block are easily
configured via a 3-register SFR interface.

The ADC converter consists of a conventional successive­approximation converter based around a capacitor DAC. The
converter accepts an analog input range of 0 to V

. A high

REF

precision, low drift, and factory calibrated 2.5 V reference is
provided on-chip. An external reference can be connected as
described later. This external reference can be in the range 1 V

DD

.

to AV

Single step or continuous conversion modes can be initiated in
software or alternatively by applying a convert signal to an
external pin. Timer 2 can also be configured to generate a repeti­tive trigger for ADC conversions. The ADC may be configured
to operate in a DMA mode whereby the ADC block continu­ously converts and captures samples to an external RAM space
without any interaction from the MCU core. This automatic
capture facility can extend through a 16 MByte external data
memory space.

The ADuC832 is shipped with factory programmed calibration
coefficients that are automatically downloaded to the ADC on
power-up, ensuring optimum ADC performance. The ADC
core contains internal offset and gain calibration registers that
can be hardware calibrated to minimize system errors.

A voltage output from an on-chip band gap reference propor­tional to absolute temperature can also be routed through the
front end ADC multiplexer (effectively a ninth ADC channel
input) facilitating a temperature sensor implementation.

ADC Transfer Function

The analog input range for the ADC is 0 V to V

. For this

REF

range, the designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when

= 2.5 V. The ideal input/output transfer characteristic for

V

REF

the 0 to V

range is shown in Figure 7.

REF

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...010

000...001

000...000
1LSB

0V

1LSB =

FS

4096

VOLTAGE INPUT

+FS
–1LSB

Figure 7. ADC Transfer Function

Typical Operation

Once configured via the ADCCON 1-3 SFRs, the ADC will con­vert the analog input and provide an ADC 12-bit result word in the
ADCDATAH/L SFRs. The top four bits of the ADCDATAH
SFR will be written with the channel selection bits so as to
identify the channel result. The format of the ADC 12-bit result
word is shown in Figure 8.

ADCDATAH SFR

CH–ID

TOP 4 BITS

HIGH 4 BITS OF
ADC RESULT WORD

LOW 8 BITS OF THE
ADC RESULT WORD

Figure 8. ADC Result Format

ADCDATAL SFR

REV. 0–18–

ADuC832

ADCCON1 – (ADC Control SFR #1)

The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes, and power-down modes as
detailed below.

SFR Address: EFH
SFR Power-On Default Value: 00H
Bit Addressable: NO

Table III. ADCCON1 SFR Bit Designations

Bit Name Description

ADCCON1.7 MD1 The Mode bit selects the active operating mode of the ADC.

Set by the user to power up the ADC.
Cleared by the user to power down the ADC.

ADCCON1.6 EXT_REF Set by the user to select an external reference.

Cleared by the user to use the internal reference.
ADCCON1.5 CK1 The ADC clock divide bits (CK1, CK0) select the divide ratio for the PLL master clock used to generate the
ADCCON1.4 CK0 ADC clock. To ensure correct ADC operation, the divider ratio must be chosen to reduce the ADC clock

to 4.5 MHz and below. A typical ADC conversion will require 17 ADC clocks.

The divider ratio is selected as follows:

CK1 CK0 MCLK Divider

008

014

1016

1132

ADCCON1.3 AQ1 The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier
ADCCON1.2 AQ0 to acquire the input signal. An acquisition of three or more ADC clocks is recommended; clocks are

selected as follows:

AQ1 AQ0 #ADC Clks

001

012

103

114

ADCCON1.1 T2C The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit be used as

the ADC convert start trigger input.
ADCCON1.0 EXC The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5 (CONVST) to

be used as the active low convert start input. This input should be an active low pulse (minimum

pulsewidth >100 ns) at the required sample rate.

REV. 0

–19–

ADuC832

ADCCON2 – (ADC Control SFR #2)

The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.

SFR Address: D8H
SFR Power-On Default Value: 00H
Bit Addressable: YES

Table IV. ADCCON2 SFR Bit Designations

Bit

ADCCON2.7 ADCI The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at

ADCCON2.6 DMA The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode opera-

ADCCON2.5 CCONV The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of

ADCCON2.4 SCONV The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is

ADCCON2.3 CS3 The channel selection bits (CS3–0) allow the user to program the ADC channel selection under
ADCCON2.2 CS2 software control. When a conversion is initiated, the channel converted will be that pointed to by
ADCCON2.1 CS1 these channel selection bits. In DMA mode, the channel selection is derived from the channel ID
ADCCON2.0 CS0 written to the external memory.

Name Description

the end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC
Interrupt Service Routine. Otherwise, the ADCI bit should be cleared by user code.

tion. A more detailed description of this mode is given in the ADC DMA Mode section. The DMA bit is
automatically set to “0” at the end of a DMA cycle. Setting this bit causes the ALE output to cease, it will
start again when DMA is started and will operate correctly after DMA is complete.

conversion. In this mode, the ADC starts converting based on the timing and channel configuration
already set up in the ADCCON SFRs; the ADC automatically starts another conversion once a previ­ous conversion has completed.

automatically reset to “0” on completion of the single conversion cycle.

CS3 CS2 CS1 CS0 CH#

00000
00011
00102
00113
01004
01015
01106
01117
1000Temp Monitor Requires minimum of 1 µs to acquire
1001DAC0 Only use with Internal DAC o/p buffer on
1010DAC1 Only use with Internal DAC o/p buffer on
1011AGND
1100VREF
1111DMA STOP Place in XRAM location to finish DMA sequence, see

the section ADC DMA Mode.

All other combinations reserved

REV. 0–20–

ADuC832

ADCCON3 – (ADC Control SFR #3)

The ADCCON3 register controls the operation of various calibra­tion modes as well as giving an indication of ADC busy status.

SFR Address: F5H
SFR Power-On Default Value: 00H
Bit Addressable: NO

Table V. ADCCON3 SFR Bit Designations

Bit Name Description

ADCCON3.7 BUSY The ADC Busy Status Bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or

calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.

ADCCON3.6 GNCLD Gain Calibration Disable Bit.

Set to “0” to Enable Gain Calibration.

Set to “1” to Disable Gain Calibration.
ADCCON3.5 AVGS1 Number of Averages Selection Bits.
ADCCON3.4 AVGS0 This bit selects the number of ADC readings averaged during a calibration cycle.

AVGS1 AVGS0 Number of Averages

0 0 15

0 1 1

1 0 31

1 1 63
ADCCON3.3 RSVD Reserved. This bit should always be written as “0.”
ADCCON3.2 RSVD This bit should always be written as “1” by the user when performing calibration.
ADCCON3.1 TYPICAL Calibration Type Select Bit.

This bit selects between Offset (zero-scale) and Gain (full-scale) calibration.

Set to “0” for Offset Calibration.

Set to “1” for Gain Calibration.
ADCCON3.0 SCAL Start Calibration Cycle Bit.

When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration

cycle is completed.

REV. 0

–21–

ADuC832

Driving the A/D Converter

The ADC incorporates a successive approximation (SAR) archi­tecture involving a charge-sampled input stage. Figure 9 shows
the equivalent circuit of the analog input section. Each ADC
conversion is divided into two distinct phases as defined by the
position of the switches in Figure 9. During the sampling phase
(with SW1 and SW2 in the “track” position) a charge propor­tional to the voltage on the analog input is developed across the
input sampling capacitor. During the conversion phase (with
both switches in the “hold” position) the capacitor DAC is
adjusted via internal SAR logic until the voltage on node A is
zero, indicating that the sampled charge on the input capacitor
is balanced out by the charge being output by the capacitor DAC.
The digital value finally contained in the SAR is then latched
out as the result of the ADC conversion. Control of the SAR,
and timing of acquisition and sampling modes, is handled
automatically by built-in ADC control logic. Acquisition and
conversion times are also fully configurable under user control.

sw1

32pF

NODE A

TRACK

ADuC832

sw2

HOLD

CAPACITOR

DAC

COMPARATOR

AIN7

AIN0

AGND

V

REF

AGND

DAC1

DAC0
TEMPERATURE MONITOR

200

TRACK

HOLD

200

Figure 9. Internal ADC Structure

Note that whenever a new input channel is selected, a residual
charge from the 32 pF sampling capacitor places a transient on
the newly selected input. The signal source must be capable of
recovering from this transient before the sampling switches click
into “hold” mode. Delays can be inserted in software (between
channel selection and conversion request) to account for input
stage settling, but a hardware solution will alleviate this burden
from the software design task and will ultimately result in a
cleaner system implementation. One hardware solution would
be to choose a very fast settling op amp to drive each analog
input. Such an op amp would need to fully settle from a small
signal transient in less than 300 ns in order to guarantee adequate
settling under all software configurations. A better solution, recom­mended for use with any amplifier, is shown in Figure 10.

Though at first glance the circuit in Figure 10 may look like a
simple antialiasing filter, it actually serves no such purpose since its
corner frequency is well above the Nyquist frequency, even at a
200 kHz sample rate. Though the R/C does help to reject some
incoming high frequency noise, its primary function is to ensure
that the transient demands of the ADC input stage are met.

ADuC832

10

0.1F

AIN0

Figure 10. Buffering Analog Inputs

It does so by providing a capacitive bank from which the 32 pF
sampling capacitor can draw its charge. Its voltage will not change
by more than one count (1/4096) of the 12-bit transfer function
when the 32 pF charge from a previous channel is dumped onto
it. A larger capacitor can be used if desired, but not a larger
resistor (for reasons described below).

The Schottky diodes in Figure 10 may be necessary to limit the
voltage applied to the analog input pin as per the data sheet
absolute maximum ratings. They are not necessary if the op
amp is powered from the same supply as the ADuC832 since
in that case the op amp is unable to generate voltages above

or below ground. An op amp of some kind is necessary

V

DD

unless the signal source is very low impedance to begin with.
DC leakage currents at the ADuC832’s analog inputs can
cause measurable dc errors with external source impedances
as little as 100 Ω or so. To ensure accurate ADC operation, keep
the total source impedance at each analog input less than 61 Ω.
The table below illustrates examples of how source impedance
can affect dc accuracy.

Source Error from 1 µAError from 10 µA
Impedance Leakage Current Leakage Current
61 Ω 61 µV = 0.1 LSB 610 µV = 1 LSB
610 Ω 610 µV = 1 LSB 6.1 mV = 10 LSB

Although Figure 10 shows the op amp operating at a gain of 1,
you can, of course, configure it for any gain needed. Also, you
can just as easily use an instrumentation amplifier in its place to
condition differential signals. Use any modern amplifier that is
capable of delivering the signal (0 to V

) with minimal satura-

REF

tion. Some single-supply rail-to-rail op amps that are useful for
this purpose include, but are certainly not limited to, the ones
given in Table VI. Check Analog Devices literature (CD ROM
data book, and so on) for details on these and other op amps
and instrumentation amps.

Table VI. Some Single-Supply Op Amps

Op Amp Model Characteristics

OP281/OP481 Micropower
OP191/OP291/OP491 I/O Good up to VDD, Low Cost
OP196/OP296/OP496 I/O to V

, Micropower, Low Cost

DD

OP183/OP283 High Gain-Bandwidth Product
OP162/OP262/OP462 High GBP, Micro Package
AD820/AD822/AD824 FET Input, Low Cost
AD823 FET Input, High GBP

Keep in mind that the ADC’s transfer function is 0 to V

REF

, and
any signal range lost to amplifier saturation near ground will
impact dynamic range. Though the op amps in Table VI are
capable of delivering output signals very closely approaching

REV. 0–22–

ADuC832

ground, no amplifier can deliver signals all the way to ground
when powered by a single supply. Therefore, if a negative
supply is available, you might consider using it to power the
front end amplifiers. If you do, however, be sure to include the
Schottky diodes shown in Figure 10 (or at least the lower of
the two diodes) to protect the analog input from undervoltage
conditions. To summarize this section, use the circuit of
Figure 10 to drive the analog input pins of the ADuC832.

Voltage Reference Connections

The on-chip 2.5 V band gap voltage reference can be used as
the reference source for the ADC and DACs. To ensure the
accuracy of the voltage reference, you must decouple the V
pin to ground with a 0.1 µF capacitor, and the C

REF

REF

pin to

ground with a 0.1 µF capacitor as shown in Figure 11.

ADuC832

2.5V

BAND GAP

REFERENCE

and C

REF

REF

V

REF

0.1F

C

REF

BUFFER

0.1F

Figure 11. Decoupling V

51

BUFFER

If the internal voltage reference is to be used as a reference for
external circuitry, the C

output should be used. However, a

REF

buffer must be used in this case to ensure that no current is
drawn from the C

pin itself. The voltage on the C

REF

REF

pin is
that of an internal node within the buffer block, and its voltage
is critical to ADC and DAC accuracy. On the ADuC812, V

REF

was the recommended output for the external reference; this
can be used but it should be noted that there will be a gain error
between this reference and that of the ADC.

The ADuC832 powers up with its internal voltage reference in
the “on” state. This is available at the V

pin, but as noted

REF

before there will be a gain error between this and that of the ADC.
The C

output becomes available when the ADC is powered up.

REF

If an external voltage reference is preferred, it should be
connected to the V

REF

and C

pins as shown in Figure 12.

REF

Bit 6 of the ADCCON1 SFR must be set to 1 to switch in the
external reference voltage.

To ensure accurate ADC operation, the voltage applied to V

REF

must be between 1 V and AVDD. In situations where analog
input signals are proportional to the power supply (such as some
strain gage applications) it may be desirable to connect the C
and V

pins directly to AVDD.

REF

REF

Operation of the ADC or DACs with a reference voltage below
1 V, however, may incur loss of accuracy, eventually resulting in
missing codes or non-monotonicity. For that reason, do not use
a reference voltage less than 1 V.

ADuC832

V

DD

EXTERNAL

VOLT AGE

REFERENCE

0.1F

0.1F

51

“0” = INTERNAL

V

REF

C

REF

“1” = EXTERNAL

2.5V

BAND GAP

REFERENCE

ADCCON1.6

BUFFER

Figure 12. Using an External Voltage Reference

To maintain compatibility with the ADuC812, the external refer­ence may also be connected to the V

pin as shown in Figure 13,

REF

to overdrive the internal reference. Note this introduces a gain
error for the ADC that has to be calibrated out; thus the previous
method is the recommended one for most users. For this method
to work, ADCCON1.6 should be configured to use the internal
reference. The external reference will then overdrive this.

ADuC832

2.5V

BAND GAP

REFERENCE

V

DD

EXTERNAL

VOLTAGE

REFERENCE

V

REF

0.1F

C

0.1F

REF

51

BUFFER

8

7

REV. 0

Figure 13. Using an External Voltage Reference

–23–

ADuC832

Configuring the ADC

The ADuC832’s successive approximation ADC is driven by a
divided down version of the master clock. To ensure adequate
ADC operation, this ADC clock must be between 400 kHz
and 6 MHz, and optimum performance is obtained with ADC
clock between 400 kHz and 4.5 MHz. Frequencies within this
range can easily be achieved with master clock frequencies from
400 kHz to well above 16 MHz with the four ADC clock divide
ratios to choose from. For example, set the ADC clock divide
ratio to 4 (i.e., ADCCLK = 16.777216 MHz/8 = 2 MHz) by
setting the appropriate bits in ADCCON1 (ADCCON1.5 = 0,
ADCCON1.4 = 0).

The total ADC conversion time is 15 ADC clocks, plus 1 ADC
clock for synchronization, plus the selected acquisition time
(1, 2, 3, or 4 ADC clocks). For the example above, with a 3-clock
acquisition time, total conversion time is 19 ADC clocks (or 9.05 µs
for a 2 MHz ADC clock).

In continuous conversion mode, a new conversion begins each
time the previous one finishes. The sample rate is then simply
the inverse of the total conversion time described above. In the
example above, the continuous conversion mode sample rate
would be 110.3 kHz.

If using the temperature sensor as the ADC input, the ADC
should be configured to use an ADCCLK of MCLK/32 and
four acquisition clocks.

Increasing the conversion time on the temperature monitor channel
improves the accuracy of the reading. To further improve the
accuracy, an external reference with low temperature drift should
also be used.

ADC DMA Mode

The on-chip ADC has been designed to run at a maximum
conversion speed of 4 µs (247 kHz sampling rate). When
converting at this rate, the ADuC832 MicroConverter has 4 µs
to read the ADC result and store the result in memory for fur­ther postprocessing, otherwise the next ADC sample could be
lost. In an interrupt driven routine, the MicroConverter would
also have to jump to the ADC Interrupt Service routine, which
will also increase the time required to store the ADC results. In
applications where the ADuC832 cannot sustain the interrupt
rate, an ADC DMA mode is provided.

To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set.
This allows the ADC results to be written directly to a 16 MByte
external static memory SRAM (mapped into data memory
space) without any interaction from the ADuC832 core. This
mode allows the ADuC832 to capture a contiguous sample
stream at full ADC update rates (247 kHz).

A Typical DMA Mode Configuration Example

To set the ADuC832 into DMA mode, a number of steps must
be followed:

1. The ADC must be powered down. This is done by ensuring
MD1 and MD0 are both set to 0 in ADCCON1.

2. The DMA address pointer must be set to the start address
of where the ADC results are to be written. This is done by
writing to the DMA mode address pointers DMAL, DMAH,
and DMAP. DMAL must be written to first, followed by
DMAH, and then by DMAP.

3. The external memory must be preconfigured. This consists of
writing the required ADC channel IDs into the top four bits
of every second memory location in the external SRAM, starting
at the first address specified by the DMA address pointer. As
the ADC DMA mode operates independent from the ADuC832
core, it is necessary to provide it with a stop command. This
is done by duplicating the last channel ID to be converted
followed by “1111” into the next channel selection field. A
typical preconfiguration of external memory is as follows:

00000AH

000000H

11 1 1

00 1 1

00 1 1

100 0

010 1

00 1 0

STOP COMMAND

REPEAT LAST CHANNEL
FOR A VALID STOP
CONDITION

CONVERT ADC CH#3

CONVERT TEMP SENSOR

CONVERT ADC CH#5

CONVERT ADC CH#2

Figure 14. Typical DMA External Memory Preconfiguration

4. The DMA is initiated by writing to the ADC SFRs in the
following sequence:

a. ADCCON2 is written to enable the DMA mode,

i.e., MOV ADCCON2, #40H; DMA mode enabled.

b. ADCCON1 is written to configure the conversion time

and power-up of the ADC. It can also enable Timer 2
driven conversions or external triggered conversions
if required.

c. ADC conversions are initiated. This is done by starting

single conversions, starting Timer 2, running for Timer 2
conversions, or receiving an external trigger.

When the DMA conversions are completed, the ADC interrupt
bit, ADCI, is set by hardware and the external SRAM contains
the new ADC conversion results as shown below. It should be
noted that no result is written to the last two memory locations.

When the DMA mode logic is active, it takes the responsibility of
storing the ADC results away from both the user and ADuC832
core logic. As it writes the results of the ADC conversions to exter­nal memory, it takes over the external memory interface from
the core. Thus, any core instructions that access the external
memory while DMA mode is enabled will not get access to it. The
core will execute the instructions and they will take the same time
to execute but they will not gain access to the external memory.

00000AH

000000H

1111

0011

0011

1000

0101

0010

STOP COMMAND

NO CONVERSION
RESULT WRITTEN HERE

CONVERSION RESULT
FOR ADC CH#3

CONVERSION RESULT
FOR TEMP SENSOR

CONVERSION RESULT
FOR ADC CH#5

CONVERSION RESULT
FOR ADC CH#2

Figure 15. Typical External Memory Configuration
Post ADC DMA Operation

REV. 0–24–