Analog Devices ADuC832 User Manual

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INSTRUCTION SET

Arithmetic Operations

ADD A,source 1,2 12

ADD A,#data 2 12

ADDC A,source 1,2 12

ADDC A,#data 2 12

SUBB A,source subtract from A 1,2 12

SUBB A,#data 2 12

INC A 1 12

INC source increment 1,2 12

INC DPTR * 124

DEC A 1 12

DEC source 1,2 12

MUL AB multiply A by B 1 48

DIV AB divide A by B 1 48

DA A decimal adjust 1 12

add source to A

add with carry

with borrow

decrement

Data Transfer Operations

MOV A,source 1,2 12

MOV A,#data 2 12

MOV dest,A move source 1,2 12

MOV dest,source 1,2,3 24

MOV dest,#data 2,3 12,24

MOV DPTR,#data16 3 24

MOVC A,@A+DPTR move from 1 24

MOVC A,@A+PC 1 24

MOVX A,@Ri 1 24

MOVX A,@DPTR move to/from 1 24

MOVX @Ri,A 1 24

MOVX @DPTR,A 1 24

PUSH direct push onto stack 2 24

POP direct pop from stack 2 24

XCH A,source exchange bytes 1,2 12

XCHD A,@Ri exchg low digits 1 12

ACALL addr11 2 24

LCALL addr16 3 24

RET return from sub. 1 24

RETI return from int. 1 24

AJMP addr11 2 24

LJMP addr16 3 24

SJMP rel 2 24

JMP @A+DPTR 1 24

JZ rel jump if A = 0 2 24

JNZ rel jump if A not 02 24

CJNE A,direct,rel 3 24

CJNE A,#data,rel compare and 3 24

CJNE Rn,#data,rel equal 3 24

CJNE @Ri,#data,rel 2 24

DJNZ Rn,rel decrement and 2 24

DJNZ direct, rel 3 24

NOP no operation 1 12

to destination

code memory

data memory

call subroutine

jump

jump if not

jump if not zero

bytes

OSC

periods

OSC

periods

OSC

periods

ASSEMBLER DIRECTIVES

EQU define symbol DATA define internal memory symbol IDATA define indirect addressing symbol XDATA define external memory symbol BIT define internal bit memory symbol CODE define program memory symbol DS reserve bytes of data memory DBIT reserve bits of bit memory DB store byte values in program memory

Rn register addressing using R0-R7

direct 8bit internal address (00h-FFh)

@Ri indirect addressing using R0 or R1

source any of [Rn, direct, @Ri]

dest any of [Rn, direct, @Ri]

#data 8bit constant included in instruction

#data16 16bit constant included in instruction

bit 8bit direct address of bit

rel signed 8bit offset

addr11 11bit address in current 2K page

addr16 16bit address

* INC DPTR increments the 24bit value DPP/DPH/DPL

Legend

Logical Operations

ANL A,source 1,2 12

ANL A,#data 2 12

ANL direct,A 2 12

logical AND

ANL direct,#data 3 24

ORL A,source 1,2 12

ORL A,#data 2 12

ORL direct,A 2 12

logical OR

ORL direct,#data 3 24

XRL A,source 1,2 12

XRL A,#data 2 12

XRL direct,A 2 12

logical XOR

XRL direct,#data 3 24

CLR A clear A to zero 1 12

CPL A complement A 1 12

RL A rotate A left 1 12

RLC A ...through C 1 12

RR A rotate A right 1 12

RRC A ...through C 1 12

SWAP A swap nibbles 1 12

Boolean Variable ManipulationProgram Branching

CLR C 1 12

CLR bit 2 12

SETB C 1 12

SETB bit 2 12

CPL C 1 12

CPL bit 2 12

ANL C,bit AND bit with C 2 24

ANL C,/bit ...NOTbit with C 2 24

ORL C,bit OR bit with C 2 24

ORL C,/bit ...NOTbit with C 2 24

MOV C,bit 2 12

MOV bit,C 2 24

JC rel jump if C set 2 24

JNC rel jmp if C not set 2 24

JB bit,rel jump if bit set 3 24

JNB bit,rel jmp if bit not set 3 24

JBC bit, rel jmp&clear if set 3 24

DW store word values in program memory ORG set segment location counter END end of assembly source file CSEG select program memory space XSEG select external data memory space DSEG select internal data memory space ISEG select indirectly addressed internal

BSEG select bit addressable memory space

clear bit to zero

set bit to one

complement bit

move bit to bit

data memory space

bytes

OSC

periods

OSC

periods

MQFP

CSP

1 56 P1.0 / ADC0 / T2

2 1 P1.1 / ADC1 / T2EX

3 2 P1.2 / ADC2

4 3 P1.3 / ADC3

54,5AVDD

6 6,7,8 AGND

79CREF

810VREF

9 11 DAC0

10 12 DAC1

PIN FUNCTIONS

545556

pin 1 identifier

2 3 4 5

ADuC832

56pin CSP

7 8

TOP VIEW

(not to scale)

11 12 13 14

434445464748495051

42 41

139

38 37

35 34

32 31

10 11

2625242322212019181716

12 13

pin 1 identifier

ADuC832

52pin MQFP

TOP VIEW

(not to scale)

11 13 P1.4 / ADC4

12 14 P1.5 / ADC5 / SS

13 15 P1.6 / ADC6

14 16 P1.7 / ADC7

15 17 RESET

16 18 P3.0 / RxD

17 19 P3.1 / TxD

18 20 P3.2 / INT0

19 21 P3.3/INT1/MISO/PWM1

20 22 DV

21 23 DGND

P3.4 / T0 / PWMC /

22 24

PWM0 / EXTCLK

23 25 P3.5 / T1 / CONVST

24 26 P3.6 / WR

25 27 P3.7 / RD

26 28 SCLOCK

MQFP

CSP

27 29 SDATA / MOSI

28 30 P2.0 / A8 / A16

29 31 P2.1 / A9 / A17

30 32 P2.2 / A10 / A18

31 33 P2.3 / A11 / A19

32 34 XTAL1 (in)

33 35 XTAL2 (out)

34 36 DVDD

35 37,38 DGND

36 39 P2.4 / A12 / A20

37 40 P2.5 / A13 / A21

38 41 P2.6/A14/A22/PWM0

39 42 P2.7/A15/A23/PWM1

MQFP

CSP

40 43 EA

41 44 PSEN

42 45 ALE

43 46 P0.0 / AD0

44 47 P0.1 / AD1

45 48 P0.2 / AD2

46 49 P0.3 / AD3

47 50 DGND

48 51 DVDD

49 52 P0.4 / AD4

50 53 P0.5 / AD5

51 54 P0.6 / AD6

52 55 P0.7 / AD7

CODE MEMORY SPACE

FFFFh F800h

F7FFh

0000h

(NOP instructions)

EA=1

internal

code space

62K bytes

Flash/EE

EA=0

external

code space

(64K

addressable)

FFFFh

0000h

INTERRUPT VECTOR ADDRESSES

Interrupt Bit

Interrupt Name

PSMCON.5 Power Supply Monitor Interrupt 43h 1 WDS WatchDog Timer Interrupt 5Bh 2

IE0 External Interrupt 0 03h 3

ADCI End of ADC Conversion Interrupt 33h 4

TF0 Timer0 Overflow Interrupt 0Bh 5 IE1 External Interrupt 1 13h 6 TF1 Timer1 Overflow Interrupt 1Bh 7

ISPI/I2CI SPI/I2C Interrupt 3Bh 8

RI/TI UART Interrupt 23h 9 TF2/EXF2 Timer2 Interrupt 2Bh 10

TIMECON.2 Time Interval Counter Interrupt 53h 11

Vector

Address

Priority

within

Level

40414243444546474849505152

38 37 36 35 34 33 32 31 30 29 28 27

26252423222120191817161514

MicroConverter

Quick Reference Guide

ADuC832

a Data Acquisition System on a Chip

the ADuC832 is:

Flash/EEPROM: 62K bytes Flash/EE program memory

microcontroller: industry standard 8052

other on-chip features: temperature sensor, power supply monitor,

ADC: 12bit, 5µs, 8channel, self calibrating

0.5LSB INL & 70dB SNR

DAC: dual, 12bit, 15µs, voltage output

1LSB DNL

4K bytes Flash/EE data memory

32 I/O lines, programmable PLL clock (131KHz to 16.8MHz from 32KHz crystal)

watchdog timer, flexible serial interface ports, voltage reference, time interval counter, dual 8/16bit PWM, power-on-reset

FUNCTIONAL BLOCK DIAGRAM

* pin numbers below refer to MQFP package

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1

P2.3

P2.4

P2.5

P2.6

P2.7

P2.3 (A11 / A19)

P2.4 (A12 / A20)

P2.5 (A13 / A21)

P2.6 (A14 / A22 / PWM0)

P2.7 (A15 / A23 / PWM1)

DAC

control

user XRAM

user RAM

watchdog

power supply

synchronous

serial interface

(SPI or I2C)

emulator

P3.0

P3.3 (INT1 / MISO / PWM1)

P3.2 (INT0)

P3.1 (TxD)

P3.0 (RxD)

DAC0

DAC1

2K x 8

256 x 8

timer

monitor

262719

MISO

SCLOCK

SDATA / MOSI

P3.7 (RD)

P3.6 (WR)

P3.5 (T1 / CONVST)

P3.4 (T0/PWMC/PWM0/EXTCLK)

25242322191817163938373631302928141312

BUF

PWM

16bit

counter

timers

time interval counter

OSC &

PLL

XTAL1

XTAL2

DAC0

DAC1

38 PWM0

39 PWM1

T2EX

INT0

INT1

P2.1

P2.0

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

hardware

23CONVST

ADC0

ADC1

ADC2

ADC3 ADC4 ADC5 ADC6 ADC7

AIN

MUX

12 13 14

TEMP sensor

2.5V

bandgap

reference

REF

AGND

PRINTED IN U.S.A. G03203-2.5-9/02 (0)

P0.0

P0.2 (AD2)

P0.1 (AD1)

P0.0 (AD0)

T/H

(-3 mV/oC)

BUF

2034354721

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

POR

P1.0 (ADC0 / T2)

P0.7 (AD7)

P0.6 (AD6)

52515049464544

12bit ADC

15RESET

DGND

P1.4 (ADC4)

P1.3 (ADC3)

P1.2 (ADC2)

P1.1 (ADC1 / T2EX)

432

4K x 8

data

Flash/EE

62K x 8

program

Flash/EE

baudrate timer

downloader

debugger

asynchronous

serial port (

UART

RxD

P2.1 (A9 / A17)

P2.0 (A8 / A16)

P1.7 (ADC7)

P1.6 (ADC6)

P1.5 (ADC5 / SS)

ADuC832

ADC

control

calibration

8052

)

424140

TxD

ALE

P2.2

P2.2 (A10 / A18)

MCU core

single-pin

PSEN

www.analog.com/microconverter REV. 0

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SFR DESCRIPTIONS

ADCCON1

DATA MEMORY: RAM, SFRs, user Flash/EE (all read/write)

SFR MAP & RESET VALUES

decimal

127

...

address

HEX

7Fh

...

30h

2Fh

2Eh

2Dh

2Ch

2Bh

2Ah

29h

28h

27h

26h

25h

24h

23h

22h

21h

20h

1Fh R7

1Eh R6

1Dh R5

1Ch R4

1Bh R3

1Ah R2

19h R1

18h R0

17h R7

16h R6

15h R5

14h R4

13h R3

12h R2

11h R1

10h R0

0Fh R7

0Eh R6

0Dh R5

0Ch R4

0Bh R3

0Ah R2

09h R1

08h R0

07h R7

06h R6

05h R5

04h R4

03h R3

02h R2

01h R1

00h R0

address

General Purpose

Bit Addressable

Area

3FFh

000h

FFh

00h

lower RAM

details

LOWER RAM

ddre

MSBa

7Fh 7Eh 7Dh 7Ch 7Bh 7Ah 79h 78h

(bit addresses)

77h 76h 75h 74h 73h 72h 71h 70h

6Fh 6Eh 6Dh 6Ch 6Bh 6Ah 69h 68h

67h 66h 65h 64h 63h 62h 61h 60h

5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h

57h 56h 55h 54h 53h 52h 51h 50h

4Fh 4Eh 4Dh 4Ch 4Bh 4Ah 49h 48h

47h 46h 45h 44h 43h 42h 41h 40h

3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h

37h 36h 35h 34h 33h 32h 31h 30h

2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h

27h 26h 25h 24h 23h 22g 21h 20h

1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h

17h 16h 15h 14h 13h 12h 11g 10h

0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h

07h 06h 05h 04h 03h 02h 01h 00h

DATA MEMORY SPACE

(read/write area)

7FFh

000h

SFR details

FFFFFFh

CFG832.0=1

internal

data

memory

2K bytes

( page 1023 )

4K bytes

(1K pages)

data

Flash/EE

(accessible

through

SFRs)

( page 0 )

128 bytes

upper RAM

(indirect

addressing

only)

128 bytes

lower RAM

(direct or

indirect

addressing)

SFRs

(direct

addressing

only)

LSBaddress

CFG832.0=0

external

data

memory

(16M bytes

addressable)

SPIDAT

(reserved)

DACCON

FDh 04h

ADCCON3

DAC1H

FCh 00h

ADCGAINH

DAC1L

FBh 00h

ADCGAINL

DAC0H

FAh 00h

ADCOFSH

DAC0L

ADCOFSL

F9h 00h

SPICON

F8h 04hBF0h 00h

SPR0

F8h 0

SPR1

F9h 0

CPHA

FAh 1

CPOL

FBh 0

SPIM

FCh 0

SPE

FDh 0

WCOL

FEh 0

ISPI

FFh 0

MAP KEY

F7h 00h

ADCCON1

F5h 00h

F4h *00h

F3h *00h

F2h *20h

F1h *00h

I2CCON

I2CI

F0h 0

I2CTX

F1h 0

I2CRS

F2h 0

I2CM

F3h 0

MDI

F4h 0

MCO

F5h 0

MDE

F6h 0

MDO

F7h 0

(reserved)

EFh 00h

(reserved)

ACC

E8h 00h

E8h 0

E9h 0

EAh 0

EBh 0

ECh 0

EDh 0

EEh 0

EFh 0

mnemonic

address

reset value

E0h 00h

E0h 0

E1h 0

E2h 0

E3h 0

E4h 0

E5h 0

E6h 0

E7h 0

PLLCON

PSMCON

DFh DEh

(reserved)

DMAP

(reserved)

DMAH

(reserved)

DMAL

DAh 00h

ADCDATAH

(reserved)

D9h 00h

ADCDATAL

PSW

D8h 00h

ADCCON2

CS0

D8h 0PD0h 0

CS1

D9h 0F1D1h 0

CS2

DAh 0OVD2h 0

CS3

RS0

DBh 0

RS1

DCh 0

SCONV

DDh 0F0D5h 0

CCONV

DMA

DEh 0ACD6h 0

ADCI

DFh 0CYD7h 0

EADRH

(reserved)

D7h 53h

EADRL

(reserved)

TH2

(reserved)

CDh 00h

TL2

(reserved)

D4h 00h

CCh 00h

(reserved)(reserved)

RCAP2H

D3h 00h

CBh 00h

CHIPID

RCAP2L

D2h 00h

CAh 00h

(reserved)

T2CON

WDCON

D0h 00h

C8h 00h

CAP2

WDWR

C8h 0

WDE

CNT2

C9h 0

TR2

WDS

CAh 0

WDIR

EXEN2

D3h 0

CBh 0

PRE0

TCLK

D4h 0

CCh 0

PRE1

RCLK

CDh 0

EXF2

PRE2

CEh 0

TF2

PRE3

CFh 0

these bits this byte

SPR0

SPR1

F8h 0

F9h 0

* calibration coefficients are preconfigured at power-up to factory calibrated values

C7h 00h

C6h 00h

C2h 2Xh

ED ATA4

BFh 00h

ED ATA3

BEh 00h

ED ATA2

BDh 00h

ED ATA1

BCh 00h

(reserved)(reserved)

ECON

B9h 00h

SPH

(not used)

PWM1H

PWM1L

PWM0H

PWM0L

CFG832

B7h 00h

PWMCON

B4h 00h

B3h 00h

B2h 00h

IEIP2

B1h 00h

DPCON

AFh 00h

INTVAL

AEh 00h

HOUR

MIN

SEC

(reserved) (reserved) (reserved) (reserved)

HTHSEC

TIMECON

A9h A0h

C0h 10hIPB8h 00hP3B0h FFhIEA8h 00hP2A0h FFh

PX0

C0h 0

PT0

C1h 0

PX1

C2h 0

PT1

C3h 0

C4h 1PSBCh 0T0B4h 1ESACh 0

PT2

C5h 0

PADC

C6h 0

PSI

C7h 0

RXD

B8h 0

B0h 1

TXD

B9h 0

B1h 1

INT0

BAh 0

B2h 1

INT1

BBh 0

B3h 1

BDh 0T1B5h 1

BEh 0WRB6h 1

BFh 0RDB7h 1EAAFh 0

EX0

A8h 0

ET0

A9h 0

EX1

AAh 0

ET1

ABh 0

ET2

ADh 0

EADC

AEh 0

are contained in

SPICON

F8h 04h

(not used)

A7h 00h

T3CON

A6h 00h

9Eh 00h

T3FD

A5h 00h

9Dh 00h

(not used)

A4h 00h

I2CADD

A3h 00h

9Bh 55h

I2CDAT

A2h 00h

9Ah 00h

SBUF

99h 00h

A1h 00h

SCON

98h 00hP190h FFh

A0h 1RI98h 0T290h 1

A1h 1TI99h 0

RB8

A2h 1

9Ah 0

TB8

A3h 1

9Bh 0

REN

A4h 1

9Ch 0

SM2

A5h 1

9Dh 0

SM1

A6h 1

9Eh 0

SM0

A7h 1

9Fh 0

mnemonic

reset value

address

(not used)

(not used)(not used)(not used)(not used)

T2EX

91h 1

92h 1

93h 1

94h 1

95h 1

96h 1

97h 1

(reserved) (reserved)

TH1

8Dh 00h

TH0

8Ch 00h

TL1

8Bh 00h

TL0

8Ah 00h

TMOD

89h 00hSP81h 07h

TCON

88h 00hP080h FFh

IT0

88h 0

IE0

89h 0

IT1

8Ah 0

IE1

8Bh 0

TR0

8Ch 0

TF0

8Dh 0

TR1

8Eh 0

TF1

8Fh 0

PCON

DPP

DPH

DPL

BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY

ADCCON1.7 ADC mode (0=off, 1=on) ADCCON1.6 external Vref select bit (0=on-chip Vref) ADCCON1.5 conversion time = 16 / ADCclk ADCCON1.4 ADCclk = 16,777,216Hz / [8,4,16,32] ADCCON1.3 acquisition time select bits ADCCON1.2 acq time = [1,2,3,4] / ADCclk ADCCON1.1 Timer2 convert enable ADCCON1.0 external CONVST enable

ADCCON2

ADCI ADC interrupt flag DMA DMA mode enable CCONV continuous conversion enable bit SCONV single conversion start bit CS3 input channel select bits:

87h 00h

CS2 0 - 7 = ADC0 - ADC7 CS1 8 = temperature sensor CS0 9=DAC0, A=DAC1, B=AGND

ADCCON3

ADCCON3.7 busy indicator flag (0=ADC not active) ADCCON3.6 gain calibration disable (0=gain cal enabled) ADCCON3.5 number of averages selection bits: ADCCON3.4 [15,1,31,63] ADCCON3.3 cal clock divide select (0=ADCclk, 1=ADCclk/2) ADCCON3.2 cal mode select (0=device, 1=system) ADCCON3.1 cal type select (0=offset, 1=gain) ADCCON3.0 start calibration bit, cleared by hardware

ADCDATAH

ADCDATAL

(reserved) (reserved)

DMAP,DMAH,DMAL

ADCGAINH ADCGAINL

ADCOFSH ADCOFSL

84h 00h

DACCON

DACCON.7 ModeSelect (0=12bit, 1=8bit) DACCON.6 DAC1 RangeSelect (0=V DACCON.5 DAC0 RangeSelect (0=V DACCON.4 Clear DAC1 (0=0V, 1=normal operation) DACCON.3 Clear DAC0 (0=0V, 1=normal operation) DACCON.2 SynchronousUpdate (1=asynchronous) DACCON.1 PowerDown DAC1 (0=off, 1=on) DACCON.0 PowerDown DAC0 (0=off, 1=on)

83h 00h

DAC1H,DAC1L

DAC0H,DAC0L

PLLCON

PLLCON.7 oscillator powerdown control bit (0=XTAL on) PLLCON.6 PLL lock indicator flag (0=out of lock) PLLCON.5 (this bit must contain zero)

82h 00h

PLLCON.4 (this bit must contain zero) PLLCON.3 fast interrupt control bit (0=normal) PLLCON.2 3-bit clock divider value, CD (default=3): PLLCON.1 PLLCON.0

TIMECON

TIMECON.6 (this bit must contain 1) TIMECON.5 INTVAL timebase select bits TIMECON.4 [128th sec, seconds, minutes, hours] TIMECON.3 single time interval control bit (0=reload&restart) TIMECON.2 time interval interrupt bit, TII TIMECON.1 time interval enable bit (0=disable&clear) TIMECON.0 time clock enable bit (0=disable)

INTVAL

HTHSEC SEC MIN HOUR

ECON

80h 1

EADRH,EADRL

EDATA1,EDATA2,EDATA3,EDATA4

81h 1

SPICON

ISPI SPI inturrupt (set at end of SPI transfer) WCOL write collision error flag SPE SPI enable (0=I2C enable, 1=SPI enable) SPIM master mode select (0=slave) CPOL clock polarity select (0=SCLK idles low)

82h 1

CPHA clock phase select (0=leading edge latch) SPR1 SPI bitrate select bits SPR0 bitrate = Fcore / [2,4,8,16] (slave: SPR0=SS)

SPIDAT

I2CCON

83h 1

MDO master mode SDATA output bit MDE master mode SDATA output enable (0=disable) MCO master mode SCLK output bit MDI master mode SDATA input bit I2CM master mode select bit (0=slave mode) I2CRS serial port reset I2CTX transmission direction status (0=RX,1=TX)

84h 1

I2CI serial interface interrupt

I2CADD

I2CDAT

PWMCON

85h 1

PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res., PWMCON.5 2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ, PWMCON.4 5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)] PWMCON.3 PWM clock divide bits PWMCON.2 PWM counter = clock / [1,4,16,64] PWMCON.1 PWM clock source bits [1=F

86h 1

PWMCON.0 3=T0 ext.int.rate, 4=F

PWM0H,PWM0L

PWM1H,PWM1L

DPCON

87h 1

DPCON.6 data pointer auto-toggle enable (0=disable) DPCON.5 shadow data pointer mode control bits DPCON.4 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl] DPCON.3 main data pointer mode control bits DPCON.2 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl] DPCON.1 (not implemented to allow INC DPCON toggling) DPCON.0 data pointer select [0=main, 1=shadow]

T3CON

T3CON.7 Timer 3 baud rate enable (0=disable) T3CON.2 binary divide factor (DIV) T3CON.1 DIV = log[F T3CON.0 (rounded down)

T3FD

T3FD = (2·F

CHIPID

ADC Control register #1

ADC Control register #2

ADC Control register #3

ADC Data registers

DMA address pointer

ADC Gain calibration coefficients

ADC Offset calibration coefficients

DAC Control register

PLL Control register

= 16,777,216Hz / 2

CORE

Time Interval Counter Control Register

TIC Interval Register

TIC Elapsed 128th Second Register

TIC Elapsed Seconds Register

TIC Elapsed Minutes Register

TIC Elapsed Hours Register

Data Flash/EE comand register

01h READ page 02h PROGRAM page 04h VERIFY page 05h ERASE page 06h ERASE ALL

Data Flash/EE data registers

SPI Control register

SPI Data register

I2C Control register

I2C Address register

I2C Data register

PWM Control register

Data Pointer Control register

Timer 3 Control register

Timer 3 Fractional Divider register

) / (baudrate·2

CORE

Chip ID Register

REF

DAC1 data registers

DAC0 data registers

82h PROGRAM byte 0Fh EXIT ULOAD mode F0h ENTER ULOAD mode (all others reserved)

Data Flash/EE address registers

XTAL

(16.777MHz)]

VCO

PWM0 data registers

PWM1 data registers

/(32·baudrate)] / log2

CORE

DIV

(2X hex = ADuC832)

, 1=VDD) , 1=VDD)

/15, 2=F

) - 64

CFG832

ADuC832 Configuration Register

CFG832.7 extended stack-pointer enable (0=disable) CFG832.6 PWM pins select (0=P2.6/P2.7,1=P3.4/P3.3) CFG832.5 DAC output buffer bypass (0=buffer enabled) CFG832.4 external clock select (0=internal clock) CFG832.3 (this bit must contain 0) CFG832.2 (this bit must contain 0) CFG832.1 (this bit must contain 0) CFG832.0 internal XRAM select (0=external XRAM)

WDCON

PRE3 watchdog timeout selection bits PRE2 0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms PRE1 8=0ms (immediate reset) PRE0 >8=reserved WDIR watchdog interrupt response bit WDS watchdog status flag (1 indicates watchdog timeout) WDE watchdog enable control (0=disabled) WDWR watchdog write enable bit (set to enable write)

PSMCON

PSMCON.6 PSM status bit (1=normal / 0=fault) PSMCON.5 PSM interrupt bit PSMCON.4 trip point select bits PSMCON.3 [4.37V, 3.08V, 2.93V, 2.63V] PSMCON.2 (this bit must contain zero) PSMCON.1 (reserved) PSMCON.0 PSM powerdown control (1=on / 0=off)

SPH

EA enable inturrupts (0=all inturrupts disabled)

EADC enable ADCI (ADC interrupt)

ET2 enable TF2/EXF2 (Timer2 overflow interrupt) ES enable RI/TI (serial port interrupt) ET1 enable TF1 (Timer1 overflow interrupt) EX1 enable IE1 (external interrupt 1) ET0 enable TF0 (Timer0 overflow interrupt) EX0 enable IE0 (external interrupt 0)

IEIP2

IEIP2.6 priority of TII interrupt (time interval) IEIP2.5 priority of PSMI interrupt (power supply monitor) IEIP2.4 priority of ISPI interrupt (serial interface) IEIP2.3 (this bit must contain zero) IEIP2.2 enable TII interrupt (time interval) IEIP2.1 enable PSMI (power supply monitor interrupt) IEIP2.0 enable ISPI interrupt (serial interface)

PSI priority of ISPI/I2CI (serial interface interrupt)

PADC priority of ADCI (ADC interrupt)

PT2 priority of TF2/EXF2 (Timer2 overflow interrupt) PS priority of RI/TI (serial port interrupt) PT1 priority of TF1 (Timer1 overflow interrupt) PX1 priority of IE1 (external interrupt 1) PT0 priority of TF0 (Timer0 overflow interrupt) PX0 priority of IE0 (external interrupt 0)

TMOD

TMOD.3/.7 gate control bit (0=ignore INTx) TMOD.2/.6 counter/timer select bit (0=timer)

TMOD.1/.5 timer mode selecton bits TMOD.0/.4 [13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT] (upper nibble = Timer1, lower nibble = Timer0)

TCON

TF1 Timer1 overflow flag (auto cleared on vector to ISR) TR1 Timer1 run control (0=off, 1=run) TF0 Timer0 overflow flag (auto cleared on vector to ISR) TR0 Timer0 run control (0=off, 1=run) IE1 external INT1 flag (auto cleared on vector to ISR) IT1 IE1 type (0=level trig, 1=edge trig) IE0 external INT0 flag (auto cleared on vector to ISR) IT0 IE0 type (0=level trig, 1=edge trig)

TH0,TL0

TH1,TL1

T2CON

TF2 overflow flag EXF2 external flag RCLK receive clock enable (0=Timer1 used for RxD clk) TCLK transmit clock enable (0=Timer1 used for TxD clk) EXEN2 external enable (0=ignore T2EX, 1=cap/rld on T2EX) TR2 run control (0=stop, 1=run) CNT2 timer/counter select (0=timer, 1=counter) CAP2 capture/reload select (0=reload, 1=capture)

TH2,TL2

RCAP2H,RCAP2L

T2EX timer/counter 2 capture/reload trigger T2 timer/counter 2 external input

RD external data memory read strobe WR external data memory write strobe T1 timer/counter 1 external input T0 timer/counter 0 external input INT1 external interrupt 1 INT0 external interrupt 0 TxD serial port transmit data line RxD serial port receive data line

SCON

SM0 UART mode control bits baud rate: SM1 00 - 8bit shift register - F

SM2 in modes 2&3, enables multiprocessor communication REN receive enable control bit TB8 in modes 2&3, 9th bit transmitted RB8 in modes 2&3, 9th bit received TI transmit interrupt flag RI receive interrupt flag

SBUF

PCON

PCON.7 double baud rate control

XTAL

PCON.4 ALE disable (0=normal, 1=forces ALE high) PCON.3 general purpose flag PCON.2 general purpose flag PCON.1 power-down control bit (recoverable with hard reset) PCON.0 idle-mode control (recoverable with enabled interrupt)

PSW

CY carry flag AC auxiliary carry flag F0 general purpose flag 0 RS1 register bank select control bits RS0 active register bank = [0,1,2,3] OV overflow flag F1 general purpose flag 1 P parity of ACC

DPP

DPH,DPL (DPTR)

ACC

Watchdog Timer control register

Power Supply Monitor control register

Stack Pointer

Stack Pointer High byte

Interrupt Enable register #1

Interrupt Enable/Priority register #2

Interrupt Priority register

Timer Mode register

Timer Control register

Timer0 registers

Timer1 registers

Timer2 Control register

Timer2 register

Port0 register

Port1 register (analog & digital inputs)

Port2 register

Port3 register

Serial communications Control register

01 - 8bit UART - variable 10 - 9bit UART - F 11 - 9bit UART - variable

Serial port Buffer register

Power Control register

Program Status Word

Accumulator

auxiliary math register

Timer2 Reload/Capture

(also A0-A7 & D0-D7)

(also A8-A15 & A16-A23)

/12

OSC

/64(x2)

OSC

Data Pointer Page

Data Pointer

Analog Devices ADuC832 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual