Analog Devices ADuC814 a Datasheet

MicroConverter®, Small Package

12-Bit ADC with Embedded Flash MCU

ADuC814

FEATURES

ANALOG I/O

6-channel 247 kSPS ADC

AIN0

12-bit resolution
ADC high speed data capture mode

AIN5

Programmable reference via on-chip DAC for low
level inputs, ADC performance specified to V

REF

= 1 V

Dual voltage output DACs

12-bit resolution, 15 µs settling time

Memory

8 kbytes on-chip Flash/EE program memory

V

REF

640 bytes on-chip Flash/EE data memory
Flash/EE, 100 year retention, 100 kcycle endurance

C

REF

3 levels of Flash/EE program memory security
In-circuit serial downlaod (no external hardware)
256 bytes on-chip data RAM

8051 based core

8051 compatible instruction set
32 kHz external crystal,
on-chip programmable PLL (16.78 MHz max)
Three 16-bit timer/counters
11 programmable I/O lines
11 interrupt sources, 2 priority levels

Power

Specified for 3 V and 5 V operation
Normal: 3 mA @ 3 V (core CLK = 2.1 MHz)
Power-down: 15 µA (32 kHz oscillator running)

On-chip peripherals

Power-on reset circuit (no need for external POR device)
Temperature monitor (±1.5°C accuracy)
Precision voltage reference
Time interval counter (wake-up/RTC timer)
UART serial I/O

2

C® compatible serial I/O

SPI®/I
Watchdog timer (WDT), power supply monitor (PSM)

Package and temperature range

28-lead TSSOP 4.4 mm × 9.7 mm package
Fully specified for −40°C to +125°C operation

APPLICATIONS

Optical networking—laser power control
Base station systems—power amplifier bias control
Precision instruments, smart sensors
Battery-powered systems, precision system monitors

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

GENERAL DESCRIPTION

The ADuC814 is a fully integrated 247 kSPS, 12-bit data acquisi­tion system incorporating a high performance multichannel
ADC, an 8-bit MCU, and program/data Flash/EE memory on a
single chip.

This low power device operates from a 32 kHz crystal with an
on-chip PLL generating a high frequency clock of 16.78 MHz.
This clock is, in turn, routed through a programmable clock
divider from which the MCU core clock operating frequency is
generated.

The microcontroller core is an 8052 and is compatible with an
8051 instruction. 8 kBytes of nonvolatile Flash/EE program
memory are provided on-chip. 640 bytes of nonvolatile Flash/EE
data memory and 256 bytes RAM are also integrated on-chip.

The ADuC814 also incorporates additional analog functionality
with dual 12-bit DACs, a power supply monitor, and a band gap
reference. On-chip digital peripherals include a watchdog timer,
time interval counter, three timer/counters, and two serial I/O
ports (SPI and UART).

On-chip factory firmware supports in-circuit serial download
and debug modes (via UART), as well as single-pin emulation
mode via the DLOAD pin. The ADuC814 is supported by a
QuickStart™ Development System.

The part operates from a single 3 V or 5 V supply over the
extended temperature range −40°C to +125°C. When operating
from 3 V supplies, the power dissipation for the part is below
10 mW. The ADuC814 is housed in a 28-lead TSSOP package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

FUNCTIONAL BLOCK DIAGRAM

ADuC814

DAC

CONTROL

LOGIC

PERIPHERALS

256 BYTES USER RAM

3 × 16-BIT

TIMER

I/O PINS

ON-CHIP MONITORS

WATCHDOG TIMER

ON

RESET

PROG.

CLOCK

OSC
AND

PLL

XTAL2XTAL1

ADC

CONTROL

LOGIC

8051-BASED MCU WITH ADDITIONAL

8 KBYTES FLASH/EE PROGRAM MEMORY

640 BYTES FLASH/EE DATA MEMORY

TIMER/COUNTERS
1 × WAKE-UP/RTC

10 × DIGITAL

AIN

MUX

TEMP

MONITOR

INTERNAL

BAND GAP

BUF

12-BIT

T/H

ADC

POWER-

V

REF

DIVIDER

Figure 1.

www.analog.com

DAC0

BUF

DAC1

BUF

POWER SUPPLY

MONITOR

UART AND SPI

SERIAL I/O

DAC0

DAC1

02748-A-001

ADuC814

TABLE OF CONTENTS

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Description ............................10

Terminology .................................................................................... 12

ADC Specifications ....................................................................12

DAC Specifications..................................................................... 12

Typical Performance Curves......................................................... 13

ADuC814 Architecture, Main Features ....................................... 16

Memory Organization ............................................................... 17

Overview of MCU-Related SFRs.............................................. 18

Accumulator SFR ................................................................... 18

B SFR........................................................................................ 18

Stack Pointer SFR ...................................................................18

Data Pointer ............................................................................18

ADC Offset and Gain Calibration Overview ......................... 28

ADC Offset and Gain Calibration Coefficients..................... 28

Calibrating the ADC.................................................................. 29

Initiating Calibration in Code .................................................. 29

Nonvolitile Flash/EE Memory ...................................................... 30

Flash/EE Memory Overview .................................................... 30

Flash/EE Memory and the ADuC814...................................... 30

ADuC814 Flash/EE Memory Reliability................................. 30

Using Flash/EE Program Memory........................................... 31

Serial Downloading (In-Circuit Programming)................ 31

Parallel Programming............................................................ 31

Flash/EE Program Memory Security....................................... 31

Lock Mode .............................................................................. 31

Secure Mode ........................................................................... 31

Serial Safe Mode ..................................................................... 31

Program Status Word SFR..................................................... 18

Power Control SFR................................................................. 19

Special Function Registers ........................................................ 20

ADC Circuit Information.............................................................. 21

General Overview....................................................................... 21

ADC Transfer Function............................................................. 21

ADC Data Output Format.................................................... 21

SFR Interface to ADC Block ..................................................... 22

ADCCON1 (ADC Control SFR 1) .......................................... 22

ADCCON2 (ADC Control SFR 2) .......................................... 23

ADCCON3 (ADC Control SFR 3) .......................................... 24

Driving the ADC............................................................................. 25

Voltage Reference Connections................................................ 26

Configuring the ADC ................................................................26

Initiating ADC Conversions ..................................................... 27

Using Flash/EE Data Memory.................................................. 32

ECON—Flash/EE Memory Control SFR ........................... 32

Flash/EE Memory Timing ........................................................ 33

Using the Flash/EE Memory Interface................................ 33

Programming a Byte.............................................................. 33

User Interface to Other On-Chip ADuC814 Peripherals.......... 34

DACs............................................................................................ 34

Using the DACs...................................................................... 35

On-Chip PLL .............................................................................. 37

Time Interval Counter (TIC).................................................... 38

Watchdog Timer......................................................................... 41

Power Supply Monitor............................................................... 42

ADuC814 Configuration Register (CFG814) ........................ 43

Serial Peripheral Interface..................................................... 43

External Clock ........................................................................ 43

ADC High Speed Data Capture Mode .................................... 27

Rev. A | Page 2 of 72

ADuC814

Serial Peripheral Interface..........................................................44

SBUF.........................................................................................53

MISO (Master In, Slave Out Data I/O Pin).........................44

MOSI (Master Out, Slave In Pin)..........................................44

SCLOCK (Serial Clock I/O Pin) ...........................................44

SS

(Slave Select Input Pin).....................................................44

Using the SPI Interface...........................................................45

SPI Interface—Master Mode .................................................45

SPI Interface—Slave Mode ....................................................45

2

I

C Compatible Interface............................................................46

8051 Compatible On-Chip Peripherals....................................47

Parallel I/O Ports 1 and 3.......................................................47

Additional Digital Outputs Pins ...........................................47

Timers/Counters.........................................................................48

Timer/Counter 0 and 1 Data Registers................................49

Timer/Counter 0 and 1 Operating Modes...............................50

Mode 0 (13-Bit Timer/Counter)...........................................50

Mode 0: 8-Bit Shift Register Mode.......................................54

Mode 1: 8-Bit UART, Variable Baud Rate ............................54

Mode 2: 9-Bit UART with Fixed Baud Rate ........................55

Mode 3: 9-Bit UART with Variable Baud Rate....................55

UART Serial Port Baud Rate Generation ............................55

Timer 2 Generated Baud Rates.............................................56

Interrupt System..........................................................................57

Interrupt Priority ....................................................................59

Interrupt Vectors .....................................................................59

ADuC814 Hardware Design Considerations..............................60

Clock Oscillator...........................................................................60

Power Supplies.............................................................................60

Power Consumption...................................................................60

Power-Saving Modes..............................................................61

Power-On Reset ......................................................................61

Mode 1 (16-Bit Timer/Counter)...........................................50

Mode 2 (8-Bit Timer/Counter with Autoreload)................50

Mode 3 (Two 8-Bit Timer/Counters)...................................50

Timer/Counter 2 Data Registers...........................................51

Timer/Counter 2 Operating Modes .........................................52

16-Bit Autoreload Mode.........................................................52

16-Bit Capture Mode..............................................................52

UART Serial Interface.................................................................53

REVISION HISTORY

12/03 – Data Sheet Changed from REV. 0 to REV. A

Added detailed description of product ........................... Universal

Changes to Specifications.................................................................4

Updated Outline Dimensions........................................................70

Changes to Ordering Guide...........................................................71

Grounding and Board Layout Recommendations .............61

Other Hardware Considerations...............................................62

In-Circuit Serial Download Access ......................................62

Embedded Serial Port Debugger ..........................................62

Single-Pin Emulation Mode..................................................63

Timing Specifications.....................................................................64

Outline Dimensions........................................................................70

Ordering Guide ...........................................................................71

Rev. A | Page 3 of 72

ADuC814

SPECIFICATIONS

Table 1. AVDD = DVDD = 2.7 V to 3.3 V or 4.5 V to 5.5 V, V
specifications T

MIN

to T

, unless otherwise specified1

MAX

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions

ADC CHANNEL SPECIFICATIONS

A GRADE

DC ACCURACY

2,3

f
Resolution 12 12 Bits
Integral Nonlinearity 2 2 LSB max 2.5 V internal reference
1 1 LSB typ

2.5 2.5 LSB typ 1.0 V external reference
Differential Nonlinearity 4 4 LSB max 2.5 V internal reference
2 2 LSB typ
5 5 LSB typ 1.0 V external reference

CALIBRATED ENDPOINT ERRORS

4, 5

Offset Error 5 5 LSB max
Offset Error Match 1 1 LSB typ
Gain Error 5 5 LSB max
Gain Error Match 1 1 LSB typ

DYNAMIC PERFORMANCE6 fIN = 10 kHz sine wave

f
Signal to Noise Ratio (SNR)7 62.5 62.5 dB typ
Total Harmonic Distortion (THD) –65 –65 dB typ
Peak Harmonic or Spurious Noise –65 –65 dB typ
Channel-to-Channel Crosstalk8 –80 –80 dB typ

B GRADE

DC ACCURACY

2, 3

f
Resolution 12 12 Bits
Integral Nonlinearity 1 1 LSB max 2.5 V internal reference

0.3 0.3 LSB typ

1.5 1.5 LSB max 1.0 V external reference11
Differential Nonlinearity 0.9 0.9 LSB max 2.5 V internal reference

0.25 0.25 LSB typ
+1.5/–0.9 1.5/–0.9 LSB max 1.0 V external reference11
Code Distribution 1 1 LSB typ ADC input is a dc voltage

CALIBRATED ENDPOINT ERRORS

4, 5

Offset Error 2 3 LSB max
Offset Error Match 1 1 LSB typ
Gain Error 2 3 LSB max
Gain Error Match 1 1 LSB typ

DYNAMIC PERFORMANCE6 fIN = 10 kHz sine wave

f
Signal to Noise Ratio (SNR)7 71 71 dB typ
Total Harmonic Distortion (THD) –85 –85 dB typ
Peak Harmonic or Spurious Noise –85 –85 dB typ
Channel-to-Channel Crosstalk8 –80 –80 dB typ

ANALOG INPUT

Input Voltage Ranges 0 to V

0 to V

REF

Leakage Current 1 1 µA max
Input Capacitance 32 32 pF typ

= 2.5 V internal reference, XTAL1/XTAL2 = 32.768 kHz crystal. All

REF

= 147 kHz

SAMPLE

= 147 kHz

SAMPLE

= 147 kHz

SAMPLE

= 147 kHz

SAMPLE

V

REF

Rev. A | Page 4 of 72

ADuC814

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions

TEMPERATURE MONITOR9

Voltage Output at 25ºC 650 650 mV typ
Voltage TC –2 –2 mV/ºC typ
Accuracy 3 3 ºC typ 2.5 V internal reference

Accuracy 1.5 1.5 ºC typ 2.5 V external reference
DAC CHANNEL SPECIFICATIONS DAC Load to AGND RL = 10 kΩ, CL = 100 pF
DC ACCURACY10

Resolution 12 12 Bits

Relative Accuracy +3 +3 LSB typ

Differential Nonlinearity11 –1 –1 LSB max Guaranteed montonic

1/2 1/2 LSB typ

Offset Error 50 50 mV max V

Gain Error 1 1 % max V

1 1 % typ AVDD range

Gain Error Mismatch 0.5 0.5 % typ Of full scale on DAC1
ANALOG OUTPUTS

Voltage Range_0 0 to V

Volts DAC V

REF

Voltage Range_1 0 to VDD Volts DAC V

Output Impedance 0.5 0.5 Ω typ

I

50 50 µA typ

SINK

DAC AC Specifications

Voltage Output Settling Time 15 15 µs typ

Digital-to-Analog Glitch Energy 10 10 nVs typ 1 LSB change at major carry
REFERENCE INPUT/OUTPUT
REFERENCE OUTPUT

Output Voltage (V

) 2.5 2.5 V

REF

Accuracy 2.5 2.5 % max Of V

Power Supply Rejection 47 57 dB typ

Reference Tempco 100 100 ppm/ºC typ

Internal V

Power-On Time12 80 80 ms typ

REF

EXTERNAL REFERENCE INPUT13

Voltage Range (V

V

)14 1.0 1.0 V min

REF

VDD V max

DD

Input Impedance 20 20 kΩ typ

Input Leakage 10 10 µA max
POWER SUPPLY MONITOR (PSM)

VDD Trip Point Selection Range 2.63 2.63 V

2.93 2.93 V Four trip points selectable in this range

3.08 3.08 V programmed via TP1–0 in PSMCON

4.63 V

VDD Power Supply Trip Point Accuracy 3.5 3.5 % max
WATCH DOG TIMER (WDT)14

Timeout Period 0 0 ms min Nine time-out periods selectable in this range

2000 2000 ms max programmed via PRE3–0 in WDCON
LOGIC INPUTS
INPUT VOLTAGES

14

All Inputs except SCLOCK, RESET, and
XTAL1

V

, Input Low Voltage 0.8 0.4 V max

INL

V

, Input High Voltage 2.0 2.0 V min

INH

range

REF

range

REF

= 2.5 V

REF

= VDD

REF

Full-scale settling time to within ½ LSB of final
value

measured at the C

REF

REF

pin

Internal band gap reference deselected via
ADCCON2.6

Rev. A | Page 5 of 72

ADuC814

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions

SCLOCK and RESET Only14
(Schmitt-Triggered Inputs)

VT+ 1.3 0.95 V min

3.0 2.5 V max
V

0.8 0.4 V min

T–

1.4 1.1 V max
V

– V

0.3 0.3 V min

T+

T–

0.85 0.85 V max

INPUT CURRENTS

P1.2–P1.7, DLOAD ±10 ±10 µA max VIN = 0 V or VDD
SCLOCK15 –10 –3 µA min VIN = 0 V, internal pull-up
–40 –15 µA max VIN = 0 V, internal pull-up
±10 ±10 µA max VIN = VDD
RESET ±10 ±10 µA max VIN = 0 V
20 10 µA min VIN = 5 V, 3 V internal pull-down
105 35 µA max VIN = 5 V, 3 V internal pull-down
P1.0, P1.1, Port 315 ±10 ±10 µA max VIN = 5 V, 3 V

(includes MISO, MOSI/SDATA and
–180 –70 µA min VIN = 2 V, VDD = 5 V, 3 V
–660 –200 µA max
–360 –100 µA typ
–20 –5 µA min VIN = 450 mV, VDD = 5 V, 3 V
–75 –25 µA max

–38 –12 µA typ
INPUT CAPACITANCE 5 5 pF typ All digital inputs
CRYSTAL OSCILLATOR

(XTAL1 AND XTAL2)

Logic Inputs, XTAL1 Only

V

, Input Low Voltage 0.8 0.4 V typ

INL

V

, Input High Voltage 3.5 2.5 V typ

INH

XTAL1 Input Capacitance 18 18 pF typ

XTAL2 Output Capacitance 18 18 pF typ
DIGITAL OUTPUTS

Output High Voltage (VOH) 2.4 2.4 V min I

Output Low Voltage (VOL)

Port 1.0 and Port 1.1 0.4 0.4 V max I

Port 1.0 and Port 1.1 0.4 0.4 V max I

SCLOCK, MISO/MOSI 0.4 0.4 V max I

All Other Outputs 0.4 0.4 V max I
MCU CORE CLOCK

MCU Clock Rate 131.1 131.1 kHz min

16.78 16.78 MHz max

START UP TIME

At Power-On 500 500 ms typ

From Idle Mode 100 100 µs typ

From Power-Down Mode

Oscillator Running OSC_PD = 0 in PLLCON SFR

I

Wake-Up with

NT0

Interrupt
Wake-Up with SPI/I2C Interrupt 100 100 µs typ
Wake-Up with TIC Interrupt 100 100 µs typ
Wake-Up with External RESET 3 3 ms typ

1 1 µA typ

S

S

)

100 100 µs typ

= 80 mA

SOURCE

= 10 mA, T

SINK

= 10 mA, T

SINK

= 4 mA

SINK

= 1.6 mA

SINK

= 85°C

MAX

= 125°C

MAX

Clock rate generated via on-chip PLL,
programmable via CD2-0 in PLLCON

Rev. A | Page 6 of 72

ADuC814

Parameter VDD = 5 V VDD = 3 V Unit Test Conditions

Oscillator Powered Down16 OSC_PD = 1 in PLLCON SFR

I

Wake-Up with

NT0

Interrupt
Wake-Up with SPI/I2C Interrupt 150 400 ms typ
Wake-Up with External RESET 150 400 ms typ

After External RESET in Normal Mode 3 3 ms typ
After WDT Reset in Normal Mode 3 3 ms typ Controlled via WDCON SFR

FLASH/EE MEMORY RELIABILITY
CHARACTERISTICS

17

Endurance18 100,000 100,000 Cycles min
Data Retention19 100 100 Years min

POWER REQUIREMENTS

20, 21

Power Supply Voltages

AVDD/DVDD – AGND 2.7 V min AVDD/DVDD = 3 V nom

3.3 V max

4.5 V min AVDD/DVDD = 5 V nom

5.5 V max
Power Supply Currents, Normal Mode

D

Current14 5 2.5 mA max Core CLK = 2.097 MHz

VDD

4 2 mA typ (CD bits in PLLCON = 3)
A

Current14 1.7 1.7 mA max

VDD

D

Current 20 10 mA max Core CLK = 16.78MHz (max)

VDD

16 8 mA typ (CD bits in PLLCON = 0)
A

Current 1.7 1.7 mA max

VDD

D

Current14 3.5 1.5 mA max Core CLK = 131.2 kHz (min)

VDD

2.8 1.2 mA typ (CD bits in PLLCON = 7)
A

Current 1.7 1.7 mA max

VDD

Power Supply Currents, Idle Mode

D

Current14 1.7 1.2 mA max Core CLK = 2.097 MHz

VDD

1.5 1 mA typ (CD Bits in PLLCON = 3)
AVDD Current14 0.15 0.15 mA max
DVDD Current14 6 3 mA max Core CLK = 16.78 MHz (max)
4 2.5 mA typ (CD bits in PLLCON = 0)
AVDD Current14 0.15 0.15 mA max
DVDD Current14 1.25 1 mA max Core CLK = 131 kHz (min)

1.1 0.7 mA typ (CD bits in PLLCON = 7)
AVDD Current14 0.15 0.15 mA max

Power Supply Currents, Power-Down
Mode

DVDD Current14 20 µA max Oscillator on
40 14 µA typ
AVDD Current 1 1 µA typ
DVDD Current 15 µA max Oscillator off
20 10 µA typ
AVDD Current 1 1 µA typ

Typical Additional Power Supply
Currents

PSM Peripheral 50 µA typ
ADC 1.5 mA typ
DAC 150 µA typ

150 400 ms typ

Core CLK = 2.097 MHz or 16.78 MHz (CD bits in
PLLCON = 3 or 0)

Core CLK = 2.097 MHz, (CD bits in PLLCON = 3)
AV

= DVDD = 5 V

DD

Rev. A | Page 7 of 72

ADuC814

1

Temperature range –40ºC to +125ºC.

2

ADC linearity is guaranteed when operating in nonpipelined mode, i.e., ADC conversion followed sequentially by a read of the ADC result. ADC linearity is also

guaranteed during normal MicroConverter core operation.

3

ADC LSB size = V

4

Offset and gain error and offset and gain error match are measured after factory calibration.

5

Based on external ADC system components the user may need to execute a system calibration to remove additional external channel errors

and achieve these specifications.

6

Measured with coherent sampling system using external 16.77 MHz clock via P3.5 (Pin 22).

7

SNR calculation includes distortion and noise components.

8

Channel-to-channel crosstalk is measured on adjacent channels.

9

The temperature monitor gives a measure of the die temperature directly; air temperature can be inferred from this result.

10

DAC linearity is calculated using a reduced code range of 48 to 4095, 0 V to V

and 100 pF.

11

DAC differential nonlinearity specified on 0 V to V

12

Measured with V

capacitor chosen for both the V

13

When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the V

need to be shorted together for correct operation.

14

These numbers are not production tested but are guaranteed by design and/or characterization data on production release.

15

Pins configured in I2C compatible mode or SPI mode; pins configured as digital inputs during this test.

16

These typical specifications assume no loading on the XTAL2 pin. Any additional loading on the XTAL2 pin increases the power-on times.

17

Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.

18

Endurance is qualified to 100 kcycles as per JEDEC Std. 22, Method A117 and measured at –40ºC, +25°C, and +125°C; typical endurance at +25°C is 700 kcycles.

19

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV

derates with junction temperature as shown in Figure 33 in the Flash/EE memory description section.

20

Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions:

Core execution suspended in power-down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR.

21

DVDD power supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.

/212, i.e., for internal V

REF

and C

REF

pins decoupled with 0.1 µF capacitors to ground. Power-up time for the internal reference is determined by the value of the decoupling

REF

REF

= 2.5 V, 1 LSB = 610 µV, and for external V

REF

and 0 to VDD ranges.

REF

and C

pins.

REF

= 1 V, 1 LSB = 244 µV.

REF

range; a reduced code range of 48 to 3950, 0 V to VDD range. DAC output load = 10 kΩ

REF

and C

REF

REF

Normal Mode: Reset and all digital I/O pins = open circuit, core Clk changed via CD bits in PLLCON, core executing internal software loop.
Idle Mode: Reset and all digital I/O pins = open circuit, core Clk changed via CD bits in PLLCON, PCON.0 = 1, core execution suspended in idle mode.
Power-Down Mode: Reset and all P1.2–P1.7 pins = 0.4 V; all other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1,

pins

Rev. A | Page 8 of 72

ADuC814

ABSOLUTE MAXIMUM RATINGS

Table 2. Temperature = 25°C, unless otherwise noted

Parameter Rating

AVDD to AGND –0.3 V to +7 V
DVDD to AGND –0.3 V to +7 V
AVDD to DVDD –0.3 V to +0.3 V
AGND to DGND1 –0.3 V to +0.3 V
Analog Input Voltage to AGND2 –0.3 V to AVDD + 0.3 V
Reference Input Voltage to AGND –0.3 V to AVDD + 0.3 V
Analog Input Current (Indefinite) 30 mA
Reference Input Current (Indefinite) 30 mA
Digital Input Voltage to DGND –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND –0.3 V to DVDD + 0.3 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 97.9°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

1

AGND and DGND are shorted internally on the ADuC814.

2

Applies to Pins P1.2 to P1.7 operating in analog or digital input mode.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 9 of 72

ADuC814

PIN CONFIGURATION AND FUNCTION DESCRIPTION

DGND

1

DLOAD

2

P3.0/RxD

P3.1/TxD
P3.2/INT0
P3.3/INT1

P3.4/T0/CONVST

P1.1/T2EX

P1.2/ADC0
P1.3/ADC1

P1.0/T2

RESET

AV

AGND

DD

3
4
5
6

ADuC814

7

TOP VIEW

8

(Not to Scale)

9
10
11
12
13
14

Figure 2. Pin Configuration

Table 3. Pin Descriptions

Pin No. Mnemonic Type Function

1 DGND S Digital Ground. Ground reference point for the digital circuitry.
2 DLOAD I

Debug/Serial Download Mode. Enables when pulled high through a resistor on power-on or RESET. In
this mode, DLOAD may also be used as an external emulation I/O pin, therefore the voltage level at
this pin must not be changed during this mode of operation because it may cause an emulation
interrupt that halts code execution. User code is executed when this pin is pulled low on power-on or
RESET.

3–7 P3.0 – P3.4 I/O

Bidirectional Port Pins with Internal Pull-Up Resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs,
with Port 3 pins being pulled low externally, they source current because of the internal pull-up
resistors. When driving a 0-to-1 output transition, a strong pull-up is active during S1 of the

instruction cycle. Port 3 pins also have various secondary functions which are described next.
3 P3.0/RxD I/O Receiver Data Input (asynchronous) or Data Input/Output (synchronous) in Serial (UART) Mode.
4 P3.1/TxD I/O Transmitter Data Output (asynchronous) or Clock Output (synchronous) in Serial (UART) Mode.
5

P3.2/

INT0

I/O

Interrupt 0, programmable edge or level-triggered interrupt input, which can be programmed to one

of two priority levels. This pin can also be used as agate control input to Timer 0.
6

P3.3/

INT1

I/O

Interrupt 1, programmable edge or level-triggered interrupt input, which can be programmed to one

of two priority levels. This pin can also be used as agate control input to Timer 1.
7

P3.4/T0/
CONVST

8–9 P1.0–P1.1 I/O

I/O Timer/Counter 0 Input and External Trigger Input for ADC Conversion Start.

Bidirectional Port Pins with Internal Pull-Up Resistors. Port 1 pins that have 1s written to them are

pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs

,with Port 1 pins being pulled low externally, they source current because of the internal pull-up

resistors When driving a 0-to-1 output transition a strong pull-up is active during S1 of the instruction

cycle. Port 1 pins also have various secondary functions which are described as follows.
8 P1.0/T2 I/O

Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response

to a 1 to 0 transition of the T2 input.
9 P1.1/T2EX I/O Digital Input. Capture/Reload trigger for Counter 2.
10 RESET I

Reset Input. A high level on this pin while the oscillator is running resets the device. There is an

internal weak pull-down and a Schmitt-trigger input stage on this pin.
11–12 P1.2–P1.3 I

Port 1.2 to P1.3. These pins have no digital output drivers, i.e., they can only function as digital inputs,

for which 0 must be written to the port bit. These port pins also have the following analog functionality:
11 P1.2/ADC0 I ADC Input Channel 0. Selected via ADCCON2 SFR.
12 P1.3/ADC1 I ADC Input Channel 1. Selected via ADCCON2 SFR.
13 AVDD S Analog Positive Supply Voltage, 3 V or 5 V.
14–15 AGND G Analog Ground. Ground reference point for the analog circuitry.
16 V

I/O

REF

Reference Input/Output. This pin is connected to the internal reference through a switch and is the

reference source for the analog to digital converter. The nominal internal reference voltage is 2.5 V

and this appears at the pin. This pin can be used to connect an external reference to the analog to

digital converter by setting ADCCON1.6 to 1. Connect 0.1 µF between this pin and AGND.

DV

28

DD

XTAL2

27
26

XTAL1

25

SCLOCK

24

P3.7/SDATA/MOSI
P3.6/MISO

23
22

P3.5/T1/SS/EXTCLK

21

P1.7/ADC5/DAC1

20

P1.6/ADC4/DAC0
P1.5/ADC3

19

P1.4/ADC2

18
17

C

REF

V

16

REF

AGND

15

02748-A-009

Rev. A | Page 10 of 72

ADuC814

Pin No. Mnemonic Type Function

17 C
18–21 P1.4–P1.7 I

18 P1.4/ADC2 I ADC Input Channel 2. Selected via ADCCON2 SFR.
19 P1.5/ADC3 I ADC Input Channel 2. Selected via ADCCON2 SFR.
20

21

22–24 P3.5–P3.7 I/O

22 P3.5/T1

22

23 P3.6/MISO I/O SPI Master Input/Slave Output Data Input/Output Pin.
24

25 SCLOCK I/O Serial Clock Pin for SPI Serial Interface Clock.
26 XTAL1 I Input to the Crystal Oscillator Inverter.
27 XTAL2 O Output from the Crystal Oscillator Inverter.
28 DVDD S Analog Positive Supply Voltage, 3 V or 5 V.

I = Input, O = Output, S = Supply, G - Ground.

I Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND.

REF

Port 1.4 to P1.7. These pins have no digital output drivers, i.e., they can only function as digital inputs,
for which 0 must be written to the port bit. These port pins also have the following analog functionality:

P1.6/ADC4/
DAC0

P1.7/
ADC5/DAC1

SS

P3.5/
/EXTCLK

P3.7/SDATA/
MOSI

I/O

I/O

I/O

I/O SPI Master Output/Slave Input Data Input/Output Pin.

ADC Input Channel 4. Selected via ADCCON2 SFR. The voltage DAC Channel 0 can also be configured
to appear on P1.6.

ADC Input Channel 5, selected via ADCCON2 SFR. The voltage DAC Channel 1 can also be configured
to appear on P1.7.

Bidirectional Port Pins with Internal Pull-Up Resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs
,with Port 3 pins being pulled low externally, they source current because of the internal pull-up
resistors. When driving a 0-to-1 output transition a strong pull-up is active during S1 of the instruction
cycle. Port 3 pins also have various secondary functions which are described as follows.

I/O Timer/Counter 1 Input. P3.5–P3.7 pins also have SPI interface functions. To enable these functions,
Bit 0 of the CFG814 SFR must be set to 1.

This pin also functions as the Slave Select input for the SPI interface when the device is operated in
slave mode. P3.5 can also function as an input for an external clock. This clock effectively bypasses the
PLL. This function is enabled by setting Bit 1 of the CFG814 SFR.

The following notes apply to the entire data sheet:

• In bit designation tables, set implies a Logic 1 state, and cleared implies a Logic 0 state, unless otherwise stated.

• Set and cleared also imply that the bit is set or cleared by the ADuC814 hardware, unless otherwise stated.

• User software should not write to reserved or unimplemented bits as they may be used in future products.

Rev. A | Page 11 of 72

ADuC814

TERMINOLOGY

ADC SPECIFICATIONS

Integral Nonlinearity

This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a
point1/2 LSB below the first code transition and full scale, a
point 1/2 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (0000 … 000) to
(0000 … 001) from the ideal, i.e., +1/2 LSB.

DAC SPECIFICATIONS

Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error.

Voltage Output Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-sec.

Full-Scale Error

This is the deviation of the last code transition from the ideal
AIN voltage (full-scale error has been adjusted out).

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by

Signal-to =- (Noise + Distortion) = (6.02N + 1.76)

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of the
harmonics to the fundamental.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
the noise peak.

/2 and including dc) to the rms value of the

S

/2), excluding dc.

S

Rev. A | Page 12 of 72

ADuC814

TYPICAL PERFORMANCE CURVES

The typical performance plots presented in this section
illustrate typical performance of the ADuC814 under various
operating conditions. Note that all typical plots in this section
were generated using the ADuC814BRU, i.e., the B-grade part.

Figure 3 and Figure 4 show typical ADC integral nonlinearity
(INL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V
supplies, respectively. The ADC is using its internal reference
(2.5 V) and operating at a sampling rate of 152 kHz. The typical
worst-case errors in both plots are just less than 0.3 LSBs.

0.4
AVDD/DVDD = 5V

f

= 152kHz

S

0.3

0.2

0.1

0

LSBs

–0.1

–0.2

–0.3

–0.4

LSBs

–0.1

–0.2

–0.3

–0.4

0

0.4
AVDD/DVDD = 3V

f

0.3

0.2

0.1

0

0

1023511 35833071255920471535 4095

Figure 3. Typical I NL Error, V

ADC CODES

DD

= 5 V

= 152kHz

S

1023511 35833071255920471535 4095

Figure 4. Typical I NL Error, V

ADC CODES

DD

= 3 V

02748-A-010

02748-A-011

Figure 5 and Figure 6 show the variation in worst-case positive
(WCP) INL and worst-case negative (WCN) INL versus
external reference input voltage.

1.2

1.0

0.8

0.6

0.4

0.2

WCP–INL (LSBs)

0

–0.2

–0.4

–0.6

0.5 1.0 1.5 2.0 2.5 5.0
EXTERNAL REFERENCE (V)

Figure 5. Typical Worst-Case INL Error vs. V

0.8

0.6

0.4

0.2

0

–0.2

WCP–INL (LSBs)

–0.4

–0.6

–0.8

0.5 1.5 2.5

EXTERNAL REFERENCE (V)

Figure 6. Typical Worst-Case INL Error vs. V

AVDD/DVDD = 5V

f

= 152kHz

S

WCP INL

WCN INL

, VDD = 5 V

REF

AVDD/DVDD = 3V

f

= 152kHz

S

WCP INL

WCN INL

3.02.01.0

, VDD = 3 V

REF

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

WCN–INL (LSBs)

02748-A-012

WCN–INL (LSBs)

02748-A-013

Figure 7 and Figure 8 show typical ADC differential nonlinearity
(DNL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V
supplies, respectively. The ADC is using its internal reference
(2.5 V) and operating at a sampling rate of 152 kHz. The typical
worst-case errors in both plots are just less than 0.2 LSBs.

Rev. A | Page 13 of 72

ADuC814

0.30

0.25

0.20

0.15

0.10

0.05
0

LSBs

–0.50
–0.10

–0.15

AVDD/DVDD = 5V

–0.20

f

= 152kHz

S

–0.25

0

1023511 35833071255920471535 4095

Figure 7. Typical DNL Error, V

ADC CODES

DD

= 5 V

02748-A-014

0.30

AVDD/DVDD = 3V

0.25

f

= 152kHz

S

0.20

0.15

0.10

0.05
0

LSBs

–0.50
–0.10

–0.15
–0.20

–0.25

0

1023511 35833071255920471535 4095

Figure 8. Typical DNL Error, V

ADC CODES

DD

= 3 V

02748-A-015

Figure 9 and Figure 10 show the variation in worst-case positive
(WCP) DNL and worst-case negative (WCN) DNL versus
external reference input voltage.

0.6

0.4

0.2

0

WCP–DNL (LSBs)

–0.2

–0.4

–0.6

0.5

1.0 2.0 2.5 5.0

1.5

EXTERNAL REFERENCE (V)

Figure 9. Typical Worst-Case DNL Error vs. V

AVDD /DVDD = 5V

f

= 152kHz

S

WCP DNL

WCN DNL

, VDD = 5 V

REF

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

WCN–DNL (LSBs)

02748-A-016

0.7

0.5

0.3

0.1

–0.1

WCP–DNL (LSBs)

–0.3

–0.5

–0.7

0.5 1.0 1.5 2.0 2.5 3.0
EXTERNAL REFERENCE (V)

Figure 10. Typical Worst-Case DNL Error vs. V

AVDD/DVDD= 3V

f

= 152kHz

S

WCP DNL

WCN DNL

, VDD = 3 V

REF

0.7

0.5

0.3

0.1

–0.1

–0.3

–0.5

–0.7

WCN–DNL (LSBs)

02748-A-017

Figure 11 shows a histogram plot of 10,000 ADC conversion
results on a dc input with V

= 5 V. The plot illustrates an

DD

excellent code distribution pointing to the low noise
performance of the on-chip precision ADC.

10000

8000

6000

4000

OCCURRENCE

2000

0

817 818 819 820 821

Figure 11. Code Histogram plot, V

CODE

DD

= 5 V

02748-A-018

Figure 12 shows a histogram plot of 10,000 ADC conversion
results on a dc input for V

= 3 V. The plot again illustrates a

DD

very tight code distribution of 1 LSB with the majority of codes
appearing in one output bin.

10000

9000

8000

7000

6000

5000

4000

OCCURRENCE

3000

2000

1000

0

817 818 819 820 821

CODE

Figure 12. Code Histogram Plot, V

DD

= 3 V

02748-A-019

Rev. A | Page 14 of 72

ADuC814

Figure 13 and Figure 14 show typical FFT plots for the ADuC814.
These plots were generated using an external clock input via
P3.5 to achieve coherent sampling. The ADC is using its internal
reference (2.5 V) sampling a full-scale, 10 kHz sine wave test
tone input at a sampling rate of 149.79 kHz. The resultant FFTs
shown at 5 V and 3 V supplies illustrate an excellent 100 dB
noise floor, a 71 dB signal-to-noise ratio (SNR), and a THD
greater than −80 dB.

20

0

–20

–40

–60

dBs

–80

–100

–120

–140

–160

20

1007060504030

FREQUENCY (kHz)

Figure 13. ADuC814 Dynamic Performance at V

20

0

–20

–40

–60

dBs

–80

–100

–120

–140

–160

20

1007060504030

FREQUENCY (kHz)

Figure 14. ADuC814 Dynamic Performance at V

AVDD/DVDD = 5V
f

= 149.79kHz

S

= 9.910kHz

f

IN

SNR = 71.3dB
THD = –88.0dB
ENOB = 11.6

= 5 V

DD

AVDD/DVDD = 3V

= 149.79kHz

f

S

= 9.910kHz

f

IN

SNR = 71.3dB
THD = –88.0dB
ENOB = 11.6

= 3 V

DD

02748-A-020

02748-A-021

Figure 15 and Figure 16 show typical dynamic performance
versus external reference voltages. Again excellent ac performance
can be observed in both plots with some roll-off being observed
as V

falls below 1 V.

REF

THD

–70

–75

–80

–85

–90

–95

–100

–70

–75

–80

–85

–90

–95

–100

THD (dBs)

THD (dBs)

02748-A-023

80

75

70

65

SNR (dBs)

60

55

50

0.5

1.0 2.0 2.5 5.0

1.5

EXTERNAL REFERENCE (V)

Figure 15. Typical Dynamic Performance vs. V

80

75

70

65

SNR (dBs)

60

55

50

0.5 1.5 2.5

1.0 2.0 3.0
EXTERNAL REFERENCE (V)

Figure 16. Typical Dynamic Performance vs. V

AVDD/DVDD = 5V

f

= 152kHz

S

SNR

THD

, VDD = 5 V

REF

AVDD/DVDD = 3V

f

= 152kHz

S

SNR

, VDD = 3 V

REF

02748-A-022

Rev. A | Page 15 of 72

ADuC814

ADuC814 ARCHITECTURE, MAIN FEATURES

The ADuC814 is a fully integrated 247 kSPS 12-bit data
acquisition system incorporating a high performance multi­channel ADC, an 8-bit MCU, and program/data Flash/EE
memory on a single chip.

This low power device operates from a 32 kHz crystal with an
on-chip PLL generating a high frequency clock of 16.78 MHz.
This clock is, in turn, routed through a programmable clock
divider from which the MCU core clock operating frequency is
generated.

The microcontroller core is an 8052, and therefore 8051,
instruction set compatible. The microcontroller core machine
cycle consists of 12 core clock periods of the selected core
operating frequency. Eight kbytes of nonvolatile Flash/EE
program memory are provided on-chip. 640 bytes of nonvolatile
Flash/EE data memory and 256 bytes RAM are also integrated
on-chip.

The ADuC814 also incorporates additional analog functionality
with dual 12-bit DACs, a power supply monitor, and a band gap

)

)

0

1

C

C

A

A

D

)

)

)

X

)

E

2

2

T

T

(

(

0

1

.

.

1

1

P

P

)

1

0

2

N

N

N

I

I

I

A

A

A

(

(

(

3

2

4

.

.

.

1

1

1

P

P

P

D

)

/

/

3

4

5

N

N

N

I

I

I

A

A

A

(

(

(

5

6

7

.

.

.

1

1

1

P

P

P

reference. On-chip digital peripherals include a watchdog timer,
time interval counter, three timer/counters, and three serial I/O

2

ports (SPI, UART, I

C).

On-chip factory firmware supports in-circuit serial download
and debug modes (via UART), as well as single-pin emulation
mode via the DLOAD pin. A detailed functional block diagram
of the ADuC814 is shown in Figure 17.

The ADuC814 is supported by a QuickStart

Development

System. This is a full-featured, low cost system, consisting of
PC-based (Windows compatible) hardware and software
development tools.

The part operates from a single 3 V or 5 V supply. When
operating from 3 V supplies, the power dissipation for the part
is below 10 mW. The ADuC814 is housed in a 28-lead TSSOP
package and is specified for operation over an extended
temperature range −40°C to +125°C.

)
K
L

)

C

1

T

D

)

/

X

)

)

)

)

1

0

D

D

X

X
T

R

(

(

0

1

.

.

3

3

P

P

)

T

T

0

N

N

I

I

T

(

(

(

3

2

4

.

.

.

3

3

3

P

P

P

I

O

E

S

/

S

I

O

S
S

M

M

(

(

(

5

6

7

.

.

.

3

3

3

P

P

P

ADC0

ADC5

V

REF

C

REF

11

21

16

17

DD

AV

AIN

T/H

MUX

TEMP MONITOR
DAC0
DAC1
V

REF

AGND

BAND GAP

REFERENCE

BUF

DD

DV

AGND

AGND

POR

ADuC814

DAC0

DAC1

T0
T1
T2
T2EX

INT0

INT1
D0
D1

02748-A-024

256 × 8

TIMER

MISO

SS

DAC0

DAC1

PROG.
CLOCK

DIVIDER

ADC

12-BIT

ADC

DOWNLOADER

ASYNCHRONOUS

SERIAL PORT

(UART)

D
N
G
D

RESET

RxD

CONTROL

640 × 8

DATA

FLASH/EE

8k × 8

PROGRAM

FLASH/EE

DEBUGGER

TxD

AND
CAL

LOGIC

8052
MCU

CORE

SINGLE-PIN

EMULATOR

DLOAD

DAC

CONTROL

LOGIC

POWER SUPPLY

SPI SERIAL
INTERFACE

0
D

/
K
C
O
L
C
S

USER RAM

WATCHDOG

MONITOR

1
D

/

I
S
O

M

16-BIT

COUNTER

TIMERS

TIME
INTERVAL
COUNTER

OSC
AND

PLL

XTAL1

XTAL2

BUF

BUF

Figure 17. ADuC814 Block Diagram

Rev. A | Page 16 of 72

ADuC814

MEMORY ORGANIZATION

The ADuC814 does not have Port 0 and Port 2 pins and
therefore does not support external program or data memory
interfaces. The device executes code from the internal 8-kByte
Flash/EE program memory. This internal code space can be
programmed via the UART serial port interface while the device
is in-circuit. The program memory space of the ADuC814 is
shown in Figure 18.

PROGRAM MEMORY SPACE

READ-ONLY

1FFFH

INTERNAL

8 kBYTE

FLASH/EE

PROGRAM

MEMORY

0000H

02748-A-025

Figure 18. Program Memory Map

The data memory address space consists of internal memory
only. The internal memory space is divided into four physically
separate and distinct blocks, namely the lower 128 bytes of
RAM, the upper 128 bytes of RAM, the 128 bytes of special
function register (SFR) area, and a 640-byte Flash/EE data
memory. While the upper 128 bytes of RAM and the SFR area
share the same address locations, they are accessed through
different addressing modes.

The lower 128 bytes of data memory can be accessed through
direct or indirect addressing, the upper 128 bytes of RAM can
be accessed through indirect addressing, and the SFR area is
accessed through direct addressing.

Also, as shown in Figure 19, an additional 640 bytes of Flash/EE
data memory are available to the user and can be accessed
indirectly via a group of control registers mapped into the SFR
area. Access to the Flash/EE data memory is discussed in detail
later as part of the Flash/EE Memory section.

9FH

00H

UPPER

128

LOWER

128

The lower 128 bytes of internal data memory are mapped as
shown in Figure 20. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 to R7. The next 16 bytes
(128 bits), locations 20H to 2FH above the register banks, form
a block of directly addressable bit locations at bit addresses 00H
through 7FH. The stack can be located anywhere in the internal
memory address space, and the stack depth can be expanded up
to 256 bytes.

BANKS

SELECTED

VIA

BITS IN PSW

11

10

01

00

Figure 20. Lower 128 Bytes of Internal Data Memory

DATA MEMORY SPACE

READ/WRITE

(PAGE 159)

640 BYTES

FLASH/EE DATA

MEMORY

ACCESSED

INDIRECTLY

VIA SFR

CONTROL REGISTERS

(PAGE 0)

INTERNAL

DATA MEMORY

SPACE

FFH

80H
7FH

AND INDIRECT

00H

ACCESSIBLE

BY

INDIRECT

ADDRESSING

ONLY

ACCESSIBLE

BY

DIRECT

ADDRESSING

SPECIAL

FUNCTION

REGISTERS

ACCESSIBLE

BY DIRECT

ADDRESSING

ONLY

Figure 19. Data Memory Map

7FH

30H

2FH

20H

18H

10H

08H

00H

1FH

17H

0FH

07H

FFH

80H

02748-A-026

GENERAL-PURPOSE
AREA

BIT-ADDRESSABLE
BIT ADDRESSES

FOUR BANKS OF EIGHT
REGISTERS
R0 R7

RESET VALUE OF
STACK POINTER

02748-A-027

RESET initializes the stack pointer to location 07H and incre­ments it once to start from location 08H, which is also the first
register (R0) of Register Bank 1. If more than one register bank
is being used, the stack pointer should be initialized to an area
of RAM not used for data storage.

Rev. A | Page 17 of 72

ADuC814

The SFR space is mapped to the upper 128 bytes of internal
data memory space and is accessed by direct addressing only. It
provides an interface between the CPU and all on-chip periph­erals. A block diagram showing the programming model of the
ADuC814 via the SFR area is shown in Figure 21. A complete
SFR map is shown in Figure 22.

640-BYTE

8-kBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

MEMORY

8051

COMPATIBLE

CORE

256 BYTES

RAM

128-BYTE

SPECIAL
FUNCTION
REGISTER

AREA

Figure 21. Programming Model

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

6-CHANNEL

12-BIT SAR ADC

OTHER ON-CHIP

PERIPHERALS

TEMPERATURE

MONITOR

DUAL 12-BIT DAC

SERIAL I/O

WDT
PSM

TIC

PLL

02748-A-028

Program Status Word SFR

The program status word (PSW) register is the program status word that contains several bits reflecting the current status of the CPU as
detailed in Table 4.

OVERVIEW OF MCU-RELATED SFRS

Accumulator SFR

ACC is the accumulator register and is used for math operations
including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the accumulator as A.

B SFR

The B register is used with the ACC for multiplication and
division operations. For other instructions it can be treated as a
general-purpose scratchpad register.

Stack Pointer SFR

The SP register is the stack pointer and is used to hold an internal
RAM address called the top of the stack. The SP register is
incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.

Data Pointer

The data pointer is made up of two 8-bit registers, named DPH
(high byte) and DPL (low byte). These registers provide memory
addresses for internal code access. The pointer may be manipu­lated as a 16-bit register (DPTR = DPH, DPL), or as two inde­pendent 8-bit registers (DPH, DPL).

SFR Address D0H
Power-On Default 00H
Bit Addressable Yes

CY AC F0 RS1 RS0 OV F1 P

Table 4. PSW SFR Bit Designations

Bit No. Name Description

7 CY Carry Flag.
6 AC Auxiliary Carry Flag.
5 F0 General-Purpose Flag.
4 RS1 Register Bank Select Bits.
3 RS0 RS1 RS0 Selected Bank

0 0 0
0 1 1
1 0 2

1 1 3
2 OV Overflow Flag.
1 F1 General-Purpose Flag.
0 P Parity Bit.

Rev. A | Page 18 of 72

ADuC814

Power Control SFR

The power control (PCON) register contains bits for power-saving options and general-purpose status flags as shown in Table 5.

SFR Address 87H
Power-On Default 00H
Bit Addressable No

SMOD SERIPD INT0PD --- GF1 GF0 PD IDL

Table 5. PCON SFR Bit Designations

Bit No. Name Description

7 SMOD Double UART Baud Rate.
6 SERIPD SPI Power-Down Interrupt Enable.
5 INT0PD

4 RSVD Reserved.
3 GF1 General-Purpose Flag Bit.
2 GF0 General-Purpose Flag Bit.
1 PD Power-Down Mode Enable.
0 IDL Idle Mode Enable.

Power-Down Interrupt Enable.

INT0

Rev. A | Page 19 of 72

ADuC814

SPECIAL FUNCTION REGISTERS

All registers, except the program counter and the four general­purpose register banks, reside in the SFR area. The SFR registers
include control, configuration, and data registers that provide an
interface between the CPU and all on-chip peripherals.

Figure 22 shows a full SFR memory map and SFR contents on
RESET; NOT USED indicates unoccupied SFR locations.

ISPI

WCOL

SPE

SPIM

CPOL

CPHA

FFH

0

FEH 0

FDH 0

FCH 0

FBH 0

F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H F1H 0 F0H 0

D1EN D0EN

D1

EFH

0

EEH 0D0EDH 0 ECH 0 EBH 0 EAH E9H 0 E8H 0

E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H E1H 0 E0H 0

ADCI

ADCSPI

CCONV

DFH

0

DEH 0

CY

D7H 0ACD6H 0F0D5H 0

TF2

EXF2

CFH 0

CEH 0

PRE3

PRE2

C7H 0

C6H 0

PSI

PADC

BFH 0

BEH 0

RD

B7H 1WRB6H 1T1B5H 1T0B4H 1

EA

EADC

AFH

AEH

00

0

SM0

TF1

SM1

9EH 0

TR1

8EH 0

9FH 0

97H 1 96H 1 95H 1 94H 1 93H 1 92H

8FH 0

SCONV

DDH 0

DCH 0

D4H 0

RCLK

CDH 0

CCH 0

PRE1

C5H 0 C4H 1

PT2

BDH 0PSBCH 0

ET2

ADHESACH 0

SM2

9DH 0

9CH 0

TF0

8DH 0

8CH 0

CS3

DBH 0

RS1

RS0

D3H 0OVD2HFID1H 0PD0H 0

TCLK

EXEN2

CBH 0

WDIR

PRE0

C3H 0

PT1

BBH 0

INT1

B3H 1

ET1

ABH 0

REN

TB8

9BH 0

TR0

IE1

8BH 0

SPR1

FAH

F9H 0

1

0

0

0

CS2

CS1

0

DAH

D9H 0

0

TR2

CNT2

0

CAH

C9H 0

WDS

0

C2HWDC1H 0

PX1

PT0

BAH

B9H 0

0

INT0

TxD

B2H

B1H 1

1

EX1

ET0

AAH

A9H 0

0

RB8

0

9AHTI99H 0RI98H 0

T2EX

1

91H 1T290H 1

IT1

IE0

0

8AH

89H 0

SPR0

F8H

CS0

D8H

CAP2

C8H 0

WDWR

C0H 0

PX0

B8H 0

RxD

B0H 1

EX0

A8H 0

IT0

88H 0

5

BITS

0

BITS

BITS

BITS

BITS

0

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

BITS

Unoccupied locations in the SFR address space are not
implemented, i.e., no register exists at this location. If an
unoccupied location is read, an unspecified value is returned.
SFR locations reserved for future use are shaded (RESERVED)
and should not be accessed by the user software.

1

SPICON

F8H

F0H 00H

DCON

E8H 00H

ACC

E0H 00H

ADCCON2

D8H 00H

PSW

D0H 00H

T2CON

C8H 00H

WDCON

C0H 10H

B8H 00H

B0H FFH

A8H 00H

NOT USED NOT USED

SCON

98H 00H

P1

90H FFH

TCON

88H 00H

NOT USED

IP

P3

IE

B

1,2

04H

1

1

1

1

1

1

1

1

1

1

DAC0L

F9H 00H

ADCOFSL

F1H 00H

1

ADCDATAL

D9H 00H

RESERVED

1

RESERVED

ECON

B9H 00H

IEIP2

A9H A0H

TIMECON

A1H

SBUF

99H 00H

TMOD

89H 00H

81H 07H

DAC0H

FAH 00H

ADCOFSH

F2H 20H

ADCDA T AH

DAH 00H

RCAP2L

CAH 00H

CHIPID

C2H 0XH

ETIM1

BAH 00H

RESERVEDRESERVED RESERVED

RESERVED RESERVED

HTHSEC

A2H A3H A4H

00H 00H 00H 00H

I2CDAT

9AH 00H

TL0

8AH 00H

SP

DPL

82H 00H

DAC1L

FBH 00H

ADCGAINL

F3H 00H

RESERVEDRESERVED

RCAP2H

CBH 00H

RESERVED

ETIM2

BBH 00H

SEC

I2CADD

9BH 55H

TL1

8BH 00H

DPH

83H 00H

DAC1H

FCH 00H

ADCGAINH

F4H 00H

CCH 00H

NOT USED

EDATA1

BCH 00H

RESERVED RESERVED

RESERVED RESERVED

TL2

MIN

DACCON

FDH 04H

ADCCON3

F5H 00H

RESERVEDRESERVEDRESERVEDRESERVEDRESERVED

RESERVEDRESERVEDRESERVEDRESERVEDRESERVED

RESERVEDRESERVEDRESERVED

RESERVEDRESERVEDRESERVED

TH2

CDH 00H

RESERVED

EDATA2

BDH 00H

HOUR IN TV A L

A5H

00H 00H

CFG814

9CH 04H

NOT USEDNOT USEDNOT USEDNOT USEDNOT USED

TH0

8CH 00H

RESERVED

TH1

8DH 00H

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

EDARL

C6H 00H

EDATA3

BEH 00H

RESERVED

RESERVED

A6H

NOT USED

NOT USED

RESERVED RESERVED

RESERVEDRESERVED

RESERVED

SPIDAT

F7H 00H

ADCCON1

EFH 00H

RESERVED

PSMCON

DFH DEH

PLLCON

D7H 53H

RESERVED

RESERVED

EDATA4

BFH 00H

NOT USED

RESERVED

NOT USEDNOT USED

NOT USED

PCON

87H 00H

SFR MAP KEY:

MNEMONIC

SFR ADDRESS
DEFAULT VALUE

THESE BITS ARE CONTAINED IN THIS BYTE.

IE0

89H 0

IT0

88H 0

TCON

88H 00H

MNEMONIC
DEFAULT VALUE

SFR ADDRESS

Figure 22. Special Function Register Locations and Reset Values

Note the following about SFRs:

• SFRs whose address ends in 0H or 8H are bit addressable.

• Only P1.0 and P1.1 can operate as digital I/O pins. P1.2–P1.7 can be configured as analog inputs (ADC inputs) or as digital inputs.

• The CHIPID SFR contains the silicon revision ID byte and may change for future silicon revisions.

• These registers are reconfigured at power-on with factory calculated calibration coefficients that can be overwritten by user code. See

the calibration options in ADCCON3 SFR.

SS

• When the SPIM bit in the SPICON SFR is cleared, the SPR0 bit reflects the level on the

Rev. A | Page 20 of 72

pin (Pin 22).

02748-0-029

ADuC814

ADC CIRCUIT INFORMATION

GENERAL OVERVIEW

The ADC block incorporates a 4.05 msec, 6-channel, 12-bit
resolution, single-supply ADC. This block provides the user
with a multichannel multiplexer, track-and-hold amplifier, on­chip reference, offset calibration features and ADC. All compo­nents in this block are easily configured via a 3-register SFR
interface.

The ADC consists of a conventional successive-approximation
converter based around a capacitor DAC. The converter accepts
an analog input range of 0 V to V
brated 2.5 V reference is provided on-chip. An external reference
may also be used via the external V
ence can be in the range 1.0 V to AV

Single or continuous conversion modes can be initiated in
software. In hardware, a convert signal can be applied to an
external pin (CONVST), or alternatively Timer 2 can be config­ured to generate a repetitive trigger for ADC conversions.

The ADuC814 has a high speed ADC to SPI interface data
capture logic implemented on-chip. Once configured, this logic
transfers the ADC data to the SPI interface without the need for
CPU intervention.

The ADC has six external input channels. Two of the ADC
channels are multiplexed with the DAC outputs, ADC4 with
DAC0, and ADC5 with DAC1. When the DAC outputs are in
use, any ADC conversion on these channels represents the DAC
output voltage. Due care must be taken to ensure that no
external signal is trying to drive these ADC/DAC channels
while the DAC outputs are enabled.

In addition to the six external channels of the ADC, five internal
signals are also routed through the front end multiplexer. These
signals include a temperature monitor, DAC0, DAC1, V
AGND. The temperature monitor is a voltage output from an
on-chip band gap reference, which is proportional to absolute
temperature. These internal channels can be selected similarly
to the external channels via CS3–CS0 bits in the ADCCON2 SFR.

The ADuC814 is shipped with factory programmed offset and
gain calibration coefficients that are automatically downloaded
to the ADC on a power-on or RESET event, ensuring optimum
ADC performance. The ADC core contains automatic endpoint
self-calibration and system calibration options that allow the
user to overwrite the factory programmed coefficients if desired
and tailor the ADC transfer function to the system in which it is
being used.

. A precision, factory cali-

REF

pin. This external refer-

REF

.

DD

REF

, and

ADC TRANSFER FUNCTION

The analog input range for the ADC is 0 V to V
range, the designed code transitions occur midway between
successive integer LSB values, i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . .
FS –3/2 LSBs. The output coding is straight binary with 1 LSB =
FS/4096 or 2.5 V/4096 = 0.61 mV when V

REF

input/output transfer characteristic for the 0 V to V
shown in Figure 23.

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...010

000...001

000...000
0V 1LSB

Figure 23. ADuC814 ADC Transfer Function

1LSB =

FS

4096

VOLTAGE INPUT

ADC Data Output Format

Once configured via the ADCCON1–3 SFRs, the ADC converts
the analog input and provides an ADC 12-bit result word in the
ADCDATAH/L SFRs. The ADCDATAL SFR contains the
bottom 8 bits of the 12-bit result. The bottom nibble of the
ADCDATAH SFR contains the top 4 bits of the result, while the
top nibble contains the channel ID of the ADC channel which
has been converted on. This ID corresponds to the channel
selection bits CD3–CD0 in the ADCCON2 SFR. The format of
the ADC 12-bit result word is shown in Figure 24.

CH–ID

TOP 4 BITS

Figure 24. ADC Result Format

HIGH 4 BITS OF
ADC RESULT WORD

LOW 8 BITS OF THE
ADC RESULT WORD

. For this

REF

= 2.5 V. The ideal

range is

REF

+FS

ADCDATAH SFR

ADCDATAL SFR

02748-A-030

02748-A-031

Rev. A | Page 21 of 72

ADuC814

SFR INTERFACE TO ADC BLOCK

The ADC operation is fully controlled via three SFRs: ADCCON1, ADCCON2, and ADCCON3. These three registers control the mode
of operation.

ADCCON1 (ADC CONTROL SFR 1)

The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed
below.

SFR Address EFH
SFR Power-on Default 00H
Bit Addressable No

MODE EXT_REF CK1 CK0 AQ1 AQ0 T2C EXC

Table 6. ADCCON1 SFR Bit Designations

Bit No. Name Description

7 MODE Mode Bit.

This bit selects the operating mode of the ADC.
Set to 1 by the user to power on the ADC.
Set to 0 by the user to power down the ADC.

6 EXT_REF External Reference Select Bit.

This bit selects which reference the ADC uses when performing a conversion.
Set to 1 by the user to switch in an external reference.

Set to 0 by the user to switch in the on-chip band gap reference.
5 CK1 ADC Clock Divide Bits.
4 CK0

3 AQ1 The ADC Acquisition Time Select Bits.
2 AQ0

1 T2C The Timer2 Conversion Bit.

0 EXC The External Trigger Enable Bit.

CK1 and CK0 combine to select the divide ratio for the PLL master clock used to generate the ADC clock. To ensure

correct ADC operation, the divider ratio must be chosen to reduce the ADC clock to 4.5 MHz and below. The

divider ratio is selected as follows:

CK1 CK0 PLL Divider

0 0 8

0 1 4

1 0 16

1 1 32

AQ1 and AQ0 combine to select the number of ADC clocks required for the input track-and-hold amplifier to

acquire the input signal. The acquisition time is selected as follows:

AQ1 AQ0 No. ADC Clks

0 0 1

0 1 2

1 0 3

1 1 4

T2C is set to enable the Timer2 overflow bit to be used as the ADC convert start trigger input.

EXC is set to allow the external CONVST pin be used as the active low convert start trigger input. When enabled, a

rising edge on this input pin trigger a conversion. This pin should remain low for a minimum pulse width of

100 nsec at the required sample rate.

Rev. A | Page 22 of 72