ANALOG DEVICES ADuC814 Service Manual
TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
INSTRUCTION SET
Arithmetic Operations
ADD A,source 1,2 12
ADD A,#data 2 12
ADDC A,source 1,2 12
ADDC A,#data 2 12
SUBB A,source subtract from A 1,2 12
SUBB A,#data 2 12
INC A 1 12
INC source increment 1,2 12
INC DPTR 1 24
DEC A 1 12
DEC source 1,2 12
MUL AB multiply A by B 1 48
DIV AB divide A by B 1 48
DA A decimal adjust 1 12
add source to A
add with carry
with borrow
decrement
Data Transfer Operations
MOV A,source 1,2 12
MOV A,#data 2 12
MOV dest,A move source 1,2 12
MOV dest,source 1,2,3 24
MOV dest,#data 2,3 12,24
MOV DPTR,#data16 3 24
MOVC A,@A+DPTR move from 1 24
MOVC A,@A+PC 1 24
MOVX A,@Ri 1 24
MOVX A,@DPTR move to/from 1 24
MOVX @Ri,A 1 24
MOVX @DPTR,A 1 24
PUSH direct push onto stack 2 24
POP direct pop from stack 2 24
XCH A,source exchange bytes 1,2 12
XCHD A,@Ri exchg low digits 1 12
ACALL addr11 2 24
LCALL addr16 3 24
RET return from sub. 1 24
RETI return from int. 1 24
AJMP addr11 2 24
LJMP addr16 3 24
SJMP rel 2 24
JMP @A+DPTR 1 24
JZ rel jump if A = 0 2 24
JNZ rel jump if A not 0 2 24
CJNE A,direct,rel 3 24
CJNE A,#data,rel compare and 3 24
CJNE Rn,#data,rel equal 3 24
CJNE @Ri,#data,rel 2 24
DJNZ Rn,rel decrement and 2 24
DJNZ direct, rel 3 24
NOP no operation 1 12
to destination
code memory
data memory
call subroutine
jump
jump if not
jump if not zero
bytes
bytes
bytes
ASSEMBLER DIRECTIVES
EQU define symbol
DATA define internal memory symbol
IDATA define indirect addressing symbol
XDATA define external memory symbol
BIT define internal bit memory symbol
CODE define program memory symbol
DS reserve bytes of data memory
DBIT reserve bits of bit memory
DB store byte values in program memory
OSC
periods
Rn register addressing using R0-R7
direct 8bit internal address (00h-FFh)
@Ri indirect addressing using R0 or R1
source any of [Rn, direct, @Ri]
dest any of [Rn, direct, @Ri]
#data 8bit constant included in instruction
#data16 16bit constant included in instruction
bit 8bit direct address of bit
rel signed 8bit offset
addr11 11bit address in current 2K page
addr16 16bit address
Legend
Logical Operations
ANL A,source 1,2 12
ANL A,#data 2 12
ANL direct,A 2 12
OSC
periods
ANL direct,#data 3 24
ORL A,source 1,2 12
ORL A,#data 2 12
ORL direct,A 2 12
ORL direct,#data 3 24
XRL A,source 1,2 12
XRL A,#data 2 12
XRL direct,A 2 12
XRL direct,#data 3 24
CLR A clear A to zero 1 12
CPL A complement A 1 12
RL A rotate A left 1 12
RLC A ...through C 1 12
RR A rotate A right 1 12
RRC A ...through C 1 12
SWAP A swap nibbles 1 12
Boolean Variable ManipulationProgram Branching
OSC
periods
CLR C 1 12
CLR bit 2 12
SETB C 1 12
SETB bit 2 12
CPL C 1 12
CPL bit 2 12
ANL C,bit AND bit with C 2 24
ANL C,/bit ...NOTbit with C 2 24
ORL C,bit OR bit with C 2 24
ORL C,/bit ...NOTbit with C 2 24
MOV C,bit 2 12
MOV bit,C 2 24
JC rel jump if C set 2 24
JNC rel jmp if C not set 2 24
JB bit,rel jump if bit set 3 24
JNB bit,rel jmp if bit not set 3 24
JBC bit, rel jmp&clear if set 3 24
DW store word values in program memory
ORG set segment location counter
END end of assembly source file
CSEG select program memory space
XSEG select external data memory space
DSEG select internal data memory space
ISEG select indirectly addressed internal
BSEG select bit addressable memory space
logical AND
logical OR
logical XOR
clear bit to zero
set bit to one
complement bit
move bit to bit
data memory space
bytes
bytes
OSC
periods
OSC
periods
PIN FUNCTIONS
pin 1 identifier
ADuC814
28pin TSSOP
TOP VIEW
(not to scale)
27
26
25
24
23
22
21
20
19
18
17
16
28 DVDD
27 XTAL2
26 XTAL1
25 SCLOCK / D0
24 P3.7 / MOSI / D1
23 P3.6 / MISO
22 P3.5 / T1 / SS / EXTCLK
21 P1.7 / ADC5 / DAC1
20 P1.6 / ADC4 / DAC0
19 P1.5 / ADC3
18 P1.4 / ADC2
17 CREF
16 VREF
15 AGND
10
11
12
13
14 15
1 DGND
2 DLOAD
3 P3.0 / RxD
4 P3.1 / TxD
5 P3.2 / INT0
6 P3.3 / INT1
7 P3.4 / T0 / CONVST
8 P1.0 / T2
9 P1.1 / T2EX
10 RESET
11 P1.2 / ADC0
12 P1.3 / ADC1
13 AVDD
14 AGND
1 28
2
3
4
5
6
7
8
9
PROGRAM MEMORY SPACE (read only)
1FFFh
0000h
(no parallel external memory interface)
internal
8K bytes
Flash/EE
8K bytes
addressable
INTERRUPT VECTOR ADDRESSES
Priority
Interrupt
Bit
Interrupt Name
PSMCON.5 Power Supply Monitor Interrupt 43h 1
PLLCON.6 PLL Lock Interrupt 4Bh 2
WDS WatchDog Timer Interrupt 5Bh 3
IE0 External Interrupt 0 03h 4
ADCI End of ADC Conversion Interrupt 33h 5
TF0 Timer0 Overflow Interrupt 0Bh 6
IE1 External Interrupt 1 13h 7
TF1 Timer1 Overflow Interrupt 1Bh 8
ISPI SPI Interrupt 3Bh 9
RI/TI UART Interrupt 23h 10
TF2/EXF2 Timer2 Interrupt 2Bh 11
TIMECON.2 Time Interval Counter Interrupt 53h 12
Vector
Address
within
Level
ADuC814
MicroConverter
Quick Reference Guide
a “Data Acquisition System on a Chip”
the ADuC814 is:
Flash/EEPROM: 8K bytes Flash/EE program memory
microcontroller: industry standard 8052
other on-chip features: temperature monitor, power supply monitor,
hardware
7CONVST
11
ADC0
12
ADC1
18
ADC2
ADC3
ADC4
ADC5
V
C
PRINTED IN U.S.A. G02945-1-4/02 (0)
AIN
19
MUX
20
21
TEMP
monitor
2.5V
bandgap
reference
16
REF
17
REF
131415
DD
AV
www.analog.com/microconverter REV. 0
ADC: 12bit, 5µs, 6channel, self calibrating,
guaranteed no missing codes, high-speed
data capture mode
DAC: dual, 12bit, 15µs, voltage output
<1LSB DNL
640 bytes Flash/EE data memory
16 I/O lines, programmable PLL clock
(131KHz to 16MHz from 32KHz crystal)
watchdog timer, flexible serial interface ports,
FUNCTIONAL BLOCK DIAGRAM
P1.2
P1.1
P1.0
P1.2 (ADC0)
P1.1 (T2EX)
P1.0 (T2)
9
8
11
P1.6
P1.5
P1.4
P1.3
P1.6 (ADC4 / DAC0)
P1.5 (ADC3)
P1.4 (ADC2)
P1.3 (ADC1)
P1.7
P1.7 (ADC5 / DAC1)
2120191812
P3.0
P3.0 (RxD)
ADuC814
ADC
asynchronous
10
RESET
640 bytes
data
Flash/EE
8K x 8
program
Flash/EE
downloader
debugger
serial port
(UART)
3
RxD
control
&
calibration
4
TxD
8052
MCU
core
emulator
single-pin
2
DLOAD
AGND
T/H
(-2 mV/oC)
BUF
AGND
POR
28
DD
DV
12bit ADC
1
DGND
P3.4
P3.3
P3.2
P3.1
P3.4 (T0 / CONVST)
P3.3 (INT1)
P3.2 (INT0)
P3.1 (TxD)
76543
DAC
control
256 x 8
user RAM
watchdog
power supply
monitor
synchronous
serial interface
(SPI)
252423
SCLOCK
®
P3.7
P3.6
P3.5
P3.7 (MOSI / D1)
P3.6 (MISO)
P3.5 (T1 / SS / EXTCLK)
242322
DAC0
DAC1
16bit
counter
timers
timer
time
interval
counter
OSC &
PLL
26
22SS
MOSI
MISO
XTAL1
BUF
BUF
27
XTAL2
20
21
7
22
8
9
5
6 INT1
25
24 D1
DAC0
DAC1
T0
T1
T2
T2EX
INT0
D0
TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
SFR DESCRIPTIONS
DATA MEMORY: RAM, SFRs, user Flash/EE (all read/write)
LOWER RAM
decimal
address
HEX
address
127
7Fh
...
30h
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh R7
1Eh R6
1Dh R5
1Ch R4
1Bh R3
1Ah R2
19h R1
18h R0
17h R7
16h R6
15h R5
14h R4
13h R3
12h R2
11h R1
10h R0
0Fh R7
0Eh R6
0Dh R5
0Ch R4
0Bh R3
0Ah R2
09h R1
08h R0
07h R7
06h R6
05h R5
04h R4
03h R3
02h R2
01h R1
00h R0
General Purpose
Area
Bit Addressable
Area
Register
Bank 3
Register
Bank 2
Register
Bank 1
Register
Bank 0
MSB
address
7Fh 7Eh 7Dh 7Ch 7Bh 7Ah 79h 78h
(bit addresses)
77h 76h 75h 74h 73h 72h 71h 70h
6Fh 6Eh 6Dh 6Ch 6Bh 6Ah 69h 68h
67h 66h 65h 64h 63h 62h 61h 60h
5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h
57h 56h 55h 54h 53h 52h 51h 50h
4Fh 4Eh 4Dh 4Ch 4Bh 4Ah 49h 48h
47h 46h 45h 44h 43h 42h 41h 40h
3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h
37h 36h 35h 34h 33h 32h 31h 30h
2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h
27h 26h 25h 24h 23h 22g 21h 20h
1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h
17h 16h 15h 14h 13h 12h 11g 10h
0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h
07h 06h 05h 04h 03h 02h 01h 00h
DATA MEMORY SPACE
(read/write area)
( page 159 )
9Fh
640 bytes
(160 pages)
data
Flash/EE
(accessible
through
SFRs)
( page 0 )
00h
FFh
lower RAM
details
00h
128 bytes
upper RAM
(indirect
addressing
only)
128 bytes
lower RAM
(direct or
indirect
addressing)
SFRs
(direct
addressing
only)
SFR details
...
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB
address
SFR MAP & RESET VALUES
SPIDAT
(reserved)
(reserved)
(reserved)
DACCON
FDh 04h
ADCCON3
DAC1H
FCh 00h
ADCGAINH
DAC1L
FBh 00h
ADCGAINL
DAC0H
FAh 00h
ADCOFSH
DAC0L
ADCOFSL
F9h 00h
SPICON
F8h 04hBF0h 00h
SPR0
F8h 0
SPR1
F9h 0
CPHA
FAh 0
CPOL
FBh 0
SPIM
FCh 0
SPE
FDh 0
WCOL
FEh 0
ISPI
FFh 0
MAP KEY
F7h 00h
ADCCON1
F5h 00h
F4h *20h
F3h *00h
F2h *20h
F1h *00h
DCON
F0h 0
F1h 0
F2h 0
D0EN
F3h 0
F4h 0
F5h 0D0EDh 0
D1EN
F6h 0
F7h 0D1EFh 0
EFh 00h
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
ACC
E8h 00h
E8h 0
E9h 0
EAh 0
EBh 0
ECh 0
EEh 0
mnemonic
address
reset value
(reserved)
PSMCON
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
ADCDATAH
(reserved)
ADCDATAL
E0h 00h
ADCCON2
CS0
E0h 0
CS1
E1h 0
CS2
E2h 0
CS3
E3h 0
E4h 0
SCONV
E5h 0
CCONV
E6h 0
ADCSPI
ADCI
E7h 0
(reserved)
D7h 53h
D0h 00h
D3h 0
D4h 0
EADRL
(reserved)
TH2
CDh 00h
TL2
CCh 00h
RCAP2H
CBh 00h
RCAP2L
CAh 00h
(reserved)
T2CON
WDCON
C8h 00h
CAP2
WDWR
C8h 0
WDE
CNT2
C9h 0
TR2
WDS
CAh 0
WDIR
EXEN2
CBh 0
PRE0
TCLK
CCh 0
PRE1
RCLK
CDh 0
EXF2
PRE2
CEh 0
TF2
PRE3
CFh 0
(reserved)(reserved)
(not used)
(reserved)(reserved)
(reserved)
PLLCON
DFh DEh
(reserved)
(reserved)
(reserved)
(reserved)
DAh 00h
D9h 00h
PSW
D8h 00h
D8h 0PD0h 0
D9h 0F1D1h 0
DAh 0OVD2h 0
RS0
DBh 0
RS1
DCh 0
DDh 0F0D5h 0
DEh 0ACD6h 0
DFh 0CYD7h 0
(reserved)
(reserved)
(reserved) (reserved) (reserved)
(reserved)
these bits this byte
SPR0
SPR1
F8h 0
F9h 0
* calibration coefficients are preconfigured at power-up to factory calibrated values
(not used)
BFh 00h
BEh 00h
BDh 00h
BCh 00h
BBh 10h
BAh 20h
B9h 00h
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
IEIP2
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
C6h 00h
EDATA4
EDATA3
EDATA2
EDATA1
ETIM2
ETIM1
ECON
C0h 10hIPB8h 00hP3B0h FFhIEA8h 00h
PX0
C0h 0
PT0
C1h 0
PX1
C2h 0
PT1
C3h 0
C4h 0PSBCh 0T0B4h 1ESACh 0
PT2
C5h 0
PADC
C6h 0
PSI
C7h 0
RXD
B8h 0
B0h 1
TXD
B9h 0
B1h 1
INT0
BAh 0
B2h 1
INT1
BBh 0
B3h 1
BDh 0T1B5h 1
BEh 0WRB6h 1
BFh 0RDB7h 1EAAFh 0
EX0
ET0
EX1
ET1
ET2
EADC
are contained in
SPICON
F8h 00h
A9h A0h
A8h 0
A9h 0
AAh 0
ABh 0
ADh 0
AEh 0
(not used)
(not used)
INTVAL
(not used)
A6h 00h
HOUR
(not used)
A5h 00h
MIN
CFG814
A4h 00h
SEC
(reserved)(reserved)
A3h 00h
HTHSEC
A2h 00h
SBUF
TIMECON
A1h 00h
SCON
(not used)
RI
TI
RB8
TB8
REN
SM2
SM1
SM0
(not used)
(not used)
(not used)
(not used)
9Ch 04h
(not used)
(not used)
(not used)
99h 00h
98h 00hP190h FFh
98h 0T290h 1
T2EX
99h 0
91h 1
9Ah 0
92h 1
9Bh 0
93h 1
9Ch 0
94h 1
9Dh 0
95h 1
9Eh 0
96h 1
9Fh 0
97h 1
mnemonic
reset value
address
(reserved)
(reserved)
TH1
8Dh 00h
TH0
8Ch 00h
TL1
8Bh 00h
TL0
8Ah 00h
TMOD
89h 00hSP81h 07h
TCON
88h 00h
IT0
88h 0
IE0
89h 0
IT1
8Ah 0
IE1
8Bh 0
TR0
8Ch 0
TF0
8Dh 0
TR1
8Eh 0
TF1
8Fh 0
PCON
87h 00h
(reserved) (reserved)
(reserved)
DPH
83h 00h
DPL
82h 00h
(not used)
ADCCON1 ADC Control register #1
ADCCON1.7 ADC mode (0=off, 1=on)
ADCCON1.6 external Vref select bit (0=on-chip Vref)
ADCCON1.5 conversion time = 16 / ADCclk
ADCCON1.4 ADCclk = 16,777,216Hz / [8,4,16,32]
ADCCON1.3 acquisition time select bits
ADCCON1.2 acq time = [1,2,3,4] / ADCclk
ADCCON1.1 Timer2 convert enable
ADCCON1.0 external CONVST enable
ADCCON2 ADC Control register #2
ADCI ADC interrupt flag
ADCSPI enables ADC-to-SPI high-speed data capture mode
CCONV continuous conversion enable bit
SCONV single conversion start bit
CS3 input channel select bits:
CS2 0 - 5 = ADC0 - ADC5
CS1 8 = temperature sensor
CS0 9=DAC0, A=DAC1, B=AGND, C=VREF
ADCCON3 ADC Control register #3
ADCCON3.7 busy indicator flag (0=ADC not active)
ADCCON3.6 gain calibration disable bit (0=gain cal enabled)
ADCCON3.5 number of averages selection bits
ADCCON3.4 [15,1,31,63] averages
ADCCON3.3 offset calibration disable bit (0=offset cal enabled)
ADCCON3.2 (this bit must contain 1)
ADCCON3.1 calibration type (0=offset cal, 1=gain cal)
ADCCON3.0 start calibration bit, set to 1 to begin cal
ADCDATAH
ADCDATAL
ADCGAINH
ADCGAINL
ADCOFSH
ADCOFSL
DACCON DAC Control register
DACCON.7 ModeSelect (0=12bit, 1=8bit)
DACCON.6 DAC1 RangeSelect (0=2.5V, 1=VDD)
DACCON.5 DAC0 RangeSelect (0=2.5V, 1=VDD)
DACCON.4 Clear DAC1 (0=0V, 1=normal operation)
DACCON.3 Clear DAC0 (0=0V, 1=normal operation)
DACCON.2 SynchronousUpdate (1=asynchronous)
DACCON.1 PowerDown DAC1 (0=off, 1=on)
DACCON.0 PowerDown DAC0 (0=off, 1=on)
DAC1H,DAC1L DAC1 data registers
ADC Data registers
ADC Gain
calibration coefficients
ADC Offset
calibration coefficients
DAC0H,DAC0L DAC0 data registers
PLLCON PLL Control register
PLLCON.7 oscillator powerdown control bit (0=normal)
PLLCON.6 PLL lock indicator flag (0=out of lock)
PLLCON.5 (this bit must contain zero)
PLLCON.4 (this bit must contain zero)
PLLCON.3 “fast interrupt” control bit (0=normal)
PLLCON.2 3-bit clock divider value, “CD” (default=3):
PLLCON.1
PLLCON.0
TIMECON Time Interval Counter Control Register
TIMECON.6 24hour select bit (0=255hour)
TIMECON.5 INTVAL timebase select bits
TIMECON.4 [128th sec, seconds, minutes, hours]
TIMECON.3 single time interval control bit (0=reload&restart)
TIMECON.2 time interval interrupt bit, “TII”
TIMECON.1 time interval enable bit (0=disable&clear)
TIMECON.0 time clock enable bit (0=disable)
INTVAL TIC Interval Register
HTHSEC TIC Elapsed 128th Second Register
SEC TIC Elapsed Seconds Register
MIN TIC Elapsed Minutes Register
HOUR TIC Elapsed Hours Register
CFG814 ADuC814 Configuration Register
CFG814.0 SPI enable (0=disabled)
CFG814.1 PLL bypas (0=XTAL+PLL, 1=P3.5)
ECON Data Flash/EE comand register
EADRL Data Flash/EE address register
EDATA1,EDATA2,EDATA3,EDATA4
f
= 16,777,216Hz ÷ 2
CORE
01h READ page
02h PROGRAM page
04h VERIFY page
Data Flash/EE data registers
CD
05h ERASE page
06h ERASE ALL
othersreserved
ETIM1,ETIM2 Data Flash/EE timing registers
SPICON SPI Control register
ISPI SPI inturrupt (set at end of SPI transfer)
WCOL write collision error flag
SPE SPI enable (0=DCON enable, 1=SPI enable)
SPIM master mode select (0=slave)
CPOL clock polarity select (0=SCLK idles low)
CPHA clock phase select (0=leading edge latch)
SPR1 SPI bitrate select bits
SPR0 bitrate = Fcore / [2,4,8,16] (slave: SPR0=SS)
SPIDAT SPI Data register
DCON D0 & D1 Control register
(enabled if SPE=0, see SPICON register above)
D1 D1 output bit
D1EN D1 output enable (0=disable)
D0 D0 output bit
D0EN D0 output enable (0=disable)
WDCON Watchdog Timer control register
PRE3 watchdog timeout selection bits
PRE2 0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms
PRE1 8=0ms (immediate reset)
PRE0 >8=reserved
WDIR watchdog interrupt response bit
WDS watchdog status flag (1 indicates watchdog timeout)
WDE watchdog enable control (0=disabled)
WDWR watchdog write enable bit (set to enable write)
PSMCON Power Supply Monitor control register
PSMCON.7 (reserved)
PSMCON.6 PSM status bit (1=normal / 0=fault)
PSMCON.5 PSM interrupt bit
PSMCON.4 trip point select bits
PSMCON.3 [4.63V, 3.08V, 2.93V, 2.63V]
PSMCON.2 (reserved)
PSMCON.1 (reserved)
PSMCON.0 PSM enable control (0=off, 1=on)
SP Stack Pointer
IE Interrupt Enable register #1
EA enable inturrupts (0=all inturrupts disabled)
EADC enable ADCI (ADC interrupt)
ET2 enable TF2/EXF2 (Timer2 overflow interrupt)
ES enable RI/TI (serial port interrupt)
ET1 enable TF1 (Timer1 overflow interrupt)
EX1 enable IE1 (external interrupt 1)
ET0 enable TF0 (Timer0 overflow interrupt)
EX0 enable IE0 (external interrupt 0)
IP Interrupt Priority register
IP.7 (not used)
PADC priority of ADCI (ADC interrupt)
PT2 priority of TF2/EXF2 (Timer2 overflow interrupt)
PS priority of RI/TI (serial port interrupt)
PT1 priority of TF1 (Timer1 overflow interrupt)
PX1 priority of IE1 (external INT1)
PT0 priority of TF0 (Timer0 overflow interrupt)
PX0 priority of IE0 (external INT0)
IEIP2 Interrupt Enable/Priority register #2
IEIP2.7 priority of LOCK interrupt (PLL lock)
IEIP2.6 priority of TII interrupt (time interval)
IEIP2.5 priority of PSMI interrupt (power supply monitor)
IEIP2.4 priority of ISPI interrupt (serial interface)
IEIP2.3 enable LOCK interrupt (PLL lock)
IEIP2.2 enable TII interrupt (time interval)
IEIP2.1 enable PSMI (power supply monitor interrupt)
IEIP2.0 enable ISPI interrupt (serial interface)
TMOD Timer Mode register
TMOD.3/.7 gate control bit (0=ignore INTx)
TMOD.2/.6 counter/timer select bit (0=timer)
TMOD.1/.5 timer mode selecton bits
TMOD.0/.4 [13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TCON Timer Control register
TF1 Timer1 overflow flag (auto cleared on vector to ISR)
TR1 Timer1 run control (0=off, 1=run)
TF0 Timer0 overflow flag (auto cleared on vector to ISR)
TR0 Timer0 run control (0=off, 1=run)
IE1 external INT1 flag (auto cleared on vector to ISR)
IT1 IE1 type (0=level trig, 1=edge trig)
IE0 external INT0 flag (auto cleared on vector to ISR)
IT0 IE0 type (0=level trig, 1=edge trig)
TH0,TL0 Timer0 registers
TH1,TL1 Timer1 registers
T2CON Timer2 Control register
TF2 overflow flag
EXF2 external flag
RCLK receive clock enable (0=Timer1 used for RxD clk)
TCLK transmit clock enable (0=Timer1 used for TxD clk)
EXEN2 external enable (0=ignore T2EX, 1=cap/rld on T2EX)
TR2 run control (0=stop, 1=run)
CNT2 timer/counter select (0=timer, 1=counter)
CAP2 capture/reload select (0=reload, 1=capture)
TH2,TL2 Timer2 register
RCAP2H,RCAP2L Timer2 Reload/Capture
P1 Port1 register
P1.2-1.7 analog/digital pins (1=analog function, 0=digital input)
T2EX timer/counter 2 capture/reload trigger
T2 timer/counter 2 external input
P3 Port3 register
RD external data memory read strobe
WR external data memory write strobe
T1 timer/counter 1 external input
T0 timer/counter 0 external input
INT1 external interrupt 1
INT0 external interrupt 0
TxD serial port transmit data line
RxD serial port receive data line
SCON Serial communications Control register
SM0 UART mode control bits baud rate:
SM1 00 - 8bit shift register - F
01 - 8bit UART - TimerOverflowRate/32(x2)
10 - 9bit UART - F
11 - 9bit UART - TimerOverflowRate/32(x2)
SM2 in modes 2&3, enables multiprocessor communication
REN receive enable control bit
TB8 in modes 2&3, 9th bit transmitted
RB8 in modes 2&3, 9th bit received
TI transmit interrupt flag
RI receive interrupt flag
SBUF Serial port Buffer register
PCON Power Control register
PCON.7 double baud rate control
PCON.6 enable serial interrupt (ISI) from power-down mode
PCON.5 enable interrupt 0 (INT0) from power-down mode
PCON.4 ALE disable (0=normal, 1=forces ALE high)
PCON.3 general purpose flag
PCON.2 general purpose flag
PCON.1 power-down control bit (recoverable with hard reset)
PCON.0 idle-mode control (recoverable with enabled interrupt)
PSW Program Status Word
CY carry flag
AC auxiliary carry flag
F0 general purpose flag 0
RS1 register bank select control bits
RS0 active register bank = [0,1,2,3]
OV overflow flag
F1 general purpose flag 1
P parity of ACC
DPH,DPL (DPTR) Data Pointer
/12
OSC
/64(x2)
OSC
ACC Accumulator
B auxiliary math register
TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
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